20.08 Samples, tutorials and reference solutions (#162)

* wolfSSL sample
* Device-to-cloud reference solution for low-power MCU
* Error handling tutorial
* Improve connection/authentication handling in Azure IoT sample; fix
  CmdArgs bug
* Fix error handling bug in HTTPS samples

.github/CODEOWNERS

@@ -2,4 +2,4 @@
 # Each line is a file pattern followed by one or more owners.
 
 # These owners will be the default owners for everything in the repo.
-*       @tokenstar @richardtaylorrt @cjoprey @cawhitworth @rebeccaleigh
+*       @tokenstar @richardtaylorrt @cjoprey @cawhitworth @rebeccaleigh @robotdad

BUILD_INSTRUCTIONS.md

@@ -4,7 +4,7 @@ The sample applications are designed to be built with Visual Studio on Windows,
 
 - [Build and run a high-level sample with Visual Studio](#build-and-run-a-sample-application-with-visual-studio)
 - [Build and run a high-level sample with Visual Studio Code](#build-and-run-a-sample-application-with-visual-studio-code)
-- [Build and run a high-level sample with the CLI](https://docs.microsoft.com/azure-sphere/install/qs-blink-application?pivots=cli) 
+- [Build and run a high-level sample with the CLI](https://docs.microsoft.com/azure-sphere/install/qs-blink-application?pivots=cli)
 
 To build and run real-time capable apps (RTApps), see [Tutorial: Build a real-time capable application](https://docs.microsoft.com/azure-sphere/install/qs-real-time-application) in the online documentation.
 
@@ -21,7 +21,7 @@ To build and run real-time capable apps (RTApps), see [Tutorial: Build a real-ti
       Several hardware definitions are provided with the Azure Sphere SDK. For example, if you're using a SEEED MT3620 Mini Dev Board, specify HardwareDefinitions/seeed_mt3620_mdb instead.
 
 1. In Visual Studio, select **View** > **Output** to display the Output window.
-1. Ensure that your device is connected to your PC by USB. 
+1. Ensure that your device is connected to your PC by USB.
 1. In the Set startup item, select **GDB Debugger (HLCore)** to build a high-level app.
 1. Press **F5** to build and deploy the application.
 
@@ -34,13 +34,12 @@ To build and run real-time capable apps (RTApps), see [Tutorial: Build a real-ti
 
 1. Start Visual Studio Code. Select **File** > **Open Folder**, and then select the folder that contains the sample you want to build. If the folder contains samples for both high-level apps and real-time capable apps (RTApps), make sure you open the correct folder.
 
-1. If the application targets hardware-specific features, open the CMakeLists.txt file and change the TARGET_DIRECTORY setting to specify the folder that contains definitions for the hardware you're using. By default, the TARGET_DIRECTORY specifies HardwareDefinitions/mt3620_rbd, which matches the Seeed Azure Sphere MT3620 Development Kit: 
+1. If the application targets hardware-specific features, open the CMakeLists.txt file and change the TARGET_DIRECTORY setting to specify the folder that contains definitions for the hardware you're using. By default, the TARGET_DIRECTORY specifies HardwareDefinitions/mt3620_rbd, which matches the Seeed Azure Sphere MT3620 Development Kit:
 
    `azsphere_target_hardware_definition(${PROJECT_NAME} TARGET_DIRECTORY "../../../HardwareDefinitions/mt3620_rdb" TARGET_DEFINITION "sample_appliance.json")`
    
-   Several hardware definitions are provided with the Azure Sphere SDK. For example, if you're using a SEEED MT3620 Mini Dev Board, specify HardwareDefinitions/seeed_mt3620_mdb instead. 
+   Several hardware definitions are provided with the Azure Sphere SDK. For example, if you're using a SEEED MT3620 Mini Dev Board, specify HardwareDefinitions/seeed_mt3620_mdb instead.
 
 1. Press F5 to build and debug the project. If the project has not previously been built, or if files have changed and rebuilding is required, Visual Studio Code will build the project before debugging starts.
 
-1. Wait several seconds for Visual Studio Code to build the application, create an image package, deploy it to the board, and start it in debug mode. You'll see status updates in the Output pane along the way. 
-
+1. Wait several seconds for Visual Studio Code to build the application, create an image package, deploy it to the board, and start it in debug mode. You'll see status updates in the Output pane along the way.

HardwareDefinitions/mt3620_rdb/inc/hw/sample_appliance.h

@@ -63,6 +63,12 @@
 // MT3620 RDB: Connect external NRF52 UART using header 2, pin 1 (RX), pin 3 (TX), pin 5 (CTS), pin 7 (RTS)
 #define SAMPLE_NRF52_UART MT3620_RDB_HEADER2_ISU0_UART
 
+// MT3620 RDB: Connect external STM32 UART using header 2, pin 1 (RX), pin 3 (TX) (no flow control)
+#define SAMPLE_STM32_UART MT3620_RDB_HEADER2_ISU0_UART
+
+// MT3620 RDB: Connect external STM32 UART using header 4, pin 6 (RX), pin 7 (TX) (no flow control)
+#define SAMPLE_DEBUG_UART MT3620_RDB_HEADER4_ISU1_UART
+
 // MT3620 RDB: LED 1 (red channel)
 #define SAMPLE_DEVICE_STATUS_LED MT3620_RDB_LED1_RED
 

HardwareDefinitions/mt3620_rdb/sample_appliance.json

@@ -36,6 +36,8 @@
         {"Name": "SAMPLE_NRF52_RESET", "Type": "Gpio", "Mapping": "MT3620_RDB_HEADER2_PIN4_GPIO", "Comment": "MT3620 RDB: Connect external NRF52 RESET GPIO using header 2, pin 4"},
         {"Name": "SAMPLE_NRF52_DFU", "Type": "Gpio", "Mapping": "MT3620_RDB_HEADER2_PIN14_GPIO", "Comment": "MT3620 RDB: Connect external NRF52 DFU GPIO using header 2, pin 14"},
         {"Name": "SAMPLE_NRF52_UART", "Type": "Uart", "Mapping": "MT3620_RDB_HEADER2_ISU0_UART", "Comment": "MT3620 RDB: Connect external NRF52 UART using header 2, pin 1 (RX), pin 3 (TX), pin 5 (CTS), pin 7 (RTS)"},
+        {"Name": "SAMPLE_STM32_UART", "Type": "Uart", "Mapping": "MT3620_RDB_HEADER2_ISU0_UART", "Comment": "MT3620 RDB: Connect external STM32 UART using header 2, pin 1 (RX), pin 3 (TX) (no flow control)"},
+        {"Name": "SAMPLE_DEBUG_UART", "Type": "Uart", "Mapping": "MT3620_RDB_HEADER4_ISU1_UART", "Comment": "MT3620 RDB: Connect external STM32 UART using header 4, pin 6 (RX), pin 7 (TX) (no flow control)"},
         {"Name": "SAMPLE_DEVICE_STATUS_LED", "Type": "Gpio", "Mapping": "MT3620_RDB_LED1_RED", "Comment": "MT3620 RDB: LED 1 (red channel)"},
         {"Name": "SAMPLE_PENDING_UPDATE_LED", "Type": "Gpio", "Mapping": "MT3620_RDB_LED3_BLUE", "Comment": "MT3620 RDB: LED 3 (blue channel)"}
     ]

Samples/ADC/ADC_HighLevelApp/eventloop_timer_utilities.c

@@ -125,7 +125,7 @@ int ConsumeEventLoopTimerEvent(EventLoopTimer *timer)
 
 int SetEventLoopTimerPeriod(EventLoopTimer *timer, const struct timespec *period)
 {
-    return SetTimerPeriod(timer->fd, /* initial */ period, /* period */ period);
+    return SetTimerPeriod(timer->fd, /* initial */ period, /* repeat */ period);
 }
 
 int SetEventLoopTimerOneShot(EventLoopTimer *timer, const struct timespec *delay)

Samples/AzureIoT/IoTHub.md

@@ -11,7 +11,7 @@ Before you run the sample with an IoT Hub:
 - Configure an IoT Hub to work with Azure Sphere based on how you want to connect to your IoT Hub. The device provisioning service is the recommended authentication method.
 - Configure the sample application with information about your Azure Sphere tenant and your IoT Hub.
 
-You can then build the application and, if you want to, use a device twin to support additional features.
+You can then build the application and, if you want to, use a device twin to support additional features. For more information about device twins, see [Understand and use device twins in IoT Hub](https://docs.microsoft.com/azure/iot-hub/iot-hub-devguide-device-twins).
 
 ## Configure an IoT Hub
 
@@ -41,13 +41,13 @@ Use the following steps to gather the information and configure the application:
 1. Find the app_manifest.json file in your sample directory and open it.
 
 1. Update the **CmdArgs** field of the app_manifest.json file.
-   - To configure the sample to use the device provisioning service to connect to the IoT Hub, copy and paste the following line into the  **CmdArgs** field of the app_manifest.json file:
+   - To configure the sample to use the device provisioning service to connect to the Azure IoT Hub, copy and paste the following line into the  **CmdArgs** field of the app_manifest.json file:
 
-      `"--ConnectionType DPS"`
+      `"--ConnectionType", "DPS"`
 
    - In the Azure portal, on the summary screen at the top right of your device provisioning service, copy the ID Scope value and append it to the **CmdArgs** field of the app_manifest.json file as shown below:
 
-      `"--ScopeID <scoped_id>"`
+      `"--ScopeID", "<scope_id>"`
 
 	  - You can also find the ID Scope value in Visual Studio Cloud Explorer. Expand **IoT Hub Device Provisioning Services** under **Azure Sphere Product Services** in Cloud Explorer, then select your device provisioning service. Click the **Properties** tab in the lower pane of Cloud Explorer and look for ID Scope in the list of properties.  
    
@@ -55,18 +55,18 @@ Use the following steps to gather the information and configure the application:
 	   
      - Your **CmdArgs** field should now look like:
    
-       `"CmdArgs": [ "--ConnectionType DPS", "--ScopeID <scopeIdOfYourDPS>" ]`
+       `"CmdArgs": [ "--ConnectionType", "DPS", "--ScopeID", "<scope_id>" ]`
 1. Update the **AllowedConnections** field of the app_manifest.json file.
 
    - On the Azure portal, under **Settings** of your device provisioning service, select **Linked IoT Hubs**. Copy the Name values(s) for the Azure IoT Hub(s) and append them to the **AllowedConnections** field of the app_manifest.json file.
 
-   - Make sure that global.azure-devices.provisioning.net remains in the list; this name is required for access to the device provisioning service.
+   - Make sure that global.azure-devices-provisioning.net remains in the list; this name is required for access to the device provisioning service.
 
    - Each connection must be surrounded by double quotes. Separate connections with a comma.
 
    - Your **AllowedConnections** field should now look like:
 
-     `"AllowedConnections": [ "global.azure-devices-provisioning.net", "<yourLinkedIoTHub>" ]`
+     `"AllowedConnections": [ "global.azure-devices-provisioning.net", "<linked_iot_hub>" ]`
 
 1. Update the **DeviceAuthentication** field of the app_manifest.json file.
 
@@ -91,18 +91,18 @@ To configure a direct connection to IoT Hub, you will need the following informa
 
 Follow these steps to gather the information and configure the application:
 
-1. Log in to the Azure Portal and navigate to your navigate to your Azure IoT Hub. You will need to refer to this later while configuring the application.
+1. Log in to the Azure Portal and navigate to your Azure IoT Hub. You will need to refer to this later while configuring the application.
 
 1. Find the app_manifest.json file in your sample directory and open it.
 
 1. Update the **CmdArgs** field of the app_manifest.json file:
    - To configure the sample to connect directly to the IoT Hub, copy and paste the following line into the  **CmdArgs** field of the app_manifest.json file:
 
-      `"--ConnectionType Direct"`
+      `"--ConnectionType", "Direct"`
 
    - In the Azure portal, on the summary screen at the top right of your device provisioning service, copy the Hostname of Azure IoT Hub and paste it into the **CmdArgs** field of the app_manifest.json file as an argument to the Hostname option, as shown below:
 
-      `"--Hostname <azure_iot_hub_hostname>"`
+      `"--Hostname", "<azure_iot_hub_hostname>"`
 
    - At the command prompt, run the following command to get the Device ID:
 
@@ -115,13 +115,13 @@ Follow these steps to gather the information and configure the application:
       ```
       - Copy the lowercase Device ID and paste it into the **CmdArgs** field of the app_manifest.json file as an argument to the DeviceID option, as shown below:
 
-        **"--DeviceID <device_id>"**
+        **"--DeviceID", "<device_id>"**
 
       - Each command line option must be surrounded by double quotes. Separate command line options with a comma.
 
       - Your **CmdArgs** field should now look like:
 
-        `"CmdArgs": [ "--ConnectionType Direct", "--Hostname <azure_iot_hub_hostname>", "--DeviceID <device_id>" ]`
+        `"CmdArgs": [ "--ConnectionType", "Direct", "--Hostname", "<azure_iot_hub_hostname>", "--DeviceID", "<device_id>" ]`
 
 1. Update the **AllowedConnections** field of the app_manifest.json file.
 
@@ -131,7 +131,7 @@ Follow these steps to gather the information and configure the application:
 
    - Your **AllowedConnections** field should now look like:
 
-     `"AllowedConnections": [ "<yourIoTHub>" ]`
+     `"AllowedConnections": [ "<iot_hub>" ]`
 
 1. Update the **DeviceAuthentication** field of the app_manifest.json file.
 
@@ -153,11 +153,11 @@ Follow these steps to gather the information and configure the application:
 
 1. See [Troubleshooting samples](../troubleshooting.md) if you encounter errors.
 
-1. After a short delay, IoT Hub output should display messages like:
+1. After a short delay, the sample app will display output messages like:
 
    **INFO: Azure IoT Hub send telemetry: { "Temperature": "33.85" }**
 
-1. Press button A on the MT3620 development board to send a button-press notification to the IoT Hub. The IoT Hub output will display a message indicating a button-press:
+1. Press button A on the MT3620 development board to send a button-press notification to the IoT Hub. The sample app will display an output message indicating a button-press:
 
     **Sending Azure IoT Hub telemetry: { "ButtonPress": "True" }**
 
@@ -171,14 +171,12 @@ You can now edit the device twin to change properties. For example, follow these
 
 1. On the **Device Details** page, select **Device Twin**.
 
-1. In the **properties** field, under **"desired"**, add `"StatusLED": { "value": true},` as shown below:
+1. In the **properties** field, under **"desired"**, add `"StatusLED": true,` as shown below:
 
    ```json
       "properties": {
          "desired": {
-            "StatusLED": {
-               "value": true
-            },
+            "StatusLED": true,
             "$metadata": {
             "$lastUpdated": "2019-01-30T22:18:19.612025Z",
    ```

Samples/AzureIoT/README.md

@@ -46,7 +46,6 @@ The sample uses the following Azure Sphere application libraries:
 |log     |  Displays messages in the Device Output window during debugging  |
 | networking | Determines whether the device is connected to the internet |
 | gpio | Manages buttons A and B and LED 4 on the device |
-|storage    | Gets the path to the certificate file that is used to authenticate the server      |
 | [EventLoop](https://docs.microsoft.com/azure-sphere/reference/applibs-reference/applibs-eventloop/eventloop-overview) | Invoke handlers for timer events |
 
 ## Prerequisites

Samples/AzureIoT/Tools/linux-x64/ShowIoTCentralConfig.pgp

@@ -1,11 +1,11 @@
 -----BEGIN PGP SIGNATURE-----
 Version: BSN Pgp v1.0.0.0
 
-iQEcBAABCAAGBQJfDw8+AAoJEOs+lK2+EinPEMsH/2rRH0/RJ2wiBGk4bpwuIS+Y
-lY4P61pBqt/IK+pOjmvq3rz7vKGdmlRKJfXU7/pNE5p2MMhd0VYwHliF/hCtWKP2
-c9LZpv0Q9qwsNllMzypRsEim7h+2LmPVjC2POwPlQslJwpJPIv9yO5CYWKwVvgUd
-GHb99qlvnqyBTXbH07mhaduDf29KeVbvO+ZrEwWwcNFptuaeobo2dPNeP3FJPBHY
-hGkBKfFTiLIDIxBJqbFH9OFndvILswZhpLflidD5rta+P3tsggP8ErCbGHwn9aCx
-C/MJm1abXuf+PWnvRDK7xRTXJDFtDk0lIf6oh38l6mf1hUY3dprZHpr9J8lYLJ8=
-=V2Sn
+iQEcBAABCAAGBQJfOej7AAoJEOs+lK2+EinPERsH/3uEM7jj8CFF9jHh9T/Ih9VN
+8gNIt9jmWOJUWFjLI1XqPU6APnU2qv9M2atFlzM9uo3SVKiMTJbP9shyB3tPKaUU
+WUpt4y54gRyjruSTRWwcCpFDtVZ/JL+U4wUgQF0mct3Ij23BDpUoVWrkBj2mn5FE
+8ndyVfH/9Sb78iOtVaI+0/TKltnmmfEoq1+lxjytv2Oj/X3WdyhBuzu0p1Z4RnuN
+ZaWgyNevs50QFNji2UXyIKf5LSXxT/OETFwhaGCwOiyChiz1+0h9k+kNT08VgGHS
+7ayqRYTwOXbxSTdztQnzdi3rfZ42lFUukHNhIXc4EAIFa5QKrNRRTsTa/5O9zeM=
+=tdb5
 -----END PGP SIGNATURE-----

Samples/AzureIoT/eventloop_timer_utilities.c

@@ -125,7 +125,7 @@ int ConsumeEventLoopTimerEvent(EventLoopTimer *timer)
 
 int SetEventLoopTimerPeriod(EventLoopTimer *timer, const struct timespec *period)
 {
-    return SetTimerPeriod(timer->fd, /* initial */ period, /* period */ period);
+    return SetTimerPeriod(timer->fd, /* initial */ period, /* repeat */ period);
 }
 
 int SetEventLoopTimerOneShot(EventLoopTimer *timer, const struct timespec *delay)

Samples/AzureIoT/main.c

@@ -28,24 +28,21 @@
 // 4. Device ID (set in 'CmdArgs' and must be in lowercase)
 // 5. Type of connection to use when connecting to the Azure IoT Hub (set in 'CmdArgs')
 
+#include <ctype.h>
+#include <errno.h>
+#include <getopt.h>
 #include <signal.h>
 #include <stdbool.h>
+#include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
-#include <time.h>
-#include <stdio.h>
-#include <stdarg.h>
-#include <errno.h>
-#include <ctype.h>
-#include <getopt.h>
 
 // applibs_versions.h defines the API struct versions to use for applibs APIs.
 #include "applibs_versions.h"
+#include <applibs/eventloop.h>
+#include <applibs/gpio.h>
 #include <applibs/log.h>
 #include <applibs/networking.h>
-#include <applibs/gpio.h>
-#include <applibs/storage.h>
-#include <applibs/eventloop.h>
 
 // The following #include imports a "sample appliance" definition. This app comes with multiple
 // implementations of the sample appliance, each in a separate directory, which allow the code to
@@ -62,6 +59,7 @@
 #include <hw/sample_appliance.h>
 
 #include "eventloop_timer_utilities.h"
+#include "parson.h" // Used to parse Device Twin messages.
 
 // Azure IoT SDK
 #include <iothub_client_core_common.h>
@@ -116,17 +114,28 @@ typedef enum {
     ConnectionType_Direct = 2
 } ConnectionType;
 
-#include "parson.h" // used to parse Device Twin messages.
+/// <summary>
+/// Authentication state of the client with respect to the Azure IoT Hub.
+/// </summary>
+typedef enum {
+    /// <summary>Client is not authenticated by the Azure IoT Hub.</summary>
+    IoTHubClientAuthenticationState_NotAuthenticated = 0,
+    /// <summary>Client has initiated authentication to the Azure IoT Hub.</summary>
+    IoTHubClientAuthenticationState_AuthenticationInitiated = 1,
+    /// <summary>Client is authenticated by the Azure IoT Hub.</summary>
+    IoTHubClientAuthenticationState_Authenticated = 2
+} IoTHubClientAuthenticationState;
 
 // Azure IoT definitions.
 static char *scopeId = NULL;                                      // ScopeId for DPS.
 static char *hubHostName = NULL;                                  // Azure IoT Hub Hostname.
 static char *deviceId = NULL;                                     // Device ID must be in lowercase.
 static ConnectionType connectionType = ConnectionType_NotDefined; // Type of connection to use.
+static IoTHubClientAuthenticationState iotHubClientAuthenticationState =
+    IoTHubClientAuthenticationState_NotAuthenticated; // Authentication state with respect to the
+                                                      // IoT Hub.
 
 static IOTHUB_DEVICE_CLIENT_LL_HANDLE iothubClientHandle = NULL;
-static const int keepalivePeriodSeconds = 20;
-static bool iothubAuthenticated = false;
 static const int deviceIdForDaaCertUsage = 1; // A constant used to direct the IoT SDK to use
                                               // the DAA cert under the hood.
 static const char NetworkInterface[] = "wlan0";
@@ -144,15 +153,15 @@ static const char *GetReasonString(IOTHUB_CLIENT_CONNECTION_STATUS_REASON reason
 static const char *GetAzureSphereProvisioningResultString(
     AZURE_SPHERE_PROV_RETURN_VALUE provisioningResult);
 static void SendTelemetry(const char *jsonMessage);
-static void SetupAzureClient(void);
+static void SetUpAzureIoTHubClient(void);
 static void SendSimulatedTelemetry(void);
 static void ButtonPollTimerEventHandler(EventLoopTimer *timer);
 static bool IsButtonPressed(int fd, GPIO_Value_Type *oldState);
 static void AzureTimerEventHandler(EventLoopTimer *timer);
 static ExitCode ValidateUserConfiguration(void);
 static void ParseCommandLineArguments(int argc, char *argv[]);
-static bool SetupAzureIoTHubClientWithDaa(void);
-static bool SetupAzureIoTHubClientWithDps(void);
+static bool SetUpAzureIoTHubClientWithDaa(void);
+static bool SetUpAzureIoTHubClientWithDps(void);
 static bool IsConnectionReadyToSendTelemetry(void);
 
 // Initialization/Cleanup
@@ -187,9 +196,10 @@ static bool statusLedOn = false;
 
 // Usage text for command line arguments in application manifest.
 static const char *cmdLineArgsUsageText =
-    "DPS connection type: \" CmdArgs \": [\"--ConnectionType DPS\", \"--ScopeID <scope_id>\"]\n"
-    "Direction connection type: \" CmdArgs \": [\" --ConnectionType Direct\", "
-    "\"--Hostname <azureiothub_hostname>\", \"--DeviceID <device_id>\"]\n";
+    "DPS connection type: \" CmdArgs \": [\"--ConnectionType\", \"DPS\", \"--ScopeID\", "
+    "\"<scope_id>\"]\n"
+    "Direction connection type: \" CmdArgs \": [\"--ConnectionType\", \"Direct\", "
+    "\"--Hostname\", \"<azureiothub_hostname>\", \"--DeviceID\", \"<device_id>\"]\n";
 
 /// <summary>
 ///     Signal handler for termination requests. This handler must be async-signal-safe.
@@ -266,8 +276,8 @@ static void AzureTimerEventHandler(EventLoopTimer *timer)
     Networking_InterfaceConnectionStatus status;
     if (Networking_GetInterfaceConnectionStatus(NetworkInterface, &status) == 0) {
         if ((status & Networking_InterfaceConnectionStatus_ConnectedToInternet) &&
-            !iothubAuthenticated) {
-            SetupAzureClient();
+            (iotHubClientAuthenticationState == IoTHubClientAuthenticationState_NotAuthenticated)) {
+            SetUpAzureIoTHubClient();
         }
     } else {
         if (errno != EAGAIN) {
@@ -278,12 +288,15 @@ static void AzureTimerEventHandler(EventLoopTimer *timer)
         }
     }
 
-    if (iothubAuthenticated) {
+    if (iotHubClientAuthenticationState == IoTHubClientAuthenticationState_Authenticated) {
         telemetryCount++;
         if (telemetryCount == AzureIoTPollPeriodsPerTelemetry) {
             telemetryCount = 0;
             SendSimulatedTelemetry();
         }
+    }
+
+    if (iothubClientHandle != NULL) {
         IoTHubDeviceClient_LL_DoWork(iothubClientHandle);
     }
 }
@@ -300,11 +313,11 @@ static void ParseCommandLineArguments(int argc, char *argv[])
                                                    {"DeviceID", required_argument, NULL, 'd'},
                                                    {NULL, 0, NULL, 0}};
 
-    // Loop over all of the options
+    // Loop over all of the options.
     while ((option = getopt_long(argc, argv, "c:s:h:d:", cmdLineOptions, NULL)) != -1) {
         // Check if arguments are missing. Every option requires an argument.
         if (optarg != NULL && optarg[0] == '-') {
-            Log_Debug("Warning: Option %c requires an argument\n", option);
+            Log_Debug("WARNING: Option %c requires an argument\n", option);
             continue;
         }
         switch (option) {
@@ -484,13 +497,17 @@ static void ConnectionStatusCallback(IOTHUB_CLIENT_CONNECTION_STATUS result,
                                      IOTHUB_CLIENT_CONNECTION_STATUS_REASON reason,
                                      void *userContextCallback)
 {
-    iothubAuthenticated = (result == IOTHUB_CLIENT_CONNECTION_AUTHENTICATED);
     Log_Debug("Azure IoT connection status: %s\n", GetReasonString(reason));
-    if (iothubAuthenticated) {
-        // Send static device twin properties when connection is established
-        TwinReportState(
-            "{\"manufacturer\":\"Microsoft\",\"model\":\"Azure Sphere Sample Device\"}");
+
+    if (result != IOTHUB_CLIENT_CONNECTION_AUTHENTICATED) {
+        iotHubClientAuthenticationState = IoTHubClientAuthenticationState_NotAuthenticated;
+        return;
     }
+
+    iotHubClientAuthenticationState = IoTHubClientAuthenticationState_Authenticated;
+
+    // Send static device twin properties when connection is established.
+    TwinReportState("{\"manufacturer\":\"Microsoft\",\"model\":\"Azure Sphere Sample Device\"}");
 }
 
 /// <summary>
@@ -498,21 +515,21 @@ static void ConnectionStatusCallback(IOTHUB_CLIENT_CONNECTION_STATUS result,
 ///     When the SAS Token for a device expires the connection needs to be recreated
 ///     which is why this is not simply a one time call.
 /// </summary>
-static void SetupAzureClient(void)
+static void SetUpAzureIoTHubClient(void)
 {
-    bool isAzureClientSetupSuccessful = false;
+    bool isClientSetupSuccessful = false;
 
     if (iothubClientHandle != NULL) {
         IoTHubDeviceClient_LL_Destroy(iothubClientHandle);
     }
 
     if (connectionType == ConnectionType_Direct) {
-        isAzureClientSetupSuccessful = SetupAzureIoTHubClientWithDaa();
+        isClientSetupSuccessful = SetUpAzureIoTHubClientWithDaa();
     } else if (connectionType == ConnectionType_DPS) {
-        isAzureClientSetupSuccessful = SetupAzureIoTHubClientWithDps();
+        isClientSetupSuccessful = SetUpAzureIoTHubClientWithDps();
     }
 
-    if (!isAzureClientSetupSuccessful) {
+    if (!isClientSetupSuccessful) {
         // If we fail to connect, reduce the polling frequency, starting at
         // AzureIoTMinReconnectPeriodSeconds and with a backoff up to
         // AzureIoTMaxReconnectPeriodSeconds
@@ -538,14 +555,10 @@ static void SetupAzureClient(void)
     struct timespec azureTelemetryPeriod = {.tv_sec = azureIoTPollPeriodSeconds, .tv_nsec = 0};
     SetEventLoopTimerPeriod(azureTimer, &azureTelemetryPeriod);
 
-    iothubAuthenticated = true;
-
-    if (IoTHubDeviceClient_LL_SetOption(iothubClientHandle, OPTION_KEEP_ALIVE,
-                                        &keepalivePeriodSeconds) != IOTHUB_CLIENT_OK) {
-        Log_Debug("ERROR: Failure setting Azure IoT Hub client option \"%s\".\n",
-                  OPTION_KEEP_ALIVE);
-        return;
-    }
+    // Set client authentication state to initiated. This is done to indicate that
+    // SetUpAzureIoTHubClient() has been called (and so should not be called again) while the
+    // client is waiting for a response via the ConnectionStatusCallback().
+    iotHubClientAuthenticationState = IoTHubClientAuthenticationState_AuthenticationInitiated;
 
     IoTHubDeviceClient_LL_SetDeviceTwinCallback(iothubClientHandle, DeviceTwinCallback, NULL);
     IoTHubDeviceClient_LL_SetDeviceMethodCallback(iothubClientHandle, DeviceMethodCallback, NULL);
@@ -557,7 +570,7 @@ static void SetupAzureClient(void)
 ///     Sets up the Azure IoT Hub connection (creates the iothubClientHandle)
 ///     with DAA
 /// </summary>
-static bool SetupAzureIoTHubClientWithDaa(void)
+static bool SetUpAzureIoTHubClientWithDaa(void)
 {
     // Set up auth type
     int retError = iothub_security_init(IOTHUB_SECURITY_TYPE_X509);
@@ -589,7 +602,7 @@ static bool SetupAzureIoTHubClientWithDaa(void)
 ///     Sets up the Azure IoT Hub connection (creates the iothubClientHandle)
 ///     with DPS
 /// </summary>
-static bool SetupAzureIoTHubClientWithDps(void)
+static bool SetUpAzureIoTHubClientWithDps(void)
 {
     AZURE_SPHERE_PROV_RETURN_VALUE provResult =
         IoTHubDeviceClient_LL_CreateWithAzureSphereDeviceAuthProvisioning(scopeId, 10000,
@@ -778,6 +791,12 @@ static bool IsConnectionReadyToSendTelemetry(void)
 /// </summary>
 static void SendTelemetry(const char *jsonMessage)
 {
+    if (iotHubClientAuthenticationState != IoTHubClientAuthenticationState_Authenticated) {
+        // AzureIoT client is not authenticated. Log a warning and return.
+        Log_Debug("WARNING: Azure IoT Hub is not authenticated. Not sending telemetry.\n");
+        return;
+    }
+
     Log_Debug("Sending Azure IoT Hub telemetry: %s.\n", jsonMessage);
 
     // Check whether the device is connected to the internet.
@@ -846,7 +865,7 @@ static void ReportedStateCallback(int result, void *context)
 /// </summary>
 void SendSimulatedTelemetry(void)
 {
-    // generate a simulated temperature
+    // Generate a simulated temperature.
     static float temperature = 50.0f;                    // starting temperature
     float delta = ((float)(rand() % 41)) / 20.0f - 1.0f; // between -1.0 and +1.0
     temperature += delta;

Samples/Certificates/Cert_HighLevelApp/eventloop_timer_utilities.c

@@ -125,7 +125,7 @@ int ConsumeEventLoopTimerEvent(EventLoopTimer *timer)
 
 int SetEventLoopTimerPeriod(EventLoopTimer *timer, const struct timespec *period)
 {
-    return SetTimerPeriod(timer->fd, /* initial */ period, /* period */ period);
+    return SetTimerPeriod(timer->fd, /* initial */ period, /* repeat */ period);
 }
 
 int SetEventLoopTimerOneShot(EventLoopTimer *timer, const struct timespec *delay)

Samples/DNSServiceDiscovery/README.md

@@ -89,8 +89,7 @@ The command registers a service instance with the following configuration:
 
 ## Build and run the sample
 
-To build and run this sample, follow the instructions in [Build a sample application](../../../BUILD_INSTRUCTIONS.md).
-
+To build and run this sample, follow the instructions in [Build a sample application](../../BUILD_INSTRUCTIONS.md).
 
 ## Testing the service connection
 

Samples/DNSServiceDiscovery/eventloop_timer_utilities.c

@@ -125,7 +125,7 @@ int ConsumeEventLoopTimerEvent(EventLoopTimer *timer)
 
 int SetEventLoopTimerPeriod(EventLoopTimer *timer, const struct timespec *period)
 {
-    return SetTimerPeriod(timer->fd, /* initial */ period, /* period */ period);
+    return SetTimerPeriod(timer->fd, /* initial */ period, /* repeat */ period);
 }
 
 int SetEventLoopTimerOneShot(EventLoopTimer *timer, const struct timespec *delay)

Samples/DeferredUpdate/DeferredUpdate_HighLevelApp/README.md

@@ -150,23 +150,23 @@ You can run the Deferred Update application inside or outside the Visual Studio
 2. If it's not already open, quickly open the Deferred Update application in the IDE and then press F5 to start debugging. You must open the application in the IDE and start debugging before the device receives the Blink/Hello World application from the cloud. LED 3 will turn blue to indicate that the update is available, and the following message will be repeated in the **Device Output** window every minute while the application defers the pending update.
 
    ```
-   INFO: Received update event: 2019-10-08 14:32:18
+   INFO: Received update event: 2020-07-17 21:02:54
    INFO: Status: Pending (1)
-   INFO: Max deferral time: 10019 minutes
+   INFO: Max deferral time: 10020 minutes
    INFO: Update Type: Application (1).
    INFO: Deferring update for 1 minute.
 
-   INFO: Received update event: 2019-10-08 14:32:18
-   INFO: Status: Rejected (3)
-   INFO: Max deferral time: 10019 minutes
+   INFO: Received update event: 2020-07-17 21:02:54
+   INFO: Status: Deferred (3)
+   INFO: Max deferral time: 10020 minutes
    INFO: Update Type: Application (1).
-   INFO: Update rejected (update has been deferred).
+   INFO: Update deferred.
    ```
 
 3. Press button A to accept the update. LED 2 will turn yellow to indicate that updates are being accepted. After a few seconds, the following update message is displayed, the Deferred Update application exits, and the Blink/Hello World application starts.
 
    ```
-   INFO: Received update event: 2019-10-08 14:35:28
+   INFO: Received update event: 2020-07-17 21:05:11
    INFO: Status: Final (2)
    INFO: Max deferral time: 0 minutes
    INFO: Update Type: Application (1).

Samples/DeferredUpdate/DeferredUpdate_HighLevelApp/eventloop_timer_utilities.c

@@ -125,7 +125,7 @@ int ConsumeEventLoopTimerEvent(EventLoopTimer *timer)
 
 int SetEventLoopTimerPeriod(EventLoopTimer *timer, const struct timespec *period)
 {
-    return SetTimerPeriod(timer->fd, /* initial */ period, /* period */ period);
+    return SetTimerPeriod(timer->fd, /* initial */ period, /* repeat */ period);
 }
 
 int SetEventLoopTimerOneShot(EventLoopTimer *timer, const struct timespec *delay)

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/.gitignore

@@ -0,0 +1,3 @@
+# Ignore output directories
+/out/
+/install/

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/.vscode/launch.json

@@ -0,0 +1,28 @@
+{
+    // Use IntelliSense to learn about possible attributes.
+    // Hover to view descriptions of existing attributes.
+    // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
+    "version": "0.2.0",
+    "configurations": [
+        {
+            "name": "Launch for Azure Sphere High-Level Applications (gdb)",
+            "type": "azurespheredbg",
+            "request": "launch",
+            "args": [],
+            "stopAtEntry": false,
+            "cwd": "${workspaceFolder}",
+            "environment": [],
+            "externalConsole": true,
+            "targetCore": "HLCore",
+            "partnerComponents": [],
+            "MIMode": "gdb",
+            "setupCommands": [
+                {
+                    "description": "Enable pretty-printing for gdb",
+                    "text": "-enable-pretty-printing",
+                    "ignoreFailures": true
+                }
+            ]
+        }
+    ]
+}

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/.vscode/settings.json

@@ -0,0 +1,11 @@
+{
+    "cmake.generator": "Ninja",
+    "cmake.buildDirectory": "${workspaceRoot}/out/${buildType}-${command:azuresphere.AzureSphereTargetApiSet}",
+    "cmake.buildToolArgs": [ "-v" ],
+    "cmake.configureSettings": {
+        "CMAKE_TOOLCHAIN_FILE": "${command:azuresphere.AzureSphereSdkDir}/CMakeFiles/AzureSphereToolchain.cmake",
+        "AZURE_SPHERE_TARGET_API_SET": "latest-lts"
+    },
+    "cmake.configureOnOpen": true,
+    "C_Cpp.default.configurationProvider": "vector-of-bool.cmake-tools"
+}

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/CMakeLists.txt

@@ -0,0 +1,35 @@
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#  Licensed under the MIT License.
+
+cmake_minimum_required(VERSION 3.10)
+
+project(LowPowerMcuToCloud C)
+
+azsphere_configure_tools(TOOLS_REVISION "20.07")
+azsphere_configure_api(TARGET_API_SET "6")
+
+add_executable(${PROJECT_NAME}
+               main.c
+               azure_iot.c
+               business_logic.c
+               cloud.c
+               color.c
+               debug_uart.c
+               eventloop_timer_utilities.c
+               logging.c
+               message_protocol.c
+               mcu_messaging.c
+               persistent_storage.c
+               parson.c
+               power.c
+               uart_transport.c
+               update.c
+               ../common/message_protocol_utilities.c)
+
+target_compile_options(${PROJECT_NAME} PRIVATE -Wall -Werror)
+target_include_directories(${PROJECT_NAME} PRIVATE ../common)
+target_link_libraries(${PROJECT_NAME} applibs pthread gcc_s c azureiot)
+
+azsphere_target_hardware_definition(${PROJECT_NAME} TARGET_DIRECTORY "../../../../HardwareDefinitions/mt3620_rdb" TARGET_DEFINITION "sample_appliance.json")
+
+azsphere_target_add_image_package(${PROJECT_NAME})

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/CMakeSettings.json

@@ -0,0 +1,47 @@
+{
+  "environments": [
+    {
+      "environment": "AzureSphere"
+    }
+  ],
+  "configurations": [
+    {
+      "name": "ARM-Debug",
+      "generator": "Ninja",
+      "configurationType": "Debug",
+      "inheritEnvironments": [
+        "AzureSphere"
+      ],
+      "buildRoot": "${projectDir}\\out\\${name}",
+      "installRoot": "${projectDir}\\install\\${name}",
+      "cmakeToolchain": "${env.AzureSphereDefaultSDKDir}CMakeFiles\\AzureSphereToolchain.cmake",
+      "buildCommandArgs": "-v",
+      "ctestCommandArgs": "",
+      "variables": [
+        {
+          "name": "AZURE_SPHERE_TARGET_API_SET",
+          "value": "latest-lts"
+        }
+      ]
+    },
+    {
+      "name": "ARM-Release",
+      "generator": "Ninja",
+      "configurationType": "Release",
+      "inheritEnvironments": [
+        "AzureSphere"
+      ],
+      "buildRoot": "${projectDir}\\out\\${name}",
+      "installRoot": "${projectDir}\\install\\${name}",
+      "cmakeToolchain": "${env.AzureSphereDefaultSDKDir}CMakeFiles\\AzureSphereToolchain.cmake",
+      "buildCommandArgs": "-v",
+      "ctestCommandArgs": "",
+      "variables": [
+        {
+          "name": "AZURE_SPHERE_TARGET_API_SET",
+          "value": "latest-lts"
+        }
+      ]
+    }
+  ]
+}

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/LICENSE.txt

@@ -0,0 +1,21 @@
+Copyright (c) Microsoft Corporation. All rights reserved.
+
+MIT License
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED *AS IS*, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/app_manifest.json

@@ -0,0 +1,17 @@
+{
+  "SchemaVersion": 1,
+  "Name": "LowPowerMcuToCloud",
+  "ComponentId": "55286fbe-3ec7-4a16-f997-6e0670fc97e2",
+  "EntryPoint": "/bin/app",
+  "CmdArgs": [ "--ScopeID", "<scopeid>" ],
+  "Capabilities": {
+    "Uart": [ "$SAMPLE_STM32_UART", "$SAMPLE_DEBUG_UART" ],
+    "MutableStorage": { "SizeKB": 8 },
+    "DeviceAuthentication": "00000000-0000-0000-0000-000000000000",
+    "AllowedConnections": [ "global.azure-devices-provisioning.net" ],
+    "SoftwareUpdateDeferral": true,
+    "SystemEventNotifications": true,
+    "PowerControls": [ "ForcePowerDown", "ForceReboot" ]
+  },
+  "ApplicationType": "Default"
+}

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/applibs_versions.h

@@ -0,0 +1,28 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#pragma once
+
+/// <summary>
+/// This identifier should be defined before including any of the networking-related header files.
+/// It indicates which version of the Wi-Fi data structures the application uses.
+/// </summary>
+#define NETWORKING_STRUCTS_VERSION 1
+
+/// <summary>
+/// This identifier must be defined before including any of the Wi-Fi related header files.
+/// It indicates which version of the Wi-Fi data structures the application uses.
+/// </summary>
+#define WIFICONFIG_STRUCTS_VERSION 1
+
+/// <summary>
+/// This identifier must be defined before including any of the UART-related header files.
+/// It indicates which version of the UART data structures the application uses.
+/// </summary>
+#define UART_STRUCTS_VERSION 1
+
+/// <summary>
+/// This identifier must be defined before including any of the SPI-related header files.
+/// It indicates which version of the SPI data structures the application uses.
+/// </summary>
+#define SPI_STRUCTS_VERSION 1

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/azure_iot.c

@@ -0,0 +1,446 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+#include <stdlib.h>
+#include <errno.h>
+
+#include "applibs_versions.h"
+#include <applibs/networking.h>
+#include <applibs/eventloop.h>
+#include <applibs/log.h>
+
+#include "eventloop_timer_utilities.h"
+
+// Azure IoT SDK
+#include <azureiot/iothub_client_core_common.h>
+#include <azureiot/iothub_device_client_ll.h>
+#include <azureiot/iothub_client_options.h>
+#include <azureiot/iothubtransportmqtt.h>
+#include <azureiot/iothub.h>
+#include <azureiot/azure_sphere_provisioning.h>
+#include <azure_prov_client/iothub_security_factory.h>
+
+#include "exitcode.h"
+#include "azure_iot.h"
+
+// Azure IoT definitions.
+static const size_t MAX_SCOPEID_LENGTH = 16;
+static char *idScope = NULL;
+
+static IOTHUB_DEVICE_CLIENT_LL_HANDLE iothubClientHandle = NULL;
+static const int keepalivePeriodSeconds = 20;
+static bool iothubAuthenticated = false;
+static const char NetworkInterface[] = "wlan0";
+
+// Function declarations
+static void SendEventCallback(IOTHUB_CLIENT_CONFIRMATION_RESULT result, void *context);
+static void DeviceTwinCallback(DEVICE_TWIN_UPDATE_STATE updateState, const unsigned char *payload,
+                               size_t payloadSize, void *userContextCallback);
+static void ConnectionStatusCallback(IOTHUB_CLIENT_CONNECTION_STATUS result,
+                                     IOTHUB_CLIENT_CONNECTION_STATUS_REASON reason,
+                                     void *userContextCallback);
+static void ReportedStateCallback(int result, void *context);
+static int DeviceMethodCallback(const char *methodName, const unsigned char *payload,
+                                size_t payloadSize, unsigned char **response, size_t *responseSize,
+                                void *userContextCallback);
+static const char *GetReasonString(IOTHUB_CLIENT_CONNECTION_STATUS_REASON reason);
+static const char *GetAzureSphereProvisioningResultString(
+    AZURE_SPHERE_PROV_RETURN_VALUE provisioningResult);
+static void SetupAzureClient(void);
+static void AzureTimerEventHandler(EventLoopTimer *timer);
+static bool SetupAzureIoTHubClientWithDps(void);
+static bool IsConnectionReadyToSendTelemetry(void);
+
+// Timer / polling
+static EventLoop *eventLoop = NULL;
+static EventLoopTimer *azureTimer = NULL;
+
+// Azure IoT poll periods
+static const int AzureIoTDefaultPollPeriodSeconds = 1;        // poll azure iot every second
+static const int AzureIoTMinReconnectPeriodSeconds = 10;      // back off when reconnecting
+static const int AzureIoTMaxReconnectPeriodSeconds = 10 * 60; // back off limit
+
+static int azureIoTPollPeriodSeconds = -1;
+
+static ExitCodeCallbackType exitCodeCallbackFunction = NULL;
+static AzureIoT_ConnectionStatusCallbackType connectionStatusCallbackFunc = NULL;
+static AzureIoT_DeviceTwinReceivedCallbackType deviceTwinReceivedCallbackFunc = NULL;
+static AzureIoT_SendTelemetryCallbackType sendTelemetryCallbackFunc = NULL;
+static AzureIoT_DeviceTwinReportStateAckCallbackType deviceTwinReportStateAckCallbackFunc = NULL;
+
+ExitCode AzureIoT_Initialize(
+    EventLoop *el, const char *scopeId, ExitCodeCallbackType failureCallback,
+    AzureIoT_ConnectionStatusCallbackType connectionStatusCallback,
+    AzureIoT_DeviceTwinReceivedCallbackType deviceTwinReceivedCallback,
+    AzureIoT_SendTelemetryCallbackType sendTelemetryCallback,
+    AzureIoT_DeviceTwinReportStateAckCallbackType deviceTwinReportStateAckCallback)
+{
+    if (scopeId == NULL) {
+        return ExitCode_AzureIoT_Init_InvalidScopeId;
+    }
+
+    exitCodeCallbackFunction = failureCallback;
+    eventLoop = el;
+    idScope = strndup(scopeId, MAX_SCOPEID_LENGTH);
+    if (idScope == NULL) {
+        return ExitCode_Init_CopyScopeId;
+    }
+
+    azureIoTPollPeriodSeconds = AzureIoTDefaultPollPeriodSeconds;
+    struct timespec azureTelemetryPeriod = {.tv_sec = azureIoTPollPeriodSeconds, .tv_nsec = 0};
+    azureTimer =
+        CreateEventLoopPeriodicTimer(eventLoop, &AzureTimerEventHandler, &azureTelemetryPeriod);
+    if (azureTimer == NULL) {
+        return ExitCode_Init_AzureTimer;
+    }
+
+    connectionStatusCallbackFunc = connectionStatusCallback;
+    deviceTwinReceivedCallbackFunc = deviceTwinReceivedCallback;
+    deviceTwinReportStateAckCallbackFunc = deviceTwinReportStateAckCallback;
+    sendTelemetryCallbackFunc = sendTelemetryCallback;
+
+    return ExitCode_Success;
+}
+
+void AzureIoT_Cleanup(void)
+{
+    free(idScope);
+    DisposeEventLoopTimer(azureTimer);
+}
+
+/// <summary>
+///     Azure timer event: Connect if necessary, do Azure IoT work
+/// </summary>
+static void AzureTimerEventHandler(EventLoopTimer *timer)
+{
+    if (ConsumeEventLoopTimerEvent(timer) != 0) {
+        Log_Debug("ERROR: Could not consume Azure IoT timer event\n");
+        if (exitCodeCallbackFunction != NULL) {
+            exitCodeCallbackFunction(ExitCode_AzureTimer_Consume);
+        }
+        return;
+    }
+
+    // Check whether the device is connected to the internet.
+    Networking_InterfaceConnectionStatus status;
+    if (Networking_GetInterfaceConnectionStatus(NetworkInterface, &status) == 0) {
+        if ((status & Networking_InterfaceConnectionStatus_ConnectedToInternet) &&
+            !iothubAuthenticated) {
+            SetupAzureClient();
+        }
+    } else {
+        if (errno != EAGAIN) {
+            Log_Debug("ERROR: Networking_GetInterfaceConnectionStatus: %d (%s)\n", errno,
+                      strerror(errno));
+            if (exitCodeCallbackFunction != NULL) {
+                exitCodeCallbackFunction(ExitCode_InterfaceConnectionStatus_Failed);
+            }
+            return;
+        }
+    }
+
+    if (iothubAuthenticated) {
+        IoTHubDeviceClient_LL_DoWork(iothubClientHandle);
+    }
+}
+
+/// <summary>
+///     Sets up the Azure IoT Hub connection (creates the iothubClientHandle)
+///     When the SAS Token for a device expires the connection needs to be recreated
+///     which is why this is not simply a one time call.
+/// </summary>
+static void SetupAzureClient(void)
+{
+    bool isAzureClientSetupSuccessful = false;
+
+    if (iothubClientHandle != NULL) {
+        IoTHubDeviceClient_LL_Destroy(iothubClientHandle);
+    }
+
+    isAzureClientSetupSuccessful = SetupAzureIoTHubClientWithDps();
+
+    if (!isAzureClientSetupSuccessful) {
+        // If we fail to connect, reduce the polling frequency, starting at
+        // AzureIoTMinReconnectPeriodSeconds and with a backoff up to
+        // AzureIoTMaxReconnectPeriodSeconds
+        if (azureIoTPollPeriodSeconds == AzureIoTDefaultPollPeriodSeconds) {
+            azureIoTPollPeriodSeconds = AzureIoTMinReconnectPeriodSeconds;
+        } else {
+            azureIoTPollPeriodSeconds *= 2;
+            if (azureIoTPollPeriodSeconds > AzureIoTMaxReconnectPeriodSeconds) {
+                azureIoTPollPeriodSeconds = AzureIoTMaxReconnectPeriodSeconds;
+            }
+        }
+
+        struct timespec azureTelemetryPeriod = {.tv_sec = azureIoTPollPeriodSeconds, .tv_nsec = 0};
+        SetEventLoopTimerPeriod(azureTimer, &azureTelemetryPeriod);
+
+        Log_Debug("ERROR: Failed to create IoTHub Handle - will retry in %i seconds.\n",
+                  azureIoTPollPeriodSeconds);
+        return;
+    }
+
+    // Successfully connected, so make sure the polling frequency is back to the default
+    azureIoTPollPeriodSeconds = AzureIoTDefaultPollPeriodSeconds;
+    struct timespec azureTelemetryPeriod = {.tv_sec = azureIoTPollPeriodSeconds, .tv_nsec = 0};
+    SetEventLoopTimerPeriod(azureTimer, &azureTelemetryPeriod);
+
+    iothubAuthenticated = true;
+
+    if (IoTHubDeviceClient_LL_SetOption(iothubClientHandle, OPTION_KEEP_ALIVE,
+                                        &keepalivePeriodSeconds) != IOTHUB_CLIENT_OK) {
+        Log_Debug("ERROR: Failure setting Azure IoT Hub client option \"%s\".\n",
+                  OPTION_KEEP_ALIVE);
+        return;
+    }
+
+    IoTHubDeviceClient_LL_SetDeviceTwinCallback(iothubClientHandle, DeviceTwinCallback, NULL);
+    IoTHubDeviceClient_LL_SetDeviceMethodCallback(iothubClientHandle, DeviceMethodCallback, NULL);
+    IoTHubDeviceClient_LL_SetConnectionStatusCallback(iothubClientHandle, ConnectionStatusCallback,
+                                                      NULL);
+}
+
+/// <summary>
+///     Sets up the Azure IoT Hub connection (creates the iothubClientHandle)
+///     with DPS
+/// </summary>
+static bool SetupAzureIoTHubClientWithDps(void)
+{
+    AZURE_SPHERE_PROV_RETURN_VALUE provResult =
+        IoTHubDeviceClient_LL_CreateWithAzureSphereDeviceAuthProvisioning(idScope, 10000,
+                                                                          &iothubClientHandle);
+    Log_Debug("IoTHubDeviceClient_LL_CreateWithAzureSphereDeviceAuthProvisioning returned '%s'.\n",
+              GetAzureSphereProvisioningResultString(provResult));
+
+    if (provResult.result != AZURE_SPHERE_PROV_RESULT_OK) {
+        return false;
+    }
+
+    return true;
+}
+
+/// <summary>
+///     Callback when the Azure IoT connection state changes.
+///     This can indicate that a new connection attempt has succeeded or failed.
+///     It can also indicate than an existing connection has expired due to SAS token expiry.
+/// </summary>
+static void ConnectionStatusCallback(IOTHUB_CLIENT_CONNECTION_STATUS result,
+                                     IOTHUB_CLIENT_CONNECTION_STATUS_REASON reason,
+                                     void *userContextCallback)
+{
+    iothubAuthenticated = (result == IOTHUB_CLIENT_CONNECTION_AUTHENTICATED);
+    Log_Debug("Azure IoT connection status: %s\n", GetReasonString(reason));
+
+    if (connectionStatusCallbackFunc != NULL) {
+        connectionStatusCallbackFunc(iothubAuthenticated);
+    } else {
+        Log_Debug("WARNING: Azure IoT - no connection status callback handler registered\n");
+    }
+}
+
+/// <summary>
+///     Callback invoked when a Direct Method is received from Azure IoT Hub.
+/// </summary>
+static int DeviceMethodCallback(const char *methodName, const unsigned char *payload,
+                                size_t payloadSize, unsigned char **response, size_t *responseSize,
+                                void *userContextCallback)
+{
+    // All methods are ignored
+    int result = -1;
+    char *responseString = "{}";
+
+    Log_Debug("Received Device Method callback: Method name %s.\n", methodName);
+
+    // if 'response' is non-NULL, the Azure IoT library frees it after use, so copy it to heap
+    *responseSize = strlen(responseString);
+    *response = malloc(*responseSize);
+    memcpy(*response, responseString, *responseSize);
+    return result;
+}
+
+/// <summary>
+///     Callback invoked when a Device Twin update is received from Azure IoT Hub.
+/// </summary>
+static void DeviceTwinCallback(DEVICE_TWIN_UPDATE_STATE updateState, const unsigned char *payload,
+                               size_t payloadSize, void *userContextCallback)
+{
+    size_t nullTerminatedJsonSize = payloadSize + 1;
+    char *nullTerminatedJsonString = (char *)malloc(nullTerminatedJsonSize);
+    if (nullTerminatedJsonString == NULL) {
+        Log_Debug("ERROR: Could not allocate buffer for twin update payload.\n");
+        abort();
+    }
+
+    // Copy the provided buffer to a null terminated buffer.
+    memcpy(nullTerminatedJsonString, payload, payloadSize);
+    // Add the null terminator at the end.
+    nullTerminatedJsonString[nullTerminatedJsonSize - 1] = 0;
+
+    Log_Debug(nullTerminatedJsonString);
+    Log_Debug("\n");
+
+    if (deviceTwinReceivedCallbackFunc != NULL) {
+        deviceTwinReceivedCallbackFunc(nullTerminatedJsonString);
+    }
+
+    free(nullTerminatedJsonString);
+}
+
+/// <summary>
+///     Converts the Azure IoT Hub connection status reason to a string.
+/// </summary>
+static const char *GetReasonString(IOTHUB_CLIENT_CONNECTION_STATUS_REASON reason)
+{
+    static char *reasonString = "unknown reason";
+    switch (reason) {
+    case IOTHUB_CLIENT_CONNECTION_EXPIRED_SAS_TOKEN:
+        reasonString = "IOTHUB_CLIENT_CONNECTION_EXPIRED_SAS_TOKEN";
+        break;
+    case IOTHUB_CLIENT_CONNECTION_DEVICE_DISABLED:
+        reasonString = "IOTHUB_CLIENT_CONNECTION_DEVICE_DISABLED";
+        break;
+    case IOTHUB_CLIENT_CONNECTION_BAD_CREDENTIAL:
+        reasonString = "IOTHUB_CLIENT_CONNECTION_BAD_CREDENTIAL";
+        break;
+    case IOTHUB_CLIENT_CONNECTION_RETRY_EXPIRED:
+        reasonString = "IOTHUB_CLIENT_CONNECTION_RETRY_EXPIRED";
+        break;
+    case IOTHUB_CLIENT_CONNECTION_NO_NETWORK:
+        reasonString = "IOTHUB_CLIENT_CONNECTION_NO_NETWORK";
+        break;
+    case IOTHUB_CLIENT_CONNECTION_COMMUNICATION_ERROR:
+        reasonString = "IOTHUB_CLIENT_CONNECTION_COMMUNICATION_ERROR";
+        break;
+    case IOTHUB_CLIENT_CONNECTION_NO_PING_RESPONSE:
+        reasonString = "IOTHUB_CLIENT_CONNECTION_NO_PING_RESPONSE";
+        break;
+    case IOTHUB_CLIENT_CONNECTION_OK:
+        reasonString = "IOTHUB_CLIENT_CONNECTION_OK";
+        break;
+    }
+    return reasonString;
+}
+
+/// <summary>
+///     Converts AZURE_SPHERE_PROV_RETURN_VALUE to a string.
+/// </summary>
+static const char *GetAzureSphereProvisioningResultString(
+    AZURE_SPHERE_PROV_RETURN_VALUE provisioningResult)
+{
+    switch (provisioningResult.result) {
+    case AZURE_SPHERE_PROV_RESULT_OK:
+        return "AZURE_SPHERE_PROV_RESULT_OK";
+    case AZURE_SPHERE_PROV_RESULT_INVALID_PARAM:
+        return "AZURE_SPHERE_PROV_RESULT_INVALID_PARAM";
+    case AZURE_SPHERE_PROV_RESULT_NETWORK_NOT_READY:
+        return "AZURE_SPHERE_PROV_RESULT_NETWORK_NOT_READY";
+    case AZURE_SPHERE_PROV_RESULT_DEVICEAUTH_NOT_READY:
+        return "AZURE_SPHERE_PROV_RESULT_DEVICEAUTH_NOT_READY";
+    case AZURE_SPHERE_PROV_RESULT_PROV_DEVICE_ERROR:
+        return "AZURE_SPHERE_PROV_RESULT_PROV_DEVICE_ERROR";
+    case AZURE_SPHERE_PROV_RESULT_GENERIC_ERROR:
+        return "AZURE_SPHERE_PROV_RESULT_GENERIC_ERROR";
+    default:
+        return "UNKNOWN_RETURN_VALUE";
+    }
+}
+
+void AzureIoT_SendTelemetry(const char *jsonMessage, void *context)
+{
+    Log_Debug("Sending Azure IoT Hub telemetry: %s.\n", jsonMessage);
+
+    // Check whether the device is connected to the internet.
+    if (IsConnectionReadyToSendTelemetry() == false) {
+        return;
+    }
+
+    IOTHUB_MESSAGE_HANDLE messageHandle = IoTHubMessage_CreateFromString(jsonMessage);
+
+    if (messageHandle == 0) {
+        Log_Debug("ERROR: unable to create a new IoTHubMessage.\n");
+        return;
+    }
+
+    if (IoTHubDeviceClient_LL_SendEventAsync(iothubClientHandle, messageHandle, SendEventCallback,
+                                             context) != IOTHUB_CLIENT_OK) {
+        Log_Debug("ERROR: failure requesting IoTHubClient to send telemetry event.\n");
+    } else {
+        Log_Debug("INFO: IoTHubClient accepted the telemetry event for delivery.\n");
+    }
+
+    IoTHubMessage_Destroy(messageHandle);
+}
+
+/// <summary>
+///     Check the network status.
+/// </summary>
+static bool IsConnectionReadyToSendTelemetry(void)
+{
+    Networking_InterfaceConnectionStatus status;
+    if (Networking_GetInterfaceConnectionStatus(NetworkInterface, &status) != 0) {
+        if (errno != EAGAIN) {
+            Log_Debug("ERROR: Networking_GetInterfaceConnectionStatus: %d (%s)\n", errno,
+                      strerror(errno));
+
+            if (exitCodeCallbackFunction != NULL) {
+                exitCodeCallbackFunction(ExitCode_InterfaceConnectionStatus_Failed);
+            }
+            return false;
+        }
+        Log_Debug(
+            "WARNING: Cannot send Azure IoT Hub telemetry because the networking stack isn't ready "
+            "yet.\n");
+        return false;
+    }
+
+    if ((status & Networking_InterfaceConnectionStatus_ConnectedToInternet) == 0) {
+        Log_Debug(
+            "WARNING: Cannot send Azure IoT Hub telemetry because the device is not connected to "
+            "the internet.\n");
+        return false;
+    }
+
+    return true;
+}
+
+/// <summary>
+///     Callback invoked when the Azure IoT Hub send event request is processed.
+/// </summary>
+static void SendEventCallback(IOTHUB_CLIENT_CONFIRMATION_RESULT result, void *context)
+{
+    Log_Debug("INFO: Azure IoT Hub send telemetry event callback: status code %d.\n", result);
+    if (sendTelemetryCallbackFunc != NULL) {
+        sendTelemetryCallbackFunc(result == IOTHUB_CLIENT_CONFIRMATION_OK, context);
+    } else {
+        Log_Debug("WARNING: No callback handler registered for send telemetry event\n");
+    }
+}
+
+void AzureIoT_DeviceTwinReportState(const char *jsonState, void *context)
+{
+    if (iothubClientHandle == NULL) {
+        Log_Debug("ERROR: Azure IoT Hub client not initialized.\n");
+    } else {
+        if (IoTHubDeviceClient_LL_SendReportedState(
+                iothubClientHandle, (const unsigned char *)jsonState, strlen(jsonState),
+                ReportedStateCallback, context) != IOTHUB_CLIENT_OK) {
+            Log_Debug("ERROR: Azure IoT Hub client error when reporting state '%s'.\n", jsonState);
+        } else {
+            Log_Debug("INFO: Azure IoT Hub client accepted request to report state '%s'.\n",
+                      jsonState);
+        }
+    }
+}
+
+/// <summary>
+///     Callback invoked when the Device Twin report state request is processed by Azure IoT Hub
+///     client.
+/// </summary>
+static void ReportedStateCallback(int result, void *context)
+{
+    Log_Debug("INFO: Azure IoT Hub device twin reported state: %d\n", result);
+    if (deviceTwinReportStateAckCallbackFunc != NULL) {
+        deviceTwinReportStateAckCallbackFunc(true, context);
+    } else {
+        Log_Debug("WARNING: No callback handler for a device twin ack.\n");
+    }
+}

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/azure_iot.h

@@ -0,0 +1,62 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#pragma once
+
+#include <applibs/eventloop.h>
+#include "exitcode.h"
+
+typedef void (*AzureIoT_DeviceTwinReceivedCallbackType)(const char *deviceTwinContent);
+typedef void (*AzureIoT_ConnectionStatusCallbackType)(bool connected);
+typedef void (*AzureIoT_SendTelemetryCallbackType)(bool success, void *context);
+typedef void (*AzureIoT_DeviceTwinReportStateAckCallbackType)(bool success, void *context);
+
+/// <summary>
+///     Initialize the Azure IoT Hub connection.
+/// </summary>
+/// <param name="el">EventLoop to register timers and events to.</param>
+/// <param name="scopeId">The scope ID for the IoT Central app.</param>
+/// <param name="failureCallback">Function called on unrecoverable failure.</param>
+/// <param name="connectionStatusCallback">Function called on connection status change.</param>
+/// <param name="deviceTwinReceivedCallback">
+///     Function called when device twin update received.
+/// </param>
+/// <param name="sendTelemetryCallback">
+///     Function called on receipt of telemetry by the Azure IoT Hub (or in case of failure).
+/// </param>
+/// <param name="deviceTwinSendUpdateAckCallback">
+///     Function called on receipt of ack (or failure) from the Azure IoT Hub in response to sending
+///     a device twin update.
+/// </param>
+/// <returns>An <see cref="ExitCode" /> indicating success or failure.</returns>
+ExitCode AzureIoT_Initialize(
+    EventLoop *el, const char *scopeId, ExitCodeCallbackType failureCallback,
+    AzureIoT_ConnectionStatusCallbackType connectionStatusCallback,
+    AzureIoT_DeviceTwinReceivedCallbackType deviceTwinReceivedCallback,
+    AzureIoT_SendTelemetryCallbackType sendTelemetryCallback,
+    AzureIoT_DeviceTwinReportStateAckCallbackType deviceTwinSendUpdateAckCallback);
+
+/// <summary>
+///     Closes and cleans up the Azure IoT Hub connection
+/// </summary>
+void AzureIoT_Cleanup(void);
+
+/// <summary>
+///     Enqueue telemetry to send to the Azure IoT Hub. The telemetry is not sent immediately; the
+///     function will return immediately, and then call the
+///     <see cref="AzureIoT_SendTelemetryCallbackType" /> (passed to
+///     <see cref="AzureIoT_Initialize" />) to indicate success or failure.
+/// </summary>
+/// <param name="jsonMessage">The telemetry to send, as a JSON string.</param>
+/// <param name="context">An optional context, which will be passed to the callback.</param>
+void AzureIoT_SendTelemetry(const char *jsonMessage, void *context);
+
+/// <summary>
+///     Enqueue a report containing Device Twin properties to send to the Azure IoT Hub. The report
+///     is not sent immediately; the function will return immediately, and then call the
+///     <see cref="AzureIoT_DeviceTwinReportStateAckCallbackType" /> (passed to
+///     <see cref="AzureIoT_Initialize" />) to indicate success or failure.
+/// </summary>
+/// <param name="jsonState">A JSON string representing the device twin properties to report.</param>
+/// <param name="context">An optional context, which will be passed to the callback.</param>
+void AzureIoT_DeviceTwinReportState(const char *jsonState, void *context);

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/business_logic.c

@@ -0,0 +1,362 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#include <stdbool.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <string.h>
+
+#include <applibs/log.h>
+
+#include "configuration.h"
+
+#include "business_logic.h"
+#include "color.h"
+#include "cloud.h"
+#include "eventloop_timer_utilities.h"
+#include "exitcode.h"
+#include "mcu_messaging.h"
+#include "persistent_storage.h"
+#include "power.h"
+#include "telemetry.h"
+#include "update.h"
+
+static void Initialize(void);
+static void CalculateAndSendTelemetry(void);
+static void LogTelemetry(const DeviceTelemetry *const telemetry);
+
+static void HandleMcuMessageFailure(void);
+static void HandleInitResponseReceived(void);
+static void HandleTelemetryResponseReceived(const DeviceTelemetry *telemetry);
+static void HandleSetLedResponseReceived(const LedColor *color);
+
+static void HandleCloudSendTelemetryAck(bool success);
+static void HandleCloudFlavorAckReceived(bool success);
+
+static void HandleTimeout(EventLoopTimer *timer);
+
+// Application state
+typedef enum {
+    State_Initializing,
+    State_WaitForMcu,
+    State_WaitForCloud,
+    State_GatherTelemetry,
+    State_WaitForTelemetry,
+    State_SendTelemetry,
+    State_WaitForTelemetryAck,
+    State_PersistTelemetry,
+    State_WaitForFlavor,
+    State_WaitForUpdate,
+    State_TimedOut,
+    State_WaitForUpdatesAfterTimeout,
+    State_Sleep,
+    State_Reboot,
+    State_Success,
+    State_Failure,
+    State_Invalid = -1
+} State;
+
+static State applicationState = State_Invalid;
+static bool mcuReady;
+static bool cloudReady;
+static bool haveTelemetry;
+static DeviceTelemetry telemetry;
+static bool telemetryReceivedByCloud;
+static bool haveFlavor;
+static char *receivedFlavorName;
+static bool flavorAckByCloud;
+static bool updateCheckComplete;
+static bool rebootNeededForUpdates;
+
+static ExitCode businessLogicExitCode;
+
+static EventLoopTimer *timeoutTimer = NULL;
+
+static const long timeoutPeriodInSeconds = 120;
+
+ExitCode BusinessLogic_Initialize(EventLoop *el)
+{
+    applicationState = State_Initializing;
+    mcuReady = false;
+    cloudReady = false;
+    haveTelemetry = false;
+    telemetryReceivedByCloud = false;
+    haveFlavor = false;
+    receivedFlavorName = NULL;
+    flavorAckByCloud = false;
+    updateCheckComplete = false;
+    rebootNeededForUpdates = false;
+    businessLogicExitCode = ExitCode_Success;
+
+    timeoutTimer = CreateEventLoopDisarmedTimer(el, HandleTimeout);
+    if (timeoutTimer == NULL) {
+        return ExitCode_BusinessLogic_TimeoutTimerCreate;
+    }
+    struct timespec ts = {.tv_sec = timeoutPeriodInSeconds, .tv_nsec = 0};
+
+    int result = SetEventLoopTimerOneShot(timeoutTimer, &ts);
+    if (result != 0) {
+        return ExitCode_BusinessLogic_SetTimeoutTimer;
+    }
+
+    return ExitCode_Success;
+}
+
+bool BusinessLogic_Run(ExitCode *ec)
+{
+    bool finished;
+    do {
+        finished = true;
+        switch (applicationState) {
+        case State_Invalid:
+            Log_Debug("ERROR: Invalid application state.\n");
+            break;
+        case State_Initializing:
+            Initialize();
+            applicationState = State_WaitForMcu;
+            break;
+        case State_WaitForMcu:
+            if (mcuReady) {
+                applicationState = State_WaitForCloud;
+                finished = false;
+            }
+            break;
+        case State_WaitForCloud:
+            if (cloudReady) {
+                applicationState = State_GatherTelemetry;
+                finished = false;
+            }
+            break;
+        case State_GatherTelemetry:
+            McuMessaging_RequestTelemetry(HandleTelemetryResponseReceived, HandleMcuMessageFailure);
+            applicationState = State_WaitForTelemetry;
+            break;
+        case State_WaitForTelemetry:
+            if (haveTelemetry) {
+                applicationState = State_SendTelemetry;
+                finished = false;
+            }
+            break;
+        case State_SendTelemetry:
+            CalculateAndSendTelemetry();
+            applicationState = State_WaitForTelemetryAck;
+            break;
+        case State_WaitForTelemetryAck:
+            if (telemetryReceivedByCloud) {
+                applicationState = State_PersistTelemetry;
+                finished = false;
+            }
+            break;
+        case State_PersistTelemetry:
+            PersistentStorage_PersistTelemetry(&telemetry);
+            applicationState = State_WaitForFlavor;
+            finished = false;
+            break;
+        case State_WaitForFlavor:
+            if (haveFlavor && flavorAckByCloud) {
+                applicationState = State_WaitForUpdate;
+                Update_NotifyBusinessLogicComplete();
+                DisarmEventLoopTimer(timeoutTimer);
+                finished = false;
+            }
+            break;
+        case State_WaitForUpdate:
+            if (updateCheckComplete) {
+                if (rebootNeededForUpdates) {
+                    applicationState = State_Reboot;
+                } else {
+                    applicationState = State_Sleep;
+                }
+                finished = false;
+            }
+            break;
+        case State_TimedOut:
+            if (updateCheckComplete) {
+                if (rebootNeededForUpdates) {
+                    applicationState = State_Reboot;
+                } else {
+                    applicationState = State_Sleep;
+                }
+            } else {
+                Log_Debug("INFO: Waiting for update check to complete after timeout\n");
+                applicationState = State_WaitForUpdatesAfterTimeout;
+            }
+            finished = false;
+            break;
+        case State_WaitForUpdatesAfterTimeout:
+            if (updateCheckComplete) {
+                applicationState = State_TimedOut;
+                finished = false;
+            }
+            break;
+        case State_Reboot:
+            Log_Debug("INFO: Requesting device reboot.\n");
+            Power_RequestReboot();
+            applicationState =
+                (businessLogicExitCode == ExitCode_Success) ? State_Success : State_Failure;
+            finished = false;
+            break;
+        case State_Sleep:
+            Log_Debug("INFO: Requesting device power-down.\n");
+            Power_RequestPowerdown();
+            applicationState =
+                (businessLogicExitCode == ExitCode_Success) ? State_Success : State_Failure;
+            finished = false;
+            break;
+        case State_Success:
+            Log_Debug("---------- COMPLETED SUCCESSFULLY ------");
+            break;
+        case State_Failure:
+            break;
+        }
+    } while (!finished);
+
+    bool logicComplete = applicationState == State_Success || applicationState == State_Failure;
+    if (logicComplete) {
+        *ec = businessLogicExitCode;
+    }
+
+    return logicComplete;
+}
+
+void BusinessLogic_NotifyCloudConnectionChange(bool connected)
+{
+    Log_Debug("INFO: Cloud connection: %s\n", connected ? "established" : "disconnected");
+    cloudReady = connected;
+}
+
+void BusinessLogic_NotifyCloudFlavorChange(const LedColor *color, const char *flavorName)
+{
+    if (color != NULL) {
+        Log_Debug("INFO: Sending SetLed RGB (%d, %d, %d)\n", color->red ? 1 : 0,
+                  color->green ? 1 : 0, color->blue ? 1 : 0);
+        McuMessaging_SetLed(color, HandleSetLedResponseReceived, HandleMcuMessageFailure);
+        if (flavorName != NULL) {
+            receivedFlavorName = strdup(flavorName);
+        }
+    } else {
+        Log_Debug("INFO: No color change - sending flavor change acknowledgement.\n");
+        Cloud_SendFlavorAcknowledgement(color, flavorName, HandleCloudFlavorAckReceived);
+    }
+}
+
+void BusinessLogic_NotifyUpdateCheckComplete(bool rebootRequired)
+{
+    updateCheckComplete = true;
+    rebootNeededForUpdates = rebootRequired;
+    Log_Debug("INFO: Update complete - reboot %s.\n", rebootRequired ? "required" : "not required");
+}
+
+void BusinessLogic_NotifyUpdateCheckFailed(ExitCode exitCode)
+{
+    Log_Debug("ERROR: Update check failed (exit code %u)\n", exitCode);
+
+    // Flag the update check as complete, but allow the business logic to continue.
+    // Save the ExitCode to return on completion.
+    updateCheckComplete = true;
+    businessLogicExitCode = exitCode;
+}
+
+void BusinessLogic_NotifyFatalError(ExitCode exitCode)
+{
+    Log_Debug("ERROR: Fatal error in business logic (exit code %u)\n", exitCode);
+
+    // At this point, the business logic is effectively terminated, so we skip forward to the
+    // update check, and save the ExitCode to return on completion.
+
+    applicationState = State_WaitForUpdate;
+    businessLogicExitCode = exitCode;
+}
+
+static void Initialize(void)
+{
+    McuMessaging_Init(HandleInitResponseReceived, HandleMcuMessageFailure);
+}
+
+static void CalculateAndSendTelemetry()
+{
+    CloudTelemetry cloudTelemetry;
+    DeviceTelemetry previousTelemetry;
+    bool retrievedTelemetry = PersistentStorage_RetrieveTelemetry(&previousTelemetry);
+
+    if (retrievedTelemetry) {
+        Log_Debug("INFO: Previous telemetry found in persistent storage: \n");
+        LogTelemetry(&previousTelemetry);
+        cloudTelemetry.dispensesSinceLastSync =
+            telemetry.lifetimeTotalDispenses - previousTelemetry.lifetimeTotalDispenses;
+    } else {
+        cloudTelemetry.dispensesSinceLastSync = telemetry.lifetimeTotalDispenses;
+    }
+
+    cloudTelemetry.lifetimeTotalDispenses = telemetry.lifetimeTotalDispenses;
+    cloudTelemetry.remainingDispenses =
+        telemetry.lifetimeTotalStockedDispenses - telemetry.lifetimeTotalDispenses;
+    cloudTelemetry.lowSoda = cloudTelemetry.remainingDispenses <= LowDispenseAlertThreshold;
+
+    Cloud_SendTelemetry(&cloudTelemetry, HandleCloudSendTelemetryAck);
+}
+
+static void HandleMcuMessageFailure(void)
+{
+    // We consider missing responses from the MCU to be fatal errors; a more sophisticated
+    // implementation may retry here.
+    Log_Debug("ERROR: Timed out waiting for MCU response.\n");
+    BusinessLogic_NotifyFatalError(ExitCode_McuMessaging_Timeout);
+}
+
+static void HandleInitResponseReceived(void)
+{
+    Log_Debug("INFO: Init sent to MCU and response received.\n");
+    mcuReady = true;
+}
+
+static void LogTelemetry(const DeviceTelemetry *const telemetry)
+{
+    Log_Debug("INFO: Total dispenses: %u\n", telemetry->lifetimeTotalDispenses);
+    Log_Debug("INFO: Total stocked dispenses: %u\n", telemetry->lifetimeTotalStockedDispenses);
+    Log_Debug("INFO: Capacity: %u\n", telemetry->capacity);
+}
+
+static void HandleTelemetryResponseReceived(const DeviceTelemetry *receivedTelemetry)
+{
+    Log_Debug("INFO: Telemetry received from MCU: \n");
+    LogTelemetry(receivedTelemetry);
+
+    telemetry = *receivedTelemetry;
+    haveTelemetry = true;
+}
+
+static void HandleSetLedResponseReceived(const LedColor *color)
+{
+    Log_Debug("INFO: SetLed sent to device and response received: RGB (%d, %d, %d).\n",
+              color->red ? 1 : 0, color->green ? 1 : 0, color->blue ? 1 : 0);
+    haveFlavor = true;
+
+    if (Cloud_SendFlavorAcknowledgement(color, receivedFlavorName, HandleCloudFlavorAckReceived)) {
+        free(receivedFlavorName);
+        receivedFlavorName = NULL;
+    }
+}
+
+static void HandleCloudSendTelemetryAck(bool success)
+{
+    Log_Debug("INFO: Telemetry received by cloud\n");
+    telemetryReceivedByCloud = success;
+}
+
+static void HandleCloudFlavorAckReceived(bool success)
+{
+    Log_Debug("INFO: Flavor ack received by cloud\n");
+    flavorAckByCloud = success;
+}
+
+static void HandleTimeout(EventLoopTimer *timer)
+{
+    Log_Debug("ERROR: Timed out before business logic could complete.\n");
+
+    if (ConsumeEventLoopTimerEvent(timer) != 0) {
+        Log_Debug("ERROR: Could not consume timeout timer event\n");
+    }
+
+    applicationState = State_TimedOut;
+}

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/business_logic.h

@@ -0,0 +1,74 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#pragma once
+
+#include <stdbool.h>
+
+#include <applibs/eventloop.h>
+
+#include "color.h"
+#include "exitcode.h"
+
+/// <summary>
+///     Initialize the business logic for the application
+/// </summary>
+ExitCode BusinessLogic_Initialize(EventLoop *el);
+
+/// <summary>
+///     Run the business logic for the application - this should be regularly polled until the
+///     return value indicates that the business logic is complete. On completion (successful or
+///     otherwise), <paramref name="ec" /> will be set as appropriate.
+/// </summary>
+/// <param name="ec">
+///     Pointer to an ExitCode; will be set if the business logic is complete, otherwise
+///     the value is undefined.
+/// </param>
+/// <returns>
+///     A boolean indicating whether the business logic is complete (successfully or otherwise).
+/// </returns>
+bool BusinessLogic_Run(ExitCode *ec);
+
+/// <summary>
+///     Notify the business logic that the check for updates has completed.
+/// </summary>
+/// <param name="rebootRequired">
+///     Indicates if a reboot is required following the update check and install.
+/// </param>
+void BusinessLogic_NotifyUpdateCheckComplete(bool rebootRequired);
+
+/// <summary>
+///     Notify the business logic that the check for updates has failed. This will allow the
+///     business logic to complete, if possible; on completion of the business logic, the exit code
+///     will be returned.
+/// </summary>
+/// <param name="businessLogicExitCode">
+///     Exit code specifying the part of the update check that has failed.
+/// </param>
+void BusinessLogic_NotifyUpdateCheckFailed(ExitCode exitCode);
+
+/// <summary>
+///     Notify the business logic that the cloud connectivity state has changed.
+/// </summary>
+/// <param name="connected">
+///     A Boolean indicating whether a connection to the cloud backend is available.
+/// </param>
+void BusinessLogic_NotifyCloudConnectionChange(bool connected);
+
+/// <summary>
+///     Notify the business logic that a request for a flavor change has been received from the
+///     cloud.
+/// </summary>
+/// <param name="color">LED color associated with this flavor.</param>
+/// <param name="flavorName">Flavor name.</param>
+void BusinessLogic_NotifyCloudFlavorChange(const LedColor *color, const char *flavorName);
+
+/// <summary>
+///     Notify the business logic that an unrecoverable error has occurred. This will cause the
+///     business logic to halt, but wait for any pending update check to complete, before shutting
+///     down or rebooting as appropriate.
+/// </summary>
+/// <param name="businessLogicExitCode">
+///     Exit code describing the fatal error.
+/// </param>
+void BusinessLogic_NotifyFatalError(ExitCode exitCode);

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/cloud.c

@@ -0,0 +1,231 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+// This contains an implementation of the cloud.h header specialised for the Azure IoT Central
+// cloud backend
+
+#include <stddef.h>
+#include <applibs/log.h>
+
+#include "azure_iot.h"
+#include "cloud.h"
+#include "exitcode.h"
+#include "telemetry.h"
+
+#include "parson.h"
+
+static const int sendTelemetryMessageIdentifier = 0x01;
+static const int acknowledgeFlavorMessageIdentifier = 0x02;
+
+static bool isConnected = false;
+
+static Cloud_FlavorReceivedCallbackType flavorReceivedCallbackFunc;
+static Cloud_ConnectionStatusCallbackType connectionStatusCallbackFunc;
+static Cloud_SendTelemetryCallbackType sendTelemetryCallbackFunc = NULL;
+static Cloud_FlavorAcknowledgementCallbackType flavorAckCallbackFunc = NULL;
+
+static void HandleConnectionStatusChange(bool connected);
+static void HandleDeviceTwinCallback(const char *content);
+static void HandleDeviceTwinUpdateAckCallback(bool success, void *context);
+static void HandleSendTelemetryCallback(bool success, void *context);
+static void SendDeviceTwinUpdate(const char *flavorName, const char *flavorColor);
+
+ExitCode Cloud_Initialize(EventLoop *el, void *backendConfiguration,
+                          ExitCodeCallbackType failureCallback,
+                          Cloud_ConnectionStatusCallbackType connectionStatusCallback,
+                          Cloud_FlavorReceivedCallbackType flavorReceivedCallback)
+{
+    isConnected = false;
+    connectionStatusCallbackFunc = connectionStatusCallback;
+    flavorReceivedCallbackFunc = flavorReceivedCallback;
+
+    return AzureIoT_Initialize(el, (const char *)backendConfiguration, failureCallback,
+                               HandleConnectionStatusChange, HandleDeviceTwinCallback,
+                               HandleSendTelemetryCallback, HandleDeviceTwinUpdateAckCallback);
+}
+
+void Cloud_Cleanup(void)
+{
+    AzureIoT_Cleanup();
+}
+
+bool Cloud_SendTelemetry(const CloudTelemetry *telemetry,
+                         Cloud_SendTelemetryCallbackType sendTelemetryCallback)
+{
+    if (!isConnected) {
+        return false;
+    }
+
+    JSON_Value *telemetryRootValue = json_value_init_object();
+
+    if (telemetryRootValue == NULL) {
+        return false;
+    }
+
+    sendTelemetryCallbackFunc = sendTelemetryCallback;
+
+    JSON_Object *telemetryRootObject = json_value_get_object(telemetryRootValue);
+
+    json_object_dotset_number(telemetryRootObject, "DispensesSinceLastUpdate",
+                              telemetry->dispensesSinceLastSync);
+    json_object_dotset_number(telemetryRootObject, "RemainingDispenses",
+                              telemetry->remainingDispenses);
+    json_object_dotset_boolean(telemetryRootObject, "LowSoda", telemetry->lowSoda);
+    json_object_dotset_number(telemetryRootObject, "LifetimeTotalDispenses",
+                              telemetry->lifetimeTotalDispenses);
+
+    char *serializedTelemetry = json_serialize_to_string(telemetryRootValue);
+    AzureIoT_SendTelemetry(serializedTelemetry, (void *)&sendTelemetryMessageIdentifier);
+    json_free_serialized_string(serializedTelemetry);
+
+    json_value_free(telemetryRootValue);
+
+    return true;
+}
+
+bool Cloud_SendFlavorAcknowledgement(const LedColor *color, const char *flavorName,
+                                     Cloud_FlavorAcknowledgementCallbackType callback)
+{
+    if (!isConnected) {
+        return false;
+    }
+
+    const char *flavorColorName = NULL;
+    if (color != NULL) {
+
+        if (!Color_TryGetNameForColor(color, &flavorColorName)) {
+            Log_Debug("ERROR: Cannot get name for color (%d, %d, %d)\n.", color->red ? 1 : 0,
+                      color->green ? 1 : 0, color->blue ? 1 : 0);
+            return false;
+        }
+    }
+
+    flavorAckCallbackFunc = callback;
+    SendDeviceTwinUpdate(flavorName, flavorColorName);
+    return true;
+}
+
+static void HandleConnectionStatusChange(bool connected)
+{
+    if (connectionStatusCallbackFunc != NULL) {
+        connectionStatusCallbackFunc(connected);
+    } else {
+        Log_Debug("WARNING: Cloud interface - no connection status callback registered\n");
+    }
+
+    isConnected = connected;
+}
+
+static void HandleSendTelemetryCallback(bool success, void *context)
+{
+    if (context == (void *)&sendTelemetryMessageIdentifier) {
+        if (sendTelemetryCallbackFunc != NULL) {
+            sendTelemetryCallbackFunc(success);
+        } else {
+            Log_Debug(
+                "WARNING: Cloud interface - no callback registered for send telemetry response");
+        }
+    }
+}
+
+static void HandleDeviceTwinCallback(const char *content)
+{
+    JSON_Value *rootProperties = NULL;
+    rootProperties = json_parse_string(content);
+    if (rootProperties == NULL) {
+        Log_Debug("WARNING: Cannot parse the string as JSON content.\n");
+        goto cleanup;
+    }
+
+    JSON_Object *rootObject = json_value_get_object(rootProperties);
+    JSON_Object *desiredProperties = json_object_get_object(rootObject, "desired");
+    if (desiredProperties == NULL) {
+        desiredProperties = rootObject;
+    }
+
+    // The desired properties should have a "NextFlavor" object
+    JSON_Object *nextFlavor = json_object_get_object(desiredProperties, "NextFlavor");
+    if (nextFlavor != NULL) {
+
+        const char *flavorName = json_object_dotget_string(nextFlavor, "Name");
+        const char *flavorColor = json_object_dotget_string(nextFlavor, "Color");
+
+        if (flavorColor != NULL) {
+            if (flavorName == NULL) {
+                Log_Debug("INFO: Requested color: %s (no change in flavor)\n", flavorColor);
+            } else {
+                Log_Debug("INFO: Requested flavor and color: %s (%s)\n", flavorName, flavorColor);
+            }
+
+            LedColor color;
+            if (Color_TryGetColorByName(flavorColor, &color)) {
+                if (flavorReceivedCallbackFunc != NULL) {
+                    flavorReceivedCallbackFunc(&color, flavorName);
+                } else {
+                    Log_Debug("WARNING: Cloud interface - no LED color callback registered\n");
+                }
+            } else {
+                Log_Debug("ERROR: Cloud interface - unknown LED color '%s' in device twin\n",
+                          flavorColor);
+            }
+        } else {
+            if (flavorName == NULL) {
+                Log_Debug("INFO: No change in requested color or name\n");
+            } else {
+                Log_Debug("INFO: Requested flavor: %s (no change in color)\n", flavorName);
+            }
+
+            if (flavorReceivedCallbackFunc != NULL) {
+                flavorReceivedCallbackFunc(NULL, flavorName);
+            } else {
+                Log_Debug("WARNING: Cloud interface - no LED color callback registered\n");
+            }
+        }
+    } else {
+        Log_Debug(
+            "WARNING: Cloud interface - reported device twin did not contain a NextFlavor desired "
+            "property\n");
+    }
+
+cleanup:
+    // Release the allocated memory.
+    if (rootProperties != NULL) {
+        json_value_free(rootProperties);
+    }
+}
+
+static void SendDeviceTwinUpdate(const char *flavorName, const char *flavorColor)
+{
+    JSON_Value *twinStateValue = NULL;
+    twinStateValue = json_value_init_object();
+    JSON_Object *twinStateRoot = json_value_get_object(twinStateValue);
+    if (flavorName != NULL) {
+        json_object_dotset_string(twinStateRoot, "NextFlavor.Name", flavorName);
+    }
+    if (flavorColor != NULL) {
+        json_object_dotset_string(twinStateRoot, "NextFlavor.Color", flavorColor);
+    }
+
+    char *serializedTwinState = json_serialize_to_string(twinStateValue);
+    AzureIoT_DeviceTwinReportState(serializedTwinState,
+                                   (void *)&acknowledgeFlavorMessageIdentifier);
+    json_free_serialized_string(serializedTwinState);
+
+    if (twinStateValue != NULL) {
+        json_value_free(twinStateValue);
+    }
+}
+
+static void HandleDeviceTwinUpdateAckCallback(bool success, void *context)
+{
+
+    if (context == &acknowledgeFlavorMessageIdentifier) {
+        if (flavorAckCallbackFunc != NULL) {
+            flavorAckCallbackFunc(success);
+        } else {
+            Log_Debug("WARNING: Cloud - no flavour ack call back handler registered\n");
+        }
+    } else {
+        Log_Debug("WARNING: Cloud - unexpected device twin ack received\n");
+    }
+}

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/cloud.h

@@ -0,0 +1,79 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#pragma once
+
+// This header defines a backend-agnostic interface for publishing telemetry to and receiving
+// state from a cloud service. The implementation of this interface will be specific for a
+// particular cloud service (for the purposes of this reference solution, this is Azure IoT Central)
+
+#include <applibs/eventloop.h>
+
+#include "color.h"
+#include "exitcode.h"
+#include "telemetry.h"
+
+typedef void (*Cloud_FlavorReceivedCallbackType)(const LedColor *color, const char *flavorName);
+typedef void (*Cloud_SendTelemetryCallbackType)(bool success);
+typedef void (*Cloud_FlavorAcknowledgementCallbackType)(bool success);
+typedef void (*Cloud_ConnectionStatusCallbackType)(bool connected);
+
+/// <summary>
+///     Initialise the cloud connection.
+/// </summary>
+/// <param name="el">The application EventLoop, for registering timers and events.</param>
+/// <param name="backendConfiguration">Backend-specific data required for initialization.</param>
+/// <param name="failureCallback">A function to be called in the event of failures.</param>
+/// <param name="connectionStatusCallback">
+///     A <see cref="Cloud_ConnectionStatusCallbackType" /> to be called on connection status
+///     change.
+/// </param>
+/// <param name="flavorReceivedCallback">
+///     A <see cref="Cloud_FlavorReceivedCallbackType" /> to be called on receipt of a new flavor
+///     from the cloud.
+///</param>
+/// <returns>An <see cref="ExitCode" /> indicating success or failure.</returns>
+ExitCode Cloud_Initialize(EventLoop *el, void *backendConfiguration,
+                          ExitCodeCallbackType failureCallback,
+                          Cloud_ConnectionStatusCallbackType connectionStatusCallback,
+                          Cloud_FlavorReceivedCallbackType flavorReceivedCallback);
+
+/// <summary>
+///     Close and cleanup the cloud connection.
+/// </summary>
+void Cloud_Cleanup(void);
+
+/// <summary>
+///     Queue telemetry for sending to the cloud; returns a Boolean indicating whether the telemetry
+///     could be queued for sending. If the telemetry was successfully queued,
+///     <paramref name="callback" /> will be invoked asynchronously to indicate successful receipt
+///     (or otherwise) by the cloud.
+/// </summary>
+/// <param name="telemetry">Pointer to telemetry to send.</param>
+/// <param name="callback">
+///     A <see cref="Cloud_SendTelemetryCallbackType" /> to be invoked, to indicate whether the
+///     telemetry was successfully received by the cloud backend.
+/// </param>
+/// <returns>
+///     A Boolean indicating whether the telemetry was successfuly queued for sending.
+/// </returns>
+bool Cloud_SendTelemetry(const CloudTelemetry *telemetry, Cloud_SendTelemetryCallbackType callback);
+
+/// <summary>
+///     Queue a message to the cloud acknowledging the new flavor sent to the device. Should be
+///     called in response to <see cref="Cloud_FlavorReceivedCallbackType" />. Returns a Boolean
+///     indicating whether the message could be queued. If the message was successfully queued,
+///     <paramref name="callback" /> will be invoked asynchronously to indicate successful receipt
+///     (or failure) by the cloud.
+/// </summary>
+/// <param name="color">LED color being acknowledged (or NULL if not specified)</param>
+/// <param name="flavorName">Name of the flavor being acknowledge (or NULL if not specified)</param>
+/// <param name="callback">
+///     A <see cref="Cloud_AcknowledgementCallbackType" /> to be invoked, to indicate whether the
+///     message was successfully receieved by the cloud backend.
+/// </param>
+/// <returns>
+///     A Boolean indicating whether the message was successfully queued for sending.
+/// </returns>
+bool Cloud_SendFlavorAcknowledgement(const LedColor *color, const char *flavorName,
+                                     Cloud_FlavorAcknowledgementCallbackType callback);

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/color.c

@@ -0,0 +1,62 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#include <stdlib.h>
+#include <string.h>
+
+#include "color.h"
+
+typedef struct NamedColor {
+    const char *name;
+    LedColor color;
+} NamedColor;
+
+/// <summary>
+/// Defines the mappings of color names to LedColor values. Note that the names must match the
+/// values defined for the "Color" value of "NextFlavour" property in the Azure IoT Central app.
+/// </summary>
+static NamedColor availableColors[] = {
+    {.name = "black", .color = {.red = false, .green = false, .blue = false}},
+    {.name = "red", .color = {.red = true, .green = false, .blue = false}},
+    {.name = "green", .color = {.red = false, .green = true, .blue = false}},
+    {.name = "blue", .color = {.red = false, .green = false, .blue = true}},
+    {.name = "yellow", .color = {.red = true, .green = true, .blue = false}},
+    {.name = "cyan", .color = {.red = false, .green = true, .blue = true}},
+    {.name = "magenta", .color = {.red = true, .green = false, .blue = true}},
+    {.name = "white", .color = {.red = true, .green = true, .blue = true}}};
+
+static const size_t numColors = sizeof(availableColors) / sizeof(NamedColor);
+
+bool Color_TryGetColorByName(const char *colorName, LedColor *color)
+{
+    if (colorName == NULL) {
+        return false;
+    }
+
+    for (int i = 0; i < numColors; i++) {
+        if (strcmp(availableColors[i].name, colorName) == 0) {
+            *color = availableColors[i].color;
+            return true;
+        }
+    }
+
+    return false;
+}
+
+bool Color_TryGetNameForColor(const LedColor *color, const char **colorName)
+{
+    if (color == NULL) {
+        return false;
+    }
+
+    for (int i = 0; i < numColors; i++) {
+        if (availableColors[i].color.red == color->red &&
+            availableColors[i].color.green == color->green &&
+            availableColors[i].color.blue == color->blue) {
+            *colorName = availableColors[i].name;
+            return true;
+        }
+    }
+
+    return false;
+}

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/color.h

@@ -0,0 +1,35 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#pragma once
+
+#include <stdbool.h>
+
+/// <summary>
+///     Defines a struct for specifying the color of an RGB LED.
+/// </summary>
+typedef struct LedColor {
+    bool red;
+    bool green;
+    bool blue;
+} LedColor;
+
+/// <summary>
+///     Try to get the LedColor by a particular color name.
+/// </summary>
+/// <param name="colorName">Name of the color.</param>
+/// <param name="color">Pointer to receive the LedColor.</param>
+/// <returns>
+///     true if the color is known (and sets <paramref name="color"/>); false otherwise.
+/// </returns>
+bool Color_TryGetColorByName(const char *colorName, LedColor *color);
+
+/// <summary>
+///     Try to get the name for a particular LedColor
+/// </summary>
+/// <param name="color">LedColor</param>
+/// <param name="colorName">Pointer to receive the name</param>
+/// <returns>
+///     true if the color is known (and sets <paramref name="colorName"/>); false otherwise.
+/// </returns>
+bool Color_TryGetNameForColor(const LedColor *color, const char **colorName);

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/debug_uart.c

@@ -0,0 +1,59 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#define _GNU_SOURCE
+#include <stdio.h>
+#include <stdarg.h>
+#include <unistd.h>
+#include <stdlib.h>
+
+#include "applibs_versions.h"
+#include <applibs/uart.h>
+
+#include "hw/sample_appliance.h"
+
+static int uartFd = -1;
+
+void DebugUart_Init(void)
+{
+    UART_Config uartConfig;
+
+    UART_InitConfig(&uartConfig);
+    uartConfig.baudRate = 115200;
+    uartConfig.dataBits = UART_DataBits_Eight;
+    uartConfig.stopBits = UART_StopBits_One;
+    uartConfig.parity = UART_Parity_None;
+    uartConfig.flowControl = UART_FlowControl_None;
+
+    uartFd = UART_Open(SAMPLE_DEBUG_UART, &uartConfig);
+}
+
+void DebugUart_Cleanup(void)
+{
+    if (uartFd != -1) {
+        close(uartFd);
+    }
+}
+
+void DebugUart_LogVarArgs(const char *fmt, va_list args)
+{
+    if (uartFd == -1) {
+        return;
+    }
+
+    char *string;
+    int length = vasprintf(&string, fmt, args);
+
+    if (length != -1) {
+        write(uartFd, string, (size_t)length);
+        free(string);
+    }
+}
+
+void DebugUart_Log(const char *fmt, ...)
+{
+    va_list args;
+    va_start(args, fmt);
+    DebugUart_LogVarArgs(fmt, args);
+    va_end(args);
+}

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/debug_uart.h

@@ -0,0 +1,29 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#pragma once
+
+#include <stdarg.h>
+
+/// <summary>
+/// Initialize the debug UART
+/// </summary>
+void DebugUart_Init(void);
+
+/// <summary>
+/// Cleanup the debug UART
+/// </summary>
+void DebugUart_Cleanup(void);
+
+/// <summary>
+/// Write a printf-formatted string to the debug UART
+/// </summary>
+/// <param name="fmt">The string to log, with optional argument parameters.</param>
+void DebugUart_Log(const char *fmt, ...) __attribute__((format(printf, 1, 2)));
+
+/// <summary>
+/// Write a printf-formatted string to the debug UART (varargs form)
+/// </summary>
+/// <param name="fmt">The string to log.</param>
+/// <param name="args">A varargs parameter list.</param>
+void DebugUart_LogVarArgs(const char *fmt, va_list args);

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/eventloop_timer_utilities.c

@@ -0,0 +1,139 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#include <stdbool.h>
+#include <stdlib.h>
+
+#include <errno.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/timerfd.h>
+
+#include <applibs/log.h>
+#include <applibs/eventloop.h>
+
+#include "eventloop_timer_utilities.h"
+
+static int SetTimerPeriod(int timerFd, const struct timespec *initial,
+                          const struct timespec *repeat);
+
+static int SetTimerPeriod(int timerFd, const struct timespec *initial,
+                          const struct timespec *repeat)
+{
+    static const struct timespec nullTimeSpec = {.tv_sec = 0, .tv_nsec = 0};
+    struct itimerspec newValue = {.it_value = initial ? *initial : nullTimeSpec,
+                                  .it_interval = repeat ? *repeat : nullTimeSpec};
+
+    if (timerfd_settime(timerFd, /* flags */ 0, &newValue, /* old_value */ NULL) == -1) {
+        Log_Debug("ERROR: Could not set timer period: %s (%d).\n", strerror(errno), errno);
+        return -1;
+    }
+
+    return 0;
+}
+
+struct EventLoopTimer {
+    EventLoop *eventLoop;
+    EventLoopTimerHandler handler;
+    int fd;
+    EventRegistration *registration;
+};
+
+// This satisfies the EventLoopIoCallback signature.
+static void TimerCallback(EventLoop *el, int fd, EventLoop_IoEvents events, void *context)
+{
+    EventLoopTimer *timer = (EventLoopTimer *)context;
+
+    timer->handler(timer);
+}
+
+EventLoopTimer *CreateEventLoopPeriodicTimer(EventLoop *eventLoop, EventLoopTimerHandler handler,
+                                             const struct timespec *period)
+{
+    if (handler == NULL) {
+        errno = EINVAL;
+        return NULL;
+    }
+
+    EventLoopTimer *timer = malloc(sizeof(EventLoopTimer));
+    if (timer == NULL) {
+        return NULL;
+    }
+
+    timer->eventLoop = eventLoop;
+    timer->handler = handler;
+
+    // Initialize to unused values in case have to clean up partially initialized object.
+    timer->fd = -1;
+    timer->registration = NULL;
+
+    timer->fd = timerfd_create(CLOCK_MONOTONIC, TFD_NONBLOCK);
+    if (timer->fd == -1) {
+        Log_Debug("ERROR: Unable to create timer: %s (%d).\n", strerror(errno), errno);
+        goto failed;
+    }
+
+    if (SetTimerPeriod(timer->fd, /* initial */ period, /* repeat */ period) == -1) {
+        goto failed;
+    }
+
+    timer->registration =
+        EventLoop_RegisterIo(eventLoop, timer->fd, EventLoop_Input, TimerCallback, timer);
+    if (timer->registration == NULL) {
+        Log_Debug("ERROR: Unable to register timer event: %s (%d).\n", strerror(errno), errno);
+        goto failed;
+    }
+
+    return timer;
+
+failed:
+    DisposeEventLoopTimer(timer);
+    return NULL;
+}
+
+EventLoopTimer *CreateEventLoopDisarmedTimer(EventLoop *eventLoop, EventLoopTimerHandler handler)
+{
+    return CreateEventLoopPeriodicTimer(eventLoop, handler, NULL);
+}
+
+void DisposeEventLoopTimer(EventLoopTimer *timer)
+{
+    if (timer == NULL) {
+        return;
+    }
+
+    EventLoop_UnregisterIo(timer->eventLoop, timer->registration);
+
+    if (timer->fd != -1) {
+        close(timer->fd);
+    }
+
+    free(timer);
+}
+
+int ConsumeEventLoopTimerEvent(EventLoopTimer *timer)
+{
+    uint64_t timerData = 0;
+
+    if (read(timer->fd, &timerData, sizeof(timerData)) == -1) {
+        Log_Debug("ERROR: Could not read timerfd %s (%d).\n", strerror(errno), errno);
+        return -1;
+    }
+
+    return 0;
+}
+
+int SetEventLoopTimerPeriod(EventLoopTimer *timer, const struct timespec *period)
+{
+    return SetTimerPeriod(timer->fd, /* initial */ period, /* repeat */ period);
+}
+
+int SetEventLoopTimerOneShot(EventLoopTimer *timer, const struct timespec *delay)
+{
+    return SetTimerPeriod(timer->fd, /* initial */ delay, /* repeat */ NULL);
+}
+
+int DisarmEventLoopTimer(EventLoopTimer *timer)
+{
+    return SetTimerPeriod(timer->fd, /* initial */ NULL, /* repeat */ NULL);
+}

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/eventloop_timer_utilities.h

@@ -0,0 +1,102 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#pragma once
+#include <time.h>
+
+#include <unistd.h>
+
+#include <applibs/eventloop.h>
+
+/// <summary>
+/// Opaque handle. Obtain via <see cref="CreateEventLoopPeriodicTimer" />
+/// or <see cref="CreateEventLoopDisarmedTimer" /> and dispose of via
+/// <see cref="DisposeEventLoopTimer" />.
+/// </summary>
+typedef struct EventLoopTimer EventLoopTimer;
+
+/// <summary>
+/// Applications implement a function with this signature to be
+/// notified when a timer expires.
+/// </summary>
+/// <param name="timer">The timer which has expired.</param>
+/// <seealso cref="CreateEventLoopPeriodicTimer" />
+/// <seealso cref="CreateEventLoopDisarmedTimer" />
+typedef void (*EventLoopTimerHandler)(EventLoopTimer *timer);
+
+/// <summary>
+/// Create a periodic timer which is invoked on the event loop. The timer
+/// will begin firing immediately.
+/// </summary>
+/// <param name="eventLoop">Event loop to which the timer will be added.</param>
+/// <param name="handler">Callback to invoke when the timer expires.</param>
+/// <param name="period">Timer period.</param>
+/// <returns>On success, pointer to new EventLoopTimer, which should be disposed of
+/// with <see cref="DisposeEventLoopTimer" />. On failure, returns NULL, with more
+/// information available in errno.</returns>.
+EventLoopTimer *CreateEventLoopPeriodicTimer(EventLoop *eventLoop, EventLoopTimerHandler handler,
+                                             const struct timespec *period);
+
+/// <summary>
+/// Create a disarmed timer. After the timer has been allocated, call
+/// <see cref="SetEventLoopTimerPeriod" /> or <see cref="SetEventLoopTimerOneShot" />
+/// to arm the timer.
+/// </summary>
+/// <param name="eventLoop">Event loop to which the timer will be added.</param>
+/// <param name="handler">Callback to invoke when the timer expires.</param>
+/// <returns>On success, pointer to new EventLoopTimer, which should be disposed of
+/// with <see cref="DisposeEventLoopTimer" />. On failure, returns NULL, with more
+/// information available in errno.</returns>.
+EventLoopTimer *CreateEventLoopDisarmedTimer(EventLoop *eventLoop, EventLoopTimerHandler handler);
+
+/// <summary>
+/// Dispose of a timer which was allocated with <see cref="CreateEventLoopPeriodicTimer" />
+/// or <see cref="CreateEventLoopDisarmedTimer" />.
+/// It is safe to call this function with a NULL pointer.
+/// </summary>
+/// <param name="timer">Successfully allocated event loop timer, or NULL.</param>
+void DisposeEventLoopTimer(EventLoopTimer *timer);
+
+/// <summary>
+/// The timer callback should call this function to consume the timer event.
+/// </summary>
+/// <param name="timer">Successfully allocated timer.</param>
+/// <returns>0 on success, -1 on failure, in which case errno contains more information.</returns>
+int ConsumeEventLoopTimerEvent(EventLoopTimer *timer);
+
+/// <summary>
+/// Change the timer's period. This function should only be called to change an existing
+/// timer's period. It does not have to be called to set the initial period - that is
+/// handled by <see cref="CreateEventLoopPeriodicTimer" />.
+/// </summary>
+/// <param name="timer">Timer previously allocated with <see cref="CreateEventLoopPeriodicTimer" />
+/// or <see cref="CreateEventLoopDisarmedTimer" />.</param>
+/// <param name="period">New timer period.</param>
+/// <returns>0 on success, -1 on failure, in which case errno contains more information.</returns>
+/// <seealso cref="SetEventLoopTimerOneShot" />
+/// <seealso cref="DisarmEventLoopTimer" />
+int SetEventLoopTimerPeriod(EventLoopTimer *timer, const struct timespec *period);
+
+/// <summary>
+/// Set the timer to expire one after a specified period.
+/// </summary>
+/// <returns>0 on succcess, -1 on failure, in which case errno contains more information.</returns>
+/// <param name="timer">Timer previously allocated with <see cref="CreateEventLoopPeriodicTimer" />
+/// or <see cref="CreateEventLoopDisarmedTimer" />.</param>
+/// <param name="delay">Period to wait before timer expires.</param>
+/// <returns>0 on success, -1 on failure, in which case errno contains more
+/// information.</returns>
+/// <seealso cref="SetEventLoopTimerPeriod" />
+/// <seealso cref="DisarmEventLoopTimer" />
+int SetEventLoopTimerOneShot(EventLoopTimer *timer, const struct timespec *delay);
+
+/// <summary>
+/// Disarm an existing event loop timer.
+/// </summary>
+/// <param name="timer">Timer previously allocated with <see cref="CreateEventLoopPeriodicTimer" />
+/// or <see cref="CreateEventLoopDisarmedTimer" />.</param>
+/// <returns>0 on success; -1 on failure, in which case errno contains more
+/// information.</returns>
+/// <seealso cref="SetEventLoopTimerOneShot" />
+/// <seealso cref="SetEventLoopTimerPeriod" />
+int DisarmEventLoopTimer(EventLoopTimer *timer);

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/exitcode.h

@@ -0,0 +1,50 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#pragma once
+
+/// <summary>
+///     Termination codes for this application. These are used for the
+///     application exit code. They must all be between zero and 255,
+///     where zero is reserved for successful termination.
+/// </summary>
+typedef enum {
+    ExitCode_Success = 0,
+
+    ExitCode_TermHandler_SigTerm = 1,
+
+    ExitCode_Init_EventLoop,
+    ExitCode_Init_CopyScopeId,
+    ExitCode_Validation_ScopeId,
+
+    ExitCode_BusinessLogic_TimeoutTimerCreate,
+    ExitCode_BusinessLogic_SetTimeoutTimer,
+
+    ExitCode_Uart_Init_OpenFail,
+    ExitCode_Uart_Init_EventRegisterFail,
+
+    ExitCode_MsgProtoInit_Timer,
+
+    ExitCode_Main_EventLoopFail,
+
+    ExitCode_McuMessaging_Timeout,
+
+    ExitCode_AzureIoT_Init_InvalidScopeId,
+    ExitCode_AzureTimer_Consume,
+    ExitCode_InterfaceConnectionStatus_Failed,
+    ExitCode_Init_AzureTimer,
+
+    ExitCode_Cloud_Init_DeviceTwinCallback,
+
+    ExitCode_Update_Init_NoUpdateEvent,
+    ExitCode_Update_Init_CreateWaitForUpdatesCheckTimer,
+    ExitCode_Update_Init_SetWaitForUpdatesCheckTimer,
+    ExitCode_Update_Init_CreateWaitForUpdatesDownloadTimer,
+    ExitCode_Update_UpdatesStarted_SetWaitForUpdatesDownloadTimer,
+
+    ExitCode_Update_UpdateCallback_GetUpdateData,
+    ExitCode_Update_UpdateCallback_DeferEvent,
+    ExitCode_Update_UpdateCallback_UnexpectedStatus
+} ExitCode;
+
+typedef void (*ExitCodeCallbackType)(ExitCode);

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/launch.vs.json

@@ -0,0 +1,21 @@
+{
+  "version": "0.2.1",
+  "defaults": {},
+  "configurations": [
+    {
+      "type": "azurespheredbg",
+      "name": "GDB Debugger (HLCore)",
+      "project": "CMakeLists.txt",
+      "inheritEnvironments": [
+        "AzureSphere"
+      ],
+      "customLauncher": "AzureSphereLaunchOptions",
+      "workingDirectory": "${workspaceRoot}",
+      "applicationPath": "${debugInfo.target}",
+      "imagePath": "${debugInfo.targetImage}",
+      "targetCore": "HLCore",
+      "targetApiSet": "${env.AzureSphereTargetApiSet}",
+      "partnerComponents": []
+    }
+  ]
+}

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/logging.c

@@ -0,0 +1,29 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#include <applibs/log.h>
+
+#include <stdarg.h>
+
+#include "debug_uart.h"
+
+/// <summary>
+///     Overrides the AppLibs <see cref="Log_Debug" /> to also write to the debug UART
+/// </summary>
+/// <param name="fmt">String to write to the log and optional parameters</param>
+/// <returns>
+///     0 for success, or -1 on failure (with errno set to indicate the error, as per
+///     <see cref="Log_Debug" />)
+/// </returns>
+int Log_Debug(const char *fmt, ...)
+{
+    va_list args;
+    va_start(args, fmt);
+
+    int result = Log_DebugVarArgs(fmt, args);
+    DebugUart_LogVarArgs(fmt, args);
+
+    va_end(args);
+
+    return result;
+}

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/main.c

@@ -0,0 +1,224 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#include <errno.h>
+#include <getopt.h>
+#include <signal.h>
+#include <stdbool.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+#include <unistd.h>
+
+// applibs_versions.h defines the API struct versions to use for applibs APIs.
+#include "applibs_versions.h"
+#include <applibs/log.h>
+#include <applibs/eventloop.h>
+
+// The following #include imports a "sample appliance" definition. This app comes with multiple
+// implementations of the sample appliance, each in a separate directory, which allow the code to
+// run on different hardware.
+//
+// By default, this app targets hardware that follows the MT3620 Reference Development Board (RDB)
+// specification, such as the MT3620 Dev Kit from Seeed Studio.
+//
+// To target different hardware, you'll need to update CMakeLists.txt. For example, to target the
+// Avnet MT3620 Starter Kit, change the TARGET_DIRECTORY argument in the call to
+// azsphere_target_hardware_definition to "HardwareDefinitions/avnet_mt3620_sk".
+//
+// See https://aka.ms/AzureSphereHardwareDefinitions for more details.
+#include <hw/sample_appliance.h>
+
+#include "business_logic.h"
+#include "cloud.h"
+#include "debug_uart.h"
+#include "eventloop_timer_utilities.h"
+#include "exitcode.h"
+#include "message_protocol.h"
+#include "mcu_messaging.h"
+#include "uart_transport.h"
+#include "update.h"
+
+static EventLoop *eventLoop = NULL;
+static const char *scopeId = NULL;
+
+// Termination state
+static volatile sig_atomic_t businessLogicExitCode = ExitCode_Success;
+
+static void TerminationHandler(int signalNumber);
+static ExitCode InitPeripheralsAndHandlers(void);
+static void ClosePeripheralsAndHandlers(void);
+
+static void ParseCommandLineArguments(int argc, char *argv[]);
+static ExitCode ValidateUserConfiguration(void);
+
+/// <summary>
+///     Signal handler for termination requests. This handler must be async-signal-safe.
+/// </summary>
+static void TerminationHandler(int signalNumber)
+{
+    // Don't use Log_Debug here, as it is not guaranteed to be async-signal-safe.
+
+    // We will receive a SIGTERM if we are shutting down because of a request shutdown or reboot
+    // but we also want to preserve any failure exit code from the business logic.
+    if (businessLogicExitCode == ExitCode_Success) {
+        businessLogicExitCode = ExitCode_TermHandler_SigTerm;
+    }
+}
+
+/// <summary>
+///     Set up SIGTERM termination handler, initialize peripherals, and set up event handlers.
+/// </summary>
+/// <returns>
+///     ExitCode_Success if all resources were allocated successfully; otherwise another
+///     ExitCode value which indicates the specific failure.
+/// </returns>
+static ExitCode InitPeripheralsAndHandlers(void)
+{
+    DebugUart_Init();
+
+    struct sigaction action;
+    memset(&action, 0, sizeof(struct sigaction));
+    action.sa_handler = TerminationHandler;
+    sigaction(SIGTERM, &action, NULL);
+
+    ExitCode ec = ValidateUserConfiguration();
+    if (ec != ExitCode_Success) {
+        return ec;
+    }
+
+    eventLoop = EventLoop_Create();
+    if (eventLoop == NULL) {
+        Log_Debug("Could not create event loop.\n");
+        return ExitCode_Init_EventLoop;
+    }
+
+    // Initialize message protocol, UART transport and cloud connection
+    ec = MessageProtocol_Initialize(eventLoop, UartTransport_Read, UartTransport_Send);
+    if (ec != ExitCode_Success) {
+        return ec;
+    }
+
+    ec = UartTransport_Initialize(eventLoop, SAMPLE_STM32_UART,
+                                  MessageProtocol_HandleReceivedMessage);
+    if (ec != ExitCode_Success) {
+        return ec;
+    }
+
+    ec = Cloud_Initialize(eventLoop, (void *)scopeId, BusinessLogic_NotifyFatalError,
+                          BusinessLogic_NotifyCloudConnectionChange,
+                          BusinessLogic_NotifyCloudFlavorChange);
+    if (ec != ExitCode_Success) {
+        return ec;
+    }
+
+    ec = Update_Initialize(eventLoop, BusinessLogic_NotifyUpdateCheckComplete,
+                           BusinessLogic_NotifyUpdateCheckFailed);
+    if (ec != ExitCode_Success) {
+        return ec;
+    }
+
+    ec = BusinessLogic_Initialize(eventLoop);
+    if (ec != ExitCode_Success) {
+        return ec;
+    }
+
+    McuMessaging_Initialize();
+
+    return ExitCode_Success;
+}
+
+/// <summary>
+///     Close peripherals and handlers.
+/// </summary>
+static void ClosePeripheralsAndHandlers(void)
+{
+    MessageProtocol_Cleanup();
+    UartTransport_Cleanup();
+    Cloud_Cleanup();
+    DebugUart_Cleanup();
+
+    EventLoop_Close(eventLoop);
+}
+
+/// <summary>
+///     Parse the command-line arguments given in the application manifest.
+/// </summary>
+static void ParseCommandLineArguments(int argc, char *argv[])
+{
+    int option = 0;
+    static const struct option cmdLineOptions[] = {
+        {name : "ScopeID", has_arg : required_argument, flag : NULL, val : 's'},
+        {name : NULL, has_arg : 0, flag : NULL, val : 0}};
+
+    // Loop over all of the options
+    while ((option = getopt_long(argc, argv, "s:", cmdLineOptions, NULL)) != -1) {
+        // Check if arguments are missing. Every option requires an argument.
+        if (optarg != NULL && optarg[0] == '-') {
+            Log_Debug("Warning: Option %c requires an argument\n", option);
+            continue;
+        }
+        switch (option) {
+        case 's':
+            scopeId = optarg;
+            break;
+        default:
+            // Unknown options are ignored.
+            break;
+        }
+    }
+}
+
+/// <summary>
+///     Validates that the scope ID was set correctly in the app manifest.
+/// </summary>
+/// <returns>
+///     ExitCode_Success if the scope ID was set correctly; otherwise another ExitCode value
+///     which indicates the specific failure.
+/// </returns>
+static ExitCode ValidateUserConfiguration(void)
+{
+    ExitCode ec = ExitCode_Success;
+
+    if (scopeId == NULL || strcmp(scopeId, "<scopeid>") == 0) {
+        ec = ExitCode_Validation_ScopeId;
+        Log_Debug(
+            "ERROR: Missing scope ID. Please specify the scope ID for your Azure IoT Central app "
+            "in the app_manifest.json:\n"
+            "    CmdArgs: [ \"--ScopeID\", \"<scopeid>\" ]\n");
+    }
+
+    Log_Debug("INFO: Using Azure IoT scope ID: %s\n", scopeId);
+    return ec;
+}
+
+/// <summary>
+///     Main entry point for this application.
+/// </summary>
+int main(int argc, char *argv[])
+{
+    Log_Debug("ExternalMcuLowPower DeviceToCloud application starting.\n");
+
+    ParseCommandLineArguments(argc, argv);
+
+    businessLogicExitCode = InitPeripheralsAndHandlers();
+
+    // Use event loop to wait for events and trigger handlers, until an error or SIGTERM happens
+    while (businessLogicExitCode == ExitCode_Success) {
+        EventLoop_Run_Result result = EventLoop_Run(eventLoop, -1, true);
+        // Continue if interrupted by signal, e.g. due to breakpoint being set.
+        if (result == EventLoop_Run_Failed && errno != EINTR) {
+            businessLogicExitCode = ExitCode_Main_EventLoopFail;
+        }
+
+        ExitCode businessLogicExitCode;
+        if (BusinessLogic_Run(&businessLogicExitCode)) {
+            businessLogicExitCode = businessLogicExitCode;
+            break;
+        }
+    }
+
+    ClosePeripheralsAndHandlers();
+    Log_Debug("Application exiting.\n");
+    return businessLogicExitCode;
+}

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/mcu_messaging.c

@@ -0,0 +1,177 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#include <string.h>
+
+#include <applibs/eventloop.h>
+#include <applibs/log.h>
+
+#include "eventloop_timer_utilities.h"
+#include "message_protocol.h"
+#include "messages.h"
+
+#include "mcu_messaging.h"
+
+static McuMessagingInitCallbackType initCallback = NULL;
+static McuMessagingRequestTelemetryCallbackType requestTelemetryCallback = NULL;
+static McuMessagingSetLedCallbackType setLedCallback = NULL;
+static McuMessagingFailureCallbackType failCallback = NULL;
+
+void McuMessaging_Initialize(void) {}
+
+static bool CheckResponse(const char *responseName, MessageProtocol_CategoryId expectedCategory,
+                          MessageProtocol_CategoryId actualCategory,
+                          MessageProtocol_RequestId expectedRequest,
+                          MessageProtocol_RequestId actualRequest, size_t expectedSize,
+                          size_t actualSize, bool timedOut)
+{
+    bool failed = false;
+
+    if (timedOut) {
+        Log_Debug("ERROR: %s response - timed out waiting for response\n", responseName);
+        failed = true;
+    } else {
+        if (actualCategory != expectedCategory) {
+            Log_Debug("ERROR: %s response - invalid category ID '%u' (expected '%u')", responseName,
+                      expectedCategory, actualCategory);
+            failed = true;
+        }
+
+        if (actualRequest != expectedRequest) {
+            Log_Debug("ERROR: %s response - invalid request ID '%u' (expected '%u')", responseName,
+                      expectedRequest, actualRequest);
+            failed = true;
+        }
+
+        if (expectedSize != actualSize) {
+            Log_Debug("ERROR: %s response - invalid body size %u bytes (expected %u bytes)",
+                      responseName, expectedSize, actualSize);
+            failed = true;
+        }
+    }
+
+    return failed;
+}
+
+static void InitResponseHandler(MessageProtocol_CategoryId categoryId,
+                                MessageProtocol_RequestId requestId, const uint8_t *data,
+                                size_t dataSize, MessageProtocol_ResponseResult result,
+                                bool timedOut)
+{
+    bool failed = CheckResponse("Init", MessageProtocol_McuToCloud_CategoryId, categoryId,
+                                MessageProtocol_McuToCloud_Init, requestId, 0, dataSize, timedOut);
+
+    if (failed) {
+        if (failCallback != NULL) {
+            failCallback();
+        } else {
+            Log_Debug("ERROR: No failure handler registered.");
+        }
+    } else {
+        if (initCallback != NULL) {
+            initCallback();
+        } else {
+            Log_Debug("WARNING: Init response - no handler registered.");
+        }
+    }
+}
+
+void McuMessaging_Init(McuMessagingInitCallbackType successCallback,
+                       McuMessagingFailureCallbackType failureCallback)
+{
+    initCallback = successCallback;
+    failCallback = failureCallback;
+
+    MessageProtocol_SendRequest(MessageProtocol_McuToCloud_CategoryId,
+                                MessageProtocol_McuToCloud_Init, NULL, 0, InitResponseHandler);
+}
+
+static void TelemetryResponseHandler(MessageProtocol_CategoryId categoryId,
+                                     MessageProtocol_RequestId requestId, const uint8_t *data,
+                                     size_t dataSize, MessageProtocol_ResponseResult result,
+                                     bool timedOut)
+{
+    bool failed =
+        CheckResponse("RequestTelemtry", MessageProtocol_McuToCloud_CategoryId, categoryId,
+                      MessageProtocol_McuToCloud_RequestTelemetry, requestId,
+                      sizeof(MessageProtocol_McuToCloud_TelemetryStruct), dataSize, timedOut);
+
+    if (failed) {
+        if (failCallback != NULL) {
+            failCallback();
+        } else {
+            Log_Debug("ERROR: No failure handler registered.");
+        }
+    } else {
+        if (requestTelemetryCallback != NULL) {
+            MessageProtocol_McuToCloud_TelemetryStruct *receivedTelemetry =
+                (MessageProtocol_McuToCloud_TelemetryStruct *)data;
+
+            DeviceTelemetry telemetry = {
+                .lifetimeTotalDispenses = receivedTelemetry->lifetimeTotalDispenses,
+                .lifetimeTotalStockedDispenses = receivedTelemetry->lifetimeTotalStockedDispenses,
+                .capacity = receivedTelemetry->capacity};
+
+            requestTelemetryCallback(&telemetry);
+
+        } else {
+            Log_Debug("WARNING: RequestTelemetry response - no handler registered.");
+        }
+    }
+}
+
+void McuMessaging_RequestTelemetry(McuMessagingRequestTelemetryCallbackType successCallback,
+                                   McuMessagingFailureCallbackType failureCallback)
+{
+    requestTelemetryCallback = successCallback;
+    failCallback = failureCallback;
+
+    MessageProtocol_SendRequest(MessageProtocol_McuToCloud_CategoryId,
+                                MessageProtocol_McuToCloud_RequestTelemetry, NULL, 0,
+                                TelemetryResponseHandler);
+}
+
+static void SetLedResponseHandler(MessageProtocol_CategoryId categoryId,
+                                  MessageProtocol_RequestId requestId, const uint8_t *data,
+                                  size_t dataSize, MessageProtocol_ResponseResult result,
+                                  bool timedOut)
+{
+    bool failed =
+        CheckResponse("SetLed", MessageProtocol_McuToCloud_CategoryId, categoryId,
+                      MessageProtocol_McuToCloud_SetLed, requestId,
+                      sizeof(MessageProtocol_McuToCloud_SetLedStruct), dataSize, timedOut);
+
+    if (failed) {
+        if (failCallback != NULL) {
+            failCallback();
+        } else {
+            Log_Debug("ERROR: No failure handler registered.");
+        }
+    } else {
+        if (setLedCallback != NULL) {
+            MessageProtocol_McuToCloud_SetLedStruct *setLed =
+                (MessageProtocol_McuToCloud_SetLedStruct *)data;
+            LedColor color = {setLed->red != 0, setLed->green != 0, setLed->blue != 0};
+
+            setLedCallback(&color);
+        } else {
+            Log_Debug("WARNING: SetLed response - no handler registered.");
+        }
+    }
+}
+
+void McuMessaging_SetLed(const LedColor *color, McuMessagingSetLedCallbackType successCallback,
+                         McuMessagingFailureCallbackType failureCallback)
+{
+    MessageProtocol_McuToCloud_SetLedStruct leds = {.red = color->red ? 0xff : 0x00,
+                                                    .green = color->green ? 0xff : 0x00,
+                                                    .blue = color->blue ? 0xff : 0x00,
+                                                    .reserved = 0};
+
+    setLedCallback = successCallback;
+    failCallback = failureCallback;
+
+    MessageProtocol_SendRequest(MessageProtocol_McuToCloud_CategoryId,
+                                MessageProtocol_McuToCloud_SetLed, (const uint8_t *)&leds,
+                                sizeof(leds), SetLedResponseHandler);
+}

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/mcu_messaging.h

@@ -0,0 +1,49 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#pragma once
+
+#include "telemetry.h"
+#include "color.h"
+
+typedef void (*McuMessagingFailureCallbackType)(void);
+
+/// <summary>
+///     Initialize comms with the external MCU.
+/// </summary>
+void McuMessaging_Initialize(void);
+
+typedef void (*McuMessagingInitCallbackType)(void);
+
+/// <summary>
+///     Send an init message to the MCU. On receipt of a successful response, call
+///     <paramref="successCallback" />; on failure, call <paramref="failureCallback" />.
+/// </summary>
+/// <param name="successCallback">Function to call on receipt of a successful response.</param>
+/// <param name="failCallback">Function to call if no response is received.</param>
+void McuMessaging_Init(McuMessagingInitCallbackType successCallback,
+                       McuMessagingFailureCallbackType failureCallback);
+
+typedef void (*McuMessagingRequestTelemetryCallbackType)(const DeviceTelemetry *telemetry);
+
+/// <summary>
+///     Send a request for telemetry to the MCU. On receipt of a successful response, call
+///     <paramref="successCallback" /> with the telemetry data; on failure, call
+///     <paramref="failureCallback" />.
+/// </summary>
+/// <param name="successCallback">Function to call on successful receipt of telemetry.</param>
+/// <param name="failCallback">Function to call if no response is received.</param>
+void McuMessaging_RequestTelemetry(McuMessagingRequestTelemetryCallbackType successCallback,
+                                   McuMessagingFailureCallbackType failureCallback);
+
+typedef void (*McuMessagingSetLedCallbackType)(const LedColor *color);
+
+/// <summary>
+///     Send a request to set the LED color to the MCU. On receipt of a successful response, call
+///     <paramref="successCallback" />; on failure, call <paramref="failureCallback" />.
+/// </summary>
+/// <param name="color">LED color to set</param>
+/// <param name="successCallback">Function to call on successful receipt of SetLed response.</param>
+/// <param name="failCallback">Function to call if no response is received.</param>
+void McuMessaging_SetLed(const LedColor *color, McuMessagingSetLedCallbackType successCallback,
+                         McuMessagingFailureCallbackType failureCallback);

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/message_protocol.c

@@ -0,0 +1,363 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#include <string.h>
+#include <errno.h>
+#include <unistd.h>
+#include <stdlib.h>
+
+#include <applibs/log.h>
+#include <applibs/eventloop.h>
+
+#include "message_protocol.h"
+#include "message_protocol_private.h"
+#include "message_protocol_utilities.h"
+#include "applibs_versions.h"
+#include "eventloop_timer_utilities.h"
+#include "exitcode.h"
+
+#define REQUEST_TIMEOUT 5u
+
+#define RECEIVED_BUFFER_SIZE 1024u
+#define SEND_BUFFER_SIZE 1024u
+
+static EventLoop *eventLoopRef = NULL;
+
+static EventLoopTimer *requestTimeoutTimer = NULL;
+
+static Transport_ReadFunctionType transportReadFunction = NULL;
+static Transport_WriteFunctionType transportWriteFunction = NULL;
+
+// Buffer for data received via transport and index at which to write future data.
+static uint8_t receiveBuffer[RECEIVED_BUFFER_SIZE];
+static uint16_t receiveBufferPos = 0;
+
+// Buffer in which to assemble messages
+static uint8_t sendBuffer[SEND_BUFFER_SIZE];
+
+// Message protocol states.
+typedef enum {
+    MessageProtocolState_Idle,
+    MessageProtocolState_RequestOutstanding
+} MessageProtocolState;
+
+// Current state of the message protocol.
+static MessageProtocolState protocolState;
+
+static MessageProtocol_ResponseHandlerType currentResponseHandler;
+
+// Request sequence number
+static uint16_t currentSequenceNumber = 0;
+
+// Event handlers list
+struct EventHandlerNode {
+    MessageProtocol_CategoryId categoryId;
+    MessageProtocol_EventId eventId;
+    MessageProtocol_EventHandlerType handler;
+    struct EventHandlerNode *nextNode;
+};
+static struct EventHandlerNode *eventHandlerList;
+
+// Idle handlers list
+struct IdleHandlerNode {
+    MessageProtocol_IdleHandlerType handler;
+    struct IdleHandlerNode *nextNode;
+};
+static struct IdleHandlerNode *idleHandlerList;
+
+static void RemoveFirstCompleteMessage(void)
+{
+    MessageProtocol_MessageHeader *messageHeader = (MessageProtocol_MessageHeader *)receiveBuffer;
+    uint16_t topMessageLength =
+        (uint16_t)(messageHeader->length + sizeof(MessageProtocol_MessageHeader));
+    if (receiveBufferPos == topMessageLength) {
+        // There is only one complete message in the buffer: set receivedBufferIndex to 0.
+        receiveBufferPos = 0;
+    } else if (receiveBufferPos > topMessageLength) {
+        // There is more than one complete message in the buffer: remove the top message, move
+        // the rest forward and subtract the message length from receiveBufferPos.
+        receiveBufferPos = (uint16_t)(receiveBufferPos - topMessageLength);
+        memmove(receiveBuffer, receiveBuffer + topMessageLength, receiveBufferPos);
+    }
+}
+
+static void RemoveInvalidBytesBeforePreamble(void)
+{
+    size_t preambleSize = sizeof(MessageProtocol_MessagePreamble);
+    bool foundPreamble = false;
+    size_t pos = 0;
+
+    while (pos < receiveBufferPos) {
+        size_t remainingDataSize = receiveBufferPos - pos;
+        // Check whether we can find a complete or partial preamble by the end of current data.
+        size_t checkPreambleSize =
+            (remainingDataSize >= preambleSize) ? preambleSize : remainingDataSize;
+        if (memcmp(MessageProtocol_MessagePreamble, receiveBuffer + pos, checkPreambleSize) == 0) {
+            foundPreamble = true;
+            break;
+        }
+        ++pos;
+    }
+    uint16_t validMessageLength = (uint16_t)(receiveBufferPos - pos);
+    receiveBufferPos = validMessageLength;
+
+    // Found complete or partial preamble. If it's not at the beginning of the
+    // message, move everything between i and (pos - 1) to the front, otherwise
+    // doing nothing as receivedBufferIndex is set to 0 already.
+    if (pos > 0 && foundPreamble) {
+        memmove(receiveBuffer, receiveBuffer + pos, validMessageLength);
+    }
+}
+
+static MessageProtocol_EventInfo *GetEventInfo(uint8_t *message, uint16_t messageLength)
+{
+    MessageProtocol_MessageHeader *messageHeader = (MessageProtocol_MessageHeader *)message;
+    if (messageLength <
+            sizeof(MessageProtocol_MessageHeaderWithType) + sizeof(MessageProtocol_EventInfo) ||
+        messageHeader->length + sizeof(MessageProtocol_MessageHeader) !=
+            sizeof(MessageProtocol_MessageHeaderWithType) + sizeof(MessageProtocol_EventInfo)) {
+        Log_Debug("ERROR: Received invalid event message - incorrect length.\n");
+        return NULL;
+    }
+    MessageProtocol_EventMessage *eventMessage = (MessageProtocol_EventMessage *)(message);
+    return &(eventMessage->eventInfo);
+}
+
+static void CallIdleHandlers(void)
+{
+    // Call all registered idle handlers as long as protocol state is still idle.
+    struct IdleHandlerNode *current = idleHandlerList;
+    while (current != NULL && protocolState == MessageProtocolState_Idle) {
+        current->handler();
+        current = current->nextNode;
+    }
+}
+
+static void CallEventHandler(void)
+{
+    MessageProtocol_EventInfo *eventInfo = GetEventInfo(receiveBuffer, receiveBufferPos);
+    if (eventInfo == NULL) {
+        Log_Debug("ERROR: Received malformed event message.\n");
+        return;
+    }
+
+    struct EventHandlerNode *current = eventHandlerList;
+    while (current != NULL) {
+        if (current->categoryId == eventInfo->categoryId &&
+            current->eventId == eventInfo->eventId && current->handler != NULL) {
+            current->handler(current->categoryId, current->eventId);
+            return;
+        }
+        current = current->nextNode;
+    }
+    Log_Debug("ERROR: Received event message with unknown Category ID and Event ID: 0x%x, 0x%x.\n",
+              eventInfo->categoryId, eventInfo->eventId);
+}
+
+static void CallResponseHandler(void)
+{
+    MessageProtocol_ResponseMessage *responseMessage =
+        (MessageProtocol_ResponseMessage *)(receiveBuffer);
+
+    if (receiveBufferPos < sizeof(MessageProtocol_ResponseHeader) ||
+        responseMessage->responseHeader.messageHeaderWithType.messageHeader.length +
+                sizeof(MessageProtocol_MessageHeader) <
+            sizeof(MessageProtocol_ResponseHeader)) {
+        Log_Debug("ERROR: Received invalid response message - too short.\n");
+        return;
+    }
+
+    if (currentSequenceNumber != responseMessage->responseHeader.sequenceNumber) {
+        Log_Debug("ERROR: Received a response with invalid sequence number: %x.\n",
+                  responseMessage->responseHeader.sequenceNumber);
+        return;
+    }
+
+    if (protocolState != MessageProtocolState_RequestOutstanding) {
+        Log_Debug("ERROR: Received a response when not expecting one\n");
+        return;
+    }
+    protocolState = MessageProtocolState_Idle;
+    DisarmEventLoopTimer(requestTimeoutTimer);
+
+    MessageProtocol_ResponseHandlerType handler = currentResponseHandler;
+    currentResponseHandler = NULL;
+
+    if (handler != NULL) {
+        size_t dataLength =
+            responseMessage->responseHeader.messageHeaderWithType.messageHeader.length +
+            sizeof(MessageProtocol_MessageHeader) - sizeof(MessageProtocol_RequestHeader);
+        handler(responseMessage->responseHeader.categoryId,
+                responseMessage->responseHeader.requestId, responseMessage->data, dataLength,
+                responseMessage->responseHeader.responseResult, false);
+    }
+
+    CallIdleHandlers();
+}
+
+void MessageProtocol_HandleReceivedMessage(void)
+{
+    // Attempt to read message from UART.
+    ssize_t bytesRead = transportReadFunction(receiveBuffer + receiveBufferPos,
+                                              RECEIVED_BUFFER_SIZE - receiveBufferPos);
+    if (bytesRead == -1) {
+        Log_Debug("ERROR: Could not read from UART: %s (%d).\n", strerror(errno), errno);
+        return;
+    }
+
+    if (bytesRead > 0) {
+        receiveBufferPos = (uint16_t)(receiveBufferPos + bytesRead);
+        // Messages in the receive buffer should always start with a preamble, so remove all invalid
+        // bytes before the preamble.
+        RemoveInvalidBytesBeforePreamble();
+        while (MessageProtocol_IsMessageComplete(receiveBuffer, (uint8_t)receiveBufferPos)) {
+            // We received a complete message, call its handler.
+            MessageProtocol_MessageHeaderWithType *messageHeader =
+                (MessageProtocol_MessageHeaderWithType *)receiveBuffer;
+            if (messageHeader->type == MessageProtocol_EventMessageType) {
+                CallEventHandler();
+            } else if (messageHeader->type == MessageProtocol_ResponseMessageType) {
+                CallResponseHandler();
+            } else {
+                Log_Debug("ERROR: Skipping message: unknown or invalid message type.\n");
+            }
+            // We have finished with this message now, so remove it from the receive buffer.
+            RemoveFirstCompleteMessage();
+        }
+    }
+}
+
+static void RequestTimeoutEventHandler(EventLoopTimer *timer)
+{
+    if (ConsumeEventLoopTimerEvent(requestTimeoutTimer) != 0) {
+        return;
+    }
+
+    // Timed out waiting for response message: change back to Idle state and call the response
+    // handler to inform it that the request has timed out.
+    protocolState = MessageProtocolState_Idle;
+    MessageProtocol_ResponseHandlerType handler = currentResponseHandler;
+    currentResponseHandler = NULL;
+    if (handler != NULL) {
+        MessageProtocol_RequestMessage *requestMessage =
+            (MessageProtocol_RequestMessage *)sendBuffer;
+        handler(requestMessage->requestHeader.categoryId, requestMessage->requestHeader.requestId,
+                NULL, 0, 0, true);
+    }
+
+    // We are idle now, so call the idle handlers.
+    CallIdleHandlers();
+}
+
+ExitCode MessageProtocol_Initialize(EventLoop *el, Transport_ReadFunctionType readFunction,
+                                    Transport_WriteFunctionType writeFunction)
+{
+    eventLoopRef = el;
+    transportReadFunction = readFunction;
+    transportWriteFunction = writeFunction;
+
+    requestTimeoutTimer = CreateEventLoopDisarmedTimer(eventLoopRef, RequestTimeoutEventHandler);
+
+    if (requestTimeoutTimer == NULL) {
+        return ExitCode_MsgProtoInit_Timer;
+    }
+
+    protocolState = MessageProtocolState_Idle;
+    currentResponseHandler = NULL;
+    eventHandlerList = NULL;
+    idleHandlerList = NULL;
+    return ExitCode_Success;
+}
+
+void MessageProtocol_Cleanup(void)
+{
+    DisposeEventLoopTimer(requestTimeoutTimer);
+    eventLoopRef = NULL;
+    transportReadFunction = NULL;
+    transportWriteFunction = NULL;
+
+    // Free all event handlers in the list.
+    struct EventHandlerNode *currentEventHandler = NULL;
+    while (eventHandlerList != NULL) {
+        currentEventHandler = eventHandlerList;
+        eventHandlerList = eventHandlerList->nextNode;
+        free(currentEventHandler);
+    }
+    // Free all idle handlers in the list.
+    struct IdleHandlerNode *currentIdleHandler = NULL;
+    while (idleHandlerList != NULL) {
+        currentIdleHandler = idleHandlerList;
+        idleHandlerList = idleHandlerList->nextNode;
+        free(currentIdleHandler);
+    }
+}
+
+void MessageProtocol_RegisterEventHandler(MessageProtocol_CategoryId categoryId,
+                                          MessageProtocol_EventId eventId,
+                                          MessageProtocol_EventHandlerType handler)
+{
+    struct EventHandlerNode *node = malloc(sizeof(struct EventHandlerNode));
+    node->categoryId = categoryId;
+    node->eventId = eventId;
+    node->handler = handler;
+    // Add it to the head of linked list.
+    node->nextNode = eventHandlerList;
+    eventHandlerList = node;
+}
+
+void MessageProtocol_RegisterIdleHandler(MessageProtocol_IdleHandlerType handler)
+{
+    struct IdleHandlerNode *node = malloc(sizeof(struct IdleHandlerNode));
+    node->handler = handler;
+    // Add it to the head of linked list.
+    node->nextNode = idleHandlerList;
+    idleHandlerList = node;
+}
+
+void MessageProtocol_SendRequest(MessageProtocol_CategoryId categoryId,
+                                 MessageProtocol_RequestId requestId, const uint8_t *body,
+                                 size_t bodyLength,
+                                 MessageProtocol_ResponseHandlerType responseHandler)
+{
+    if (protocolState != MessageProtocolState_Idle) {
+        Log_Debug("INFO: Protocol busy, can't send request: %x, %x.\n", categoryId, requestId);
+        return;
+    }
+
+    // Set request message data in-place.
+    MessageProtocol_RequestMessage *requestMessage = (MessageProtocol_RequestMessage *)sendBuffer;
+    memcpy(requestMessage->requestHeader.messageHeaderWithType.messageHeader.preamble,
+           MessageProtocol_MessagePreamble, sizeof(MessageProtocol_MessagePreamble));
+    requestMessage->requestHeader.messageHeaderWithType.messageHeader.length = (uint16_t)(
+        sizeof(MessageProtocol_RequestHeader) - sizeof(MessageProtocol_MessageHeader) + bodyLength);
+    requestMessage->requestHeader.messageHeaderWithType.type = MessageProtocol_RequestMessageType;
+    requestMessage->requestHeader.messageHeaderWithType.reserved = 0x00;
+    requestMessage->requestHeader.categoryId = categoryId;
+    requestMessage->requestHeader.requestId = requestId;
+    requestMessage->requestHeader.sequenceNumber = ++currentSequenceNumber;
+    memset(requestMessage->requestHeader.reserved, 0, 2);
+
+    // Check message length is within UART send buffer size limit.
+    uint16_t messageLength =
+        (uint16_t)(requestMessage->requestHeader.messageHeaderWithType.messageHeader.length +
+                   sizeof(MessageProtocol_MessageHeader));
+    if (messageLength > SEND_BUFFER_SIZE) {
+        Log_Debug("ERROR: Request message length (%d) exceeds send buffer size.\n", messageLength);
+        return;
+    }
+    memcpy(requestMessage->data, body, bodyLength);
+
+    currentResponseHandler = responseHandler;
+
+    // Start timer for response to this request.
+    const struct timespec sendRequestMessageCheckPeriod = {REQUEST_TIMEOUT, 0};
+    SetEventLoopTimerOneShot(requestTimeoutTimer, &sendRequestMessageCheckPeriod);
+    protocolState = MessageProtocolState_RequestOutstanding;
+
+    transportWriteFunction(sendBuffer, messageLength);
+}
+
+bool MessageProtocol_IsIdle(void)
+{
+    return (protocolState == MessageProtocolState_Idle);
+}

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/message_protocol.h

@@ -0,0 +1,80 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#pragma once
+#include <sys/types.h>
+#include <stdbool.h>
+
+#include "message_protocol_public.h"
+#include "exitcode.h"
+
+typedef ssize_t (*Transport_ReadFunctionType)(char *buffer, size_t amount);
+
+typedef ssize_t (*Transport_WriteFunctionType)(const char *buffer, size_t amount);
+
+/// <summary>
+///     Initialize the message protocol and UART.
+/// </summary>
+/// <param name="epollFd">epoll file descriptor to use for event polling.</param>
+/// <param name="readFunction">Function to call to read data from the transport.</param>
+/// <param name="writeFunction">Function to call to write data to the transport.</param>
+/// <returns>An <see cref="ExitCode" /> indicating success or failure.</returns>
+ExitCode MessageProtocol_Initialize(EventLoop *el, Transport_ReadFunctionType readFunction,
+                                    Transport_WriteFunctionType writeFunction);
+
+/// <summary>
+///     Clean up the message protocol callback handlers.
+/// </summary>
+void MessageProtocol_Cleanup(void);
+
+/// <summary>
+///     Call this function to cause the message protocol to attempt to read a message from the
+///     transport (and call the relevant handlers)
+/// </summary>
+void MessageProtocol_HandleReceivedMessage(void);
+
+typedef void (*MessageProtocol_EventHandlerType)(MessageProtocol_CategoryId categoryId,
+                                                 MessageProtocol_EventId eventId);
+
+/// <summary>
+///     Register a callback handler for incoming message protocol event messages.
+/// </summary>
+/// <param name="categoryId">The message protocol category ID.</param>
+/// <param name="eventId">The message protocol event ID.</param>
+/// <param name="handler">The callback handler to register.</param>
+void MessageProtocol_RegisterEventHandler(MessageProtocol_CategoryId categoryId,
+                                          MessageProtocol_EventId eventId,
+                                          MessageProtocol_EventHandlerType handler);
+
+typedef void (*MessageProtocol_IdleHandlerType)(void);
+
+/// <summary>
+///     Register a callback handler for the idle event.
+/// </summary>
+/// <param name="handler">The callback handler to register.</param>
+void MessageProtocol_RegisterIdleHandler(MessageProtocol_IdleHandlerType handler);
+
+typedef void (*MessageProtocol_ResponseHandlerType)(MessageProtocol_CategoryId categoryId,
+                                                    MessageProtocol_RequestId requestId,
+                                                    const uint8_t *data, size_t dataSize,
+                                                    MessageProtocol_ResponseResult result,
+                                                    bool timedOut);
+
+/// <summary>
+///     Send a request using the message protocol.
+/// </summary>
+/// <param name="categoryId">The message protocol category ID.</param>
+/// <param name="requestId">The message protocol request ID.</param>
+/// <param name="body">The body of the message.</param>
+/// <param name="bodyLength">The length of the message body in bytes.</param>
+/// <param name="responseHandler">The callback handler for the response message.</param>
+void MessageProtocol_SendRequest(MessageProtocol_CategoryId categoryId,
+                                 MessageProtocol_RequestId requestId, const uint8_t *body,
+                                 size_t bodyLength,
+                                 MessageProtocol_ResponseHandlerType responseHandler);
+
+/// <summary>
+///     Query whether the message protocol is currently idle.
+/// </summary>
+/// <returns>True if the message protocol is currently idle; false if it is busy.</returns>
+bool MessageProtocol_IsIdle(void);

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/parson.h

@@ -0,0 +1,234 @@
+/*
+    This source code comes from Git repository
+    https://github.com/kgabis/parson at commit id 4f3eaa6
+    Patched to avoid any usage of fopen(), and removed implicit
+    cast warnings by making them explicit.
+*/
+
+/*
+ Parson ( http://kgabis.github.com/parson/ )
+ Copyright (c) 2012 - 2017 Krzysztof Gabis
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ THE SOFTWARE.
+*/
+
+#ifndef parson_parson_h
+#define parson_parson_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stddef.h> /* size_t */
+
+/* Types and enums */
+typedef struct json_object_t JSON_Object;
+typedef struct json_array_t JSON_Array;
+typedef struct json_value_t JSON_Value;
+
+enum json_value_type {
+    JSONError = -1,
+    JSONNull = 1,
+    JSONString = 2,
+    JSONNumber = 3,
+    JSONObject = 4,
+    JSONArray = 5,
+    JSONBoolean = 6
+};
+typedef int JSON_Value_Type;
+
+enum json_result_t { JSONSuccess = 0, JSONFailure = -1 };
+typedef int JSON_Status;
+
+typedef void *(*JSON_Malloc_Function)(size_t);
+typedef void (*JSON_Free_Function)(void *);
+
+/* Call only once, before calling any other function from parson API. If not called, malloc and free
+   from stdlib will be used for all allocations */
+void json_set_allocation_functions(JSON_Malloc_Function malloc_fun, JSON_Free_Function free_fun);
+
+/*  Parses first JSON value in a string, returns NULL in case of error */
+JSON_Value *json_parse_string(const char *string);
+
+/*  Parses first JSON value in a string and ignores comments (/ * * / and //),
+    returns NULL in case of error */
+JSON_Value *json_parse_string_with_comments(const char *string);
+
+/* Serialization */
+size_t json_serialization_size(const JSON_Value *value); /* returns 0 on fail */
+JSON_Status json_serialize_to_buffer(const JSON_Value *value, char *buf, size_t buf_size_in_bytes);
+char *json_serialize_to_string(const JSON_Value *value);
+
+/* Pretty serialization */
+size_t json_serialization_size_pretty(const JSON_Value *value); /* returns 0 on fail */
+JSON_Status json_serialize_to_buffer_pretty(const JSON_Value *value, char *buf,
+                                            size_t buf_size_in_bytes);
+char *json_serialize_to_string_pretty(const JSON_Value *value);
+
+void json_free_serialized_string(char *string); /* frees string from json_serialize_to_string and
+                                                   json_serialize_to_string_pretty */
+
+/* Comparing */
+int json_value_equals(const JSON_Value *a, const JSON_Value *b);
+
+/* Validation
+   This is *NOT* JSON Schema. It validates json by checking if object have identically
+   named fields with matching types.
+   For example schema {"name":"", "age":0} will validate
+   {"name":"Joe", "age":25} and {"name":"Joe", "age":25, "gender":"m"},
+   but not {"name":"Joe"} or {"name":"Joe", "age":"Cucumber"}.
+   In case of arrays, only first value in schema is checked against all values in tested array.
+   Empty objects ({}) validate all objects, empty arrays ([]) validate all arrays,
+   null validates values of every type.
+ */
+JSON_Status json_validate(const JSON_Value *schema, const JSON_Value *value);
+
+/*
+ * JSON Object
+ */
+JSON_Value *json_object_get_value(const JSON_Object *object, const char *name);
+const char *json_object_get_string(const JSON_Object *object, const char *name);
+JSON_Object *json_object_get_object(const JSON_Object *object, const char *name);
+JSON_Array *json_object_get_array(const JSON_Object *object, const char *name);
+double json_object_get_number(const JSON_Object *object, const char *name); /* returns 0 on fail */
+int json_object_get_boolean(const JSON_Object *object, const char *name);   /* returns -1 on fail */
+
+/* dotget functions enable addressing values with dot notation in nested objects,
+ just like in structs or c++/java/c# objects (e.g. objectA.objectB.value).
+ Because valid names in JSON can contain dots, some values may be inaccessible
+ this way. */
+JSON_Value *json_object_dotget_value(const JSON_Object *object, const char *name);
+const char *json_object_dotget_string(const JSON_Object *object, const char *name);
+JSON_Object *json_object_dotget_object(const JSON_Object *object, const char *name);
+JSON_Array *json_object_dotget_array(const JSON_Object *object, const char *name);
+double json_object_dotget_number(const JSON_Object *object,
+                                 const char *name); /* returns 0 on fail */
+int json_object_dotget_boolean(const JSON_Object *object,
+                               const char *name); /* returns -1 on fail */
+
+/* Functions to get available names */
+size_t json_object_get_count(const JSON_Object *object);
+const char *json_object_get_name(const JSON_Object *object, size_t index);
+JSON_Value *json_object_get_value_at(const JSON_Object *object, size_t index);
+JSON_Value *json_object_get_wrapping_value(const JSON_Object *object);
+
+/* Functions to check if object has a value with a specific name. Returned value is 1 if object has
+ * a value and 0 if it doesn't. dothas functions behave exactly like dotget functions. */
+int json_object_has_value(const JSON_Object *object, const char *name);
+int json_object_has_value_of_type(const JSON_Object *object, const char *name,
+                                  JSON_Value_Type type);
+
+int json_object_dothas_value(const JSON_Object *object, const char *name);
+int json_object_dothas_value_of_type(const JSON_Object *object, const char *name,
+                                     JSON_Value_Type type);
+
+/* Creates new name-value pair or frees and replaces old value with a new one.
+ * json_object_set_value does not copy passed value so it shouldn't be freed afterwards. */
+JSON_Status json_object_set_value(JSON_Object *object, const char *name, JSON_Value *value);
+JSON_Status json_object_set_string(JSON_Object *object, const char *name, const char *string);
+JSON_Status json_object_set_number(JSON_Object *object, const char *name, double number);
+JSON_Status json_object_set_boolean(JSON_Object *object, const char *name, int boolean);
+JSON_Status json_object_set_null(JSON_Object *object, const char *name);
+
+/* Works like dotget functions, but creates whole hierarchy if necessary.
+ * json_object_dotset_value does not copy passed value so it shouldn't be freed afterwards. */
+JSON_Status json_object_dotset_value(JSON_Object *object, const char *name, JSON_Value *value);
+JSON_Status json_object_dotset_string(JSON_Object *object, const char *name, const char *string);
+JSON_Status json_object_dotset_number(JSON_Object *object, const char *name, double number);
+JSON_Status json_object_dotset_boolean(JSON_Object *object, const char *name, int boolean);
+JSON_Status json_object_dotset_null(JSON_Object *object, const char *name);
+
+/* Frees and removes name-value pair */
+JSON_Status json_object_remove(JSON_Object *object, const char *name);
+
+/* Works like dotget function, but removes name-value pair only on exact match. */
+JSON_Status json_object_dotremove(JSON_Object *object, const char *key);
+
+/* Removes all name-value pairs in object */
+JSON_Status json_object_clear(JSON_Object *object);
+
+/*
+ *JSON Array
+ */
+JSON_Value *json_array_get_value(const JSON_Array *array, size_t index);
+const char *json_array_get_string(const JSON_Array *array, size_t index);
+JSON_Object *json_array_get_object(const JSON_Array *array, size_t index);
+JSON_Array *json_array_get_array(const JSON_Array *array, size_t index);
+double json_array_get_number(const JSON_Array *array, size_t index); /* returns 0 on fail */
+int json_array_get_boolean(const JSON_Array *array, size_t index);   /* returns -1 on fail */
+size_t json_array_get_count(const JSON_Array *array);
+JSON_Value *json_array_get_wrapping_value(const JSON_Array *array);
+
+/* Frees and removes value at given index, does nothing and returns JSONFailure if index doesn't
+ * exist. Order of values in array may change during execution.  */
+JSON_Status json_array_remove(JSON_Array *array, size_t i);
+
+/* Frees and removes from array value at given index and replaces it with given one.
+ * Does nothing and returns JSONFailure if index doesn't exist.
+ * json_array_replace_value does not copy passed value so it shouldn't be freed afterwards. */
+JSON_Status json_array_replace_value(JSON_Array *array, size_t i, JSON_Value *value);
+JSON_Status json_array_replace_string(JSON_Array *array, size_t i, const char *string);
+JSON_Status json_array_replace_number(JSON_Array *array, size_t i, double number);
+JSON_Status json_array_replace_boolean(JSON_Array *array, size_t i, int boolean);
+JSON_Status json_array_replace_null(JSON_Array *array, size_t i);
+
+/* Frees and removes all values from array */
+JSON_Status json_array_clear(JSON_Array *array);
+
+/* Appends new value at the end of array.
+ * json_array_append_value does not copy passed value so it shouldn't be freed afterwards. */
+JSON_Status json_array_append_value(JSON_Array *array, JSON_Value *value);
+JSON_Status json_array_append_string(JSON_Array *array, const char *string);
+JSON_Status json_array_append_number(JSON_Array *array, double number);
+JSON_Status json_array_append_boolean(JSON_Array *array, int boolean);
+JSON_Status json_array_append_null(JSON_Array *array);
+
+/*
+ *JSON Value
+ */
+JSON_Value *json_value_init_object(void);
+JSON_Value *json_value_init_array(void);
+JSON_Value *json_value_init_string(const char *string); /* copies passed string */
+JSON_Value *json_value_init_number(double number);
+JSON_Value *json_value_init_boolean(int boolean);
+JSON_Value *json_value_init_null(void);
+JSON_Value *json_value_deep_copy(const JSON_Value *value);
+void json_value_free(JSON_Value *value);
+
+JSON_Value_Type json_value_get_type(const JSON_Value *value);
+JSON_Object *json_value_get_object(const JSON_Value *value);
+JSON_Array *json_value_get_array(const JSON_Value *value);
+const char *json_value_get_string(const JSON_Value *value);
+double json_value_get_number(const JSON_Value *value);
+int json_value_get_boolean(const JSON_Value *value);
+JSON_Value *json_value_get_parent(const JSON_Value *value);
+
+/* Same as above, but shorter */
+JSON_Value_Type json_type(const JSON_Value *value);
+JSON_Object *json_object(const JSON_Value *value);
+JSON_Array *json_array(const JSON_Value *value);
+const char *json_string(const JSON_Value *value);
+double json_number(const JSON_Value *value);
+int json_boolean(const JSON_Value *value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/persistent_storage.c

@@ -0,0 +1,142 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#include <stdint.h>
+#include <errno.h>
+#include <string.h>
+#include <unistd.h>
+#include <stdbool.h>
+
+#include <applibs/storage.h>
+#include <applibs/log.h>
+
+#include "telemetry.h"
+#include "persistent_storage.h"
+
+static const uint32_t magicWord0 = ('M' << 24) | ('S' << 16) | ('A' << 8) | 'S';
+static const uint32_t magicWord1 = ('S' << 24) | ('O' << 16) | ('D' << 8) | 'A';
+
+bool PersistentStorage_RetrieveTelemetry(DeviceTelemetry *telemetry)
+{
+    int storageFd = -1;
+
+    if (telemetry == NULL) {
+        Log_Debug("ERROR: Telemetry pointer cannot be NULL\n");
+        goto fail;
+    }
+
+    memset(telemetry, 0, sizeof(DeviceTelemetry));
+
+    storageFd = Storage_OpenMutableFile();
+    if (storageFd == -1) {
+        Log_Debug("ERROR: Failed to open mutable storage - %s (%d)\n", strerror(errno), errno);
+        goto fail;
+    }
+
+    uint32_t header[3];
+    ssize_t bytesRead = read(storageFd, &header[0], sizeof(header));
+    if (bytesRead == -1) {
+        Log_Debug("ERROR: Failed to read telemetry header from mutable storage - %s (%d)\n",
+                  strerror(errno), errno);
+        goto fail;
+    }
+
+    if (bytesRead < sizeof(header)) {
+        Log_Debug(
+            "Failed to read telemetry header from mutable storage: incomplete header (%d bytes "
+            "when %u were expected)\n",
+            bytesRead, sizeof(header));
+        goto fail;
+    }
+
+    if (header[0] != magicWord0 || header[1] != magicWord1) {
+        Log_Debug(
+            "Mutable storage does not contain header bytes; no stored telemetry available.\n");
+        goto fail;
+    }
+
+    uint32_t persistedTelemetryVersion = header[2];
+    if (persistedTelemetryVersion != telemetryStructVersion) {
+        Log_Debug(
+            "Persisted telemetry struct version (%d) differs from expected version (%d); no stored "
+            "telemetry available",
+            persistedTelemetryVersion, telemetryStructVersion);
+        goto fail;
+    }
+
+    bytesRead = read(storageFd, telemetry, sizeof(DeviceTelemetry));
+
+    if (bytesRead == -1) {
+        Log_Debug("ERROR: Failed to read telemetry from mutable storage - %s (%d)", strerror(errno),
+                  errno);
+        goto fail;
+    }
+
+    if (bytesRead < sizeof(DeviceTelemetry)) {
+        Log_Debug(
+            "ERROR: Failed to read full telemetry struct from mutable storage; no stored telemetry "
+            "available");
+        goto fail;
+    }
+
+    return true;
+
+fail:
+
+    if (storageFd != 0) {
+        close(storageFd);
+    }
+    return false;
+}
+
+void PersistentStorage_PersistTelemetry(const DeviceTelemetry *telemetry)
+{
+    int storageFd = -1;
+
+    if (telemetry == NULL) {
+        Log_Debug("ERROR: Telemetry pointer cannot be NULL\n");
+        goto cleanup;
+    }
+
+    storageFd = Storage_OpenMutableFile();
+    if (storageFd == -1) {
+        Log_Debug("ERROR: Failed to open mutable storage - %s (%d)\n", strerror(errno), errno);
+        goto cleanup;
+    }
+
+    uint32_t header[] = {magicWord0, magicWord1, telemetryStructVersion};
+    ssize_t bytesWritten = write(storageFd, &header, sizeof(header));
+    if (bytesWritten == -1) {
+        Log_Debug("ERROR: Failed to write telemetry header to persistent storage - %s (%d)\n",
+                  strerror(errno), errno);
+        goto cleanup;
+    }
+
+    if (bytesWritten < sizeof(header)) {
+        Log_Debug(
+            "ERROR: Failed to write full telemetry header to persistent storage - only wrote %d of "
+            "%u bytes\n",
+            bytesWritten, sizeof(header));
+        goto cleanup;
+    }
+
+    bytesWritten = write(storageFd, telemetry, sizeof(DeviceTelemetry));
+    if (bytesWritten == -1) {
+        Log_Debug("ERROR: Failed to write telemetry to persistent storage - %s (%d)\n",
+                  strerror(errno), errno);
+        goto cleanup;
+    }
+
+    if (bytesWritten < sizeof(DeviceTelemetry)) {
+        Log_Debug(
+            "ERROR: Failed to write full telemetry to persistent storage - only wrote %d of %u "
+            "bytes\n",
+            bytesWritten, sizeof(DeviceTelemetry));
+        goto cleanup;
+    }
+
+cleanup:
+    if (storageFd != 0) {
+        close(storageFd);
+    }
+}

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/persistent_storage.h

@@ -0,0 +1,24 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#pragma once
+
+#include <stdbool.h>
+#include "telemetry.h"
+
+/// <summary>
+///     Persist device telemetry to storage, for retrieval on a future run.
+/// </summary>
+/// <param name="telemetry">Pointer to a telemetry object to persist.</param>
+void PersistentStorage_PersistTelemetry(const DeviceTelemetry *telemetry);
+
+/// <summary>
+///     Attempt to retrieve previously persisted device telemetry from storage. If no previous
+///     telemetry can be found, returns false and sets all fields of the supplied telemetry object
+///     to zero; otherwise, returns true and populates the supplied telemetry object.
+/// </summary>
+/// <param name="telemetry">
+///     Pointer to a device telemetry object to receive the persisted data.
+/// </param>
+/// <returns>true if previously-persisted telemetry is found; false if not.</returns>
+bool PersistentStorage_RetrieveTelemetry(DeviceTelemetry *telemetry);

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/power.c

@@ -0,0 +1,29 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#include <errno.h>
+#include <string.h>
+
+#include <applibs/powermanagement.h>
+
+#include <applibs/log.h>
+
+const unsigned int powerdownResidencyTimeSeconds = 120;
+
+void Power_RequestPowerdown(void)
+{
+    if (PowerManagement_ForceSystemPowerDown(powerdownResidencyTimeSeconds) != 0) {
+        Log_Debug("ERROR: Unable to force a system power down: %s (%d).\n", strerror(errno), errno);
+    } else {
+        Log_Debug("INFO: System power down requested.\n");
+    }
+}
+
+void Power_RequestReboot(void)
+{
+    if (PowerManagement_ForceSystemReboot() != 0) {
+        Log_Debug("ERROR: Unable to force a system reboot. %s (%d).\n", strerror(errno), errno);
+    } else {
+        Log_Debug("INFO: System reboot requested.\n");
+    }
+}

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/power.h

@@ -0,0 +1,14 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#pragma once
+
+/// <summary>
+///     Request that the device powers down for a period.
+/// </summary>
+void Power_RequestPowerdown(void);
+
+/// <summary>
+///     Request that the device reboots.
+/// </summary>
+void Power_RequestReboot(void);

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/telemetry.h

@@ -0,0 +1,56 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#pragma once
+
+#include <stdint.h>
+
+/// <summary>
+/// Defines the version of the telemetry struct; increment if the struct below is modified.
+/// </summary>
+static const uint32_t telemetryStructVersion = 1u;
+
+/// <summary>
+///     Telemetry read from the device.
+/// </summary>
+typedef struct DeviceTelemetry {
+    /// <summary>
+    /// Accumulated total number of dispenses made by the machine (since first run)
+    /// </summary>
+    uint32_t lifetimeTotalDispenses;
+
+    /// <summary>
+    /// Accumulated total number of dispenses stocked in the machine (since first run)
+    /// </summary>
+    uint32_t lifetimeTotalStockedDispenses;
+
+    /// <summary>
+    /// Maximum number of dispenses that can be stocked at once
+    /// </summary>
+    uint32_t capacity;
+} DeviceTelemetry;
+
+/// <summary>
+///     Telemetry for sending to the cloud.
+/// </summary>
+typedef struct CloudTelemetry {
+    /// <summary>
+    /// Accumulated total number of dispenses made by the machine (since first run)
+    /// </summary>
+    uint32_t lifetimeTotalDispenses;
+
+    /// <summary>
+    /// Number of dispenses since last sync with the cloud backend
+    /// </summary>
+    uint32_t dispensesSinceLastSync;
+
+    /// <summary>
+    /// Point-in-time snapshot of remaining dispenses
+    /// </summary>
+    uint32_t remainingDispenses;
+
+    /// <summary>
+    /// Boolean indicating if the machine is running low on soda
+    /// </summary>
+    bool lowSoda;
+} CloudTelemetry;

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/uart_transport.c

@@ -0,0 +1,170 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#include <sys/types.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <errno.h>
+#include <unistd.h>
+#include <string.h>
+
+#define UART_STRUCTS_VERSION 1
+#include <applibs/eventloop.h>
+#include <applibs/uart.h>
+#include <applibs/log.h>
+
+#include "uart_transport.h"
+#include "exitcode.h"
+
+#define UART_SEND_BUFFER_SIZE 247u // This is the max MTU size of BLE GATT.
+
+static EventLoop *eventLoopRef = NULL;
+static int messageUartFd = -1;
+
+static UartTransport_DataReadyCallback dataReadyCallback = NULL;
+
+// True if the UART event is registered for EventLoop_Output; false if EventLoop_Input
+static bool uartEventOutputEnabled = false;
+
+// Buffer for data to be writtern via UART.
+static uint8_t sendBuffer[UART_SEND_BUFFER_SIZE];
+
+// Total amount of data in sendBuffer.
+static size_t sendBufferDataLength = 0;
+
+// Amount of data so far written to the UART.
+static size_t sendBufferDataSent = 0;
+
+static EventRegistration *uartEventRegistration = NULL;
+
+static void UartEventHandler(EventLoop *el, int fd, EventLoop_IoEvents events, void *context);
+static void SendUartMessage(void);
+
+/// <summary>
+/// Handle events from the UART fd.
+/// </summary>
+static void UartEventHandler(EventLoop *el, int fd, EventLoop_IoEvents events, void *context)
+{
+    switch (events) {
+    case EventLoop_Input:
+        dataReadyCallback();
+        break;
+
+    case EventLoop_Output:
+        SendUartMessage();
+        break;
+
+    default:
+        Log_Debug("ERROR: Unexpected UART IO event %u\n", events);
+        break;
+    }
+}
+
+/// <summary>
+/// Attempt to send the data in <see cref="sendBuffer" /> over the UART. If this fails because the
+/// device is busy (as indicated by EAGAIN), then we modify the UART event registration to wait for
+/// EventLoop_Output, indicating the device is ready again and we should retry writing.
+/// </summary>
+static void SendUartMessage(void)
+{
+    if (uartEventOutputEnabled) {
+        EventLoop_ModifyIoEvents(eventLoopRef, uartEventRegistration, EventLoop_Input);
+        uartEventOutputEnabled = false;
+    }
+
+    while (sendBufferDataSent < sendBufferDataLength) {
+        // Send as much of the remaining data as possible.
+        size_t bytesLeftToSend = (size_t)(sendBufferDataLength - sendBufferDataSent);
+        const uint8_t *remainingMessageToSend = sendBuffer + sendBufferDataSent;
+        ssize_t bytesSent = write(messageUartFd, remainingMessageToSend, bytesLeftToSend);
+        if (bytesSent == -1) {
+            if (errno != EAGAIN) {
+                Log_Debug("ERROR: Failed to write to UART: %s (%d).\n", strerror(errno), errno);
+            } else {
+                // Register an output event to send the rest
+                EventLoop_ModifyIoEvents(eventLoopRef, uartEventRegistration, EventLoop_Output);
+                uartEventOutputEnabled = true;
+            }
+            return;
+        }
+        sendBufferDataSent += (size_t)bytesSent;
+    }
+}
+
+ssize_t UartTransport_Read(char *buffer, size_t amount)
+{
+    return read(messageUartFd, (void *)buffer, amount);
+}
+
+ssize_t UartTransport_Send(const char *buffer, size_t length)
+{
+    if (length > UART_SEND_BUFFER_SIZE) {
+        return 0;
+    }
+
+    if (messageUartFd == -1) {
+        return 0;
+    }
+
+    memcpy(sendBuffer, buffer, length);
+
+    sendBufferDataLength = length;
+    sendBufferDataSent = 0;
+    SendUartMessage();
+
+    return (ssize_t)length;
+}
+
+ExitCode UartTransport_Initialize(EventLoop *eventLoop, UART_Id uartId,
+                                  UartTransport_DataReadyCallback uartDataReadyCallback)
+{
+    eventLoopRef = eventLoop;
+
+    UART_Config config;
+    UART_InitConfig(&config);
+    config.baudRate = 115200;
+    config.dataBits = 8;
+    config.parity = UART_Parity_None;
+    config.stopBits = 1;
+    config.flowControl = UART_FlowControl_None;
+
+    messageUartFd = UART_Open(uartId, &config);
+    if (messageUartFd == -1) {
+        Log_Debug("ERROR: Failed to open UART: %s (%d)\n", strerror(errno), errno);
+        return ExitCode_Uart_Init_OpenFail;
+    }
+
+    dataReadyCallback = uartDataReadyCallback;
+
+    uartEventRegistration =
+        EventLoop_RegisterIo(eventLoop, messageUartFd, EventLoop_Input, UartEventHandler, NULL);
+    if (uartEventRegistration == NULL) {
+        Log_Debug("ERROR: Failed to register UART fd to event loop: %s (%d)", strerror(errno),
+                  errno);
+        return ExitCode_Uart_Init_EventRegisterFail;
+    }
+
+    return ExitCode_Success;
+}
+
+void UartTransport_Cleanup(void)
+{
+    if (uartEventRegistration != NULL) {
+        int result = EventLoop_UnregisterIo(eventLoopRef, uartEventRegistration);
+        if (result == -1) {
+            Log_Debug("ERROR: Failed to unregister UART from event loop: %s (%d)", strerror(errno),
+                      errno);
+        }
+    }
+
+    if (messageUartFd != -1) {
+        int result = close(messageUartFd);
+        if (result == -1) {
+            Log_Debug("ERROR: Failed to close UART fd: %s (%d)", strerror(errno), errno);
+        }
+    }
+
+    eventLoopRef = NULL;
+    dataReadyCallback = NULL;
+}

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/uart_transport.h

@@ -0,0 +1,48 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#pragma once
+
+#define UART_STRUCTS_VERSION 1
+#include <applibs/uart.h>
+#include "exitcode.h"
+
+typedef void (*UartTransport_DataReadyCallback)(void);
+
+/// <summary>
+///     Initialize the UART transport
+/// </summary>
+/// <param name="eventLoop">Pointer to the main application EventLoop.</param>
+/// <param name="uartId">ID of the UART to open.</param>
+/// <param name="receivedDataCallback">
+///     Function to call when data is ready to be read from the UART.
+/// </param>
+/// <returns>An <see cref="ExitCode" /> indicating success or failure.</returns>
+ExitCode UartTransport_Initialize(EventLoop *eventLoop, UART_Id uartId,
+                                  UartTransport_DataReadyCallback receivedDataCallback);
+
+/// <summary>
+///     Close the UART transport - closes the device and de-registers any events from the EventLoop.
+/// </summary>
+void UartTransport_Cleanup(void);
+
+/// <summary>
+///     Queue data to be sent over the UART. This function will return immediately, but the
+///     transfer may occur asynchronously, completing after the function returns.
+/// </summary>
+/// <param name="buffer">The data to be sent over the UART.</param>
+/// <param name="length">Length of the data to be sent - must not be zero.</param>
+/// <returns>
+///     0 if the UART is not initialized or if the data is too long to send; otherwise, the length
+///     of the queued data.
+/// </returns>
+ssize_t UartTransport_Send(const char *buffer, size_t length);
+
+/// <summary>
+///     Attempt to read data from the UART. This should be called upon receipt of a
+///     <see cref="UartTransport_DataReadyCallBack" />.
+/// </summary>
+/// <param name="buffer">Buffer into which data read from the UART should be written.</param>
+/// <param name="amount">Amount of data to attempt to read.</param>
+/// <returns>The amount of data read, or -1 if the operation failed.</returns>
+ssize_t UartTransport_Read(char *buffer, size_t amount);

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/update.c

@@ -0,0 +1,240 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#include <errno.h>
+#include <string.h>
+
+#include <applibs/eventloop.h>
+#include <applibs/log.h>
+#include <applibs/powermanagement.h>
+#include <applibs/sysevent.h>
+
+#include "eventloop_timer_utilities.h"
+#include "exitcode.h"
+#include "update.h"
+
+static void WaitForUpdatesCheckTimerEventHandler(EventLoopTimer *timer);
+static void WaitForUpdatesDownloadTimerEventHandler(EventLoopTimer *timer);
+static void HandleUpdateEvent(SysEvent_Events event, SysEvent_Status status,
+                              const SysEvent_Info *info, void *context);
+static void NoUpdateAvailable(void);
+static void FinishAndReboot(void);
+static void UpdatesStarted(void);
+static void UpdateReadyForInstall(SysEvent_Status status, const SysEvent_Info *info, void *context);
+static const char *UpdateTypeToString(SysEvent_UpdateType updateType);
+
+static bool businessLogicComplete = false;
+static bool pendingUpdatesDeferred = false;
+
+static Update_UpdatesCompleteCallback updateCompleteCallbackFunc = NULL;
+static ExitCodeCallbackType exitCodeCallbackFunc = NULL;
+static EventRegistration *updateEventRegistration = NULL;
+
+// We allow two minutes for an update check
+static EventLoopTimer *waitForUpdatesCheckTimer = NULL;
+static const struct timespec waitForUpdatesCheckTimerInterval = {.tv_sec = 120, .tv_nsec = 0};
+
+static EventLoopTimer *waitForUpdatesToDownloadTimer = NULL;
+static const struct timespec waitForUpdatesToDownloadTimerInterval = {.tv_sec = 300, .tv_nsec = 0};
+
+ExitCode Update_Initialize(EventLoop *el, Update_UpdatesCompleteCallback updateCompleteCallback,
+                           ExitCodeCallbackType failureCallback)
+{
+    updateEventRegistration =
+        SysEvent_RegisterForEventNotifications(el, SysEvent_Events_Mask, HandleUpdateEvent, NULL);
+    if (updateEventRegistration == NULL) {
+        Log_Debug("ERROR: Failed to register for no-update event notification: %s (%d)\n",
+                  strerror(errno), errno);
+        return ExitCode_Update_Init_NoUpdateEvent;
+    }
+
+    waitForUpdatesCheckTimer =
+        CreateEventLoopDisarmedTimer(el, &WaitForUpdatesCheckTimerEventHandler);
+    if (waitForUpdatesCheckTimer == NULL) {
+        return ExitCode_Update_Init_CreateWaitForUpdatesCheckTimer;
+    }
+    int result =
+        SetEventLoopTimerOneShot(waitForUpdatesCheckTimer, &waitForUpdatesCheckTimerInterval);
+    if (result != 0) {
+        return ExitCode_Update_Init_SetWaitForUpdatesCheckTimer;
+    }
+
+    waitForUpdatesToDownloadTimer =
+        CreateEventLoopDisarmedTimer(el, &WaitForUpdatesDownloadTimerEventHandler);
+    if (waitForUpdatesToDownloadTimer == NULL) {
+        return ExitCode_Update_Init_CreateWaitForUpdatesDownloadTimer;
+    }
+
+    updateCompleteCallbackFunc = updateCompleteCallback;
+    exitCodeCallbackFunc = failureCallback;
+    businessLogicComplete = false;
+    pendingUpdatesDeferred = false;
+
+    return ExitCode_Success;
+}
+
+void Update_Cleanup(void)
+{
+    if (updateEventRegistration != NULL) {
+        SysEvent_UnregisterForEventNotifications(updateEventRegistration);
+    }
+
+    DisposeEventLoopTimer(waitForUpdatesCheckTimer);
+    DisposeEventLoopTimer(waitForUpdatesToDownloadTimer);
+}
+
+void Update_NotifyBusinessLogicComplete(void)
+{
+    businessLogicComplete = true;
+}
+
+static void WaitForUpdatesCheckTimerEventHandler(EventLoopTimer *timer)
+{
+    Log_Debug("WARNING: Timed out waiting for check for updates.\n");
+    ConsumeEventLoopTimerEvent(timer);
+
+    NoUpdateAvailable();
+}
+
+static void WaitForUpdatesDownloadTimerEventHandler(EventLoopTimer *timer)
+{
+    ConsumeEventLoopTimerEvent(timer);
+    Log_Debug("WARNING: Timed out waiting for updates to download.\n");
+
+    FinishAndReboot();
+}
+
+static void HandleUpdateEvent(SysEvent_Events event, SysEvent_Status status,
+                              const SysEvent_Info *info, void *context)
+{
+    // If we've received an update event, we can disable the update check timer.
+    if (DisarmEventLoopTimer(waitForUpdatesCheckTimer) == -1) {
+        Log_Debug("ERROR: Failed to disarm update check timer: %s (%d)\n", strerror(errno), errno);
+    }
+
+    switch (event) {
+    case SysEvent_Events_NoUpdateAvailable:
+        NoUpdateAvailable();
+        break;
+
+    case SysEvent_Events_UpdateStarted:
+        UpdatesStarted();
+        break;
+
+    case SysEvent_Events_UpdateReadyForInstall:
+        UpdateReadyForInstall(status, info, context);
+        break;
+
+    default:
+        Log_Debug("WARNING: Unexpected SysEvent '%u'\n", event);
+        break;
+    }
+}
+
+static void NoUpdateAvailable(void)
+{
+    if (updateCompleteCallbackFunc != NULL) {
+        updateCompleteCallbackFunc(false);
+    } else {
+        Log_Debug("WARNING: No update complete callback handler registered\n");
+    }
+}
+
+static void FinishAndReboot(void)
+{
+    if (updateCompleteCallbackFunc != NULL) {
+        updateCompleteCallbackFunc(true);
+    } else {
+        Log_Debug(
+            "ERROR: No update complete callback handler registered - unable to signal reboot\n");
+    }
+}
+
+static void UpdatesStarted(void)
+{
+    int result = SetEventLoopTimerOneShot(waitForUpdatesToDownloadTimer,
+                                          &waitForUpdatesToDownloadTimerInterval);
+    if (result != 0) {
+        Log_Debug("ERROR: Failed to start update download timer.\n");
+        if (exitCodeCallbackFunc != NULL) {
+            exitCodeCallbackFunc(ExitCode_Update_UpdatesStarted_SetWaitForUpdatesDownloadTimer);
+        } else {
+            Log_Debug("WARNING: No fatal error callback handler registered.\n");
+        }
+    }
+}
+
+static void UpdateReadyForInstall(SysEvent_Status status, const SysEvent_Info *info, void *context)
+{
+    SysEvent_Info_UpdateData data;
+    int result = SysEvent_Info_GetUpdateData(info, &data);
+
+    if (result == -1) {
+        Log_Debug("ERROR: SysEvent_Info_GetUpdateData failed: %s (%d).\n", strerror(errno), errno);
+        if (exitCodeCallbackFunc != NULL) {
+            exitCodeCallbackFunc(ExitCode_Update_UpdateCallback_GetUpdateData);
+        } else {
+            Log_Debug("WARNING: No fatal error callback handler registered.\n");
+        }
+        return;
+    }
+
+    Log_Debug("INFO: Update available - type: %s (%u).\n", UpdateTypeToString(data.update_type),
+              data.update_type);
+
+    switch (status) {
+    case SysEvent_Status_Pending:
+        if (businessLogicComplete) {
+            Log_Debug("INFO: Allowing update.\n");
+            SysEvent_ResumeEvent(SysEvent_Events_UpdateReadyForInstall);
+
+        } else {
+            Log_Debug("INFO: Max deferral time: %u minutes\n", data.max_deferral_time_in_minutes);
+            Log_Debug("INFO: Deferring update for 1 minute.\n");
+            result = SysEvent_DeferEvent(SysEvent_Events_UpdateReadyForInstall, 1);
+
+            if (result == -1) {
+                Log_Debug("ERROR: SysEvent_DeferEvent: %s (%d).\n", strerror(errno), errno);
+                if (exitCodeCallbackFunc != NULL) {
+                    exitCodeCallbackFunc(ExitCode_Update_UpdateCallback_DeferEvent);
+                } else {
+                    Log_Debug("WARNING: No fatal error callback handler registered.\n");
+                }
+            }
+        }
+        break;
+
+    case SysEvent_Status_Final:
+        Log_Debug("INFO: Final update. App will update in 10 seconds.\n");
+        FinishAndReboot();
+        break;
+
+    case SysEvent_Status_Deferred:
+        Log_Debug("INFO: Update deferred.\n");
+        break;
+
+    case SysEvent_Status_Complete:
+    default:
+        Log_Debug("ERROR: Unexpected status %d.\n", status);
+        if (exitCodeCallbackFunc != NULL) {
+            exitCodeCallbackFunc(ExitCode_Update_UpdateCallback_UnexpectedStatus);
+        } else {
+            Log_Debug("WARNING: No fatal error callback handler registered.\n");
+        }
+        break;
+    }
+}
+
+static const char *UpdateTypeToString(SysEvent_UpdateType updateType)
+{
+    switch (updateType) {
+    case SysEvent_UpdateType_Invalid:
+        return "Invalid";
+    case SysEvent_UpdateType_App:
+        return "Application";
+    case SysEvent_UpdateType_System:
+        return "System";
+    default:
+        return "Unknown";
+    }
+}

Samples/DeviceToCloud/ExternalMcuLowPower/AzureSphere_HighLevelApp/update.h

@@ -0,0 +1,39 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#pragma once
+
+#include <applibs/eventloop.h>
+
+#include "exitcode.h"
+
+typedef void (*Update_UpdatesCompleteCallback)(bool rebootRequired);
+
+/// <summary>
+///     Initialize update and powerdown handling. Once called, any pending updates will be deferred
+///     until <see cref="Update_NotifyBusinessLogicComplete" /> is called.
+///     Once any updates have been completed, <paramref name="updateCompleteCallback" /> is
+///     invoked, indicating whether a reboot is required. In the event of a fatal error,
+///     <paramref name="failureCallback" /> is invoked with a suitable exit code.
+/// </summary>
+/// <param name="el">EventLoop to register events and timers.</param>
+/// <param name="updateCompleteCallback">
+///     Function to be invoked when update processing is complete.
+/// </param>
+/// <param name="updateCompleteCallback">
+///     Function to be invoked when a fatal error occurs during update check.
+/// </param>
+/// <returns>An <see cref="ExitCode" /> indicating success or failure.</returns>
+ExitCode Update_Initialize(EventLoop *el, Update_UpdatesCompleteCallback updateCompleteCallback,
+                           ExitCodeCallbackType failureCallback);
+
+/// <summary>
+///     Clean up update handling.
+/// </summary>
+void Update_Cleanup(void);
+
+/// <summary>
+///     Indicate to update handling that business logic is complete (and so pending updates
+///     can now be installed)
+/// </summary>
+void Update_NotifyBusinessLogicComplete(void);

Samples/DeviceToCloud/ExternalMcuLowPower/BuildMcuToCloud.md

@@ -0,0 +1,124 @@
+# Build and deploy the External MCU, Low Power reference solution
+
+To build and run this application you will need to do the following:
+
+- Wire up the external MCU and connect it to an Azure Sphere development board.
+- Create an IoT Central application and add views.
+- Build and deploy the external MCU and MT3620 high-level apps.
+
+## Prerequisites
+
+Set up your device and development environment as described in the [Azure Sphere documentation](https://docs.microsoft.com/azure-sphere/install/overview).  
+
+**Parts list:**
+
+| Quantity        |Item        |
+| ------------- |-------------|
+| 1|NUCLEO-L031K6 - Dev Board |
+| 1|RGB LED|
+| 1|Gadgeteer USB-Serial interface module (optional) |
+| 3|330 Ohm Resistor |
+| 2|4K7 Resistor |
+| 1| Breadboard and pre cut M-M jumper leads|
+| 2|Tactile Switch |
+|1 |150mm F-F jumper leads |
+|7 |200mm M-F jumper leads |
+|5 |200mm M-M jumper leads |
+
+## Wire up the external MCU and connect it to an Azure Sphere development board
+
+![Connection diagram](./media/MCU-to-Cloud-wiring-75.png)
+
+Make the following connections between the STM NUCLEO-L031K6 and MT3620 dev boards using the jumper wires:
+
+- external MCU pin D4 to 330 ohm resistor to RGB LED Pin Blue
+- external MCU pin D5 to 330 ohm resistor to RGB LED Pin Green
+- external MCU pin D9 to Dispense button
+- external MCU pin D10 to Refill button
+- external MCU pin D11 to 330 ohm resistor to RGB LED Pin Red
+- external MCU pin D12 to MT3620 RDB pin H3.4
+- Dispense button to 4.7K pull-up resistor; 4.7K pull-up resistor to power strip (+)
+- Dispense button to ground strip (-) 
+- Refill button to 4.7K pull-up resistor; 4.7K pull-up resistor to power strip (+)
+- Refill button to circuit ground strip (-)
+- RGB LED ground pin to ground strip (-)
+- external MCU pin 3.3v to power strip (+)
+- external MCU pin A2 to MT36220 RDB pin H2.3
+- external MCU pin A7 to MT3620 RDB pin H2.1
+- Ground strip to MT3620 RDB pin H1.2 (GND)
+- external MCU pin GND to ground strip.
+- MT3620 RDB pin H3.2 to MT3620 RDB pin H3.10.
+
+    **Note:** The connection between MT3620 RDB pins H3.2 and H3.10 is not required for RDB versions 1.6 and later.
+
+**Optional debug UART connections**
+
+Output from Log_Debug can also be seen on the optional debug UART. This can be useful for observing application behavior without a debugger connection. For example, after device shutdown or restart.
+
+- MT3620 RDB pin H4.2 to USB-Serial GND
+- MT3620 RDB pin H4.5 to USB-Serial P4
+- MT3620 RDB pin H4.7 to USB-Serial P5
+
+## Build and deploy the MCU app
+
+If you haven't done so already:
+
+- Download and install the [STM32Cube IDE](https://www.st.com/en/development-tools/stm32cubeide.html#get-software).
+
+- Connect the Azure Sphere development board and the NUCLEO-L031K6 developer board to your computer via USB.
+
+To build and run the MCU app do the following:
+
+1. Open the STM32Cube IDE.
+1. In the **File menu** select **Open Projects from File System**.
+1. In the **Import Projects from File System or Archive** window, click **Directory** and navigate to the *McuSoda* folder. Click **Select Folder**.
+1. Click **Finish**.
+1. In the **Project** menu select **Build All**
+1. In the **Run** menu select **Run** or **Debug**.
+
+    **Note:**  The first time you run or debug, a configuration menu will pop up. Select the defaults.
+
+## Create an IoT Central application and add views
+
+To create an IoT Central app, see [IOT Central Setup](./IOTCentralSetup.md).
+
+## Build and deploy the Azure Sphere MT3620 high-level app
+
+To build and run the high-level app, follow the instructions in [Build a sample application](../../BUILD_INSTRUCTIONS.md).
+
+## Run the app
+
+**MCU Interactions:**
+
+On startup the external MCU turns on and waits for the Azure Sphere MT3620 to send it a flavor and color. When the External MCU receives the flavor color from the MT3620, it will turn on the soda dispense color. Each time a new flavor is sent, the external MCU will update the dispense flavor color.
+
+Every 2 minutes, the MT3620 will wake up the external MCU collect data and send the data to IoT Central. This is a default parameter to show data updates in the sample but should be changed to a longer time period for use in a production low power application.
+
+**IoT Central interactions**
+
+1. On startup, the MT3620 connects to IoT Central.
+1. Go to IoT Central and select "devices" and migrate the new device that appears to the Soda Machine Device Template.
+1. Select the device and then select "Next Flavor".
+1. In the flavor box, provide the new flavor name (such as "Cherry") and set the color with the drop down then select save.
+1. In the debug output from the MT3620, you will see the device receive the new flavor and pass it to the external MCU which will light up with the new flavor color.
+
+**User interactions**
+
+- Press the **Dispense** button (connected to pin D9 on the NUCLEO-L031K6 board) to dispense one unit of the soda. The external MCU RGB LED will flash once with the current flavor.
+
+- Press the **Refill** button (connected to pin D10 on the NUCLEO-L031K6 board) to refill the soda machine syrups and carbonated water.
+
+## Build your own solution
+
+To change the following settings, open the configuration.h file (*.../LocalSamples/DeviceToCloud/ExternalMcuLowPower/common/configuration.h*), which is located in the folder and change the value of the corresponding constant.
+
+| Setting  |Default value  | Description  |
+| ------------- |-------------| -----|
+| MachineCapacity |5 |The capacity (maximum units) of the soda machine |
+|LowDispenseAlertThreshold|2|The number of remaining units that will initiate a low stock alert.
+
+## License
+For details on license, see LICENSE.txt in this directory.
+
+## Code of Conduct
+This project has adopted the [Microsoft Open Source Code of Conduct](https://opensource.microsoft.com/codeofconduct/).

Samples/DeviceToCloud/ExternalMcuLowPower/IOTCentralSetup.md

@@ -0,0 +1,85 @@
+
+# IoT Central Setup
+
+## Create an Azure IoT Central application
+
+1. Go to [Azure IoT Central](https://apps.azureiotcentral.com/build) in your browser.
+1. Choose Custom apps and sign in with your Microsoft account, or create a new account.
+1. Use the default Application name and URL or modify it, if you prefer.
+1. Under Application template, choose Custom Application.
+1. Either choose 7 day free trial and provide your contact info, or provide your billing info.
+1. Click **Create** at the bottom of the page.
+
+## Configure the Azure IoT Central application
+
+1. In the left navigation pane on the Home Page, select **Device Templates**
+1. In the **Device Templates** pane, select **+ (New)**.
+1. In the **Select Template Type** pane, select **IoT Device > Next: Customize**. 
+1. Fill in the Device template name with any name you choose (for example: Soda Machine) and select **Next: Review > Create**. 
+1. Select **Import capability model** and select the SodaMachineTemplate.json file from the root folder of the reference solution. 
+
+## Add the views
+
+Add two Views to the Device Template, one to display the soda machine state and one to select the next flavor.
+
+   To display the soda machine state:
+
+   1. Select **Views > Visualizing the device**.
+   1. Customize the **View name** with "Soda Machine State". 
+   1. Drag the **Dispenses (since last update)** telemetry to the empty dotted rectangle to the right side of the form. Use the **Change Visualization** button on the graph to change the view to a KPI. You may also resize the graph using the **Size Available** button to **2x1**.
+   1. Drag the **Lifetime total dispenses** telemetry to the dotted rectangle on the right side of the form. Select the **Settings** button on the graph and then select the **Settings** button on the **Lifetime total dispenses** telemetry value to change the data aggregation from Average to Sum. Select **Update** to save the graph option.
+   1. Drag the **Low Soda** telemetry to the dotted rectangle on the right side of the form. Use the **Change Visualization** button on the graph to change the view to the **Last Known Value**. You may also resize the graph using the **Size Available** button to **1x1**.
+   1. Drag the **Remaining Dispenses** telemetry to the dotted rectangle on the right side of the form. Use the **Change Visualization** button on the graph to change the view to the **Last Known Value**. You may also resize the graph using the **Size Available** button to **1x1**.
+   1. Drag the **Next Flavor** property to the dotted rectangle on the right side of the form.
+   1. The view should look like the following image. Select **Save**.
+
+       ![alt text](./media/IOT1-50.png)
+
+   To select the next flavor:
+
+   1. Select **Views > Editing device and cloud data**
+   1. Customize the **Form name** with "Next Flavor".
+   1. Drag the **Next Flavor** Property to the empty dotted rectangle to the right side of the form.
+   1. The view should look like the following image. Select **Save**.
+   1. Select **Publish > Publish**.
+
+       ![alt text](./media/IOT2-50.png)
+
+## Set up Azure IoT Central to work with Azure Sphere
+
+1. Verify the identity of your Azure Sphere tenant by following the steps in [set up Azure IoT Central](https://docs.microsoft.com/azure-sphere/app-development/setup-iot-central#step-2-download-the-tenant-authentication-ca-certificate). Start at step 2 and perform steps 2-5.
+
+1. Configure the sample application to work with your Azure Sphere tenant and devices.
+
+   To configure the sample application, you'll need to supply the following information in the app_manifest.json file for AzureIoT:
+
+   - The Tenant ID for your Azure Sphere device
+   - The Scope ID for your Azure IoT Central application
+   - The allowed connections for your Azure Sphere device
+  
+    Follow these steps to gather the information and configure the application:
+
+    1. Find the app_manifest.json file in your sample directory and open it.
+
+    1. At the command prompt, run the ShowIoTCentralConfig program from the Windows or Linux folder in the sample repository. For example: On Windows, the path is Samples\AzureIoT\Tools\win-x64\ShowIoTCentralConfig.exe. When running this tool on a Linux machine you may need to explicitly set permissions. For example: From a terminal, run `chmod +x ShowIoTCentralConfig` to set permissions on the tool.
+
+    1. Follow the prompts that the tool provides, and copy the information from the output into the app_manifest.json file. The tool will require the following input:
+
+       *IoT Central App URL* – this can be found in your browser address bar. For Example: http://myiotcentralapp.azureiotcentral.com/. Paste the URL into the **AllowedConnections** field of the app manifest.
+
+       *API token* – this can be generated from your IoT Central application. In the Azure IoT Central application, select **Administration** > **API Tokens** > **Generate Token**, and then provide a name for the  token. For example, "AzureSphereSample" - select **Administrator** as the role, and then click **Generate**. Copy the token to the clipboard. The token starts with **SharedAccessSignature**.
+
+       *ID Scope* - In the Azure IoT Central application, select **Administration** > **Device Connection** and then copy everything in this section and paste it into the **CmdArgs** field of the app manifest.
+
+    1. At the command prompt, run the following command to get the Tenant ID. Paste the GUID for your tenant into the **DeviceAuthentication** field of the app_manifest.json file:
+
+       `azsphere tenant show-selected`
+
+       Your updated app-manifest.json file should look like the following example:
+
+       ![Example app_manifest.json file](media/iot-correct-app-manifest-json-file.png)
+
+    1. Save the updated application manifest.
+
+    1. Ensure that the **Auto approve** option is enabled. From the Azure IoT Central Application, click **Administration** > **Device connection**, then on the **Auto approve** option, select **Enabled**.
+

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/.cproject

@@ -0,0 +1,175 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.388435546">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.388435546" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.388435546" name="Debug" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug">
+					<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.388435546." name="/" resourcePath="">
+						<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug.824446985" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug">
+							<option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.133606226" name="Internal Toolchain Type" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.1095489848" name="Internal Toolchain Version" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.version" value="7-2018-q2-update" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.1152131244" name="Mcu" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" value="STM32L031K6Tx" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.859468634" name="CpuId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.322911612" name="CpuCoreId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1828442017" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" value="NUCLEO-L031K6" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1674766906" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.3 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || NUCLEO-L031K6 || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32L0xx_HAL_Driver/Inc | ../Drivers/CMSIS/Device/ST/STM32L0xx/Include | ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy ||  ||  || USE_HAL_DRIVER | STM32L031xx ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32L031K6TX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o || " valueType="string"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.387359702" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
+							<builder buildPath="${workspace_loc:/TestProject}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.34611706" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.914759136" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.671018911" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g3" valueType="enumerated"/>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.2087071939" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1987663650" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.813850699" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.639114195" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.og" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.1684522751" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32L031xx"/>
+									<listOptionValue builtIn="false" value="DEBUG"/>
+								</option>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.1270628286" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../Core/Inc"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32L0xx_HAL_Driver/Inc"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32L0xx/Include"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy"/>
+									<listOptionValue builtIn="false" value="../../common"/>
+								</option>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1493741992" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.1574647299" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.1884844094" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.893290985" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false"/>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.1692878088" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.1224040559" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32L031K6TX_FLASH.ld}" valueType="string"/>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.92009347" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.188619915" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script.55786821" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script" value="${workspace_loc:/${ProjName}/STM32L031K6TX_FLASH.ld}" valueType="string"/>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.12916426" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.952405826" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.466721134" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.241900337" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1342886619" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1688260045" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1049220989" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.595019107" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+		<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1867315447">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1867315447" moduleId="org.eclipse.cdt.core.settings" name="Release">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1867315447" name="Release" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release">
+					<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1867315447." name="/" resourcePath="">
+						<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release.97435642" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release">
+							<option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.1535934397" name="Internal Toolchain Type" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.504203182" name="Internal Toolchain Version" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.version" value="7-2018-q2-update" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.2026044751" name="Mcu" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" value="STM32L031K6Tx" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1685640649" name="CpuId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.2000236084" name="CpuCoreId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1618837" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" value="NUCLEO-L031K6" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1556982071" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.3 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || NUCLEO-L031K6 || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32L0xx_HAL_Driver/Inc | ../Drivers/CMSIS/Device/ST/STM32L0xx/Include | ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy ||  ||  || USE_HAL_DRIVER | STM32L031xx ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32L031K6TX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o || " valueType="string"/>
+							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.97893365" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
+							<builder buildPath="${workspace_loc:/TestProject}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.420007328" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.1540949100" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.1888942259" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.1007736118" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1317458854" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.771419166" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.165424119" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.os" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.1842505306" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
+									<listOptionValue builtIn="false" value="STM32L031xx"/>
+								</option>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.803811958" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
+									<listOptionValue builtIn="false" value="../Core/Inc"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32L0xx_HAL_Driver/Inc"/>
+									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32L0xx/Include"/>
+									<listOptionValue builtIn="false" value="../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy"/>
+									<listOptionValue builtIn="false" value="../../common"/>
+								</option>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.978499503" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.618151577" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.642384622" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.1231709710" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.value.os" valueType="enumerated"/>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.1832036776" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.703284553" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32L031K6TX_FLASH.ld}" valueType="string"/>
+								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.21878320" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.2056111718" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script.1769333585" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.option.script" value="${workspace_loc:/${ProjName}/STM32L031K6TX_FLASH.ld}" valueType="string"/>
+							</tool>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.1483780237" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.101318428" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.905872938" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.1248162737" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1381702981" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.468010063" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.167868253" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
+							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1773452878" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="TestProject.null.987032273" name="TestProject"/>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.388435546;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.388435546.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1987663650;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1493741992">
+			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1867315447;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1867315447.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1317458854;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.978499503">
+			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="refreshScope"/>
+</cproject>

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/.mxproject

@@ -0,0 +1,25 @@
+[PreviousLibFiles]
+LibFiles=Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h;Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h;Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l031xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;
+
+[PreviousUsedCubeIDEFiles]
+SourceFiles=Core\Src\main.c;Core\Src\stm32l0xx_it.c;Core\Src\stm32l0xx_hal_msp.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c;Core\Src/system_stm32l0xx.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c;Core\Src/system_stm32l0xx.c;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;;
+HeaderPath=Drivers\STM32L0xx_HAL_Driver\Inc;Drivers\STM32L0xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32L0xx\Include;Drivers\CMSIS\Include;Core\Inc;
+CDefines=USE_HAL_DRIVER;STM32L031xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
+[PreviousGenFiles]
+AdvancedFolderStructure=true
+HeaderFileListSize=3
+HeaderFiles#0=./Core/Inc/stm32l0xx_it.h
+HeaderFiles#1=./Core/Inc/stm32l0xx_hal_conf.h
+HeaderFiles#2=./Core/Inc/main.h
+HeaderFolderListSize=1
+HeaderPath#0=./Core/Inc
+HeaderFiles=;
+SourceFileListSize=3
+SourceFiles#0=./Core/Src/stm32l0xx_it.c
+SourceFiles#1=./Core/Src/stm32l0xx_hal_msp.c
+SourceFiles#2=./Core/Src/main.c
+SourceFolderListSize=1
+SourcePath#0=./Core/Src
+SourceFiles=;
+

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/.project

@@ -0,0 +1,65 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>McuSoda</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.st.stm32cube.ide.mcu.MCUProjectNature</nature>
+		<nature>com.st.stm32cube.ide.mcu.MCUCubeProjectNature</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAProjectNature</nature>
+		<nature>com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature</nature>
+		<nature>com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature</nature>
+		<nature>com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature</nature>
+		<nature>com.st.stm32cube.ide.mcu.MCURootProjectNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Core/Inc/configuration.h</name>
+			<type>1</type>
+			<locationURI>PARENT-1-PROJECT_LOC/common/configuration.h</locationURI>
+		</link>
+		<link>
+			<name>Core/Inc/message_protocol_private.h</name>
+			<type>1</type>
+			<locationURI>PARENT-1-PROJECT_LOC/common/message_protocol_private.h</locationURI>
+		</link>
+		<link>
+			<name>Core/Inc/message_protocol_public.h</name>
+			<type>1</type>
+			<locationURI>PARENT-1-PROJECT_LOC/common/message_protocol_public.h</locationURI>
+		</link>
+		<link>
+			<name>Core/Inc/message_protocol_utilities.h</name>
+			<type>1</type>
+			<locationURI>PARENT-1-PROJECT_LOC/common/message_protocol_utilities.h</locationURI>
+		</link>
+		<link>
+			<name>Core/Inc/messages.h</name>
+			<type>1</type>
+			<locationURI>PARENT-1-PROJECT_LOC/common/messages.h</locationURI>
+		</link>
+		<link>
+			<name>Core/Src/message_protocol_utilities.c</name>
+			<type>1</type>
+			<locationURI>PARENT-1-PROJECT_LOC/common/message_protocol_utilities.c</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Core/Inc/main.h

@@ -0,0 +1,133 @@
+/* USER CODE BEGIN Header */
+/* Portions copyright Microsoft. */
+/**
+  ******************************************************************************
+  * @file           : main.h
+  * @brief          : Header for main.c file.
+  *                   This file contains the common defines of the application.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include <stdbool.h>
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+_Noreturn void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+extern UART_HandleTypeDef huart2;
+
+#define NO_PREV_ISR					0xFFFFFFFF
+#define DEBOUNCE_PERIOD_MS			250
+// The GPIO which wakes up the MT3620 is held low for this amount of time.
+// This must be less than DEBOUNCE_PERIOD_MS, else the main loop in soda.c
+// will go into WFI without systick enabled before the period ends.
+#define TO_MT3620_WAKEUP_PERIOD_MS	10
+
+extern __IO uint32_t lastActivity;
+
+typedef struct {
+	// Maximum number of units this machine can hold.
+	const int machineCapacity;
+	// When the number of units reaches this value, alert the MT3620.
+	const int alertThreshold;
+	// Total number of units which have been added to this machine.
+	// (Not the current number of units in the machine.)
+	int stockedDispenses;
+	// Total number of units which have been dispensed.
+	int issuedDispenses;
+} MachineState;
+
+extern MachineState state;
+
+_Noreturn void RunSodaMachine(void);
+void ReadMessageAsync(void);
+
+void HandleWakeupFromMT3620(void);
+void HandleButtonPress(void);
+void HandleMessage(void);
+void StopWakingUpMT3620(void);
+
+void RestoreStateFromFlash(void);
+void WriteLatestMachineState(void);
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define MT3620_TO_MCU_WAKEUP_Pin GPIO_PIN_0
+#define MT3620_TO_MCU_WAKEUP_GPIO_Port GPIOA
+#define MT3620_TO_MCU_WAKEUP_EXTI_IRQn EXTI0_1_IRQn
+#define VCP_TX_Pin GPIO_PIN_2
+#define VCP_TX_GPIO_Port GPIOA
+#define VCP_RX_Pin GPIO_PIN_3
+#define VCP_RX_GPIO_Port GPIOA
+#define DISPENSE_Pin GPIO_PIN_8
+#define DISPENSE_GPIO_Port GPIOA
+#define DISPENSE_EXTI_IRQn EXTI4_15_IRQn
+#define RESTOCK_Pin GPIO_PIN_11
+#define RESTOCK_GPIO_Port GPIOA
+#define RESTOCK_EXTI_IRQn EXTI4_15_IRQn
+#define TMS_Pin GPIO_PIN_13
+#define TMS_GPIO_Port GPIOA
+#define TCK_Pin GPIO_PIN_14
+#define TCK_GPIO_Port GPIOA
+#define LD3_Pin GPIO_PIN_3
+#define LD3_GPIO_Port GPIOB
+#define MCU_TO_MT3620_WAKEUP_Pin GPIO_PIN_4
+#define MCU_TO_MT3620_WAKEUP_GPIO_Port GPIOB
+#define TRILED_R_Pin GPIO_PIN_5
+#define TRILED_R_GPIO_Port GPIOB
+#define TRILED_G_Pin GPIO_PIN_6
+#define TRILED_G_GPIO_Port GPIOB
+#define TRILED_B_Pin GPIO_PIN_7
+#define TRILED_B_GPIO_Port GPIOB
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Core/Inc/stm32l0xx_hal_conf.h

@@ -0,0 +1,302 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration template file. 
+  *          This file should be copied to the application folder and renamed
+  *          to stm32l0xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the 
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_CONF_H
+#define __STM32L0xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+
+#define HAL_MODULE_ENABLED  
+  /*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CRC_MODULE_ENABLED   */
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_DAC_MODULE_ENABLED   */
+/*#define HAL_FIREWALL_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_LCD_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_TSC_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_EXTI_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal Multiple Speed oscillator (MSI) default value.
+  *        This value is the default MSI range value after Reset.
+  */
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)2097000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+   
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator for USB (HSI48) value.
+  */
+#if !defined  (HSI48_VALUE) 
+#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI48_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  ((uint32_t)37000U)       /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/   
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT  ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */           
+#define  TICK_INT_PRIORITY            ((uint32_t)0U)    /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U     
+#define  PREFETCH_ENABLE              0U              
+#define  PREREAD_ENABLE               1U
+#define  BUFFER_CACHE_DISABLE         0U
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32l0xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32l0xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32l0xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32l0xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+   
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32l0xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32l0xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32l0xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+   
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32l0xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32l0xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32l0xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FIREWALL_MODULE_ENABLED
+  #include "stm32l0xx_hal_firewall.h"
+#endif /* HAL_FIREWALL_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32l0xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+ 
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32l0xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32l0xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32l0xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32l0xx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32l0xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+   
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32l0xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32l0xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32l0xx_hal_rtc.h"
+
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32l0xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32l0xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+ #include "stm32l0xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32l0xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32l0xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32l0xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32l0xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32l0xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32l0xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32l0xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_CONF_H */
+ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Core/Inc/stm32l0xx_it.h

@@ -0,0 +1,68 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_it.h
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+ ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_IT_H
+#define __STM32L0xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void SVC_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void EXTI0_1_IRQHandler(void);
+void EXTI4_15_IRQHandler(void);
+void USART2_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Core/Src/button.c

@@ -0,0 +1,151 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#include "main.h"
+
+static void SetFlagIfDebounceExpired(uint32_t *lastIsrTime, __IO bool *event);
+static void WakeUpMT3620(void);
+
+// The last time (in ticks) when an interrupt (button, wakeup, or UART) occurred.
+__IO uint32_t lastActivity = NO_PREV_ISR;
+
+// Called when an event occurs. If less than DEBOUNCE_PERIOD_MS have elapsed
+// since the event was last recorded, sets *event to true. Otherwise does nothing.
+static void SetFlagIfDebounceExpired(uint32_t *lastIsrTime, __IO bool *event)
+{
+	bool expired = false;
+	uint32_t currentTime = HAL_GetTick();
+
+	lastActivity = currentTime;
+
+	// Is this the first interrupt?
+	if (*lastIsrTime == NO_PREV_ISR) {
+		expired = true;
+	}
+	// Has current time wrapped around?
+	else if (currentTime < *lastIsrTime) {
+		expired = true;
+	}
+	// Has enough time passed since the last interrupt?
+	else if (currentTime - *lastIsrTime > DEBOUNCE_PERIOD_MS) {
+		expired = true;
+	}
+
+	if (expired) {
+		*lastIsrTime = currentTime;
+		*event = true;
+	}
+}
+
+static __IO bool dispenseButtonPressed = false;
+static uint32_t dispenseIsrTime = NO_PREV_ISR;
+
+static __IO bool restockButtonPressed = false;
+static uint32_t restockIsrTime = NO_PREV_ISR;
+
+static __IO bool wakeupSignalReceived = false;
+static uint32_t wakeupIsrTime = NO_PREV_ISR;
+
+// Handle button press or wakeup interrupt.
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+	switch (GPIO_Pin) {
+	case DISPENSE_Pin:
+		SetFlagIfDebounceExpired(&dispenseIsrTime, &dispenseButtonPressed);
+		break;
+	case RESTOCK_Pin:
+		SetFlagIfDebounceExpired(&restockIsrTime, &restockButtonPressed);
+		break;
+	case MT3620_TO_MCU_WAKEUP_Pin:
+		SetFlagIfDebounceExpired(&wakeupIsrTime, &wakeupSignalReceived);
+		break;
+	default:
+		Error_Handler();
+		break;
+	}
+}
+
+// Called from non-interrupt context to check whether any buttons have
+// been pressed.
+void HandleButtonPress(void)
+{
+	int availUnits = state.stockedDispenses - state.issuedDispenses;
+
+	if (dispenseButtonPressed) {
+		if (availUnits == 0) {
+			// Cannot dispense because no stock.
+		} else {
+			// If require restock then wake up the MT3620. This only happens when the
+			// inventory passes the threshold. It does not happen for every subsequent dispense.
+			if (availUnits - 1 == state.alertThreshold) {
+				WakeUpMT3620();
+			}
+
+			++state.issuedDispenses;
+			// In a real application, would not necessarily write to flash for every update.
+			// This statement is included to demonstrate how the storage mechanism works.
+			WriteLatestMachineState();
+		}
+
+		dispenseButtonPressed = false;
+	}
+
+	if (restockButtonPressed) {
+		int unitsToAdd = state.machineCapacity - availUnits;
+
+		state.stockedDispenses += unitsToAdd;
+		restockButtonPressed = false;
+
+		// In a real application, would not necessarily write to flash for every update.
+		// This statement is included to demonstrate how the storage mechanism works.
+		if (unitsToAdd > 0) {
+			WriteLatestMachineState();
+		}
+
+		WakeUpMT3620();
+	}
+}
+
+void HandleWakeupFromMT3620(void)
+{
+	if (wakeupSignalReceived) {
+		// The MT3620 has driven the GPIO low to indicate the MCU should wake up.
+		wakeupSignalReceived = false;
+	}
+}
+
+// Whether the wakeup GPIO is being held high.
+static bool mt3620BeingWokenUp = false;
+// If mt3620BeingWokenUp is true, when the wakeup GPIO was pulled high.
+static uint32_t mt3620WakeUpEndTime;
+
+static void WakeUpMT3620(void)
+{
+	if (mt3620BeingWokenUp) {
+		return;
+	}
+
+	// Pull GPIO line low for at least 1ms to wake up MT3620.
+	HAL_GPIO_WritePin(MCU_TO_MT3620_WAKEUP_GPIO_Port, MCU_TO_MT3620_WAKEUP_Pin, GPIO_PIN_RESET);
+
+	uint32_t currentTime = HAL_GetTick();
+	mt3620WakeUpEndTime = currentTime + TO_MT3620_WAKEUP_PERIOD_MS;
+	mt3620BeingWokenUp = true;
+}
+
+// Called from non-interrupt context to stop waking up the MT3620 if required.
+void StopWakingUpMT3620(void)
+{
+	if (! mt3620BeingWokenUp) {
+		return;
+	}
+
+	uint32_t currentTime = HAL_GetTick();
+	if (currentTime <= mt3620WakeUpEndTime) {
+		return;
+	}
+
+	// Pull GPIO line back high. MT3620 should be restarting by now.
+	HAL_GPIO_WritePin(MCU_TO_MT3620_WAKEUP_GPIO_Port, MCU_TO_MT3620_WAKEUP_Pin, GPIO_PIN_SET);
+	mt3620BeingWokenUp = false;
+}

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Core/Src/main.c

@@ -0,0 +1,278 @@
+/* USER CODE BEGIN Header */
+/* Portions copyright Microsoft. */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+UART_HandleTypeDef huart2;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_USART2_UART_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_USART2_UART_Init();
+  /* USER CODE BEGIN 2 */
+  RunSodaMachine();
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+
+  /** Configure the main internal regulator output voltage 
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4;
+  RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2;
+  PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief USART2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART2_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART2_Init 0 */
+
+  /* USER CODE END USART2_Init 0 */
+
+  /* USER CODE BEGIN USART2_Init 1 */
+
+  /* USER CODE END USART2_Init 1 */
+  huart2.Instance = USART2;
+  huart2.Init.BaudRate = 115200;
+  huart2.Init.WordLength = UART_WORDLENGTH_8B;
+  huart2.Init.StopBits = UART_STOPBITS_1;
+  huart2.Init.Parity = UART_PARITY_NONE;
+  huart2.Init.Mode = UART_MODE_TX_RX;
+  huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart2.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART2_Init 2 */
+  /* USER CODE END USART2_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOB, LD3_Pin|TRILED_R_Pin|TRILED_G_Pin|TRILED_B_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(MCU_TO_MT3620_WAKEUP_GPIO_Port, MCU_TO_MT3620_WAKEUP_Pin, GPIO_PIN_SET);
+
+  /*Configure GPIO pin : MT3620_TO_MCU_WAKEUP_Pin */
+  GPIO_InitStruct.Pin = MT3620_TO_MCU_WAKEUP_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
+  GPIO_InitStruct.Pull = GPIO_PULLUP;
+  HAL_GPIO_Init(MT3620_TO_MCU_WAKEUP_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : DISPENSE_Pin RESTOCK_Pin */
+  GPIO_InitStruct.Pin = DISPENSE_Pin|RESTOCK_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : LD3_Pin MCU_TO_MT3620_WAKEUP_Pin TRILED_R_Pin TRILED_G_Pin 
+                           TRILED_B_Pin */
+  GPIO_InitStruct.Pin = LD3_Pin|MCU_TO_MT3620_WAKEUP_Pin|TRILED_R_Pin|TRILED_G_Pin 
+                          |TRILED_B_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* EXTI interrupt init*/
+  HAL_NVIC_SetPriority(EXTI0_1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(EXTI0_1_IRQn);
+
+  HAL_NVIC_SetPriority(EXTI4_15_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(EXTI4_15_IRQn);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+_Noreturn void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+	// Switch on LED and spin, to tell user something is wrong.
+	HAL_GPIO_WritePin(LD3_GPIO_Port, LD3_Pin, GPIO_PIN_SET);
+	for (;;) {
+		// empty.
+	}
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Core/Src/message.c

@@ -0,0 +1,190 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#include <string.h>
+#include "main.h"
+
+#include "messages.h"
+#include "message_protocol_utilities.h"
+
+static void ReadMessageNextByteAsync(void);
+
+static void HandleRequest(const MessageProtocol_RequestMessage *request);
+static void HandleInitRequest(const MessageProtocol_RequestMessage *request);
+static void HandleTelemetryRequest(const MessageProtocol_RequestMessage *request);
+static void HandleSetLedRequest(const MessageProtocol_RequestMessage *request);
+
+static void SendMessageLen(uint8_t *msg, uint16_t len);
+static void SendResponse(
+	const MessageProtocol_RequestMessage *request, void *body, size_t bodyLength);
+
+static __IO ITStatus rxStatus;
+static size_t rxBytesReceived;
+static uint8_t _Alignas(MessageProtocol_RequestMessage) rxBuffer[sizeof(MessageProtocol_RequestMessage)];
+
+// Moved from RESET -> SET when TX completes.
+static __IO ITStatus txStatus;
+static MessageProtocol_ResponseMessage txResponse;
+
+void ReadMessageAsync(void)
+{
+	rxStatus = RESET;
+	rxBytesReceived = 0;
+
+	ReadMessageNextByteAsync();
+}
+
+// Read a single byte from the UART which is connected to the Azure Sphere device.
+static void ReadMessageNextByteAsync(void)
+{
+	if (HAL_UART_Receive_IT(&huart2, &rxBuffer[rxBytesReceived], 1) != HAL_OK) {
+		Error_Handler();
+	}
+}
+
+// Called when the MCU has received a single byte from the Azure Sphere device.
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef * handle)
+{
+	lastActivity = HAL_GetTick();
+
+	// If latest data would overflow RX buffer then abort.
+	size_t currLength = ++rxBytesReceived;
+	if (currLength > sizeof(rxBuffer)) {
+		Error_Handler();
+	}
+
+	// If still in header and does not match expected header then discard.
+	// This discards noise at the beginning of the transfer.
+	if (currLength <= sizeof(MessageProtocol_MessagePreamble)) {
+		if (rxBuffer[currLength - 1] != MessageProtocol_MessagePreamble[currLength - 1]) {
+			rxBytesReceived = 0;
+			ReadMessageNextByteAsync();
+			return;
+		}
+	}
+
+	// If received an entire message, set a flag to handle the message when
+	// the ISR completes. Otherwise, read another byte from the Azure Sphere device.
+	if (MessageProtocol_IsMessageComplete(rxBuffer, currLength)) {
+		rxStatus = SET;
+	} else {
+		ReadMessageNextByteAsync();
+	}
+}
+
+// Called from non-interrupt context to handle a message.
+void HandleMessage(void)
+{
+	// Do nothing if a completed message has not yet been received.
+	if (rxStatus == RESET) {
+		return;
+	}
+
+	// Listen for the next command. This should occur before the response
+	// has been sent because the attached device may send the next request
+	// before the MCU has begun to wait for it.
+	ReadMessageAsync();
+
+	const MessageProtocol_MessageHeaderWithType *header = (MessageProtocol_MessageHeaderWithType *) rxBuffer;
+	if (header->type == MessageProtocol_RequestMessageType) {
+		HandleRequest((const MessageProtocol_RequestMessage *) header);
+	}
+
+	// Abort if unrecognized message type.
+	else {
+		Error_Handler();
+	}
+}
+
+static void HandleRequest(const MessageProtocol_RequestMessage *request)
+{
+    if (request->requestHeader.requestId == MessageProtocol_McuToCloud_Init) {
+    	HandleInitRequest(request);
+    } else if (request->requestHeader.requestId == MessageProtocol_McuToCloud_RequestTelemetry) {
+    	HandleTelemetryRequest(request);
+    } else if (request->requestHeader.requestId == MessageProtocol_McuToCloud_SetLed) {
+    	HandleSetLedRequest(request);
+    }
+
+    // Abort if unrecognized request type.
+    else {
+    	Error_Handler();
+    }
+}
+
+static void HandleInitRequest(const MessageProtocol_RequestMessage *request)
+{
+	SendResponse(request, /* body */ NULL, /* bodyLength */ 0);
+}
+
+static void HandleTelemetryRequest(const MessageProtocol_RequestMessage *request)
+{
+	MessageProtocol_McuToCloud_TelemetryStruct t = {
+		.lifetimeTotalDispenses = state.issuedDispenses,
+		.lifetimeTotalStockedDispenses = state.stockedDispenses,
+		.capacity = state.machineCapacity
+	};
+
+	SendResponse(request, &t, sizeof(t));
+}
+
+static void HandleSetLedRequest(const MessageProtocol_RequestMessage *request)
+{
+	const MessageProtocol_McuToCloud_SetLedStruct *sls =
+		(const MessageProtocol_McuToCloud_SetLedStruct *) request->data;
+
+	HAL_GPIO_WritePin(TRILED_R_GPIO_Port, TRILED_R_Pin, sls->red ? GPIO_PIN_SET : GPIO_PIN_RESET);
+	HAL_GPIO_WritePin(TRILED_G_GPIO_Port, TRILED_G_Pin, sls->green ? GPIO_PIN_SET : GPIO_PIN_RESET);
+	HAL_GPIO_WritePin(TRILED_B_GPIO_Port, TRILED_B_Pin, sls->blue ? GPIO_PIN_SET : GPIO_PIN_RESET);
+
+	// Echo back LEDStruct as a response.
+	SendResponse(request, (void *)sls, sizeof(*sls));
+}
+
+static void SendMessageLen(uint8_t *msg, uint16_t len)
+{
+	txStatus = RESET;
+
+	if (HAL_UART_Transmit_IT(&huart2, msg, len) != HAL_OK) {
+		Error_Handler();
+	}
+
+	while (txStatus != SET) {
+		// empty.
+	}
+}
+
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *handle)
+{
+	lastActivity = HAL_GetTick();
+	txStatus = SET;
+}
+
+// Populates the response object based on the supplied request and copies
+// the supplied payload (if any) into the response.
+static void SendResponse(
+	const MessageProtocol_RequestMessage *request, void *body, size_t bodyLength)
+{
+	memset(&txResponse, 0, sizeof(txResponse));
+
+    memcpy(&txResponse.responseHeader.messageHeaderWithType.messageHeader.preamble,
+        MessageProtocol_MessagePreamble, sizeof(MessageProtocol_MessagePreamble));
+	txResponse.responseHeader.messageHeaderWithType.messageHeader.length =
+		(uint16_t) (
+			sizeof(MessageProtocol_ResponseHeader) - sizeof(MessageProtocol_MessageHeader) + bodyLength);
+	txResponse.responseHeader.messageHeaderWithType.type = MessageProtocol_ResponseMessageType;
+	txResponse.responseHeader.messageHeaderWithType.reserved = 0;
+
+	txResponse.responseHeader.categoryId = request->requestHeader.categoryId;
+	txResponse.responseHeader.requestId = request->requestHeader.requestId;
+	txResponse.responseHeader.sequenceNumber = request->requestHeader.sequenceNumber;
+	txResponse.responseHeader.responseResult = 0;
+	txResponse.responseHeader.reserved = 0;
+
+	if (body != NULL) {
+		memcpy(&txResponse.data, body, bodyLength);
+	}
+
+	SendMessageLen((uint8_t *)&txResponse, sizeof(txResponse));
+}
+

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Core/Src/persist.c

@@ -0,0 +1,128 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#include "main.h"
+
+// Persistent storage takes up two 128-byte pages of flash at 0x0800_4000, which is
+// 16KB after the start of flash. If the application code extends into this page, the
+// data page must be moved.
+//
+// The first page contains the magic words <"MSAS", "SODA">, followed by a sequence of
+// <stocked, issued> pairs.
+//
+// When the application starts, it reads the first two words of the first page.  If they
+// are not contain the magic values, it erases both pages, which sets all bytes to 0x00.
+// The application then writes the magic words to the start of the first page.
+//
+// When the application stores a new <stocked, issued> pair, it overwrites the first pair
+// of <0x00000000, 0x00000000> words that it finds. If all pages are full, it erases them,
+// re-writes the magic header, followed by the state, to the start of the first page.
+//
+// This is intentionally simple.  In a full application, the number of erase cycles could
+// be reduced by only writing the machine state when it powers down.
+
+static void EraseAllPages(void);
+static void ReadStateFromExistingPage(void);
+
+#define DATA_AREA_ADDR		(FLASH_BASE + (128 * FLASH_PAGE_SIZE))
+#define DATA_AREA_LENGTH	(2 * FLASH_PAGE_SIZE)
+#define DATA_AREA_END		(DATA_AREA_ADDR + DATA_AREA_LENGTH)
+
+static const uint32_t DATA_AREA_SECTORS = OB_WRP_Pages128to159;
+
+static const uint32_t MAGIC_WORD_0 = ('M' << 24) | ('S' << 16) | ('A' << 8) | 'S';
+static const uint32_t MAGIC_WORD_1 = ('S' << 24) | ('O' << 16) | ('D' << 8) | 'A';
+static const uint32_t MAGIC_HEADER_SIZE = 2 * sizeof(uint32_t);
+
+// { uint32_t stocked; uint32_t issued; }
+static const uint32_t DATA_ENTRY_SIZE = 2 * sizeof(uint32_t);
+
+// Address in flash where last valid entry was written.
+static uint32_t lastEntryAddr;
+
+void RestoreStateFromFlash(void)
+{
+	HAL_FLASH_Unlock();
+	HAL_FLASH_OB_Unlock();
+
+	FLASH_OBProgramInitTypeDef ob = { };
+	HAL_FLASHEx_OBGetConfig(&ob);
+
+	// Ensure page is not write-protected.
+	// (If it is, write-protection can be disabled with HAL_FLASHEx_OBProgram.)
+	if ((ob.WRPSector & DATA_AREA_SECTORS) == DATA_AREA_SECTORS) {
+		Error_Handler();
+	}
+
+	uint32_t magic0 = *(__IO uint32_t*) DATA_AREA_ADDR;
+	uint32_t magic1 = *(__IO uint32_t*) (DATA_AREA_ADDR + sizeof(uint32_t));
+
+	// If this is the first time that the device has been used, erase the data page.
+	bool hasBeenFormatted = (magic0 == MAGIC_WORD_0 && magic1 == MAGIC_WORD_1);
+	if (! hasBeenFormatted) {
+		EraseAllPages();
+	} else {
+		ReadStateFromExistingPage();
+	}
+}
+
+// Erase all pages which are used to store the machine state and write
+// the magic header followed by the current machine state to the start
+// of the first page.
+static void EraseAllPages(void)
+{
+	FLASH_EraseInitTypeDef ei = { };
+	ei.TypeErase = FLASH_TYPEERASE_PAGES;
+	ei.PageAddress = DATA_AREA_ADDR;
+	ei.NbPages = DATA_AREA_LENGTH / FLASH_PAGE_SIZE;
+
+	uint32_t pageError;
+
+	if (HAL_FLASHEx_Erase(&ei, &pageError) != HAL_OK) {
+		Error_Handler();
+	}
+
+	HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, DATA_AREA_ADDR + 0 * sizeof(uint32_t), MAGIC_WORD_0);
+	HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, DATA_AREA_ADDR + 1 * sizeof(uint32_t), MAGIC_WORD_1);
+
+	lastEntryAddr = DATA_AREA_ADDR + MAGIC_HEADER_SIZE;
+	HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, lastEntryAddr, ~state.stockedDispenses);
+	HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, lastEntryAddr + sizeof(uint32_t), ~state.issuedDispenses);
+}
+
+// Populate the global state variable with the most recently-written data.
+// This assumes the data pages have already been initialized with EraseAllPages.
+static void ReadStateFromExistingPage(void)
+{
+	// Find the most recently-written data entry.
+	uint32_t searchAddr = DATA_AREA_ADDR + MAGIC_HEADER_SIZE;
+	while (searchAddr < DATA_AREA_END) {
+		uint32_t searchStockCmpl = *(__IO uint32_t*) searchAddr;
+		if (searchStockCmpl == 0x0) {
+			break;
+		}
+		searchAddr += DATA_ENTRY_SIZE;
+	}
+
+	lastEntryAddr = searchAddr - DATA_ENTRY_SIZE;
+	uint32_t stockCmpl = *(__IO uint32_t*) lastEntryAddr;
+	state.stockedDispenses = ~stockCmpl;
+	uint32_t dispCmpl = *(__IO uint32_t*) (lastEntryAddr + sizeof(uint32_t));
+	state.issuedDispenses = ~dispCmpl;
+}
+
+// Append the current machine state to the flash memory. If the flash memory has been
+// exhausted, erase it and write the state to the start of the first page.
+void WriteLatestMachineState(void)
+{
+	lastEntryAddr += DATA_ENTRY_SIZE;
+
+	if (lastEntryAddr >= DATA_AREA_END) {
+		EraseAllPages();
+	} else {
+		HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, lastEntryAddr, ~state.stockedDispenses);
+		HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, lastEntryAddr + sizeof(uint32_t), ~state.issuedDispenses);
+	}
+}
+
+

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Core/Src/soda.c

@@ -0,0 +1,44 @@
+/* Copyright (c) Microsoft Corporation. All rights reserved.
+   Licensed under the MIT License. */
+
+#include <stdbool.h>
+#include <string.h>
+#include <stdio.h>
+
+#include "configuration.h"
+#include "main.h"
+
+// Initial machine state. The first time this program is run this state
+// is written to NVM. Thereafter, the initial state is loaded from NVM.
+MachineState state = {
+	.machineCapacity = MachineCapacity,
+	.alertThreshold = LowDispenseAlertThreshold,
+	.stockedDispenses = 0,
+	.issuedDispenses = 0
+};
+
+// Infinite loop waits for and then handled external events, viz. button press,
+// wakeup, and UART RX.
+_Noreturn void RunSodaMachine(void)
+{
+	RestoreStateFromFlash();
+
+	ReadMessageAsync();
+	for (;;) {
+		HAL_SuspendTick();
+		HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+		HAL_ResumeTick();
+
+		// The system tick is stopped during WFI, so don't sleep if still in
+		// a debounce period because when the device wakes because of an interrupt,
+		// the handler will think it is still in the debounce period.
+
+		while (lastActivity == NO_PREV_ISR || HAL_GetTick() < lastActivity + (2 * DEBOUNCE_PERIOD_MS)) {
+			HandleWakeupFromMT3620();
+			StopWakingUpMT3620();
+			HandleButtonPress();
+			HandleMessage();
+		}
+	}
+}
+

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Core/Src/stm32l0xx_hal_msp.c

@@ -0,0 +1,154 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32l0xx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(huart->Instance==USART2)
+  {
+  /* USER CODE BEGIN USART2_MspInit 0 */
+
+  /* USER CODE END USART2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART2_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**USART2 GPIO Configuration    
+    PA2     ------> USART2_TX
+    PA3     ------> USART2_RX 
+    */
+    GPIO_InitStruct.Pin = VCP_TX_Pin|VCP_RX_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF4_USART2;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* USART2 interrupt Init */
+    HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(USART2_IRQn);
+  /* USER CODE BEGIN USART2_MspInit 1 */
+
+  /* USER CODE END USART2_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==USART2)
+  {
+  /* USER CODE BEGIN USART2_MspDeInit 0 */
+
+  /* USER CODE END USART2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART2_CLK_DISABLE();
+  
+    /**USART2 GPIO Configuration    
+    PA2     ------> USART2_TX
+    PA3     ------> USART2_RX 
+    */
+    HAL_GPIO_DeInit(GPIOA, VCP_TX_Pin|VCP_RX_Pin);
+
+    /* USART2 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(USART2_IRQn);
+  /* USER CODE BEGIN USART2_MspDeInit 1 */
+
+  /* USER CODE END USART2_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Core/Src/stm32l0xx_it.c

@@ -0,0 +1,188 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_it.c
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32l0xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern UART_HandleTypeDef huart2;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex-M0+ Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable Interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVC_IRQn 0 */
+
+  /* USER CODE END SVC_IRQn 0 */
+  /* USER CODE BEGIN SVC_IRQn 1 */
+
+  /* USER CODE END SVC_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32L0xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32l0xx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles EXTI line 0 and line 1 interrupts.
+  */
+void EXTI0_1_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI0_1_IRQn 0 */
+
+  /* USER CODE END EXTI0_1_IRQn 0 */
+  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
+  /* USER CODE BEGIN EXTI0_1_IRQn 1 */
+
+  /* USER CODE END EXTI0_1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles EXTI line 4 to 15 interrupts.
+  */
+void EXTI4_15_IRQHandler(void)
+{
+  /* USER CODE BEGIN EXTI4_15_IRQn 0 */
+
+  /* USER CODE END EXTI4_15_IRQn 0 */
+  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
+  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
+  /* USER CODE BEGIN EXTI4_15_IRQn 1 */
+
+  /* USER CODE END EXTI4_15_IRQn 1 */
+}
+
+/**
+  * @brief This function handles USART2 global interrupt / USART2 wake-up interrupt through EXTI line 26.
+  */
+void USART2_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART2_IRQn 0 */
+
+  /* USER CODE END USART2_IRQn 0 */
+  HAL_UART_IRQHandler(&huart2);
+  /* USER CODE BEGIN USART2_IRQn 1 */
+
+  /* USER CODE END USART2_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Core/Src/syscalls.c

@@ -0,0 +1,159 @@
+/**
+ ******************************************************************************
+ * @file      syscalls.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include <sys/stat.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <stdio.h>
+#include <signal.h>
+#include <time.h>
+#include <sys/time.h>
+#include <sys/times.h>
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+	return 1;
+}
+
+int _kill(int pid, int sig)
+{
+	errno = EINVAL;
+	return -1;
+}
+
+void _exit (int status)
+{
+	_kill(status, -1);
+	while (1) {}		/* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		*ptr++ = __io_getchar();
+	}
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+	int DataIdx;
+
+	for (DataIdx = 0; DataIdx < len; DataIdx++)
+	{
+		__io_putchar(*ptr++);
+	}
+	return len;
+}
+
+int _close(int file)
+{
+	return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _isatty(int file)
+{
+	return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+	return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+	/* Pretend like we always fail */
+	return -1;
+}
+
+int _wait(int *status)
+{
+	errno = ECHILD;
+	return -1;
+}
+
+int _unlink(char *name)
+{
+	errno = ENOENT;
+	return -1;
+}
+
+int _times(struct tms *buf)
+{
+	return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int _link(char *old, char *new)
+{
+	errno = EMLINK;
+	return -1;
+}
+
+int _fork(void)
+{
+	errno = EAGAIN;
+	return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+	errno = ENOMEM;
+	return -1;
+}

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Core/Src/sysmem.c

@@ -0,0 +1,58 @@
+/**
+ ******************************************************************************
+ * @file      sysmem.c
+ * @author    Auto-generated by STM32CubeIDE
+ * @brief     STM32CubeIDE Minimal System Memory calls file
+ *
+ *            For more information about which c-functions
+ *            need which of these lowlevel functions
+ *            please consult the Newlib libc-manual
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Includes */
+#include <errno.h>
+#include <stdio.h>
+
+/* Variables */
+extern int errno;
+register char * stack_ptr asm("sp");
+
+/* Functions */
+
+/**
+ _sbrk
+ Increase program data space. Malloc and related functions depend on this
+**/
+caddr_t _sbrk(int incr)
+{
+	extern char end asm("end");
+	static char *heap_end;
+	char *prev_heap_end;
+
+	if (heap_end == 0)
+		heap_end = &end;
+
+	prev_heap_end = heap_end;
+	if (heap_end + incr > stack_ptr)
+	{
+		errno = ENOMEM;
+		return (caddr_t) -1;
+	}
+
+	heap_end += incr;
+
+	return (caddr_t) prev_heap_end;
+}
+

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Core/Src/system_stm32l0xx.c

@@ -0,0 +1,279 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l0xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32l0xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l0xx_system
+  * @{
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32l0xx.h"
+
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (MSI_VALUE)
+  #define MSI_VALUE    ((uint32_t)2097152U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Defines
+  * @{
+  */
+/************************* Miscellaneous Configuration ************************/
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x100. */
+/******************************************************************************/
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 2097152U; /* 32.768 kHz * 2^6 */
+  const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+  const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
+  const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+/*!< Set MSION bit */
+  RCC->CR |= (uint32_t)0x00000100U;
+
+  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+  RCC->CFGR &= (uint32_t) 0x88FF400CU;
+
+  /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFF6U;
+
+  /*!< Reset HSI48ON  bit */
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+
+  /*!< Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFFU;
+
+  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+  RCC->CFGR &= (uint32_t)0xFF02FFFFU;
+
+  /*!< Disable all interrupts */
+  RCC->CIER = 0x00000000U;
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock according to Clock Register Values
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
+  *             value as defined by the MSI range.
+  *
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *
+  *         (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
+  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00U:  /* MSI used as system clock */
+      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> RCC_ICSCR_MSIRANGE_Pos;
+      SystemCoreClock = (32768U * (1U << (msirange + 1U)));
+      break;
+    case 0x04U:  /* HSI used as system clock */
+      if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
+      {
+        SystemCoreClock = HSI_VALUE / 4U;
+      }
+      else
+      {
+        SystemCoreClock = HSI_VALUE;
+      }
+      break;
+    case 0x08U:  /* HSE used as system clock */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    default:  /* PLL used as system clock */
+      /* Get PLL clock source and multiplication factor ----------------------*/
+      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+      pllmul = PLLMulTable[(pllmul >> RCC_CFGR_PLLMUL_Pos)];
+      plldiv = (plldiv >> RCC_CFGR_PLLDIV_Pos) + 1U;
+
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+      if (pllsource == 0x00U)
+      {
+        /* HSI oscillator clock selected as PLL clock entry */
+        if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
+        {
+          SystemCoreClock = (((HSI_VALUE / 4U) * pllmul) / plldiv);
+        }
+        else
+        {
+          SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+        }
+      }
+      else
+      {
+        /* HSE selected as PLL clock entry */
+        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+      }
+      break;
+  }
+  /* Compute HCLK clock frequency --------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+  /* HCLK clock frequency */
+  SystemCoreClock >>= tmp;
+}
+
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Core/Startup/startup_stm32l031k6tx.s

@@ -0,0 +1,273 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l031xx.s
+  * @author    MCD Application Team
+  * @brief     STM32L031xx Devices vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M0+ processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * 
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m0plus
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+   ldr   r0, =_estack
+   mov   sp, r0          /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2]
+  adds r2, r2, #4
+
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl  main
+
+LoopForever:
+    b LoopForever
+
+
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M0.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  0
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */
+  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
+  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
+  .word     FLASH_IRQHandler                  /* FLASH                        */
+  .word     RCC_IRQHandler                    /* RCC                          */
+  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
+  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
+  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
+  .word     0                                 /* Reserved                     */
+  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
+  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
+  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
+  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
+  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
+  .word     0                                 /* Reserved                     */
+  .word     TIM2_IRQHandler                   /* TIM2                         */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     TIM21_IRQHandler                  /* TIM21                        */
+  .word     0                                 /* Reserved                     */
+  .word     TIM22_IRQHandler                  /* TIM22                        */
+  .word     I2C1_IRQHandler                   /* I2C1                         */
+  .word     0                                 /* Reserved                     */
+  .word     SPI1_IRQHandler                   /* SPI1                         */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     USART2_IRQHandler                 /* USART2                       */
+  .word     LPUART1_IRQHandler                /* LPUART1                      */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler
+
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler
+
+   .weak      PVD_IRQHandler
+   .thumb_set PVD_IRQHandler,Default_Handler
+
+   .weak      RTC_IRQHandler
+   .thumb_set RTC_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_1_IRQHandler
+   .thumb_set EXTI0_1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_3_IRQHandler
+   .thumb_set EXTI2_3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_15_IRQHandler
+   .thumb_set EXTI4_15_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel1_IRQHandler
+   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel2_3_IRQHandler
+   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Channel4_5_6_7_IRQHandler
+   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
+
+   .weak      ADC1_COMP_IRQHandler
+   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
+
+   .weak      LPTIM1_IRQHandler
+   .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+   .weak      TIM2_IRQHandler
+   .thumb_set TIM2_IRQHandler,Default_Handler
+
+   .weak      TIM21_IRQHandler
+   .thumb_set TIM21_IRQHandler,Default_Handler
+
+   .weak      TIM22_IRQHandler
+   .thumb_set TIM22_IRQHandler,Default_Handler
+
+   .weak      I2C1_IRQHandler
+   .thumb_set I2C1_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      LPUART1_IRQHandler
+   .thumb_set LPUART1_IRQHandler,Default_Handler
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h

@@ -0,0 +1,238 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
+  *          This file contains all the peripheral register's definitions, bits 
+  *          definitions and memory mapping for STM32L0xx devices.            
+  *            
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The device used in the target application
+  *              - To use or not the peripheral's drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral's registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_HAL_DRIVER"
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************  
+  */ 
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l0xx
+  * @{
+  */
+    
+#ifndef __STM32L0xx_H
+#define __STM32L0xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+   
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32L0)
+#define STM32L0
+#endif /* STM32L0 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+
+#if !defined (STM32L010x4) && !defined (STM32L010x6) && !defined (STM32L010x8) && !defined (STM32L010xB) && \
+    !defined (STM32L011xx) && !defined (STM32L021xx) && \
+    !defined (STM32L031xx) && !defined (STM32L041xx) && \
+    !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && \
+    !defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) && \
+    !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && \
+    !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx)
+  /* #define STM32L010x4 */   /*!< STM32L010K4, STM32L010F4 Devices                                                                                                                      */
+  /* #define STM32L010x6 */   /*!< STM32L010C6 Devices                                                                                                                                   */
+  /* #define STM32L010x8 */   /*!< STM32L010K8, STM32L010R8 Devices                                                                                                                      */
+  /* #define STM32L010xB */   /*!< STM32L010RB Devices                                                                                                                                   */
+  /* #define STM32L011xx */   /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices                                                                               */
+  /* #define STM32L021xx */   /*!< STM32L021D4, STM32L021F4, STM32L021G4, STM32L021K4 Devices                                                                                            */
+  /* #define STM32L031xx */   /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices                                                                               */
+  /* #define STM32L041xx */   /*!< STM32L041C6, STM32L041K6, STM32L041G6, STM32L041F6, STM32L041E6 Devices                                                                               */
+  /* #define STM32L051xx */   /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8, STM32L051K6, STM32L051T6, STM32L051T8 Devices                                        */
+  /* #define STM32L052xx */   /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8, STM32L052T6, STM32L052T8 Devices                                        */
+  /* #define STM32L053xx */   /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices                                                                                            */
+  /* #define STM32L061xx */   /*!< */
+  /* #define STM32L062xx */   /*!< STM32L062K8 Devices                                                                                                                                   */
+  /* #define STM32L063xx */   /*!< STM32L063C8, STM32L063R8 Devices                                                                                                                      */
+  /* #define STM32L071xx */   /*!< STM32L071V8, STM32L071K8, STM32L071VB, STM32L071RB, STM32L071CB, STM32L071KB, STM32L071VZ, STM32L071RZ, STM32L071CZ, STM32L071KZ, STM32L071C8 Devices */
+  /* #define STM32L072xx */   /*!< STM32L072V8, STM32L072VB, STM32L072RB, STM32L072CB, STM32L072VZ, STM32L072RZ, STM32L072CZ, STM32L072KB, STM32L072KZ Devices                           */
+  /* #define STM32L073xx */   /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ, STM32L073CB, STM32L073CZ Devices                                                     */
+  /* #define STM32L081xx */   /*!< STM32L081CB, STM32L081CZ, STM32L081KZ Devices                                                                                                         */
+  /* #define STM32L082xx */   /*!< STM32L082KB, STM32L082KZ, STM32L082CZ Devices                                                                                                         */
+  /* #define STM32L083xx */   /*!< STM32L083V8, STM32L083VB, STM32L083RB, STM32L083VZ, STM32L083RZ, STM32L083CB, STM32L083CZ Devices                                                     */
+#endif
+   
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number
+  */
+#define __STM32L0xx_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32L0xx_CMSIS_VERSION_SUB1   (0x09) /*!< [23:16] sub1 version */
+#define __STM32L0xx_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32L0xx_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32L0xx_CMSIS_VERSION        ((__STM32L0xx_CMSIS_VERSION_MAIN     << 24)\
+                                         |(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
+                                         |(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
+                                         |(__STM32L0xx_CMSIS_VERSION_RC))
+                                             
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+#if defined(STM32L010xB)
+  #include "stm32l010xb.h"
+#elif defined(STM32L010x8)
+  #include "stm32l010x8.h"
+#elif defined(STM32L010x6)
+  #include "stm32l010x6.h"
+#elif defined(STM32L010x4)
+  #include "stm32l010x4.h"
+#elif defined(STM32L011xx)
+  #include "stm32l011xx.h"
+#elif defined(STM32L021xx)
+  #include "stm32l021xx.h"
+#elif defined(STM32L031xx)
+  #include "stm32l031xx.h"
+#elif defined(STM32L041xx)
+  #include "stm32l041xx.h"
+#elif defined(STM32L051xx)
+  #include "stm32l051xx.h"
+#elif defined(STM32L052xx)
+  #include "stm32l052xx.h"
+#elif defined(STM32L053xx)
+  #include "stm32l053xx.h"
+#elif defined(STM32L062xx)
+  #include "stm32l062xx.h"
+#elif defined(STM32L063xx)
+  #include "stm32l063xx.h"
+#elif defined(STM32L061xx)
+  #include "stm32l061xx.h"
+#elif defined(STM32L071xx)
+  #include "stm32l071xx.h"
+#elif defined(STM32L072xx)
+  #include "stm32l072xx.h"
+#elif defined(STM32L073xx)
+  #include "stm32l073xx.h"
+#elif defined(STM32L082xx)
+  #include "stm32l082xx.h"
+#elif defined(STM32L083xx)
+  #include "stm32l083xx.h"
+#elif defined(STM32L081xx)
+  #include "stm32l081xx.h"
+#else
+ #error "Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */ 
+typedef enum 
+{
+  RESET = 0, 
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum 
+{
+  DISABLE = 0, 
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum 
+{
+  SUCCESS = 0,
+  ERROR = !SUCCESS
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32l0xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L0xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h

@@ -0,0 +1,109 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l0xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l0xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32L0XX_H
+#define __SYSTEM_STM32L0XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32L0xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32L0xx_System_Exported_types
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+/*
+*/
+extern const uint8_t AHBPrescTable[16];   /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8];    /*!< APB prescalers table values */
+extern const uint8_t PLLMulTable[9];      /*!< PLL multipiers table values */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L0xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32L0XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Drivers/CMSIS/Include/arm_common_tables.h

@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. October 2015
+* $Revision: 	V.1.4.5 a
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+/* extern const q31_t realCoefAQ31[1024]; */
+/* extern const q31_t realCoefBQ31[1024]; */
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Drivers/CMSIS/Include/arm_const_structs.h

@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Drivers/CMSIS/Include/cmsis_armcc.h

@@ -0,0 +1,734 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS Cortex-M Core Function/Instruction Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+
+#if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in integer value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in two unsigned short values.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/**
+  \brief   Reverse byte order in signed short value
+  \details Reverses the byte order in a signed short value with sign extension to integer.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    value  Value to rotate
+  \param [in]    value  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (__CORTEX_M >= 0x04U)  /* only for Cortex-M4 and above */
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Drivers/CMSIS/Include/core_cm0.h

@@ -0,0 +1,798 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (0x00U)                                      /*!< Cortex-M Core */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
+  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+  #define __STATIC_INLINE  static inline
+
+#else
+  #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "core_cmInstr.h"                /* Core Instruction Access */
+#include "core_cmFunc.h"                 /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable External Interrupt
+  \details Enables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Disable External Interrupt
+  \details Disables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of an external interrupt.
+  \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of an external interrupt.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of an interrupt.
+  \note    The priority cannot be set for every core interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) < 0)
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of an interrupt.
+           The interrupt number can be positive to specify an external (device specific) interrupt,
+           or negative to specify an internal (core) interrupt.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) < 0)
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Drivers/CMSIS/Include/core_cm0plus.h

@@ -0,0 +1,914 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U)                                   /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x1EU)                                   /*!< [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (0x00U)                                      /*!< Cortex-M Core */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
+  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+  #define __STATIC_INLINE  static inline
+
+#else
+  #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "core_cmInstr.h"                /* Core Instruction Access */
+#include "core_cmFunc.h"                 /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable External Interrupt
+  \details Enables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Disable External Interrupt
+  \details Disables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of an external interrupt.
+  \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of an external interrupt.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of an interrupt.
+  \note    The priority cannot be set for every core interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) < 0)
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of an interrupt.
+           The interrupt number can be positive to specify an external (device specific) interrupt,
+           or negative to specify an internal (core) interrupt.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) < 0)
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Drivers/CMSIS/Include/core_cmFunc.h

@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Drivers/CMSIS/Include/core_cmInstr.h

@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Drivers/CMSIS/Include/core_cmSimd.h

@@ -0,0 +1,96 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Drivers/CMSIS/Include/core_sc000.h

@@ -0,0 +1,926 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (0x04U)                                    /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (0x1EU)                                    /*!< [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC000_CMSIS_VERSION_SUB           )    /*!< CMSIS HAL version number */
+
+#define __CORTEX_SC                 (000U)                                     /*!< Cortex secure core */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
+  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+  #define __STATIC_INLINE  static inline
+
+#else
+  #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "core_cmInstr.h"                /* Core Instruction Access */
+#include "core_cmFunc.h"                 /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000U
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+        uint32_t RESERVED1[154U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable External Interrupt
+  \details Enables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Disable External Interrupt
+  \details Disables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of an external interrupt.
+  \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of an external interrupt.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of an interrupt.
+  \note    The priority cannot be set for every core interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) < 0)
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of an interrupt.
+           The interrupt number can be positive to specify an external (device specific) interrupt,
+           or negative to specify an internal (core) interrupt.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) < 0)
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h

@@ -0,0 +1,456 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for the HAL
+  *          module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_H
+#define __STM32L0xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_conf.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL HAL
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+  * @{
+  */
+
+/** @defgroup SYSCFG_BootMode Boot Mode
+  * @{
+  */
+#define SYSCFG_BOOT_MAINFLASH          ((uint32_t)0x00000000U)
+#define SYSCFG_BOOT_SYSTEMFLASH        ((uint32_t)SYSCFG_CFGR1_BOOT_MODE_0)
+#define SYSCFG_BOOT_SRAM               ((uint32_t)SYSCFG_CFGR1_BOOT_MODE)
+
+/**
+  * @}
+  */
+
+/** @defgroup DBGMCU_Low_Power_Config DBGMCU Low Power Configuration
+  * @{
+  */
+#define DBGMCU_SLEEP                 DBGMCU_CR_DBG_SLEEP
+#define DBGMCU_STOP                  DBGMCU_CR_DBG_STOP
+#define DBGMCU_STANDBY               DBGMCU_CR_DBG_STANDBY
+#define IS_DBGMCU_PERIPH(__PERIPH__) ((((__PERIPH__) & (~(DBGMCU_CR_DBG))) == 0x00U) && ((__PERIPH__) != 0x00U))
+
+
+/**
+  * @}
+  */
+
+#if defined (LCD_BASE) /* STM32L0x3xx only */
+/** @defgroup SYSCFG_LCD_EXT_CAPA SYSCFG LCD External Capacitors
+  * @{
+  */
+#define SYSCFG_LCD_EXT_CAPA             SYSCFG_CFGR2_CAPA /*!< Connection of internal Vlcd rail to external capacitors */
+#define SYSCFG_VLCD_PB2_EXT_CAPA_ON     SYSCFG_CFGR2_CAPA_0  /*!< Connection on PB2   */
+#define SYSCFG_VLCD_PB12_EXT_CAPA_ON    SYSCFG_CFGR2_CAPA_1  /*!< Connection on PB12  */
+#define SYSCFG_VLCD_PB0_EXT_CAPA_ON     SYSCFG_CFGR2_CAPA_2  /*!< Connection on PB0   */
+#if defined (SYSCFG_CFGR2_CAPA_3)
+#define SYSCFG_VLCD_PE11_EXT_CAPA_ON    SYSCFG_CFGR2_CAPA_3  /*!< Connection on PE11  */
+#endif
+#if defined (SYSCFG_CFGR2_CAPA_4)
+#define SYSCFG_VLCD_PE12_EXT_CAPA_ON    SYSCFG_CFGR2_CAPA_4  /*!< Connection on PE12  */
+#endif
+
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup SYSCFG_VREFINT_OUT_SELECT SYSCFG VREFINT Out Selection
+  * @{
+  */
+#define SYSCFG_VREFINT_OUT_NONE          ((uint32_t)0x00000000U) /* no pad connected */
+#define SYSCFG_VREFINT_OUT_PB0           SYSCFG_CFGR3_VREF_OUT_0 /* Selects PBO as output for the Vrefint */
+#define SYSCFG_VREFINT_OUT_PB1           SYSCFG_CFGR3_VREF_OUT_1 /* Selects PB1 as output for the Vrefint */
+#define SYSCFG_VREFINT_OUT_PB0_PB1       SYSCFG_CFGR3_VREF_OUT   /* Selects PBO and PB1 as output for the Vrefint */
+
+#define IS_SYSCFG_VREFINT_OUT_SELECT(OUTPUT)   (((OUTPUT) == SYSCFG_VREFINT_OUT_NONE)  || \
+                                                ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0)  || \
+                                                ((OUTPUT) == SYSCFG_VREFINT_OUT_PB1)  || \
+                                                ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0_PB1))
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_flags_definition SYSCFG Flags Definition
+  * @{
+  */
+#define SYSCFG_FLAG_VREFINT_READY      SYSCFG_CFGR3_VREFINT_RDYF
+
+#define IS_SYSCFG_FLAG(FLAG)           ((FLAG) == SYSCFG_FLAG_VREFINT_READY))
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast Mode Plus on GPIO
+  * @{
+  */
+/** @brief  Fast mode Plus driving capability on a specific GPIO
+  */
+#if defined (SYSCFG_CFGR2_I2C_PB6_FMP)
+#define SYSCFG_FASTMODEPLUS_PB6       SYSCFG_CFGR2_I2C_PB6_FMP  /* Enable Fast Mode Plus on PB6 */
+#endif
+#if defined (SYSCFG_CFGR2_I2C_PB7_FMP)
+#define SYSCFG_FASTMODEPLUS_PB7       SYSCFG_CFGR2_I2C_PB7_FMP  /* Enable Fast Mode Plus on PB7 */
+#endif
+#if defined (SYSCFG_CFGR2_I2C_PB8_FMP)
+#define SYSCFG_FASTMODEPLUS_PB8       SYSCFG_CFGR2_I2C_PB8_FMP  /* Enable Fast Mode Plus on PB8 */
+#endif
+#if defined (SYSCFG_CFGR2_I2C_PB9_FMP)
+#define SYSCFG_FASTMODEPLUS_PB9       SYSCFG_CFGR2_I2C_PB9_FMP  /* Enable Fast Mode Plus on PB9 */
+#endif
+
+#define IS_SYSCFG_FASTMODEPLUS(PIN) ((((PIN) & (SYSCFG_FASTMODEPLUS_PB6)) == SYSCFG_FASTMODEPLUS_PB6)  || \
+                                     (((PIN) & (SYSCFG_FASTMODEPLUS_PB7)) == SYSCFG_FASTMODEPLUS_PB7)  || \
+                                     (((PIN) & (SYSCFG_FASTMODEPLUS_PB8)) == SYSCFG_FASTMODEPLUS_PB8)  || \
+                                     (((PIN) & (SYSCFG_FASTMODEPLUS_PB9)) == SYSCFG_FASTMODEPLUS_PB9)  )
+/**
+ * @}
+ */
+ /**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+  * @{
+  */
+
+/** @brief  Freeze/Unfreeze Peripherals in Debug mode
+  */
+#if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP)
+/**
+  * @brief  TIM2 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM2()     SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM2()   CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP)
+#endif
+
+#if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP)
+/**
+  * @brief  TIM3 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM3()     SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM3()   CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP)
+#endif
+
+#if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP)
+/**
+  * @brief  TIM6 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM6()     SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM6()   CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
+#endif
+
+#if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP)
+/**
+  * @brief  TIM7 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM7()     SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM7()   CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
+#endif
+
+#if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP)
+/**
+  * @brief  RTC Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_RTC()      SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
+#define __HAL_DBGMCU_UNFREEZE_RTC()    CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
+#endif
+
+#if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP)
+/**
+  * @brief  WWDG Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_WWDG()     SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_WWDG()   CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
+#endif
+
+#if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP)
+/**
+  * @brief  IWDG Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_IWDG()     SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_IWDG()   CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
+#endif
+
+#if defined (DBGMCU_APB1_FZ_DBG_I2C1_STOP)
+/**
+  * @brief  I2C1 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP)
+#endif
+
+#if defined (DBGMCU_APB1_FZ_DBG_I2C2_STOP)
+/**
+  * @brief  I2C2 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT_DBGMCU()   SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP)
+#endif
+
+#if defined (DBGMCU_APB1_FZ_DBG_I2C3_STOP)
+/**
+  * @brief  I2C3 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP)
+#endif
+
+#if defined (DBGMCU_APB1_FZ_DBG_LPTIMER_STOP)
+/**
+  * @brief  LPTIMER Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_LPTIMER()        SET_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIMER()      CLEAR_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP)
+#endif
+
+#if defined (DBGMCU_APB2_FZ_DBG_TIM22_STOP)
+/**
+  * @brief  TIM22 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM22()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM22()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP)
+#endif
+
+#if defined (DBGMCU_APB2_FZ_DBG_TIM21_STOP)
+/**
+  * @brief  TIM21 Peripherals Debug mode
+  */
+#define __HAL_DBGMCU_FREEZE_TIM21()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM21()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP)
+#endif
+
+/** @brief  Main Flash memory mapped at 0x00000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_FLASH()     CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
+
+/** @brief  System Flash memory mapped at 0x00000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()      MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0)
+
+
+/** @brief  Embedded SRAM mapped at 0x00000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_SRAM()             MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1)
+
+/** @brief  Configuration of the DBG Low Power mode.
+  * @param  __DBGLPMODE__ bit field to indicate in wich Low Power mode DBG is still active.
+  *         This parameter can be a value of
+  *         - DBGMCU_SLEEP
+  *         - DBGMCU_STOP
+  *         - DBGMCU_STANDBY
+  */
+#define __HAL_SYSCFG_DBG_LP_CONFIG(__DBGLPMODE__)    do {assert_param(IS_DBGMCU_PERIPH(__DBGLPMODE__)); \
+                                                       MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG, (__DBGLPMODE__)); \
+                                                     } while (0)
+
+#if defined (LCD_BASE) /* STM32L0x3xx only */
+
+/** @brief  Macro to configure the VLCD Decoupling capacitance connection.
+  *
+  * @param  __SYSCFG_VLCD_CAPA__ specifies the decoupling of LCD capacitance for rails connection on GPIO.
+  *          This parameter can be a combination of following values (when available):
+  *            @arg SYSCFG_VLCD_PB2_EXT_CAPA_ON:  Connection on PB2
+  *            @arg SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12
+  *            @arg SYSCFG_VLCD_PB0_EXT_CAPA_ON:  Connection on PB0
+  *            @arg SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11
+  *            @arg SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12
+  * @retval None
+  */
+#define __HAL_SYSCFG_VLCD_CAPA_CONFIG(__SYSCFG_VLCD_CAPA__) \
+                  MODIFY_REG(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA, (uint32_t)(__SYSCFG_VLCD_CAPA__))
+
+/**
+  * @brief  Returns the decoupling of LCD capacitance configured by user.
+  * @retval The LCD capacitance connection as configured by user. The returned can be a combination of :
+  *            SYSCFG_VLCD_PB2_EXT_CAPA_ON:  Connection on PB2
+  *            SYSCFG_VLCD_PB12_EXT_CAPA_ON: Connection on PB12
+  *            SYSCFG_VLCD_PB0_EXT_CAPA_ON:  Connection on PB0
+  *            SYSCFG_VLCD_PE11_EXT_CAPA_ON: Connection on PE11
+  *            SYSCFG_VLCD_PE12_EXT_CAPA_ON: Connection on PE12
+  */
+#define __HAL_SYSCFG_GET_VLCD_CAPA_CONFIG()          READ_BIT(SYSCFG->CFGR2, SYSCFG_LCD_EXT_CAPA)
+
+#endif
+
+/**
+  * @brief  Returns the boot mode as configured by user.
+  * @retval The boot mode as configured by user. The returned can be a value of :
+  *     - SYSCFG_BOOT_MAINFLASH
+  *     - SYSCFG_BOOT_SYSTEMFLASH
+  *     - SYSCFG_BOOT_SRAM
+  */
+#define __HAL_SYSCFG_GET_BOOT_MODE()          READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOT_MODE)
+
+
+/** @brief  Check whether the specified SYSCFG flag is set or not.
+  * @param  __FLAG__ specifies the flag to check.
+  *         The only parameter supported is SYSCFG_FLAG_VREFINT_READY
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SYSCFG_GET_FLAG(__FLAG__) (((SYSCFG->CFGR3) & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Fast mode Plus driving capability enable macro
+  * @param __FASTMODEPLUS__ This parameter can be a value of :
+  *     @arg SYSCFG_FASTMODEPLUS_PB6
+  *     @arg SYSCFG_FASTMODEPLUS_PB7
+  *     @arg SYSCFG_FASTMODEPLUS_PB8
+  *     @arg SYSCFG_FASTMODEPLUS_PB9
+  */
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
+                                                                SET_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__));                 \
+                                                               }while(0)
+/** @brief  Fast mode Plus driving capability disable macro
+  * @param __FASTMODEPLUS__ This parameter can be a value of :
+  *     @arg SYSCFG_FASTMODEPLUS_PB6
+  *     @arg SYSCFG_FASTMODEPLUS_PB7
+  *     @arg SYSCFG_FASTMODEPLUS_PB8
+  *     @arg SYSCFG_FASTMODEPLUS_PB9
+  */
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
+                                                                CLEAR_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__));               \
+                                                               }while(0)
+
+
+/**
+  * @}
+  */
+
+/* Exported variables --------------------------------------------------------*/
+/** @defgroup HAL_Exported_Variables HAL Exported Variables
+  * @{
+  */
+extern __IO uint32_t uwTick;
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+  * @{
+  */
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and de-initialization functions
+ * @{
+  */
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group2 Peripheral Control functions
+  * @brief    Peripheral Control functions
+  * @{
+  */
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group3 DBGMCU Peripheral Control functions
+  * @brief    DBGMCU Peripheral Control functions
+  * @{
+  */
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+void HAL_DBGMCU_DBG_EnableLowPowerConfig(uint32_t Periph);
+void HAL_DBGMCU_DBG_DisableLowPowerConfig(uint32_t Periph);
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group4 SYSCFG Peripheral Control functions
+  * @brief    SYSCFG Peripheral Control functions
+  * @{
+  */
+uint32_t  HAL_SYSCFG_GetBootMode(void);
+void HAL_SYSCFG_Enable_Lock_VREFINT(void);
+void HAL_SYSCFG_Disable_Lock_VREFINT(void);
+void HAL_SYSCFG_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT);
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup HAL_Private HAL Private
+  * @{
+  */
+/**
+  * @}
+  */
+/**************************************************************/
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h

@@ -0,0 +1,365 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_CORTEX_H
+#define __STM32L0xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX CORTEX
+  * @{
+  */ 
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
+  * @{
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+  * @{
+  */
+typedef struct
+{
+  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
+
+  uint8_t                Enable;                /*!< Specifies the status of the region.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
+  uint8_t                Number;                /*!< Specifies the number of the region to protect.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
+
+  uint8_t                Size;                  /*!< Specifies the size of the region to protect.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
+  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
+                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
+  uint8_t                TypeExtField;          /*!< This parameter is NOT used but is kept to keep API unified through all families*/
+
+  uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
+  uint8_t                DisableExec;           /*!< Specifies the instruction access status.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
+  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
+  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
+  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
+}MPU_Region_InitTypeDef;
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEx Exported Constants
+  * @{
+  */
+
+
+#define IS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__)  ((__PRIORITY__) < 0x4U)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= 0x0)
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick Clock Source
+  * @{
+  */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000U)
+#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004U)
+#define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \
+                                       ((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+/**
+  * @}
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
+  * @{
+  */
+#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000U)
+#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002U)
+#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004U)
+#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006U)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+  * @{
+  */
+#define  MPU_REGION_ENABLE           ((uint8_t)0x01U)
+#define  MPU_REGION_DISABLE          ((uint8_t)0x00U)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+  * @{
+  */
+#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00U)
+#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01U)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+  * @{
+  */
+#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01U)
+#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00U)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+  * @{
+  */
+#define  MPU_ACCESS_CACHEABLE        ((uint8_t)0x01U)
+#define  MPU_ACCESS_NOT_CACHEABLE    ((uint8_t)0x00U)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+  * @{
+  */
+#define  MPU_ACCESS_BUFFERABLE       ((uint8_t)0x01U)
+#define  MPU_ACCESS_NOT_BUFFERABLE   ((uint8_t)0x00U)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+  * @{
+  */
+#define   MPU_REGION_SIZE_32B        ((uint8_t)0x04U)
+#define   MPU_REGION_SIZE_64B        ((uint8_t)0x05U)
+#define   MPU_REGION_SIZE_128B       ((uint8_t)0x06U)
+#define   MPU_REGION_SIZE_256B       ((uint8_t)0x07U)
+#define   MPU_REGION_SIZE_512B       ((uint8_t)0x08U)
+#define   MPU_REGION_SIZE_1KB        ((uint8_t)0x09U)
+#define   MPU_REGION_SIZE_2KB        ((uint8_t)0x0AU)
+#define   MPU_REGION_SIZE_4KB        ((uint8_t)0x0BU)
+#define   MPU_REGION_SIZE_8KB        ((uint8_t)0x0CU)
+#define   MPU_REGION_SIZE_16KB       ((uint8_t)0x0DU)
+#define   MPU_REGION_SIZE_32KB       ((uint8_t)0x0EU)
+#define   MPU_REGION_SIZE_64KB       ((uint8_t)0x0FU)
+#define   MPU_REGION_SIZE_128KB      ((uint8_t)0x10U)
+#define   MPU_REGION_SIZE_256KB      ((uint8_t)0x11U)
+#define   MPU_REGION_SIZE_512KB      ((uint8_t)0x12U)
+#define   MPU_REGION_SIZE_1MB        ((uint8_t)0x13U)
+#define   MPU_REGION_SIZE_2MB        ((uint8_t)0x14U)
+#define   MPU_REGION_SIZE_4MB        ((uint8_t)0x15U)
+#define   MPU_REGION_SIZE_8MB        ((uint8_t)0x16U)
+#define   MPU_REGION_SIZE_16MB       ((uint8_t)0x17U)
+#define   MPU_REGION_SIZE_32MB       ((uint8_t)0x18U)
+#define   MPU_REGION_SIZE_64MB       ((uint8_t)0x19U)
+#define   MPU_REGION_SIZE_128MB      ((uint8_t)0x1AU)
+#define   MPU_REGION_SIZE_256MB      ((uint8_t)0x1BU)
+#define   MPU_REGION_SIZE_512MB      ((uint8_t)0x1CU)
+#define   MPU_REGION_SIZE_1GB        ((uint8_t)0x1DU)
+#define   MPU_REGION_SIZE_2GB        ((uint8_t)0x1EU)
+#define   MPU_REGION_SIZE_4GB        ((uint8_t)0x1FU)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
+  * @{
+  */
+#define  MPU_REGION_NO_ACCESS        ((uint8_t)0x00U)
+#define  MPU_REGION_PRIV_RW          ((uint8_t)0x01U)
+#define  MPU_REGION_PRIV_RW_URO      ((uint8_t)0x02U)
+#define  MPU_REGION_FULL_ACCESS      ((uint8_t)0x03U)
+#define  MPU_REGION_PRIV_RO          ((uint8_t)0x05U)
+#define  MPU_REGION_PRIV_RO_URO      ((uint8_t)0x06U)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+  * @{
+  */
+#define  MPU_REGION_NUMBER0          ((uint8_t)0x00U)
+#define  MPU_REGION_NUMBER1          ((uint8_t)0x01U)
+#define  MPU_REGION_NUMBER2          ((uint8_t)0x02U)
+#define  MPU_REGION_NUMBER3          ((uint8_t)0x03U)
+#define  MPU_REGION_NUMBER4          ((uint8_t)0x04U)
+#define  MPU_REGION_NUMBER5          ((uint8_t)0x05U)
+#define  MPU_REGION_NUMBER6          ((uint8_t)0x06U)
+#define  MPU_REGION_NUMBER7          ((uint8_t)0x07U)
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+
+/**
+  * @}
+  */  
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+  
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 
+ *  @brief    Initialization and Configuration functions
+ * @{
+  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+  * @}
+  */
+  
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   Cortex control functions
+ * @{
+ */
+ 
+uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+#if (__MPU_PRESENT == 1U)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+  
+  /**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+  * @{
+  */
+
+#if (__MPU_PRESENT == 1)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+                                     ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_256B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FFU)
+#endif /* __MPU_PRESENT */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L0xx_HAL_CORTEX_H */
+ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h

@@ -0,0 +1,190 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_def.h
+  * @author  MCD Application Team
+  * @brief   This file contains HAL common defines, enumeration, macros and
+  *          structures definitions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L0xx_HAL_DEF
+#define __STM32L0xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx.h"
+#include "Legacy/stm32_hal_legacy.h"
+#include <stddef.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  HAL Status structures definition
+  */
+typedef enum
+{
+  HAL_OK       = 0x00U,
+  HAL_ERROR    = 0x01U,
+  HAL_BUSY     = 0x02U,
+  HAL_TIMEOUT  = 0x03U
+} HAL_StatusTypeDef;
+
+/**
+  * @brief  HAL Lock structures definition
+  */
+typedef enum
+{
+  HAL_UNLOCKED = 0x00U,
+  HAL_LOCKED   = 0x01U
+} HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+
+#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */
+
+#define HAL_MAX_DELAY      0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)             \
+                        do{                                                    \
+                            (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+                            (__DMA_HANDLE__).Parent = (__HANDLE__);             \
+                          } while(0)
+
+/** @brief Reset the Handle's State field.
+  * @param __HANDLE__: specifies the Peripheral Handle.
+  * @note  This macro can be used for the following purpose:
+  *          - When the Handle is declared as local variable; before passing it as parameter
+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+  *            to set to 0 the Handle's "State" field.
+  *            Otherwise, "State" field may have any random value and the first time the function
+  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
+  *            (i.e. HAL_PPP_MspInit() will not be executed).
+  *          - When there is a need to reconfigure the low level hardware: instead of calling
+  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
+  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
+  * @retval None
+  */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
+
+#if (USE_RTOS == 1)
+
+  /* Reserved for future use */
+  #error "USE_RTOS should be 0 in the current HAL release"
+
+#else
+  #define __HAL_LOCK(__HANDLE__)                                               \
+                                do{                                            \
+                                    if((__HANDLE__)->Lock == HAL_LOCKED)       \
+                                    {                                          \
+                                       return HAL_BUSY;                        \
+                                    }                                          \
+                                    else                                       \
+                                    {                                          \
+                                       (__HANDLE__)->Lock = HAL_LOCKED;        \
+                                    }                                          \
+                                  }while (0)
+
+  #define __HAL_UNLOCK(__HANDLE__)                                             \
+                                  do{                                          \
+                                      (__HANDLE__)->Lock = HAL_UNLOCKED;       \
+                                    }while (0)
+#endif /* USE_RTOS */
+
+#if  defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+  #ifndef __weak
+    #define __weak   __attribute__((weak))
+  #endif /* __weak */
+  #ifndef __packed
+    #define __packed __attribute__((__packed__))
+  #endif /* __packed */
+
+  #define __NOINLINE __attribute__ ( (noinline) )
+
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined   (__GNUC__) && !defined (__CC_ARM) /* GNU Compiler */
+  #ifndef __ALIGN_END
+    #define __ALIGN_END    __attribute__ ((aligned (4)))
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #define __ALIGN_BEGIN
+  #endif /* __ALIGN_BEGIN */
+#else
+  #ifndef __ALIGN_END
+    #define __ALIGN_END
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #if defined   (__CC_ARM)      /* ARM Compiler */
+      #define __ALIGN_BEGIN    __align(4)
+    #elif defined (__ICCARM__)    /* IAR Compiler */
+      #define __ALIGN_BEGIN
+    #endif /* __CC_ARM */
+  #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/**
+  * @brief  __RAM_FUNC definition
+  */
+#if defined ( __CC_ARM   )
+/* ARM Compiler
+   ------------
+   RAM functions are defined using the toolchain options.
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const'
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog.
+*/
+#define __RAM_FUNC
+
+#define __NOINLINE __attribute__ ( (noinline) )
+
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC __ramfunc
+
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#elif defined   (  __GNUC__  )
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC  __attribute__((section(".RamFunc")))
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32L0xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

Samples/DeviceToCloud/ExternalMcuLowPower/McuSoda/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h

@@ -0,0 +1,675 @@
+/**
+  ******************************************************************************
+  * @file    stm32l0xx_hal_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32L0xx_HAL_DMA_H
+#define STM32L0xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l0xx_hal_def.h"
+
+/** @addtogroup STM32L0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Types DMA Exported Types
+  * @{
+  */
+
+/**
+  * @brief  DMA Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Request;                   /*!< Specifies the request selected for the specified channel.
+                                           This parameter can be a value of @ref DMA_request */
+
+  uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
+                                           from memory to memory or from peripheral to memory.
+                                           This parameter can be a value of @ref DMA_Data_transfer_direction */
+
+  uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
+                                           This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
+  uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
+                                           This parameter can be a value of @ref DMA_Memory_incremented_mode */
+
+  uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
+                                           This parameter can be a value of @ref DMA_Peripheral_data_size */
+
+  uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
+                                           This parameter can be a value of @ref DMA_Memory_data_size */
+
+  uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
+                                           This parameter can be a value of @ref DMA_mode
+                                           @note The circular buffer mode cannot be used if the memory-to-memory
+                                                 data transfer is configured on the selected Channel */
+
+  uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.
+                                           This parameter can be a value of @ref DMA_Priority_level */
+} DMA_InitTypeDef;
+
+/**
+  * @brief  HAL DMA State structures definition
+  */
+typedef enum
+{
+  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled    */
+  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use      */
+  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing                 */
+  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                      */
+}HAL_DMA_StateTypeDef;
+
+/**
+  * @brief  HAL DMA Error Code structure definition
+  */
+typedef enum
+{
+  HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_HALF_TRANSFER      = 0x01U     /*!< Half Transfer     */
+}HAL_DMA_LevelCompleteTypeDef;
+
+
+/**
+  * @brief  HAL DMA Callback ID structure definition
+  */
+typedef enum
+{
+  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
+  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half transfer     */
+  HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,    /*!< Error             */
+  HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,    /*!< Abort             */
+  HAL_DMA_XFER_ALL_CB_ID           = 0x04U     /*!< All               */
+}HAL_DMA_CallbackIDTypeDef;
+
+/**
+  * @brief  DMA handle Structure definition
+  */
+typedef struct __DMA_HandleTypeDef
+{
+  DMA_Channel_TypeDef    *Instance;                                                  /*!< Register base address                */
+
+  DMA_InitTypeDef       Init;                                                        /*!< DMA communication parameters         */
+
+  HAL_LockTypeDef       Lock;                                                        /*!< DMA locking object                   */
+
+  __IO HAL_DMA_StateTypeDef  State;                                                  /*!< DMA transfer state                   */
+
+  void                  *Parent;                                                     /*!< Parent object state                  */
+
+  void                  (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback       */
+
+  void                  (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback  */
+
+  void                  (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback          */
+
+  void                  (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer abort callback          */
+
+  __IO uint32_t          ErrorCode;                                                  /*!< DMA Error code                       */
+
+  DMA_TypeDef            *DmaBaseAddress;                                            /*!< DMA Channel Base Address             */
+
+  uint32_t               ChannelIndex;                                               /*!< DMA Channel Index                    */
+
+}DMA_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+  * @{
+  */
+#define HAL_DMA_ERROR_NONE                 0x00000000U    /*!< No error                                */
+#define HAL_DMA_ERROR_TE                   0x00000001U    /*!< Transfer error                          */
+#define HAL_DMA_ERROR_NO_XFER              0x00000004U    /*!< Abort requested with no Xfer ongoing    */
+#define HAL_DMA_ERROR_TIMEOUT              0x00000020U    /*!< Timeout error                           */
+#define HAL_DMA_ERROR_NOT_SUPPORTED        0x00000100U    /*!< Not supported mode                      */
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_request DMA request
+  * @{
+  */
+
+#if defined (STM32L010x4) || defined (STM32L010x6) || defined (STM32L010x8) || defined (STM32L010xC)
+
+#define DMA_REQUEST_0                     0U
+#define DMA_REQUEST_1                     1U
+#define DMA_REQUEST_4                     4U
+#define DMA_REQUEST_5                     5U
+#define DMA_REQUEST_6                     6U
+#define DMA_REQUEST_8                     8U
+
+#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
+                                     ((REQUEST) == DMA_REQUEST_1) || \
+                                     ((REQUEST) == DMA_REQUEST_4) || \
+                                     ((REQUEST) == DMA_REQUEST_5) || \
+                                     ((REQUEST) == DMA_REQUEST_6) || \
+                                     ((REQUEST) == DMA_REQUEST_8))
+
+/* STM32L010x4 || STM32L010x6 || STM32L010x8 || STM32L010xC */
+
+#elif defined (STM32L021xx) || defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
+
+#define DMA_REQUEST_0                     0U
+#define DMA_REQUEST_1                     1U
+#define DMA_REQUEST_2                     2U
+#define DMA_REQUEST_3                     3U
+#define DMA_REQUEST_4                     4U
+#define DMA_REQUEST_5                     5U
+#define DMA_REQUEST_6                     6U
+#define DMA_REQUEST_7                     7U
+#define DMA_REQUEST_8                     8U
+#define DMA_REQUEST_9                     9U
+#define DMA_REQUEST_10                   10U
+#define DMA_REQUEST_11                   11U  /* AES product only */
+#define DMA_REQUEST_12                   12U
+#define DMA_REQUEST_13                   13U
+#define DMA_REQUEST_14                   14U
+#define DMA_REQUEST_15                   15U
+
+#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
+                                     ((REQUEST) == DMA_REQUEST_1) || \
+                                     ((REQUEST) == DMA_REQUEST_2) || \
+                                     ((REQUEST) == DMA_REQUEST_3) || \
+                                     ((REQUEST) == DMA_REQUEST_4) || \
+                                     ((REQUEST) == DMA_REQUEST_5) || \
+                                     ((REQUEST) == DMA_REQUEST_6) || \
+                                     ((REQUEST) == DMA_REQUEST_7) || \
+                                     ((REQUEST) == DMA_REQUEST_8) || \
+                                     ((REQUEST) == DMA_REQUEST_9) || \
+                                     ((REQUEST) == DMA_REQUEST_10) || \
+                                     ((REQUEST) == DMA_REQUEST_11) || \
+                                     ((REQUEST) == DMA_REQUEST_12) || \
+                                     ((REQUEST) == DMA_REQUEST_13) || \
+                                     ((REQUEST) == DMA_REQUEST_14) || \
+                                     ((REQUEST) == DMA_REQUEST_15))
+
+/* (STM32L021xx) || (STM32L041xx) || (STM32L061xx) || (STM32L062xx) || (STM32L063xx) || (STM32L081xx) || (STM32L082xx) || (STM32L083xx) */
+
+#else
+
+#define DMA_REQUEST_0                     0U
+#define DMA_REQUEST_1                     1U
+#define DMA_REQUEST_2                     2U
+#define DMA_REQUEST_3                     3U
+#define DMA_REQUEST_4                     4U
+#define DMA_REQUEST_5                     5U
+#define DMA_REQUEST_6                     6U
+#define DMA_REQUEST_7                     7U
+#define DMA_REQUEST_8                     8U
+#define DMA_REQUEST_9                     9U
+#define DMA_REQUEST_10                   10U
+#define DMA_REQUEST_12                   12U
+#define DMA_REQUEST_13                   13U
+#define DMA_REQUEST_14                   14U
+#define DMA_REQUEST_15                   15U
+
+#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
+                                     ((REQUEST) == DMA_REQUEST_1) || \
+                                     ((REQUEST) == DMA_REQUEST_2) || \
+                                     ((REQUEST) == DMA_REQUEST_3) || \
+                                     ((REQUEST) == DMA_REQUEST_4) || \
+                                     ((REQUEST) == DMA_REQUEST_5) || \
+                                     ((REQUEST) == DMA_REQUEST_6) || \
+                                     ((REQUEST) == DMA_REQUEST_7) || \
+                                     ((REQUEST) == DMA_REQUEST_8) || \
+                                     ((REQUEST) == DMA_REQUEST_9) || \
+                                     ((REQUEST) == DMA_REQUEST_10) || \
+                                     ((REQUEST) == DMA_REQUEST_12) || \
+                                     ((REQUEST) == DMA_REQUEST_13) || \
+                                     ((REQUEST) == DMA_REQUEST_14) || \
+                                     ((REQUEST) == DMA_REQUEST_15))
+
+#endif /* (STM32L031xx) || (STM32L051xx) || (STM32L052xx) || (STM32L053xx) || (STM32L071xx) || (STM32L072xx) || (STM32L073xx) */
+
+
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+  * @{
+  */
+#define DMA_PERIPH_TO_MEMORY         0x00000000U        /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH         DMA_CCR_DIR        /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY         DMA_CCR_MEM2MEM    /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+  * @{
+  */
+#define DMA_PINC_ENABLE              DMA_CCR_PINC  /*!< Peripheral increment mode Enable */
+#define DMA_PINC_DISABLE             0x00000000U   /*!< Peripheral increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+  * @{
+  */
+#define DMA_MINC_ENABLE              DMA_CCR_MINC   /*!< Memory increment mode Enable  */
+#define DMA_MINC_DISABLE             0x00000000U    /*!< Memory increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+  * @{
+  */
+#define DMA_PDATAALIGN_BYTE          0x00000000U     /*!< Peripheral data alignment : Byte     */
+#define DMA_PDATAALIGN_HALFWORD      DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
+#define DMA_PDATAALIGN_WORD          DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+  * @{
+  */
+#define DMA_MDATAALIGN_BYTE          0x00000000U     /*!< Memory data alignment : Byte     */
+#define DMA_MDATAALIGN_HALFWORD      DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
+#define DMA_MDATAALIGN_WORD          DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_mode DMA mode
+  * @{
+  */
+#define DMA_NORMAL                   0x00000000U     /*!< Normal mode                  */
+#define DMA_CIRCULAR                 DMA_CCR_CIRC    /*!< Circular mode                */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+  * @{
+  */
+#define DMA_PRIORITY_LOW             0x00000000U      /*!< Priority level : Low       */
+#define DMA_PRIORITY_MEDIUM          DMA_CCR_PL_0     /*!< Priority level : Medium    */
+#define DMA_PRIORITY_HIGH            DMA_CCR_PL_1     /*!< Priority level : High      */
+#define DMA_PRIORITY_VERY_HIGH       DMA_CCR_PL       /*!< Priority level : Very_High */
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+  * @{
+  */
+#define DMA_IT_TC                         DMA_CCR_TCIE
+#define DMA_IT_HT                         DMA_CCR_HTIE
+#define DMA_IT_TE                         DMA_CCR_TEIE
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+  * @{
+  */
+#define DMA_FLAG_GL1                      DMA_ISR_GIF1
+#define DMA_FLAG_TC1                      DMA_ISR_TCIF1
+#define DMA_FLAG_HT1                      DMA_ISR_HTIF1
+#define DMA_FLAG_TE1                      DMA_ISR_TEIF1
+#define DMA_FLAG_GL2                      DMA_ISR_GIF2
+#define DMA_FLAG_TC2                      DMA_ISR_TCIF2
+#define DMA_FLAG_HT2                      DMA_ISR_HTIF2
+#define DMA_FLAG_TE2                      DMA_ISR_TEIF2
+#define DMA_FLAG_GL3                      DMA_ISR_GIF3
+#define DMA_FLAG_TC3                      DMA_ISR_TCIF3
+#define DMA_FLAG_HT3                      DMA_ISR_HTIF3
+#define DMA_FLAG_TE3                      DMA_ISR_TEIF3
+#define DMA_FLAG_GL4                      DMA_ISR_GIF4
+#define DMA_FLAG_TC4                      DMA_ISR_TCIF4
+#define DMA_FLAG_HT4                      DMA_ISR_HTIF4
+#define DMA_FLAG_TE4                      DMA_ISR_TEIF4
+#define DMA_FLAG_GL5                      DMA_ISR_GIF5
+#define DMA_FLAG_TC5                      DMA_ISR_TCIF5
+#define DMA_FLAG_HT5                      DMA_ISR_HTIF5
+#define DMA_FLAG_TE5                      DMA_ISR_TEIF5
+#define DMA_FLAG_GL6                      DMA_ISR_GIF6
+#define DMA_FLAG_TC6                      DMA_ISR_TCIF6
+#define DMA_FLAG_HT6                      DMA_ISR_HTIF6
+#define DMA_FLAG_TE6                      DMA_ISR_TEIF6
+#define DMA_FLAG_GL7                      DMA_ISR_GIF7
+#define DMA_FLAG_TC7                      DMA_ISR_TCIF7
+#define DMA_FLAG_HT7                      DMA_ISR_HTIF7
+#define DMA_FLAG_TE7                      DMA_ISR_TEIF7
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @brief  Reset DMA handle state.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+  * @brief  Enable the specified DMA Channel.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
+
+/**
+  * @brief  Disable the specified DMA Channel.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
+
+
+/* Interrupt & Flag management */
+
+/**
+  * @brief  Return the current DMA Channel transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer complete flag index.
+  */
+
+#if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx)
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ DMA_FLAG_TC5)
+#else
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+   DMA_FLAG_TC7)
+#endif
+/**
+  * @brief  Return the current DMA Channel half transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified half transfer complete flag index.
+  */
+#if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx)
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ DMA_FLAG_HT5)
+#else
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+   DMA_FLAG_HT7)
+#endif
+/**
+  * @brief  Returns the current DMA Channel transfer error flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx)
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ DMA_FLAG_TE5)
+#else
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+   DMA_FLAG_TE7)
+#endif
+/**
+  * @brief  Returns the current DMA Channel Global interrupt flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx)
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
+   DMA_ISR_GIF5)
+#else
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
+   DMA_ISR_GIF7)
+#endif
+/**
+  * @brief  Get the DMA Channel pending flags.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx:  Transfer complete flag
+  *            @arg DMA_FLAG_HTIFx:  Half transfer complete flag
+  *            @arg DMA_FLAG_TEIFx:  Transfer error flag
+  *            @arg DMA_ISR_GIFx: Global interrupt flag
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
+
+/**
+  * @brief  Clears the DMA Channel pending flags.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCx:  Transfer complete flag
+  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
+  *            @arg DMA_FLAG_TEx:  Transfer error flag
+  *            @arg DMA_FLAG_GLx:  Global interrupt flag
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
+  * @retval None
+  */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
+
+/**
+  * @brief  Enable the specified DMA Channel interrupts.
+  * @param  __HANDLE__: DMA handle
+  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified DMA Channel interrupts.
+  * @param  __HANDLE__: DMA handle
+  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
+  * @retval The state of DMA_IT (SET or RESET).
+  */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
+
+/**
+  * @brief  Return the number of remaining data units in the current DMA Channel transfer.
+  * @param  __HANDLE__: DMA handle
+  * @retval The number of remaining data units in the current DMA Channel transfer.
+  */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DMA_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State and Error functions ***************************************/
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Define the private group ***********************************/
+/**************************************************************/
+/** @defgroup DMA_Private DMA Private
+  * @{
+  */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+                                            ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
+                                        ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
+                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+                                           ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
+                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
+                           ((MODE) == DMA_CIRCULAR))
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
+                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
+                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+/**
+  * @}
+  */
+/**************************************************************/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32L0xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/