Fedor Indutny
Родитель
3122e0eae6
Коммит
ada85d7307
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@ -42,6 +42,13 @@ OUTPUTS = \
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x64-elf-gas/whrlpool/wp-x86_64.s \
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x64-elf-gas/modes/ghash-x86_64.s \
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x64-elf-gas/x86_64cpuid.s \
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arm-elf-gas/aes/aes-armv4.S \
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arm-elf-gas/bn/armv4-mont.S \
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arm-elf-gas/bn/armv4-gf2m.S \
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arm-elf-gas/sha/sha1-armv4-large.S \
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arm-elf-gas/sha/sha256-armv4.S \
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arm-elf-gas/sha/sha512-armv4.S \
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arm-elf-gas/modes/ghash-armv4.S \
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x86-macosx-gas/aes/aes-586.s \
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x86-macosx-gas/aes/aesni-x86.s \
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x86-macosx-gas/aes/vpaes-x86.s \
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@ -121,7 +128,7 @@ OUTPUTS = \
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x64-win32-masm/modes/ghash-x86_64.asm \
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x64-win32-masm/x86_64cpuid.asm \
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x64-elf-gas/%.s x86-elf-gas/%.s:
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arm-elf-gas/%.S x64-elf-gas/%.s x86-elf-gas/%.s:
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$(PERL) $< elf > $@
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x64-macosx-gas/%.s x86-macosx-gas/%.s:
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@ -262,3 +269,10 @@ x86-win32-masm/sha/sha512-586.asm: ../openssl/crypto/sha/asm/sha512-586.pl
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x86-win32-masm/whrlpool/wp-mmx.asm: ../openssl/crypto/whrlpool/asm/wp-mmx.pl
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x86-win32-masm/modes/ghash-x86.asm: ../openssl/crypto/modes/asm/ghash-x86.pl
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x86-win32-masm/x86cpuid.asm: ../openssl/crypto/x86cpuid.pl
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arm-elf-gas/aes/aes-armv4.S: ../openssl/crypto/aes/asm/aes-armv4.pl
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arm-elf-gas/bn/armv4-mont.S: ../openssl/crypto/bn/asm/armv4-mont.pl
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arm-elf-gas/bn/armv4-gf2m.S: ../openssl/crypto/bn/asm/armv4-gf2m.pl
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arm-elf-gas/sha/sha1-armv4-large.S: ../openssl/crypto/sha/asm/sha1-armv4-large.pl
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arm-elf-gas/sha/sha512-armv4.S: ../openssl/crypto/sha/asm/sha512-armv4.pl
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arm-elf-gas/sha/sha256-armv4.S: ../openssl/crypto/sha/asm/sha256-armv4.pl
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arm-elf-gas/modes/ghash-armv4.S: ../openssl/crypto/modes/asm/ghash-armv4.pl
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -0,0 +1,214 @@
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#include "arm_arch.h"
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.text
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.code 32
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#if __ARM_ARCH__>=7
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.fpu neon
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.type mul_1x1_neon,%function
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.align 5
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mul_1x1_neon:
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vshl.u64 d2,d16,#8 @ q1-q3 are slided
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vmull.p8 q0,d16,d17 @ a·bb
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vshl.u64 d4,d16,#16
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vmull.p8 q1,d2,d17 @ a<<8·bb
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vshl.u64 d6,d16,#24
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vmull.p8 q2,d4,d17 @ a<<16·bb
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vshr.u64 d2,#8
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vmull.p8 q3,d6,d17 @ a<<24·bb
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vshl.u64 d3,#24
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veor d0,d2
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vshr.u64 d4,#16
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veor d0,d3
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vshl.u64 d5,#16
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veor d0,d4
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vshr.u64 d6,#24
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veor d0,d5
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vshl.u64 d7,#8
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veor d0,d6
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veor d0,d7
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.word 0xe12fff1e
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.size mul_1x1_neon,.-mul_1x1_neon
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#endif
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.type mul_1x1_ialu,%function
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.align 5
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mul_1x1_ialu:
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mov r4,#0
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bic r5,r1,#3<<30 @ a1=a&0x3fffffff
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str r4,[sp,#0] @ tab[0]=0
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add r6,r5,r5 @ a2=a1<<1
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str r5,[sp,#4] @ tab[1]=a1
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eor r7,r5,r6 @ a1^a2
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str r6,[sp,#8] @ tab[2]=a2
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mov r8,r5,lsl#2 @ a4=a1<<2
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str r7,[sp,#12] @ tab[3]=a1^a2
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eor r9,r5,r8 @ a1^a4
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str r8,[sp,#16] @ tab[4]=a4
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eor r4,r6,r8 @ a2^a4
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str r9,[sp,#20] @ tab[5]=a1^a4
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eor r7,r7,r8 @ a1^a2^a4
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str r4,[sp,#24] @ tab[6]=a2^a4
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and r8,r12,r0,lsl#2
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str r7,[sp,#28] @ tab[7]=a1^a2^a4
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and r9,r12,r0,lsr#1
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ldr r5,[sp,r8] @ tab[b & 0x7]
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and r8,r12,r0,lsr#4
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ldr r7,[sp,r9] @ tab[b >> 3 & 0x7]
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and r9,r12,r0,lsr#7
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ldr r6,[sp,r8] @ tab[b >> 6 & 0x7]
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eor r5,r5,r7,lsl#3 @ stall
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mov r4,r7,lsr#29
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ldr r7,[sp,r9] @ tab[b >> 9 & 0x7]
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and r8,r12,r0,lsr#10
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eor r5,r5,r6,lsl#6
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eor r4,r4,r6,lsr#26
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ldr r6,[sp,r8] @ tab[b >> 12 & 0x7]
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and r9,r12,r0,lsr#13
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eor r5,r5,r7,lsl#9
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eor r4,r4,r7,lsr#23
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ldr r7,[sp,r9] @ tab[b >> 15 & 0x7]
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and r8,r12,r0,lsr#16
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eor r5,r5,r6,lsl#12
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eor r4,r4,r6,lsr#20
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ldr r6,[sp,r8] @ tab[b >> 18 & 0x7]
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and r9,r12,r0,lsr#19
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eor r5,r5,r7,lsl#15
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eor r4,r4,r7,lsr#17
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ldr r7,[sp,r9] @ tab[b >> 21 & 0x7]
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and r8,r12,r0,lsr#22
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eor r5,r5,r6,lsl#18
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eor r4,r4,r6,lsr#14
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ldr r6,[sp,r8] @ tab[b >> 24 & 0x7]
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and r9,r12,r0,lsr#25
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eor r5,r5,r7,lsl#21
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eor r4,r4,r7,lsr#11
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ldr r7,[sp,r9] @ tab[b >> 27 & 0x7]
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tst r1,#1<<30
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and r8,r12,r0,lsr#28
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eor r5,r5,r6,lsl#24
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eor r4,r4,r6,lsr#8
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ldr r6,[sp,r8] @ tab[b >> 30 ]
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eorne r5,r5,r0,lsl#30
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eorne r4,r4,r0,lsr#2
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tst r1,#1<<31
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eor r5,r5,r7,lsl#27
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eor r4,r4,r7,lsr#5
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eorne r5,r5,r0,lsl#31
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eorne r4,r4,r0,lsr#1
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eor r5,r5,r6,lsl#30
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eor r4,r4,r6,lsr#2
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mov pc,lr
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.size mul_1x1_ialu,.-mul_1x1_ialu
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.global bn_GF2m_mul_2x2
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.type bn_GF2m_mul_2x2,%function
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.align 5
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bn_GF2m_mul_2x2:
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#if __ARM_ARCH__>=7
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ldr r12,.LOPENSSL_armcap
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.Lpic: ldr r12,[pc,r12]
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tst r12,#1
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beq .Lialu
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veor d18,d18
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vmov.32 d19,r3,r3 @ two copies of b1
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vmov.32 d18[0],r1 @ a1
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veor d20,d20
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vld1.32 d21[],[sp,:32] @ two copies of b0
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vmov.32 d20[0],r2 @ a0
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mov r12,lr
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vmov d16,d18
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vmov d17,d19
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bl mul_1x1_neon @ a1·b1
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vmov d22,d0
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vmov d16,d20
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vmov d17,d21
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bl mul_1x1_neon @ a0·b0
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vmov d23,d0
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veor d16,d20,d18
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veor d17,d21,d19
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veor d20,d23,d22
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bl mul_1x1_neon @ (a0+a1)·(b0+b1)
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veor d0,d20 @ (a0+a1)·(b0+b1)-a0·b0-a1·b1
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vshl.u64 d1,d0,#32
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vshr.u64 d0,d0,#32
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veor d23,d1
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veor d22,d0
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vst1.32 {d23[0]},[r0,:32]!
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vst1.32 {d23[1]},[r0,:32]!
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vst1.32 {d22[0]},[r0,:32]!
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vst1.32 {d22[1]},[r0,:32]
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bx r12
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.align 4
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.Lialu:
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#endif
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stmdb sp!,{r4-r10,lr}
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mov r10,r0 @ reassign 1st argument
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mov r0,r3 @ r0=b1
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ldr r3,[sp,#32] @ load b0
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mov r12,#7<<2
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sub sp,sp,#32 @ allocate tab[8]
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bl mul_1x1_ialu @ a1·b1
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str r5,[r10,#8]
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str r4,[r10,#12]
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eor r0,r0,r3 @ flip b0 and b1
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eor r1,r1,r2 @ flip a0 and a1
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eor r3,r3,r0
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eor r2,r2,r1
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eor r0,r0,r3
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eor r1,r1,r2
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bl mul_1x1_ialu @ a0·b0
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str r5,[r10]
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str r4,[r10,#4]
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eor r1,r1,r2
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eor r0,r0,r3
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bl mul_1x1_ialu @ (a1+a0)·(b1+b0)
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ldmia r10,{r6-r9}
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eor r5,r5,r4
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eor r4,r4,r7
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eor r5,r5,r6
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eor r4,r4,r8
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eor r5,r5,r9
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eor r4,r4,r9
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str r4,[r10,#8]
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eor r5,r5,r4
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add sp,sp,#32 @ destroy tab[8]
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str r5,[r10,#4]
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#if __ARM_ARCH__>=5
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ldmia sp!,{r4-r10,pc}
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#else
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ldmia sp!,{r4-r10,lr}
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tst lr,#1
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moveq pc,lr @ be binary compatible with V4, yet
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.word 0xe12fff1e @ interoperable with Thumb ISA:-)
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#endif
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.size bn_GF2m_mul_2x2,.-bn_GF2m_mul_2x2
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#if __ARM_ARCH__>=7
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.align 5
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.LOPENSSL_armcap:
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.word OPENSSL_armcap_P-(.Lpic+8)
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#endif
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.asciz "GF(2^m) Multiplication for ARMv4/NEON, CRYPTOGAMS by <appro@openssl.org>"
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.align 5
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.comm OPENSSL_armcap_P,4,4
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@ -0,0 +1,147 @@
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.text
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.global bn_mul_mont
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.type bn_mul_mont,%function
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.align 2
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bn_mul_mont:
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stmdb sp!,{r0,r2} @ sp points at argument block
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ldr r0,[sp,#3*4] @ load num
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cmp r0,#2
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movlt r0,#0
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addlt sp,sp,#2*4
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blt .Labrt
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stmdb sp!,{r4-r12,lr} @ save 10 registers
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mov r0,r0,lsl#2 @ rescale r0 for byte count
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sub sp,sp,r0 @ alloca(4*num)
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sub sp,sp,#4 @ +extra dword
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sub r0,r0,#4 @ "num=num-1"
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add r4,r2,r0 @ &bp[num-1]
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add r0,sp,r0 @ r0 to point at &tp[num-1]
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ldr r8,[r0,#14*4] @ &n0
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ldr r2,[r2] @ bp[0]
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ldr r5,[r1],#4 @ ap[0],ap++
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ldr r6,[r3],#4 @ np[0],np++
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ldr r8,[r8] @ *n0
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str r4,[r0,#15*4] @ save &bp[num]
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umull r10,r11,r5,r2 @ ap[0]*bp[0]
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str r8,[r0,#14*4] @ save n0 value
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mul r8,r10,r8 @ "tp[0]"*n0
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mov r12,#0
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umlal r10,r12,r6,r8 @ np[0]*n0+"t[0]"
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mov r4,sp
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.L1st:
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ldr r5,[r1],#4 @ ap[j],ap++
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mov r10,r11
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ldr r6,[r3],#4 @ np[j],np++
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mov r11,#0
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umlal r10,r11,r5,r2 @ ap[j]*bp[0]
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mov r14,#0
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umlal r12,r14,r6,r8 @ np[j]*n0
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adds r12,r12,r10
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str r12,[r4],#4 @ tp[j-1]=,tp++
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adc r12,r14,#0
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cmp r4,r0
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bne .L1st
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adds r12,r12,r11
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ldr r4,[r0,#13*4] @ restore bp
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mov r14,#0
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ldr r8,[r0,#14*4] @ restore n0
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adc r14,r14,#0
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str r12,[r0] @ tp[num-1]=
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str r14,[r0,#4] @ tp[num]=
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||||
|
||||
.Louter:
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sub r7,r0,sp @ "original" r0-1 value
|
||||
sub r1,r1,r7 @ "rewind" ap to &ap[1]
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ldr r2,[r4,#4]! @ *(++bp)
|
||||
sub r3,r3,r7 @ "rewind" np to &np[1]
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ldr r5,[r1,#-4] @ ap[0]
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ldr r10,[sp] @ tp[0]
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ldr r6,[r3,#-4] @ np[0]
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||||
ldr r7,[sp,#4] @ tp[1]
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||||
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mov r11,#0
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umlal r10,r11,r5,r2 @ ap[0]*bp[i]+tp[0]
|
||||
str r4,[r0,#13*4] @ save bp
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||||
mul r8,r10,r8
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mov r12,#0
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||||
umlal r10,r12,r6,r8 @ np[0]*n0+"tp[0]"
|
||||
mov r4,sp
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||||
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||||
.Linner:
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||||
ldr r5,[r1],#4 @ ap[j],ap++
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adds r10,r11,r7 @ +=tp[j]
|
||||
ldr r6,[r3],#4 @ np[j],np++
|
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mov r11,#0
|
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umlal r10,r11,r5,r2 @ ap[j]*bp[i]
|
||||
mov r14,#0
|
||||
umlal r12,r14,r6,r8 @ np[j]*n0
|
||||
adc r11,r11,#0
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||||
ldr r7,[r4,#8] @ tp[j+1]
|
||||
adds r12,r12,r10
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||||
str r12,[r4],#4 @ tp[j-1]=,tp++
|
||||
adc r12,r14,#0
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cmp r4,r0
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||||
bne .Linner
|
||||
|
||||
adds r12,r12,r11
|
||||
mov r14,#0
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||||
ldr r4,[r0,#13*4] @ restore bp
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||||
adc r14,r14,#0
|
||||
ldr r8,[r0,#14*4] @ restore n0
|
||||
adds r12,r12,r7
|
||||
ldr r7,[r0,#15*4] @ restore &bp[num]
|
||||
adc r14,r14,#0
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||||
str r12,[r0] @ tp[num-1]=
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||||
str r14,[r0,#4] @ tp[num]=
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|
||||
cmp r4,r7
|
||||
bne .Louter
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||||
|
||||
|
||||
ldr r2,[r0,#12*4] @ pull rp
|
||||
add r0,r0,#4 @ r0 to point at &tp[num]
|
||||
sub r5,r0,sp @ "original" num value
|
||||
mov r4,sp @ "rewind" r4
|
||||
mov r1,r4 @ "borrow" r1
|
||||
sub r3,r3,r5 @ "rewind" r3 to &np[0]
|
||||
|
||||
subs r7,r7,r7 @ "clear" carry flag
|
||||
.Lsub: ldr r7,[r4],#4
|
||||
ldr r6,[r3],#4
|
||||
sbcs r7,r7,r6 @ tp[j]-np[j]
|
||||
str r7,[r2],#4 @ rp[j]=
|
||||
teq r4,r0 @ preserve carry
|
||||
bne .Lsub
|
||||
sbcs r14,r14,#0 @ upmost carry
|
||||
mov r4,sp @ "rewind" r4
|
||||
sub r2,r2,r5 @ "rewind" r2
|
||||
|
||||
and r1,r4,r14
|
||||
bic r3,r2,r14
|
||||
orr r1,r1,r3 @ ap=borrow?tp:rp
|
||||
|
||||
.Lcopy: ldr r7,[r1],#4 @ copy or in-place refresh
|
||||
str sp,[r4],#4 @ zap tp
|
||||
str r7,[r2],#4
|
||||
cmp r4,r0
|
||||
bne .Lcopy
|
||||
|
||||
add sp,r0,#4 @ skip over tp[num+1]
|
||||
ldmia sp!,{r4-r12,lr} @ restore registers
|
||||
add sp,sp,#2*4 @ skip over {r0,r2}
|
||||
mov r0,#1
|
||||
.Labrt: tst lr,#1
|
||||
moveq pc,lr @ be binary compatible with V4, yet
|
||||
.word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
||||
.size bn_mul_mont,.-bn_mul_mont
|
||||
.asciz "Montgomery multiplication for ARMv4, CRYPTOGAMS by <appro@openssl.org>"
|
||||
.align 2
|
||||
|
|
@ -0,0 +1,415 @@
|
|||
#include "arm_arch.h"
|
||||
|
||||
.text
|
||||
.code 32
|
||||
|
||||
.type rem_4bit,%object
|
||||
.align 5
|
||||
rem_4bit:
|
||||
.short 0x0000,0x1C20,0x3840,0x2460
|
||||
.short 0x7080,0x6CA0,0x48C0,0x54E0
|
||||
.short 0xE100,0xFD20,0xD940,0xC560
|
||||
.short 0x9180,0x8DA0,0xA9C0,0xB5E0
|
||||
.size rem_4bit,.-rem_4bit
|
||||
|
||||
.type rem_4bit_get,%function
|
||||
rem_4bit_get:
|
||||
sub r2,pc,#8
|
||||
sub r2,r2,#32 @ &rem_4bit
|
||||
b .Lrem_4bit_got
|
||||
nop
|
||||
.size rem_4bit_get,.-rem_4bit_get
|
||||
|
||||
.global gcm_ghash_4bit
|
||||
.type gcm_ghash_4bit,%function
|
||||
gcm_ghash_4bit:
|
||||
sub r12,pc,#8
|
||||
add r3,r2,r3 @ r3 to point at the end
|
||||
stmdb sp!,{r3-r11,lr} @ save r3/end too
|
||||
sub r12,r12,#48 @ &rem_4bit
|
||||
|
||||
ldmia r12,{r4-r11} @ copy rem_4bit ...
|
||||
stmdb sp!,{r4-r11} @ ... to stack
|
||||
|
||||
ldrb r12,[r2,#15]
|
||||
ldrb r14,[r0,#15]
|
||||
.Louter:
|
||||
eor r12,r12,r14
|
||||
and r14,r12,#0xf0
|
||||
and r12,r12,#0x0f
|
||||
mov r3,#14
|
||||
|
||||
add r7,r1,r12,lsl#4
|
||||
ldmia r7,{r4-r7} @ load Htbl[nlo]
|
||||
add r11,r1,r14
|
||||
ldrb r12,[r2,#14]
|
||||
|
||||
and r14,r4,#0xf @ rem
|
||||
ldmia r11,{r8-r11} @ load Htbl[nhi]
|
||||
add r14,r14,r14
|
||||
eor r4,r8,r4,lsr#4
|
||||
ldrh r8,[sp,r14] @ rem_4bit[rem]
|
||||
eor r4,r4,r5,lsl#28
|
||||
ldrb r14,[r0,#14]
|
||||
eor r5,r9,r5,lsr#4
|
||||
eor r5,r5,r6,lsl#28
|
||||
eor r6,r10,r6,lsr#4
|
||||
eor r6,r6,r7,lsl#28
|
||||
eor r7,r11,r7,lsr#4
|
||||
eor r12,r12,r14
|
||||
and r14,r12,#0xf0
|
||||
and r12,r12,#0x0f
|
||||
eor r7,r7,r8,lsl#16
|
||||
|
||||
.Linner:
|
||||
add r11,r1,r12,lsl#4
|
||||
and r12,r4,#0xf @ rem
|
||||
subs r3,r3,#1
|
||||
add r12,r12,r12
|
||||
ldmia r11,{r8-r11} @ load Htbl[nlo]
|
||||
eor r4,r8,r4,lsr#4
|
||||
eor r4,r4,r5,lsl#28
|
||||
eor r5,r9,r5,lsr#4
|
||||
eor r5,r5,r6,lsl#28
|
||||
ldrh r8,[sp,r12] @ rem_4bit[rem]
|
||||
eor r6,r10,r6,lsr#4
|
||||
ldrplb r12,[r2,r3]
|
||||
eor r6,r6,r7,lsl#28
|
||||
eor r7,r11,r7,lsr#4
|
||||
|
||||
add r11,r1,r14
|
||||
and r14,r4,#0xf @ rem
|
||||
eor r7,r7,r8,lsl#16 @ ^= rem_4bit[rem]
|
||||
add r14,r14,r14
|
||||
ldmia r11,{r8-r11} @ load Htbl[nhi]
|
||||
eor r4,r8,r4,lsr#4
|
||||
ldrplb r8,[r0,r3]
|
||||
eor r4,r4,r5,lsl#28
|
||||
eor r5,r9,r5,lsr#4
|
||||
ldrh r9,[sp,r14]
|
||||
eor r5,r5,r6,lsl#28
|
||||
eor r6,r10,r6,lsr#4
|
||||
eor r6,r6,r7,lsl#28
|
||||
eorpl r12,r12,r8
|
||||
eor r7,r11,r7,lsr#4
|
||||
andpl r14,r12,#0xf0
|
||||
andpl r12,r12,#0x0f
|
||||
eor r7,r7,r9,lsl#16 @ ^= rem_4bit[rem]
|
||||
bpl .Linner
|
||||
|
||||
ldr r3,[sp,#32] @ re-load r3/end
|
||||
add r2,r2,#16
|
||||
mov r14,r4
|
||||
#if __ARM_ARCH__>=7 && defined(__ARMEL__)
|
||||
rev r4,r4
|
||||
str r4,[r0,#12]
|
||||
#elif defined(__ARMEB__)
|
||||
str r4,[r0,#12]
|
||||
#else
|
||||
mov r9,r4,lsr#8
|
||||
strb r4,[r0,#12+3]
|
||||
mov r10,r4,lsr#16
|
||||
strb r9,[r0,#12+2]
|
||||
mov r11,r4,lsr#24
|
||||
strb r10,[r0,#12+1]
|
||||
strb r11,[r0,#12]
|
||||
#endif
|
||||
cmp r2,r3
|
||||
#if __ARM_ARCH__>=7 && defined(__ARMEL__)
|
||||
rev r5,r5
|
||||
str r5,[r0,#8]
|
||||
#elif defined(__ARMEB__)
|
||||
str r5,[r0,#8]
|
||||
#else
|
||||
mov r9,r5,lsr#8
|
||||
strb r5,[r0,#8+3]
|
||||
mov r10,r5,lsr#16
|
||||
strb r9,[r0,#8+2]
|
||||
mov r11,r5,lsr#24
|
||||
strb r10,[r0,#8+1]
|
||||
strb r11,[r0,#8]
|
||||
#endif
|
||||
ldrneb r12,[r2,#15]
|
||||
#if __ARM_ARCH__>=7 && defined(__ARMEL__)
|
||||
rev r6,r6
|
||||
str r6,[r0,#4]
|
||||
#elif defined(__ARMEB__)
|
||||
str r6,[r0,#4]
|
||||
#else
|
||||
mov r9,r6,lsr#8
|
||||
strb r6,[r0,#4+3]
|
||||
mov r10,r6,lsr#16
|
||||
strb r9,[r0,#4+2]
|
||||
mov r11,r6,lsr#24
|
||||
strb r10,[r0,#4+1]
|
||||
strb r11,[r0,#4]
|
||||
#endif
|
||||
|
||||
|
||||
#if __ARM_ARCH__>=7 && defined(__ARMEL__)
|
||||
rev r7,r7
|
||||
str r7,[r0,#0]
|
||||
#elif defined(__ARMEB__)
|
||||
str r7,[r0,#0]
|
||||
#else
|
||||
mov r9,r7,lsr#8
|
||||
strb r7,[r0,#0+3]
|
||||
mov r10,r7,lsr#16
|
||||
strb r9,[r0,#0+2]
|
||||
mov r11,r7,lsr#24
|
||||
strb r10,[r0,#0+1]
|
||||
strb r11,[r0,#0]
|
||||
#endif
|
||||
|
||||
|
||||
bne .Louter
|
||||
|
||||
add sp,sp,#36
|
||||
#if __ARM_ARCH__>=5
|
||||
ldmia sp!,{r4-r11,pc}
|
||||
#else
|
||||
ldmia sp!,{r4-r11,lr}
|
||||
tst lr,#1
|
||||
moveq pc,lr @ be binary compatible with V4, yet
|
||||
.word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
||||
#endif
|
||||
.size gcm_ghash_4bit,.-gcm_ghash_4bit
|
||||
|
||||
.global gcm_gmult_4bit
|
||||
.type gcm_gmult_4bit,%function
|
||||
gcm_gmult_4bit:
|
||||
stmdb sp!,{r4-r11,lr}
|
||||
ldrb r12,[r0,#15]
|
||||
b rem_4bit_get
|
||||
.Lrem_4bit_got:
|
||||
and r14,r12,#0xf0
|
||||
and r12,r12,#0x0f
|
||||
mov r3,#14
|
||||
|
||||
add r7,r1,r12,lsl#4
|
||||
ldmia r7,{r4-r7} @ load Htbl[nlo]
|
||||
ldrb r12,[r0,#14]
|
||||
|
||||
add r11,r1,r14
|
||||
and r14,r4,#0xf @ rem
|
||||
ldmia r11,{r8-r11} @ load Htbl[nhi]
|
||||
add r14,r14,r14
|
||||
eor r4,r8,r4,lsr#4
|
||||
ldrh r8,[r2,r14] @ rem_4bit[rem]
|
||||
eor r4,r4,r5,lsl#28
|
||||
eor r5,r9,r5,lsr#4
|
||||
eor r5,r5,r6,lsl#28
|
||||
eor r6,r10,r6,lsr#4
|
||||
eor r6,r6,r7,lsl#28
|
||||
eor r7,r11,r7,lsr#4
|
||||
and r14,r12,#0xf0
|
||||
eor r7,r7,r8,lsl#16
|
||||
and r12,r12,#0x0f
|
||||
|
||||
.Loop:
|
||||
add r11,r1,r12,lsl#4
|
||||
and r12,r4,#0xf @ rem
|
||||
subs r3,r3,#1
|
||||
add r12,r12,r12
|
||||
ldmia r11,{r8-r11} @ load Htbl[nlo]
|
||||
eor r4,r8,r4,lsr#4
|
||||
eor r4,r4,r5,lsl#28
|
||||
eor r5,r9,r5,lsr#4
|
||||
eor r5,r5,r6,lsl#28
|
||||
ldrh r8,[r2,r12] @ rem_4bit[rem]
|
||||
eor r6,r10,r6,lsr#4
|
||||
ldrplb r12,[r0,r3]
|
||||
eor r6,r6,r7,lsl#28
|
||||
eor r7,r11,r7,lsr#4
|
||||
|
||||
add r11,r1,r14
|
||||
and r14,r4,#0xf @ rem
|
||||
eor r7,r7,r8,lsl#16 @ ^= rem_4bit[rem]
|
||||
add r14,r14,r14
|
||||
ldmia r11,{r8-r11} @ load Htbl[nhi]
|
||||
eor r4,r8,r4,lsr#4
|
||||
eor r4,r4,r5,lsl#28
|
||||
eor r5,r9,r5,lsr#4
|
||||
ldrh r8,[r2,r14] @ rem_4bit[rem]
|
||||
eor r5,r5,r6,lsl#28
|
||||
eor r6,r10,r6,lsr#4
|
||||
eor r6,r6,r7,lsl#28
|
||||
eor r7,r11,r7,lsr#4
|
||||
andpl r14,r12,#0xf0
|
||||
andpl r12,r12,#0x0f
|
||||
eor r7,r7,r8,lsl#16 @ ^= rem_4bit[rem]
|
||||
bpl .Loop
|
||||
#if __ARM_ARCH__>=7 && defined(__ARMEL__)
|
||||
rev r4,r4
|
||||
str r4,[r0,#12]
|
||||
#elif defined(__ARMEB__)
|
||||
str r4,[r0,#12]
|
||||
#else
|
||||
mov r9,r4,lsr#8
|
||||
strb r4,[r0,#12+3]
|
||||
mov r10,r4,lsr#16
|
||||
strb r9,[r0,#12+2]
|
||||
mov r11,r4,lsr#24
|
||||
strb r10,[r0,#12+1]
|
||||
strb r11,[r0,#12]
|
||||
#endif
|
||||
|
||||
|
||||
#if __ARM_ARCH__>=7 && defined(__ARMEL__)
|
||||
rev r5,r5
|
||||
str r5,[r0,#8]
|
||||
#elif defined(__ARMEB__)
|
||||
str r5,[r0,#8]
|
||||
#else
|
||||
mov r9,r5,lsr#8
|
||||
strb r5,[r0,#8+3]
|
||||
mov r10,r5,lsr#16
|
||||
strb r9,[r0,#8+2]
|
||||
mov r11,r5,lsr#24
|
||||
strb r10,[r0,#8+1]
|
||||
strb r11,[r0,#8]
|
||||
#endif
|
||||
|
||||
|
||||
#if __ARM_ARCH__>=7 && defined(__ARMEL__)
|
||||
rev r6,r6
|
||||
str r6,[r0,#4]
|
||||
#elif defined(__ARMEB__)
|
||||
str r6,[r0,#4]
|
||||
#else
|
||||
mov r9,r6,lsr#8
|
||||
strb r6,[r0,#4+3]
|
||||
mov r10,r6,lsr#16
|
||||
strb r9,[r0,#4+2]
|
||||
mov r11,r6,lsr#24
|
||||
strb r10,[r0,#4+1]
|
||||
strb r11,[r0,#4]
|
||||
#endif
|
||||
|
||||
|
||||
#if __ARM_ARCH__>=7 && defined(__ARMEL__)
|
||||
rev r7,r7
|
||||
str r7,[r0,#0]
|
||||
#elif defined(__ARMEB__)
|
||||
str r7,[r0,#0]
|
||||
#else
|
||||
mov r9,r7,lsr#8
|
||||
strb r7,[r0,#0+3]
|
||||
mov r10,r7,lsr#16
|
||||
strb r9,[r0,#0+2]
|
||||
mov r11,r7,lsr#24
|
||||
strb r10,[r0,#0+1]
|
||||
strb r11,[r0,#0]
|
||||
#endif
|
||||
|
||||
|
||||
#if __ARM_ARCH__>=5
|
||||
ldmia sp!,{r4-r11,pc}
|
||||
#else
|
||||
ldmia sp!,{r4-r11,lr}
|
||||
tst lr,#1
|
||||
moveq pc,lr @ be binary compatible with V4, yet
|
||||
.word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
||||
#endif
|
||||
.size gcm_gmult_4bit,.-gcm_gmult_4bit
|
||||
#if __ARM_ARCH__>=7
|
||||
.fpu neon
|
||||
|
||||
.global gcm_gmult_neon
|
||||
.type gcm_gmult_neon,%function
|
||||
.align 4
|
||||
gcm_gmult_neon:
|
||||
sub r1,#16 @ point at H in GCM128_CTX
|
||||
vld1.64 d29,[r0,:64]!@ load Xi
|
||||
vmov.i32 d5,#0xe1 @ our irreducible polynomial
|
||||
vld1.64 d28,[r0,:64]!
|
||||
vshr.u64 d5,#32
|
||||
vldmia r1,{d0-d1} @ load H
|
||||
veor q12,q12
|
||||
#ifdef __ARMEL__
|
||||
vrev64.8 q14,q14
|
||||
#endif
|
||||
veor q13,q13
|
||||
veor q11,q11
|
||||
mov r1,#16
|
||||
veor q10,q10
|
||||
mov r3,#16
|
||||
veor d2,d2
|
||||
vdup.8 d4,d28[0] @ broadcast lowest byte
|
||||
b .Linner_neon
|
||||
.size gcm_gmult_neon,.-gcm_gmult_neon
|
||||
|
||||
.global gcm_ghash_neon
|
||||
.type gcm_ghash_neon,%function
|
||||
.align 4
|
||||
gcm_ghash_neon:
|
||||
vld1.64 d21,[r0,:64]! @ load Xi
|
||||
vmov.i32 d5,#0xe1 @ our irreducible polynomial
|
||||
vld1.64 d20,[r0,:64]!
|
||||
vshr.u64 d5,#32
|
||||
vldmia r0,{d0-d1} @ load H
|
||||
veor q12,q12
|
||||
nop
|
||||
#ifdef __ARMEL__
|
||||
vrev64.8 q10,q10
|
||||
#endif
|
||||
.Louter_neon:
|
||||
vld1.64 d29,[r2]! @ load inp
|
||||
veor q13,q13
|
||||
vld1.64 d28,[r2]!
|
||||
veor q11,q11
|
||||
mov r1,#16
|
||||
#ifdef __ARMEL__
|
||||
vrev64.8 q14,q14
|
||||
#endif
|
||||
veor d2,d2
|
||||
veor q14,q10 @ inp^=Xi
|
||||
veor q10,q10
|
||||
vdup.8 d4,d28[0] @ broadcast lowest byte
|
||||
.Linner_neon:
|
||||
subs r1,r1,#1
|
||||
vmull.p8 q9,d1,d4 @ H.lo·Xi[i]
|
||||
vmull.p8 q8,d0,d4 @ H.hi·Xi[i]
|
||||
vext.8 q14,q12,#1 @ IN>>=8
|
||||
|
||||
veor q10,q13 @ modulo-scheduled part
|
||||
vshl.i64 d22,#48
|
||||
vdup.8 d4,d28[0] @ broadcast lowest byte
|
||||
veor d3,d18,d20
|
||||
|
||||
veor d21,d22
|
||||
vuzp.8 q9,q8
|
||||
vsli.8 d2,d3,#1 @ compose the "carry" byte
|
||||
vext.8 q10,q12,#1 @ Z>>=8
|
||||
|
||||
vmull.p8 q11,d2,d5 @ "carry"·0xe1
|
||||
vshr.u8 d2,d3,#7 @ save Z's bottom bit
|
||||
vext.8 q13,q9,q12,#1 @ Qlo>>=8
|
||||
veor q10,q8
|
||||
bne .Linner_neon
|
||||
|
||||
veor q10,q13 @ modulo-scheduled artefact
|
||||
vshl.i64 d22,#48
|
||||
veor d21,d22
|
||||
|
||||
@ finalization, normalize Z:Zo
|
||||
vand d2,d5 @ suffices to mask the bit
|
||||
vshr.u64 d3,d20,#63
|
||||
vshl.i64 q10,#1
|
||||
subs r3,#16
|
||||
vorr q10,q1 @ Z=Z:Zo<<1
|
||||
bne .Louter_neon
|
||||
|
||||
#ifdef __ARMEL__
|
||||
vrev64.8 q10,q10
|
||||
#endif
|
||||
sub r0,#16
|
||||
|
||||
vst1.64 d21,[r0,:64]! @ write out Xi
|
||||
vst1.64 d20,[r0,:64]
|
||||
|
||||
.word 0xe12fff1e
|
||||
.size gcm_ghash_neon,.-gcm_ghash_neon
|
||||
#endif
|
||||
.asciz "GHASH for ARMv4/NEON, CRYPTOGAMS by <appro@openssl.org>"
|
||||
.align 2
|
||||
|
|
@ -0,0 +1,452 @@
|
|||
#include "arm_arch.h"
|
||||
|
||||
.text
|
||||
|
||||
.global sha1_block_data_order
|
||||
.type sha1_block_data_order,%function
|
||||
|
||||
.align 2
|
||||
sha1_block_data_order:
|
||||
stmdb sp!,{r4-r12,lr}
|
||||
add r2,r1,r2,lsl#6 @ r2 to point at the end of r1
|
||||
ldmia r0,{r3,r4,r5,r6,r7}
|
||||
.Lloop:
|
||||
ldr r8,.LK_00_19
|
||||
mov r14,sp
|
||||
sub sp,sp,#15*4
|
||||
mov r5,r5,ror#30
|
||||
mov r6,r6,ror#30
|
||||
mov r7,r7,ror#30 @ [6]
|
||||
.L_00_15:
|
||||
#if __ARM_ARCH__<7
|
||||
ldrb r10,[r1,#2]
|
||||
ldrb r9,[r1,#3]
|
||||
ldrb r11,[r1,#1]
|
||||
add r7,r8,r7,ror#2 @ E+=K_00_19
|
||||
ldrb r12,[r1],#4
|
||||
orr r9,r9,r10,lsl#8
|
||||
eor r10,r5,r6 @ F_xx_xx
|
||||
orr r9,r9,r11,lsl#16
|
||||
add r7,r7,r3,ror#27 @ E+=ROR(A,27)
|
||||
orr r9,r9,r12,lsl#24
|
||||
#else
|
||||
ldr r9,[r1],#4 @ handles unaligned
|
||||
add r7,r8,r7,ror#2 @ E+=K_00_19
|
||||
eor r10,r5,r6 @ F_xx_xx
|
||||
add r7,r7,r3,ror#27 @ E+=ROR(A,27)
|
||||
#ifdef __ARMEL__
|
||||
rev r9,r9 @ byte swap
|
||||
#endif
|
||||
#endif
|
||||
and r10,r4,r10,ror#2
|
||||
add r7,r7,r9 @ E+=X[i]
|
||||
eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
|
||||
str r9,[r14,#-4]!
|
||||
add r7,r7,r10 @ E+=F_00_19(B,C,D)
|
||||
#if __ARM_ARCH__<7
|
||||
ldrb r10,[r1,#2]
|
||||
ldrb r9,[r1,#3]
|
||||
ldrb r11,[r1,#1]
|
||||
add r6,r8,r6,ror#2 @ E+=K_00_19
|
||||
ldrb r12,[r1],#4
|
||||
orr r9,r9,r10,lsl#8
|
||||
eor r10,r4,r5 @ F_xx_xx
|
||||
orr r9,r9,r11,lsl#16
|
||||
add r6,r6,r7,ror#27 @ E+=ROR(A,27)
|
||||
orr r9,r9,r12,lsl#24
|
||||
#else
|
||||
ldr r9,[r1],#4 @ handles unaligned
|
||||
add r6,r8,r6,ror#2 @ E+=K_00_19
|
||||
eor r10,r4,r5 @ F_xx_xx
|
||||
add r6,r6,r7,ror#27 @ E+=ROR(A,27)
|
||||
#ifdef __ARMEL__
|
||||
rev r9,r9 @ byte swap
|
||||
#endif
|
||||
#endif
|
||||
and r10,r3,r10,ror#2
|
||||
add r6,r6,r9 @ E+=X[i]
|
||||
eor r10,r10,r5,ror#2 @ F_00_19(B,C,D)
|
||||
str r9,[r14,#-4]!
|
||||
add r6,r6,r10 @ E+=F_00_19(B,C,D)
|
||||
#if __ARM_ARCH__<7
|
||||
ldrb r10,[r1,#2]
|
||||
ldrb r9,[r1,#3]
|
||||
ldrb r11,[r1,#1]
|
||||
add r5,r8,r5,ror#2 @ E+=K_00_19
|
||||
ldrb r12,[r1],#4
|
||||
orr r9,r9,r10,lsl#8
|
||||
eor r10,r3,r4 @ F_xx_xx
|
||||
orr r9,r9,r11,lsl#16
|
||||
add r5,r5,r6,ror#27 @ E+=ROR(A,27)
|
||||
orr r9,r9,r12,lsl#24
|
||||
#else
|
||||
ldr r9,[r1],#4 @ handles unaligned
|
||||
add r5,r8,r5,ror#2 @ E+=K_00_19
|
||||
eor r10,r3,r4 @ F_xx_xx
|
||||
add r5,r5,r6,ror#27 @ E+=ROR(A,27)
|
||||
#ifdef __ARMEL__
|
||||
rev r9,r9 @ byte swap
|
||||
#endif
|
||||
#endif
|
||||
and r10,r7,r10,ror#2
|
||||
add r5,r5,r9 @ E+=X[i]
|
||||
eor r10,r10,r4,ror#2 @ F_00_19(B,C,D)
|
||||
str r9,[r14,#-4]!
|
||||
add r5,r5,r10 @ E+=F_00_19(B,C,D)
|
||||
#if __ARM_ARCH__<7
|
||||
ldrb r10,[r1,#2]
|
||||
ldrb r9,[r1,#3]
|
||||
ldrb r11,[r1,#1]
|
||||
add r4,r8,r4,ror#2 @ E+=K_00_19
|
||||
ldrb r12,[r1],#4
|
||||
orr r9,r9,r10,lsl#8
|
||||
eor r10,r7,r3 @ F_xx_xx
|
||||
orr r9,r9,r11,lsl#16
|
||||
add r4,r4,r5,ror#27 @ E+=ROR(A,27)
|
||||
orr r9,r9,r12,lsl#24
|
||||
#else
|
||||
ldr r9,[r1],#4 @ handles unaligned
|
||||
add r4,r8,r4,ror#2 @ E+=K_00_19
|
||||
eor r10,r7,r3 @ F_xx_xx
|
||||
add r4,r4,r5,ror#27 @ E+=ROR(A,27)
|
||||
#ifdef __ARMEL__
|
||||
rev r9,r9 @ byte swap
|
||||
#endif
|
||||
#endif
|
||||
and r10,r6,r10,ror#2
|
||||
add r4,r4,r9 @ E+=X[i]
|
||||
eor r10,r10,r3,ror#2 @ F_00_19(B,C,D)
|
||||
str r9,[r14,#-4]!
|
||||
add r4,r4,r10 @ E+=F_00_19(B,C,D)
|
||||
#if __ARM_ARCH__<7
|
||||
ldrb r10,[r1,#2]
|
||||
ldrb r9,[r1,#3]
|
||||
ldrb r11,[r1,#1]
|
||||
add r3,r8,r3,ror#2 @ E+=K_00_19
|
||||
ldrb r12,[r1],#4
|
||||
orr r9,r9,r10,lsl#8
|
||||
eor r10,r6,r7 @ F_xx_xx
|
||||
orr r9,r9,r11,lsl#16
|
||||
add r3,r3,r4,ror#27 @ E+=ROR(A,27)
|
||||
orr r9,r9,r12,lsl#24
|
||||
#else
|
||||
ldr r9,[r1],#4 @ handles unaligned
|
||||
add r3,r8,r3,ror#2 @ E+=K_00_19
|
||||
eor r10,r6,r7 @ F_xx_xx
|
||||
add r3,r3,r4,ror#27 @ E+=ROR(A,27)
|
||||
#ifdef __ARMEL__
|
||||
rev r9,r9 @ byte swap
|
||||
#endif
|
||||
#endif
|
||||
and r10,r5,r10,ror#2
|
||||
add r3,r3,r9 @ E+=X[i]
|
||||
eor r10,r10,r7,ror#2 @ F_00_19(B,C,D)
|
||||
str r9,[r14,#-4]!
|
||||
add r3,r3,r10 @ E+=F_00_19(B,C,D)
|
||||
teq r14,sp
|
||||
bne .L_00_15 @ [((11+4)*5+2)*3]
|
||||
sub sp,sp,#25*4
|
||||
#if __ARM_ARCH__<7
|
||||
ldrb r10,[r1,#2]
|
||||
ldrb r9,[r1,#3]
|
||||
ldrb r11,[r1,#1]
|
||||
add r7,r8,r7,ror#2 @ E+=K_00_19
|
||||
ldrb r12,[r1],#4
|
||||
orr r9,r9,r10,lsl#8
|
||||
eor r10,r5,r6 @ F_xx_xx
|
||||
orr r9,r9,r11,lsl#16
|
||||
add r7,r7,r3,ror#27 @ E+=ROR(A,27)
|
||||
orr r9,r9,r12,lsl#24
|
||||
#else
|
||||
ldr r9,[r1],#4 @ handles unaligned
|
||||
add r7,r8,r7,ror#2 @ E+=K_00_19
|
||||
eor r10,r5,r6 @ F_xx_xx
|
||||
add r7,r7,r3,ror#27 @ E+=ROR(A,27)
|
||||
#ifdef __ARMEL__
|
||||
rev r9,r9 @ byte swap
|
||||
#endif
|
||||
#endif
|
||||
and r10,r4,r10,ror#2
|
||||
add r7,r7,r9 @ E+=X[i]
|
||||
eor r10,r10,r6,ror#2 @ F_00_19(B,C,D)
|
||||
str r9,[r14,#-4]!
|
||||
add r7,r7,r10 @ E+=F_00_19(B,C,D)
|
||||
ldr r9,[r14,#15*4]
|
||||
ldr r10,[r14,#13*4]
|
||||
ldr r11,[r14,#7*4]
|
||||
add r6,r8,r6,ror#2 @ E+=K_xx_xx
|
||||
ldr r12,[r14,#2*4]
|
||||
eor r9,r9,r10
|
||||
eor r11,r11,r12 @ 1 cycle stall
|
||||
eor r10,r4,r5 @ F_xx_xx
|
||||
mov r9,r9,ror#31
|
||||
add r6,r6,r7,ror#27 @ E+=ROR(A,27)
|
||||
eor r9,r9,r11,ror#31
|
||||
str r9,[r14,#-4]!
|
||||
and r10,r3,r10,ror#2 @ F_xx_xx
|
||||
@ F_xx_xx
|
||||
add r6,r6,r9 @ E+=X[i]
|
||||
eor r10,r10,r5,ror#2 @ F_00_19(B,C,D)
|
||||
add r6,r6,r10 @ E+=F_00_19(B,C,D)
|
||||
ldr r9,[r14,#15*4]
|
||||
ldr r10,[r14,#13*4]
|
||||
ldr r11,[r14,#7*4]
|
||||
add r5,r8,r5,ror#2 @ E+=K_xx_xx
|
||||
ldr r12,[r14,#2*4]
|
||||
eor r9,r9,r10
|
||||
eor r11,r11,r12 @ 1 cycle stall
|
||||
eor r10,r3,r4 @ F_xx_xx
|
||||
mov r9,r9,ror#31
|
||||
add r5,r5,r6,ror#27 @ E+=ROR(A,27)
|
||||
eor r9,r9,r11,ror#31
|
||||
str r9,[r14,#-4]!
|
||||
and r10,r7,r10,ror#2 @ F_xx_xx
|
||||
@ F_xx_xx
|
||||
add r5,r5,r9 @ E+=X[i]
|
||||
eor r10,r10,r4,ror#2 @ F_00_19(B,C,D)
|
||||
add r5,r5,r10 @ E+=F_00_19(B,C,D)
|
||||
ldr r9,[r14,#15*4]
|
||||
ldr r10,[r14,#13*4]
|
||||
ldr r11,[r14,#7*4]
|
||||
add r4,r8,r4,ror#2 @ E+=K_xx_xx
|
||||
ldr r12,[r14,#2*4]
|
||||
eor r9,r9,r10
|
||||
eor r11,r11,r12 @ 1 cycle stall
|
||||
eor r10,r7,r3 @ F_xx_xx
|
||||
mov r9,r9,ror#31
|
||||
add r4,r4,r5,ror#27 @ E+=ROR(A,27)
|
||||
eor r9,r9,r11,ror#31
|
||||
str r9,[r14,#-4]!
|
||||
and r10,r6,r10,ror#2 @ F_xx_xx
|
||||
@ F_xx_xx
|
||||
add r4,r4,r9 @ E+=X[i]
|
||||
eor r10,r10,r3,ror#2 @ F_00_19(B,C,D)
|
||||
add r4,r4,r10 @ E+=F_00_19(B,C,D)
|
||||
ldr r9,[r14,#15*4]
|
||||
ldr r10,[r14,#13*4]
|
||||
ldr r11,[r14,#7*4]
|
||||
add r3,r8,r3,ror#2 @ E+=K_xx_xx
|
||||
ldr r12,[r14,#2*4]
|
||||
eor r9,r9,r10
|
||||
eor r11,r11,r12 @ 1 cycle stall
|
||||
eor r10,r6,r7 @ F_xx_xx
|
||||
mov r9,r9,ror#31
|
||||
add r3,r3,r4,ror#27 @ E+=ROR(A,27)
|
||||
eor r9,r9,r11,ror#31
|
||||
str r9,[r14,#-4]!
|
||||
and r10,r5,r10,ror#2 @ F_xx_xx
|
||||
@ F_xx_xx
|
||||
add r3,r3,r9 @ E+=X[i]
|
||||
eor r10,r10,r7,ror#2 @ F_00_19(B,C,D)
|
||||
add r3,r3,r10 @ E+=F_00_19(B,C,D)
|
||||
|
||||
ldr r8,.LK_20_39 @ [+15+16*4]
|
||||
cmn sp,#0 @ [+3], clear carry to denote 20_39
|
||||
.L_20_39_or_60_79:
|
||||
ldr r9,[r14,#15*4]
|
||||
ldr r10,[r14,#13*4]
|
||||
ldr r11,[r14,#7*4]
|
||||
add r7,r8,r7,ror#2 @ E+=K_xx_xx
|
||||
ldr r12,[r14,#2*4]
|
||||
eor r9,r9,r10
|
||||
eor r11,r11,r12 @ 1 cycle stall
|
||||
eor r10,r5,r6 @ F_xx_xx
|
||||
mov r9,r9,ror#31
|
||||
add r7,r7,r3,ror#27 @ E+=ROR(A,27)
|
||||
eor r9,r9,r11,ror#31
|
||||
str r9,[r14,#-4]!
|
||||
eor r10,r4,r10,ror#2 @ F_xx_xx
|
||||
@ F_xx_xx
|
||||
add r7,r7,r9 @ E+=X[i]
|
||||
add r7,r7,r10 @ E+=F_20_39(B,C,D)
|
||||
ldr r9,[r14,#15*4]
|
||||
ldr r10,[r14,#13*4]
|
||||
ldr r11,[r14,#7*4]
|
||||
add r6,r8,r6,ror#2 @ E+=K_xx_xx
|
||||
ldr r12,[r14,#2*4]
|
||||
eor r9,r9,r10
|
||||
eor r11,r11,r12 @ 1 cycle stall
|
||||
eor r10,r4,r5 @ F_xx_xx
|
||||
mov r9,r9,ror#31
|
||||
add r6,r6,r7,ror#27 @ E+=ROR(A,27)
|
||||
eor r9,r9,r11,ror#31
|
||||
str r9,[r14,#-4]!
|
||||
eor r10,r3,r10,ror#2 @ F_xx_xx
|
||||
@ F_xx_xx
|
||||
add r6,r6,r9 @ E+=X[i]
|
||||
add r6,r6,r10 @ E+=F_20_39(B,C,D)
|
||||
ldr r9,[r14,#15*4]
|
||||
ldr r10,[r14,#13*4]
|
||||
ldr r11,[r14,#7*4]
|
||||
add r5,r8,r5,ror#2 @ E+=K_xx_xx
|
||||
ldr r12,[r14,#2*4]
|
||||
eor r9,r9,r10
|
||||
eor r11,r11,r12 @ 1 cycle stall
|
||||
eor r10,r3,r4 @ F_xx_xx
|
||||
mov r9,r9,ror#31
|
||||
add r5,r5,r6,ror#27 @ E+=ROR(A,27)
|
||||
eor r9,r9,r11,ror#31
|
||||
str r9,[r14,#-4]!
|
||||
eor r10,r7,r10,ror#2 @ F_xx_xx
|
||||
@ F_xx_xx
|
||||
add r5,r5,r9 @ E+=X[i]
|
||||
add r5,r5,r10 @ E+=F_20_39(B,C,D)
|
||||
ldr r9,[r14,#15*4]
|
||||
ldr r10,[r14,#13*4]
|
||||
ldr r11,[r14,#7*4]
|
||||
add r4,r8,r4,ror#2 @ E+=K_xx_xx
|
||||
ldr r12,[r14,#2*4]
|
||||
eor r9,r9,r10
|
||||
eor r11,r11,r12 @ 1 cycle stall
|
||||
eor r10,r7,r3 @ F_xx_xx
|
||||
mov r9,r9,ror#31
|
||||
add r4,r4,r5,ror#27 @ E+=ROR(A,27)
|
||||
eor r9,r9,r11,ror#31
|
||||
str r9,[r14,#-4]!
|
||||
eor r10,r6,r10,ror#2 @ F_xx_xx
|
||||
@ F_xx_xx
|
||||
add r4,r4,r9 @ E+=X[i]
|
||||
add r4,r4,r10 @ E+=F_20_39(B,C,D)
|
||||
ldr r9,[r14,#15*4]
|
||||
ldr r10,[r14,#13*4]
|
||||
ldr r11,[r14,#7*4]
|
||||
add r3,r8,r3,ror#2 @ E+=K_xx_xx
|
||||
ldr r12,[r14,#2*4]
|
||||
eor r9,r9,r10
|
||||
eor r11,r11,r12 @ 1 cycle stall
|
||||
eor r10,r6,r7 @ F_xx_xx
|
||||
mov r9,r9,ror#31
|
||||
add r3,r3,r4,ror#27 @ E+=ROR(A,27)
|
||||
eor r9,r9,r11,ror#31
|
||||
str r9,[r14,#-4]!
|
||||
eor r10,r5,r10,ror#2 @ F_xx_xx
|
||||
@ F_xx_xx
|
||||
add r3,r3,r9 @ E+=X[i]
|
||||
add r3,r3,r10 @ E+=F_20_39(B,C,D)
|
||||
teq r14,sp @ preserve carry
|
||||
bne .L_20_39_or_60_79 @ [+((12+3)*5+2)*4]
|
||||
bcs .L_done @ [+((12+3)*5+2)*4], spare 300 bytes
|
||||
|
||||
ldr r8,.LK_40_59
|
||||
sub sp,sp,#20*4 @ [+2]
|
||||
.L_40_59:
|
||||
ldr r9,[r14,#15*4]
|
||||
ldr r10,[r14,#13*4]
|
||||
ldr r11,[r14,#7*4]
|
||||
add r7,r8,r7,ror#2 @ E+=K_xx_xx
|
||||
ldr r12,[r14,#2*4]
|
||||
eor r9,r9,r10
|
||||
eor r11,r11,r12 @ 1 cycle stall
|
||||
eor r10,r5,r6 @ F_xx_xx
|
||||
mov r9,r9,ror#31
|
||||
add r7,r7,r3,ror#27 @ E+=ROR(A,27)
|
||||
eor r9,r9,r11,ror#31
|
||||
str r9,[r14,#-4]!
|
||||
and r10,r4,r10,ror#2 @ F_xx_xx
|
||||
and r11,r5,r6 @ F_xx_xx
|
||||
add r7,r7,r9 @ E+=X[i]
|
||||
add r7,r7,r10 @ E+=F_40_59(B,C,D)
|
||||
add r7,r7,r11,ror#2
|
||||
ldr r9,[r14,#15*4]
|
||||
ldr r10,[r14,#13*4]
|
||||
ldr r11,[r14,#7*4]
|
||||
add r6,r8,r6,ror#2 @ E+=K_xx_xx
|
||||
ldr r12,[r14,#2*4]
|
||||
eor r9,r9,r10
|
||||
eor r11,r11,r12 @ 1 cycle stall
|
||||
eor r10,r4,r5 @ F_xx_xx
|
||||
mov r9,r9,ror#31
|
||||
add r6,r6,r7,ror#27 @ E+=ROR(A,27)
|
||||
eor r9,r9,r11,ror#31
|
||||
str r9,[r14,#-4]!
|
||||
and r10,r3,r10,ror#2 @ F_xx_xx
|
||||
and r11,r4,r5 @ F_xx_xx
|
||||
add r6,r6,r9 @ E+=X[i]
|
||||
add r6,r6,r10 @ E+=F_40_59(B,C,D)
|
||||
add r6,r6,r11,ror#2
|
||||
ldr r9,[r14,#15*4]
|
||||
ldr r10,[r14,#13*4]
|
||||
ldr r11,[r14,#7*4]
|
||||
add r5,r8,r5,ror#2 @ E+=K_xx_xx
|
||||
ldr r12,[r14,#2*4]
|
||||
eor r9,r9,r10
|
||||
eor r11,r11,r12 @ 1 cycle stall
|
||||
eor r10,r3,r4 @ F_xx_xx
|
||||
mov r9,r9,ror#31
|
||||
add r5,r5,r6,ror#27 @ E+=ROR(A,27)
|
||||
eor r9,r9,r11,ror#31
|
||||
str r9,[r14,#-4]!
|
||||
and r10,r7,r10,ror#2 @ F_xx_xx
|
||||
and r11,r3,r4 @ F_xx_xx
|
||||
add r5,r5,r9 @ E+=X[i]
|
||||
add r5,r5,r10 @ E+=F_40_59(B,C,D)
|
||||
add r5,r5,r11,ror#2
|
||||
ldr r9,[r14,#15*4]
|
||||
ldr r10,[r14,#13*4]
|
||||
ldr r11,[r14,#7*4]
|
||||
add r4,r8,r4,ror#2 @ E+=K_xx_xx
|
||||
ldr r12,[r14,#2*4]
|
||||
eor r9,r9,r10
|
||||
eor r11,r11,r12 @ 1 cycle stall
|
||||
eor r10,r7,r3 @ F_xx_xx
|
||||
mov r9,r9,ror#31
|
||||
add r4,r4,r5,ror#27 @ E+=ROR(A,27)
|
||||
eor r9,r9,r11,ror#31
|
||||
str r9,[r14,#-4]!
|
||||
and r10,r6,r10,ror#2 @ F_xx_xx
|
||||
and r11,r7,r3 @ F_xx_xx
|
||||
add r4,r4,r9 @ E+=X[i]
|
||||
add r4,r4,r10 @ E+=F_40_59(B,C,D)
|
||||
add r4,r4,r11,ror#2
|
||||
ldr r9,[r14,#15*4]
|
||||
ldr r10,[r14,#13*4]
|
||||
ldr r11,[r14,#7*4]
|
||||
add r3,r8,r3,ror#2 @ E+=K_xx_xx
|
||||
ldr r12,[r14,#2*4]
|
||||
eor r9,r9,r10
|
||||
eor r11,r11,r12 @ 1 cycle stall
|
||||
eor r10,r6,r7 @ F_xx_xx
|
||||
mov r9,r9,ror#31
|
||||
add r3,r3,r4,ror#27 @ E+=ROR(A,27)
|
||||
eor r9,r9,r11,ror#31
|
||||
str r9,[r14,#-4]!
|
||||
and r10,r5,r10,ror#2 @ F_xx_xx
|
||||
and r11,r6,r7 @ F_xx_xx
|
||||
add r3,r3,r9 @ E+=X[i]
|
||||
add r3,r3,r10 @ E+=F_40_59(B,C,D)
|
||||
add r3,r3,r11,ror#2
|
||||
teq r14,sp
|
||||
bne .L_40_59 @ [+((12+5)*5+2)*4]
|
||||
|
||||
ldr r8,.LK_60_79
|
||||
sub sp,sp,#20*4
|
||||
cmp sp,#0 @ set carry to denote 60_79
|
||||
b .L_20_39_or_60_79 @ [+4], spare 300 bytes
|
||||
.L_done:
|
||||
add sp,sp,#80*4 @ "deallocate" stack frame
|
||||
ldmia r0,{r8,r9,r10,r11,r12}
|
||||
add r3,r8,r3
|
||||
add r4,r9,r4
|
||||
add r5,r10,r5,ror#2
|
||||
add r6,r11,r6,ror#2
|
||||
add r7,r12,r7,ror#2
|
||||
stmia r0,{r3,r4,r5,r6,r7}
|
||||
teq r1,r2
|
||||
bne .Lloop @ [+18], total 1307
|
||||
|
||||
#if __ARM_ARCH__>=5
|
||||
ldmia sp!,{r4-r12,pc}
|
||||
#else
|
||||
ldmia sp!,{r4-r12,lr}
|
||||
tst lr,#1
|
||||
moveq pc,lr @ be binary compatible with V4, yet
|
||||
.word 0xe12fff1e @ interoperable with Thumb ISA:-)
|
||||
#endif
|
||||
.align 2
|
||||
.LK_00_19: .word 0x5a827999
|
||||
.LK_20_39: .word 0x6ed9eba1
|
||||
.LK_40_59: .word 0x8f1bbcdc
|
||||
.LK_60_79: .word 0xca62c1d6
|
||||
.size sha1_block_data_order,.-sha1_block_data_order
|
||||
.asciz "SHA1 block transform for ARMv4, CRYPTOGAMS by <appro@openssl.org>"
|
||||
.align 2
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -651,7 +651,7 @@
|
|||
['exclude', 'store/.*$']
|
||||
],
|
||||
'conditions': [
|
||||
['target_arch!="ia32" and target_arch!="x64"', {
|
||||
['target_arch!="ia32" and target_arch!="x64" and target_arch!="arm"', {
|
||||
# Disable asm
|
||||
'defines': [
|
||||
'OPENSSL_NO_ASM'
|
||||
|
|
@ -676,27 +676,32 @@
|
|||
# Enable asm
|
||||
'defines': [
|
||||
'AES_ASM',
|
||||
'VPAES_ASM',
|
||||
'BF_ASM',
|
||||
'BNCO_ASM',
|
||||
'BN_ASM',
|
||||
'CPUID_ASM',
|
||||
'DES_ASM',
|
||||
'LIB_BN_ASM',
|
||||
'MD5_ASM',
|
||||
'OPENSSL_BN_ASM',
|
||||
'OPENSSL_BN_ASM_MONT',
|
||||
'OPENSSL_CPUID_OBJ',
|
||||
'RIP_ASM',
|
||||
'RMD160_ASM',
|
||||
'SHA1_ASM',
|
||||
'SHA256_ASM',
|
||||
'SHA512_ASM',
|
||||
'GHASH_ASM',
|
||||
'WHIRLPOOL_ASM',
|
||||
'WP_ASM'
|
||||
],
|
||||
'conditions': [
|
||||
# Extended assembly on non-arm platforms
|
||||
['target_arch!="arm"', {
|
||||
'defines': [
|
||||
'VPAES_ASM',
|
||||
'BN_ASM',
|
||||
'BF_ASM',
|
||||
'BNCO_ASM',
|
||||
'DES_ASM',
|
||||
'LIB_BN_ASM',
|
||||
'MD5_ASM',
|
||||
'OPENSSL_BN_ASM',
|
||||
'RIP_ASM',
|
||||
'RMD160_ASM',
|
||||
'WHIRLPOOL_ASM',
|
||||
'WP_ASM',
|
||||
],
|
||||
}],
|
||||
['OS!="win" and OS!="mac" and target_arch=="ia32"', {
|
||||
'sources': [
|
||||
'asm/x86-elf-gas/aes/aes-586.s',
|
||||
|
|
@ -821,6 +826,33 @@
|
|||
'openssl/crypto/des/fcrypt_b.c'
|
||||
]
|
||||
}],
|
||||
['target_arch=="arm"', {
|
||||
'sources': [
|
||||
'asm/arm-elf-gas/aes/aes-armv4.s',
|
||||
'asm/arm-elf-gas/bn/armv4-mont.s',
|
||||
'asm/arm-elf-gas/bn/armv4-gf2m.s',
|
||||
'asm/arm-elf-gas/sha/sha1-armv4-large.s',
|
||||
'asm/arm-elf-gas/sha/sha512-armv4.s',
|
||||
'asm/arm-elf-gas/sha/sha256-armv4.s',
|
||||
'asm/arm-elf-gas/modes/ghash-armv4.s',
|
||||
# No asm available
|
||||
'openssl/crypto/aes/aes_cbc.c',
|
||||
'openssl/crypto/bf/bf_enc.c',
|
||||
'openssl/crypto/bn/bn_asm.c',
|
||||
'openssl/crypto/cast/c_enc.c',
|
||||
'openssl/crypto/camellia/camellia.c',
|
||||
'openssl/crypto/camellia/cmll_cbc.c',
|
||||
'openssl/crypto/camellia/cmll_misc.c',
|
||||
'openssl/crypto/des/des_enc.c',
|
||||
'openssl/crypto/des/fcrypt_b.c',
|
||||
'openssl/crypto/rc4/rc4_enc.c',
|
||||
'openssl/crypto/rc4/rc4_skey.c',
|
||||
'openssl/crypto/whrlpool/wp_block.c',
|
||||
# PCAP stuff
|
||||
'openssl/crypto/armcap.c',
|
||||
'openssl/crypto/armv4cpuid.S',
|
||||
]
|
||||
}],
|
||||
['OS=="win" and target_arch=="ia32"', {
|
||||
'sources': [
|
||||
'asm/x86-win32-masm/aes/aes-586.asm',
|
||||
|
|
@ -938,9 +970,6 @@
|
|||
'HAVE_DLFCN_H'
|
||||
],
|
||||
}],
|
||||
['target_arch=="arm"', {
|
||||
'sources': ['openssl/crypto/armcap.c'],
|
||||
}],
|
||||
],
|
||||
'include_dirs': [
|
||||
'.',
|
||||
|
|
|
|||
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