зеркало из https://github.com/github/ruby.git
Support extended registers
and move argument registers to a couple of them.
This commit is contained in:
Takashi Kokubun
Родитель
d7dba4c510
Коммит
2b8d1c93ea
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@ -3,16 +3,29 @@ module RubyVM::MJIT
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# https://www.intel.com/content/dam/develop/public/us/en/documents/325383-sdm-vol-2abcd.pdf
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# Mostly an x86_64 assembler, but this also has some stuff that is useful for any architecture.
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class Assembler
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# A thin Fiddle wrapper to write bytes to memory
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ByteWriter = CType::Immediate.parse('char')
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# Used for rel8 jumps
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class Label < Data.define(:id, :name); end
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# rel32 is inserted as [Rel32, Rel32Pad..] and converted on #resolve_rel32
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class Rel32 < Data.define(:addr); end
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Rel32Pad = Object.new
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ByteWriter = CType::Immediate.parse('char')
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# A set of ModR/M values encoded on #insn
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class ModRM < Data.define(:mod, :reg, :rm)
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def initialize(mod:, reg: nil, rm: nil) = super
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end
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Mod00 = 0b00 # Mod 00: [reg]
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Mod01 = 0b01 # Mod 01: [reg]+disp8
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Mod10 = 0b10 # Mod 10: [reg]+disp16
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Mod11 = 0b11 # Mod 11: reg
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### prefix ###
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# REX = 0100WR0B
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REX_B = 0b01000001
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REX_R = 0b01000100
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REX_W = 0b01001000
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def initialize
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@ -47,24 +60,24 @@ module RubyVM::MJIT
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def add(dst, src)
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case [dst, src]
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# ADD r/m64, imm8 (Mod 11)
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# ADD r/m64, imm8 (Mod 11: reg)
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in [Symbol => dst_reg, Integer => src_imm] if r64?(dst_reg) && imm8?(src_imm)
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# REX.W + 83 /0 ib
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# MI: Operand 1: ModRM:r/m (r, w), Operand 2: imm8/16/32
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insn(
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prefix: REX_W,
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opcode: 0x83,
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mod_rm: mod_rm(mod: 0b11, rm: reg_code(dst_reg)),
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mod_rm: ModRM[mod: Mod11, rm: dst_reg],
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imm: imm8(src_imm),
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)
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# ADD r/m64, imm8 (Mod 00)
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# ADD r/m64, imm8 (Mod 00: [reg])
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in [[Symbol => dst_reg], Integer => src_imm] if r64?(dst_reg) && imm8?(src_imm)
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# REX.W + 83 /0 ib
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# MI: Operand 1: ModRM:r/m (r, w), Operand 2: imm8/16/32
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insn(
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prefix: REX_W,
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opcode: 0x83,
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mod_rm: mod_rm(mod: 0b00, rm: reg_code(dst_reg)), # Mod 00: [reg]
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mod_rm: ModRM[mod: Mod00, rm: dst_reg],
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imm: imm8(src_imm),
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)
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else
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@ -98,42 +111,51 @@ module RubyVM::MJIT
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case dst
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in Symbol => dst_reg
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case src
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# MOV r64, r/m64 (Mod 00)
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# MOV r64, r/m64 (Mod 00: [reg])
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in [Symbol => src_reg] if r64?(dst_reg) && r64?(src_reg)
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# REX.W + 8B /r
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# RM: Operand 1: ModRM:reg (w), Operand 2: ModRM:r/m (r)
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insn(
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prefix: REX_W,
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opcode: 0x8b,
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mod_rm: mod_rm(mod: 0b00, reg: reg_code(dst_reg), rm: reg_code(src_reg)), # Mod 00: [reg]
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mod_rm: ModRM[mod: Mod00, reg: dst_reg, rm: src_reg],
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)
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# MOV r32 r/m32 (Mod 01)
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in [Symbol => src_reg, Integer => src_disp] if r32?(dst_reg) && imm8?(src_disp)
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# 8B /r
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# RM: Operand 1: ModRM:reg (w), Operand 2: ModRM:r/m (r)
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insn(
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opcode: 0x8b,
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mod_rm: mod_rm(mod: 0b01, reg: reg_code(dst_reg), rm: reg_code(src_reg)), # Mod 01: [reg]+disp8
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disp: src_disp,
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)
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# MOV r64, r/m64 (Mod 01)
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# MOV r64, r/m64 (Mod 01: [reg]+disp8)
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in [Symbol => src_reg, Integer => src_disp] if r64?(dst_reg) && r64?(src_reg) && imm8?(src_disp)
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# REX.W + 8B /r
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# RM: Operand 1: ModRM:reg (w), Operand 2: ModRM:r/m (r)
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insn(
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prefix: REX_W,
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opcode: 0x8b,
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mod_rm: mod_rm(mod: 0b01, reg: reg_code(dst_reg), rm: reg_code(src_reg)), # Mod 01: [reg]+disp8
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mod_rm: ModRM[mod: Mod01, reg: dst_reg, rm: src_reg],
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disp: src_disp,
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)
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# MOV r/m64, imm32 (Mod 11)
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# MOV r64, r/m64 (Mod 11: reg)
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in Symbol => src_reg if r64?(dst_reg) && r64?(src_reg)
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# REX.W + 8B /r
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# RM: Operand 1: ModRM:reg (w), Operand 2: ModRM:r/m (r)
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insn(
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prefix: REX_W,
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opcode: 0x8b,
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mod_rm: ModRM[mod: Mod11, reg: dst_reg, rm: src_reg],
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)
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# MOV r32 r/m32 (Mod 01: [reg]+disp8)
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in [Symbol => src_reg, Integer => src_disp] if r32?(dst_reg) && imm8?(src_disp)
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# 8B /r
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# RM: Operand 1: ModRM:reg (w), Operand 2: ModRM:r/m (r)
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insn(
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opcode: 0x8b,
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mod_rm: ModRM[mod: Mod01, reg: dst_reg, rm: src_reg],
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disp: src_disp,
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)
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# MOV r/m64, imm32 (Mod 11: reg)
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in Integer => src_imm if r64?(dst_reg) && imm32?(src_imm)
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# REX.W + C7 /0 id
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# MI: Operand 1: ModRM:r/m (w), Operand 2: imm8/16/32/64
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insn(
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prefix: REX_W,
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opcode: 0xc7,
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mod_rm: mod_rm(mod: 0b11, rm: reg_code(dst_reg)), # Mod 11: reg
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mod_rm: ModRM[mod: Mod11, rm: dst_reg],
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imm: imm32(src_imm),
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)
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# MOV r64, imm64
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@ -142,7 +164,8 @@ module RubyVM::MJIT
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# OI: Operand 1: opcode + rd (w), Operand 2: imm8/16/32/64
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insn(
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prefix: REX_W,
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opcode: 0xb8 + reg_code(dst_reg),
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opcode: 0xb8,
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rd: dst_reg,
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imm: imm64(src_imm),
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)
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else
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@ -150,24 +173,24 @@ module RubyVM::MJIT
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end
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in [Symbol => dst_reg]
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case src
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# MOV r/m64, imm32 (Mod 00)
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# MOV r/m64, imm32 (Mod 00: [reg])
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in Integer => src_imm if r64?(dst_reg) && imm32?(src_imm)
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# REX.W + C7 /0 id
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# MI: Operand 1: ModRM:r/m (w), Operand 2: imm8/16/32/64
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insn(
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prefix: REX_W,
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opcode: 0xc7,
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mod_rm: mod_rm(mod: 0b00, rm: reg_code(dst_reg)), # Mod 00: [reg]
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mod_rm: ModRM[mod: Mod00, rm: dst_reg],
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imm: imm32(src_imm),
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)
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# MOV r/m64, r64 (Mod 00)
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# MOV r/m64, r64 (Mod 00: [reg])
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in Symbol => src_reg if r64?(dst_reg) && r64?(src_reg)
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# REX.W + 89 /r
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# MR: Operand 1: ModRM:r/m (w), Operand 2: ModRM:reg (r)
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insn(
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prefix: REX_W,
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opcode: 0x89,
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mod_rm: mod_rm(mod: 0b00, reg: reg_code(src_reg), rm: reg_code(dst_reg)), # Mod 00: [reg]
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mod_rm: ModRM[mod: Mod00, reg: src_reg, rm: dst_reg],
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)
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else
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raise NotImplementedError, "mov: not-implemented operands: #{dst.inspect}, #{src.inspect}"
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@ -177,25 +200,25 @@ module RubyVM::MJIT
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return mov([dst_reg], src) if dst_disp == 0
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case src
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# MOV r/m64, imm32 (Mod 01)
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# MOV r/m64, imm32 (Mod 01: [reg]+disp8)
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in Integer => src_imm if r64?(dst_reg) && imm8?(dst_disp) && imm32?(src_imm)
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# REX.W + C7 /0 id
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# MI: Operand 1: ModRM:r/m (w), Operand 2: imm8/16/32/64
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insn(
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prefix: REX_W,
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opcode: 0xc7,
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mod_rm: mod_rm(mod: 0b01, rm: reg_code(dst_reg)), # Mod 01: [reg]+disp8
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mod_rm: ModRM[mod: Mod01, rm: dst_reg],
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disp: dst_disp,
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imm: imm32(src_imm),
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)
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# MOV r/m64, r64 (Mod 01)
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# MOV r/m64, r64 (Mod 01: [reg]+disp8)
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in Symbol => src_reg if r64?(dst_reg) && imm8?(dst_disp) && r64?(src_reg)
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# REX.W + 89 /r
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# MR: Operand 1: ModRM:r/m (w), Operand 2: ModRM:reg (r)
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insn(
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prefix: REX_W,
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opcode: 0x89,
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mod_rm: mod_rm(mod: 0b01, reg: reg_code(src_reg), rm: reg_code(dst_reg)), # Mod 01: [reg]+disp8
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mod_rm: ModRM[mod: Mod01, reg: src_reg, rm: dst_reg],
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disp: dst_disp,
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)
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else
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@ -212,7 +235,7 @@ module RubyVM::MJIT
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in Symbol => src_reg if r64?(src_reg)
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# 50+rd
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# O: Operand 1: opcode + rd (r)
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insn(opcode: 0x50 + reg_code(src_reg))
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insn(opcode: 0x50, rd: src_reg)
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else
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raise NotImplementedError, "push: not-implemented operands: #{src.inspect}"
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end
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@ -224,7 +247,7 @@ module RubyVM::MJIT
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in Symbol => dst_reg if r64?(dst_reg)
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# 58+ rd
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# O: Operand 1: opcode + rd (r)
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insn(opcode: 0x58 + reg_code(dst_reg))
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insn(opcode: 0x58, rd: dst_reg)
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else
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raise NotImplementedError, "pop: not-implemented operands: #{dst.inspect}"
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end
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@ -238,13 +261,13 @@ module RubyVM::MJIT
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def test(left, right)
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case [left, right]
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# TEST r/m32, r32 (Mod 11)
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# TEST r/m32, r32 (Mod 11: reg)
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in [Symbol => left_reg, Symbol => right_reg] if r32?(left_reg) && r32?(right_reg)
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# 85 /r
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# MR: Operand 1: ModRM:r/m (r), Operand 2: ModRM:reg (r)
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insn(
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opcode: 0x85,
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mod_rm: mod_rm(mod: 0b11, reg: reg_code(right_reg), rm: reg_code(left_reg)), # Mod 11: reg
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mod_rm: ModRM[mod: Mod11, reg: right_reg, rm: left_reg],
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)
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else
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raise NotImplementedError, "pop: not-implemented operands: #{dst.inspect}"
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@ -284,13 +307,29 @@ module RubyVM::MJIT
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private
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def insn(prefix: nil, opcode:, mod_rm: nil, disp: nil, imm: nil)
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if prefix
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def insn(prefix: 0, opcode:, rd: nil, mod_rm: nil, disp: nil, imm: nil)
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# Determine prefix
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if rd
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prefix |= REX_B if extended_reg?(rd)
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opcode += reg_code(rd)
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end
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if mod_rm
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prefix |= REX_R if mod_rm.reg && extended_reg?(mod_rm.reg)
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prefix |= REX_B if mod_rm.rm && extended_reg?(mod_rm.rm)
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end
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# Encode insn
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if prefix > 0
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@bytes.push(prefix)
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end
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@bytes.push(*Array(opcode))
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if mod_rm
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@bytes.push(mod_rm)
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mod_rm_byte = encode_mod_rm(
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mod: mod_rm.mod,
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reg: mod_rm.reg ? reg_code(mod_rm.reg) : 0,
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rm: mod_rm.rm ? reg_code(mod_rm.rm) : 0,
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)
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@bytes.push(mod_rm_byte)
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end
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if disp
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unless imm8?(disp) # TODO: support displacement in 2 or 4 bytes as well
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@ -304,15 +343,33 @@ module RubyVM::MJIT
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end
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def reg_code(reg)
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reg_code_extended(reg).first
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end
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def extended_reg?(reg)
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reg_code_extended(reg).last
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end
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def reg_code_extended(reg)
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case reg
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when :al, :ax, :eax, :rax then 0
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when :cl, :cx, :ecx, :rcx then 1
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when :dl, :dx, :edx, :rdx then 2
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when :bl, :bx, :ebx, :rbx then 3
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when :ah, :sp, :esp, :rsp then 4
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when :ch, :bp, :ebp, :rbp then 5
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when :dh, :si, :esi, :rsi then 6
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when :bh, :di, :edi, :rdi then 7
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# Not extended
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when :al, :ax, :eax, :rax then [0, false]
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when :cl, :cx, :ecx, :rcx then [1, false]
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when :dl, :dx, :edx, :rdx then [2, false]
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when :bl, :bx, :ebx, :rbx then [3, false]
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when :ah, :sp, :esp, :rsp then [4, false]
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when :ch, :bp, :ebp, :rbp then [5, false]
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when :dh, :si, :esi, :rsi then [6, false]
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when :bh, :di, :edi, :rdi then [7, false]
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# Extended
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when :r8b, :r8w, :r8d, :r8 then [0, true]
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when :r9b, :r9w, :r9d, :r9 then [1, true]
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when :r10b, :r10w, :r10d, :r10 then [2, true]
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when :r11b, :r11w, :r11d, :r11 then [3, true]
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when :r12b, :r12w, :r12d, :r12 then [4, true]
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when :r13b, :r13w, :r13d, :r13 then [5, true]
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when :r14b, :r14w, :r14d, :r14 then [6, true]
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when :r15b, :r15w, :r15d, :r15 then [7, true]
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else raise ArgumentError, "unexpected reg: #{reg.inspect}"
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end
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end
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@ -330,7 +387,7 @@ module RubyVM::MJIT
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#
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# /0: R/M is 0 (not used)
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# /r: R/M is a register
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def mod_rm(mod:, reg: 0, rm: 0)
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def encode_mod_rm(mod:, reg: 0, rm: 0)
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if mod > 0b11
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raise ArgumentError, "too large Mod: #{mod}"
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end
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@ -389,11 +446,19 @@ module RubyVM::MJIT
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end
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def r32?(reg)
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reg.start_with?('e')
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if extended_reg?(reg)
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reg.end_with?('d')
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else
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reg.start_with?('e')
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end
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end
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def r64?(reg)
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reg.start_with?('r')
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if extended_reg?(reg)
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reg.match?(/\Ar\d+\z/)
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else
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reg.start_with?('r')
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end
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end
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def rel32(addr)
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@ -16,9 +16,10 @@ module RubyVM::MJIT
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Qnil = Fiddle::Qnil
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Qundef = Fiddle::Qundef
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# Fixed registers
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EC = :rdi # TODO: change this
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CFP = :rsi # TODO: change this
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# Callee-saved registers
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# TODO: support using r12/r13 here
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EC = :r14
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CFP = :r15
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SP = :rbx
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class Compiler
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@ -64,9 +65,15 @@ module RubyVM::MJIT
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asm.comment("MJIT entry")
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# Save callee-saved registers used by JITed code
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asm.push(CFP)
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asm.push(EC)
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asm.push(SP)
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# Load sp to a register
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# Move arguments EC and CFP to dedicated registers
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asm.mov(EC, :rdi)
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asm.mov(CFP, :rsi)
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# Load sp to a dedicated register
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asm.mov(SP, [CFP, C.rb_control_frame_t.offsetof(:sp)]) # rbx = cfp->sp
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end
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@ -26,6 +26,8 @@ module RubyVM::MJIT
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# Restore callee-saved registers
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asm.pop(SP)
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asm.pop(EC)
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asm.pop(CFP)
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asm.mov(:rax, Qundef)
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asm.ret
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@ -1,7 +1,4 @@
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module RubyVM::MJIT
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# ec: rdi
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# cfp: rsi
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# sp: rbx
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# scratch regs: rax
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#
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# 4/101
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@ -123,6 +120,8 @@ module RubyVM::MJIT
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# Restore callee-saved registers
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asm.pop(SP)
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asm.pop(EC)
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asm.pop(CFP)
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asm.ret
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EndBlock
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Загрузка…
Ссылка в новой задаче