зеркало из https://github.com/github/ruby.git
Implement mov encoding properly
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Родитель
2700d35b7b
Коммит
396d575451
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@ -1,17 +1,17 @@
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module RubyVM::MJIT
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class InsnCompiler
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def on_putnil(_asm)
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def putnil(_asm)
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# TODO
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KeepCompiling
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end
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def on_leave(asm)
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def leave(asm)
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# pop the current frame (ec->cfp++)
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asm.add(:rsi, C.rb_control_frame_t.size)
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asm.mov([:rdi, C.rb_execution_context_t.offsetof(:cfp)], :rsi)
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# return a value
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asm.mov(:rax, 7)
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asm.mov(:rax, 1001)
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asm.ret
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EndBlock
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end
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@ -1,7 +1,13 @@
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# frozen_string_literal: true
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# https://www.intel.com/content/dam/develop/public/us/en/documents/325383-sdm-vol-2abcd.pdf
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module RubyVM::MJIT
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class X86Assembler
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ByteWriter = CType::Immediate.parse('char')
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### prefix ###
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# REX = 0100WR0B
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REX_W = 0b01001000
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def initialize
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@bytes = []
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end
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@ -23,21 +29,114 @@ module RubyVM::MJIT
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@bytes.push(0x48, 0x83, 0xc6, imm)
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end
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def mov(reg, val)
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case reg
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when :rax
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# REX.W [C7] RAX imm32
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@bytes.push(0x48, 0xc7, 0xc0, val, 0x00, 0x00, 0x00)
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def mov(dst, src)
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case [dst, src]
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# MOV r/m64, imm32
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in [Symbol => dst_reg, Integer => src_imm] if r_reg?(dst_reg)
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# REX.W + C7 /0
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insn(
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prefix: REX_W,
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opcode: 0xc7,
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mod_rm: mod_rm(mod: 0b11, reg: reg_code(dst_reg)),
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imm: imm32(src_imm),
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)
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# MOV r/m64, r64
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in [[Symbol => dst_reg, Integer => dst_offset], Symbol => src_reg] if r_reg?(dst_reg) && r_reg?(src_reg) && dst_offset <= 0xff
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# REX.W + 89 /r
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insn(
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prefix: REX_W,
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opcode: 0x89,
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mod_rm: mod_rm(mod: 0b01, reg: reg_code(src_reg), rm: reg_code(dst_reg)), # disp8
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disp: dst_offset,
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)
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else
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# REX.W [89] [rdi+val],rsi
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@bytes.push(0x48, 0x89, 0x77, reg.last)
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raise NotImplementedError, "mov got not-implemented input: #{reg.inspect}, #{val.inspect}"
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end
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end
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# RET
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def ret
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# Near return
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# [C3]
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@bytes.push(0xc3)
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# Near return: A return to a procedure within the current code segment
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insn(opcode: 0xc3)
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end
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private
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def insn(prefix: nil, opcode:, mod_rm: nil, disp: nil, imm: nil)
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if prefix
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@bytes.push(prefix)
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end
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@bytes.push(opcode)
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if mod_rm
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@bytes.push(mod_rm)
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end
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if disp
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if disp < 0 || disp > 0xff # TODO: support displacement in 2 or 4 bytes as well
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raise NotImplementedError, "not-implemented disp: #{disp}"
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end
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@bytes.push(disp)
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end
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if imm
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@bytes.push(*imm)
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end
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end
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def reg_code(reg)
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case reg
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when :al, :ax, :eax, :rax then 0
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when :cl, :cx, :ecx, :rcx then 1
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when :dl, :dx, :edx, :rdx then 2
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when :bl, :bx, :ebx, :rbx then 3
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when :ah, :sp, :esp, :rsp then 4
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when :ch, :bp, :ebp, :rbp then 5
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when :dh, :si, :esi, :rsi then 6
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when :bh, :di, :edi, :rdi then 7
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else raise ArgumentError, "unexpected reg: #{reg.inspect}"
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end
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end
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# Table 2-2. 32-Bit Addressing Forms with the ModR/M Byte
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#
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# 7 6 5 4 3 2 1 0
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# +--+--+--+--+--+--+--+--+
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# | Mod | Reg/ | R/M |
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# | | Opcode | |
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# +--+--+--+--+--+--+--+--+
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#
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# The r/m field can specify a register as an operand or it can be combined
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# with the mod field to encode an addressing mode.
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#
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# /0: R/M is 0 (not used)
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# /r: R/M is a register
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def mod_rm(mod:, reg:, rm: 0)
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if mod > 0b11
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raise ArgumentError, "too large Mod: #{mod}"
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end
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if reg > 0b111
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raise ArgumentError, "too large Reg/Opcode: #{reg}"
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end
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if rm > 0b111
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raise ArgumentError, "too large R/M: #{rm}"
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end
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(mod << 6) + (reg << 3) + rm
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end
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# id: 4 bytes
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def imm32(imm)
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bytes = []
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bits = imm
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4.times do
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bytes << (bits & 0xff)
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bits >>= 8
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end
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if bits != 0
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raise ArgumentError, "unexpected imm32: #{imm}"
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end
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bytes
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end
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def r_reg?(reg)
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reg.start_with?('r')
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end
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end
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end
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@ -26,8 +26,7 @@ module RubyVM::MJIT
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return if iseq.body.location.label == '<main>'
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iseq.body.jit_func = compile_block(iseq)
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rescue Exception => e
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# TODO: check --mjit-verbose
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$stderr.puts e.full_message
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$stderr.puts e.full_message # TODO: check verbose
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end
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def write_addr
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@ -36,6 +35,20 @@ module RubyVM::MJIT
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private
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def compile(asm)
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start_addr = write_addr
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C.mjit_mark_writable
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@write_pos += asm.compile(start_addr)
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C.mjit_mark_executable
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end_addr = write_addr
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if C.mjit_opts.dump_disasm && start_addr < end_addr
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dump_disasm(start_addr, end_addr)
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end
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start_addr
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end
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# ec -> RDI, cfp -> RSI
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def compile_block(iseq)
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addr = write_addr
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@ -56,26 +69,12 @@ module RubyVM::MJIT
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def compile_insn(asm, insn)
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case insn.name
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when :putnil then @insn_compiler.on_putnil(asm)
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when :leave then @insn_compiler.on_leave(asm)
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when :putnil then @insn_compiler.putnil(asm)
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when :leave then @insn_compiler.leave(asm)
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else raise NotImplementedError, "insn '#{insn.name}' is not supported yet"
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end
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end
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def compile(asm)
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start_addr = write_addr
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C.mjit_mark_writable
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@write_pos += asm.compile(start_addr)
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C.mjit_mark_executable
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end_addr = write_addr
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if C.mjit_opts.dump_disasm && start_addr < end_addr
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dump_disasm(start_addr, end_addr)
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end
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start_addr
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end
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def decode_insn(encoded)
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INSNS.fetch(C.rb_vm_insn_decode(encoded))
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end
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