зеркало из https://github.com/github/ruby.git
Load mem displacement when necessary on AArch64 (https://github.com/Shopify/ruby/pull/382)
* LDR instruction for AArch64 * Split loads in arm64_split when memory address displacements do not fit
This commit is contained in:
Kevin Newton
Takashi Kokubun
Родитель
85d6d76e41
Коммит
b8846dd2f8
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@ -39,7 +39,7 @@ pub struct LoadLiteral {
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impl LoadLiteral {
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/// LDR (load literal)
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/// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDR--literal---Load-Register--literal--?lang=en
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pub fn ldr(rt: u8, imm19: i32, num_bits: u8) -> Self {
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pub fn ldr_literal(rt: u8, imm19: i32, num_bits: u8) -> Self {
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Self { rt, imm19, opc: num_bits.into() }
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}
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}
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@ -75,14 +75,14 @@ mod tests {
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#[test]
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fn test_ldr_positive() {
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let inst = LoadLiteral::ldr(0, 5, 64);
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let inst = LoadLiteral::ldr_literal(0, 5, 64);
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let result: u32 = inst.into();
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assert_eq!(0x580000a0, result);
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}
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#[test]
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fn test_ldr_negative() {
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let inst = LoadLiteral::ldr(0, -5, 64);
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let inst = LoadLiteral::ldr_literal(0, -5, 64);
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let result: u32 = inst.into();
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assert_eq!(0x58ffff60, result);
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}
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@ -0,0 +1,108 @@
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/// Whether or not to shift the register.
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enum S {
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Shift = 1,
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NoShift = 0
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}
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/// The option for this instruction.
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enum Option {
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UXTW = 0b010,
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LSL = 0b011,
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SXTW = 0b110,
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SXTX = 0b111
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}
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/// The size of the operands of this instruction.
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enum Size {
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Size32 = 0b10,
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Size64 = 0b11
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}
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/// A convenience function so that we can convert the number of bits of an
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/// register operand directly into a Size enum variant.
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impl From<u8> for Size {
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fn from(num_bits: u8) -> Self {
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match num_bits {
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64 => Size::Size64,
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32 => Size::Size32,
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_ => panic!("Invalid number of bits: {}", num_bits)
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}
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}
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}
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/// The struct that represents an A64 load instruction that can be encoded.
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///
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/// LDR
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/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
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/// | 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 09 08 | 07 06 05 04 | 03 02 01 00 |
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/// | 1 1 1 0 0 0 0 1 1 1 0 |
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/// | size. rm.............. option.. S rn.............. rt.............. |
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/// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
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///
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pub struct LoadRegister {
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/// The number of the register to load the value into.
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rt: u8,
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/// The base register with which to form the address.
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rn: u8,
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/// Whether or not to shift the value of the register.
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s: S,
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/// The option associated with this instruction that controls the shift.
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option: Option,
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/// The number of the offset register.
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rm: u8,
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/// The size of the operands.
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size: Size
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}
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impl LoadRegister {
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/// LDR
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/// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/LDR--register---Load-Register--register--?lang=en
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pub fn ldr(rt: u8, rn: u8, rm: u8, num_bits: u8) -> Self {
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Self { rt, rn, s: S::NoShift, option: Option::LSL, rm, size: num_bits.into() }
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}
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}
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/// https://developer.arm.com/documentation/ddi0602/2022-03/Index-by-Encoding/Loads-and-Stores?lang=en
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const FAMILY: u32 = 0b0100;
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impl From<LoadRegister> for u32 {
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/// Convert an instruction into a 32-bit value.
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fn from(inst: LoadRegister) -> Self {
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0
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| ((inst.size as u32) << 30)
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| (0b11 << 28)
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| (FAMILY << 25)
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| (0b11 << 21)
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| ((inst.rm as u32) << 16)
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| ((inst.option as u32) << 13)
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| ((inst.s as u32) << 12)
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| (0b10 << 10)
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| ((inst.rn as u32) << 5)
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| (inst.rt as u32)
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}
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}
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impl From<LoadRegister> for [u8; 4] {
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/// Convert an instruction into a 4 byte array.
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fn from(inst: LoadRegister) -> [u8; 4] {
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let result: u32 = inst.into();
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result.to_le_bytes()
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}
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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#[test]
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fn test_ldr() {
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let inst = LoadRegister::ldr(0, 1, 2, 64);
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let result: u32 = inst.into();
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assert_eq!(0xf8626820, result);
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}
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}
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@ -10,6 +10,7 @@ mod conditional;
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mod data_imm;
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mod data_reg;
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mod load_literal;
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mod load_register;
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mod load_store;
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mod logical_imm;
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mod logical_reg;
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@ -30,6 +31,7 @@ pub use conditional::Conditional;
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pub use data_imm::DataImm;
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pub use data_reg::DataReg;
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pub use load_literal::LoadLiteral;
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pub use load_register::LoadRegister;
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pub use load_store::LoadStore;
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pub use logical_imm::LogicalImm;
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pub use logical_reg::LogicalReg;
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@ -374,11 +374,26 @@ pub fn ldp_post(cb: &mut CodeBlock, rt1: A64Opnd, rt2: A64Opnd, rn: A64Opnd) {
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cb.write_bytes(&bytes);
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}
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/// LDR - load a memory address into a register with a register offset
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pub fn ldr(cb: &mut CodeBlock, rt: A64Opnd, rn: A64Opnd, rm: A64Opnd) {
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let bytes: [u8; 4] = match (rt, rn, rm) {
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(A64Opnd::Reg(rt), A64Opnd::Reg(rn), A64Opnd::Reg(rm)) => {
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assert!(rt.num_bits == rn.num_bits, "Expected registers to be the same size");
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assert!(rn.num_bits == rm.num_bits, "Expected registers to be the same size");
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LoadRegister::ldr(rt.reg_no, rn.reg_no, rm.reg_no, rt.num_bits).into()
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},
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_ => panic!("Invalid operand combination to ldr instruction.")
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};
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cb.write_bytes(&bytes);
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}
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/// LDR - load a PC-relative memory address into a register
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pub fn ldr(cb: &mut CodeBlock, rt: A64Opnd, rn: i32) {
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pub fn ldr_literal(cb: &mut CodeBlock, rt: A64Opnd, rn: i32) {
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let bytes: [u8; 4] = match rt {
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A64Opnd::Reg(rt) => {
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LoadLiteral::ldr(rt.reg_no, rn, rt.num_bits).into()
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LoadLiteral::ldr_literal(rt.reg_no, rn, rt.num_bits).into()
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},
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_ => panic!("Invalid operand combination to ldr instruction."),
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};
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@ -386,12 +401,18 @@ pub fn ldr(cb: &mut CodeBlock, rt: A64Opnd, rn: i32) {
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cb.write_bytes(&bytes);
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}
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/// Whether or not a memory address displacement fits into the maximum number of
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/// bits such that it can be used without loading it into a register first.
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pub fn mem_disp_fits_bits(disp: i32) -> bool {
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imm_fits_bits(disp.into(), 9)
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}
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/// LDR (post-index) - load a register from memory, update the base pointer after loading it
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pub fn ldr_post(cb: &mut CodeBlock, rt: A64Opnd, rn: A64Opnd) {
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let bytes: [u8; 4] = match (rt, rn) {
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(A64Opnd::Reg(rt), A64Opnd::Mem(rn)) => {
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assert!(rt.num_bits == rn.num_bits, "All operands must be of the same size.");
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assert!(imm_fits_bits(rn.disp.into(), 9), "The displacement must be 9 bits or less.");
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assert!(mem_disp_fits_bits(rn.disp), "The displacement must be 9 bits or less.");
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LoadStore::ldr_post(rt.reg_no, rn.base_reg_no, rn.disp as i16, rt.num_bits).into()
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},
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@ -406,7 +427,7 @@ pub fn ldr_pre(cb: &mut CodeBlock, rt: A64Opnd, rn: A64Opnd) {
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let bytes: [u8; 4] = match (rt, rn) {
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(A64Opnd::Reg(rt), A64Opnd::Mem(rn)) => {
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assert!(rt.num_bits == rn.num_bits, "All operands must be of the same size.");
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assert!(imm_fits_bits(rn.disp.into(), 9), "The displacement must be 9 bits or less.");
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assert!(mem_disp_fits_bits(rn.disp), "The displacement must be 9 bits or less.");
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LoadStore::ldr_pre(rt.reg_no, rn.base_reg_no, rn.disp as i16, rt.num_bits).into()
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},
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@ -426,7 +447,7 @@ pub fn ldur(cb: &mut CodeBlock, rt: A64Opnd, rn: A64Opnd) {
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},
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(A64Opnd::Reg(rt), A64Opnd::Mem(rn)) => {
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assert!(rt.num_bits == rn.num_bits, "Expected registers to be the same size");
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assert!(imm_fits_bits(rn.disp.into(), 9), "Expected displacement to be 9 bits or less");
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assert!(mem_disp_fits_bits(rn.disp), "Expected displacement to be 9 bits or less");
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LoadStore::ldur(rt.reg_no, rn.base_reg_no, rn.disp as i16, rt.num_bits).into()
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},
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@ -441,7 +462,7 @@ pub fn ldursw(cb: &mut CodeBlock, rt: A64Opnd, rn: A64Opnd) {
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let bytes: [u8; 4] = match (rt, rn) {
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(A64Opnd::Reg(rt), A64Opnd::Mem(rn)) => {
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assert!(rt.num_bits == rn.num_bits, "Expected registers to be the same size");
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assert!(imm_fits_bits(rn.disp.into(), 9), "Expected displacement to be 9 bits or less");
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assert!(mem_disp_fits_bits(rn.disp), "Expected displacement to be 9 bits or less");
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LoadStore::ldursw(rt.reg_no, rn.base_reg_no, rn.disp as i16).into()
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},
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@ -670,7 +691,7 @@ pub fn str_post(cb: &mut CodeBlock, rt: A64Opnd, rn: A64Opnd) {
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let bytes: [u8; 4] = match (rt, rn) {
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(A64Opnd::Reg(rt), A64Opnd::Mem(rn)) => {
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assert!(rt.num_bits == rn.num_bits, "All operands must be of the same size.");
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assert!(imm_fits_bits(rn.disp.into(), 9), "The displacement must be 9 bits or less.");
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assert!(mem_disp_fits_bits(rn.disp), "The displacement must be 9 bits or less.");
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LoadStore::str_post(rt.reg_no, rn.base_reg_no, rn.disp as i16, rt.num_bits).into()
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},
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@ -685,7 +706,7 @@ pub fn str_pre(cb: &mut CodeBlock, rt: A64Opnd, rn: A64Opnd) {
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let bytes: [u8; 4] = match (rt, rn) {
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(A64Opnd::Reg(rt), A64Opnd::Mem(rn)) => {
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assert!(rt.num_bits == rn.num_bits, "All operands must be of the same size.");
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assert!(imm_fits_bits(rn.disp.into(), 9), "The displacement must be 9 bits or less.");
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assert!(mem_disp_fits_bits(rn.disp), "The displacement must be 9 bits or less.");
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LoadStore::str_pre(rt.reg_no, rn.base_reg_no, rn.disp as i16, rt.num_bits).into()
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},
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@ -700,7 +721,7 @@ pub fn stur(cb: &mut CodeBlock, rt: A64Opnd, rn: A64Opnd) {
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let bytes: [u8; 4] = match (rt, rn) {
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(A64Opnd::Reg(rt), A64Opnd::Mem(rn)) => {
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assert!(rt.num_bits == rn.num_bits, "Expected registers to be the same size");
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assert!(imm_fits_bits(rn.disp.into(), 9), "Expected displacement to be 9 bits or less");
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assert!(mem_disp_fits_bits(rn.disp), "Expected displacement to be 9 bits or less");
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LoadStore::stur(rt.reg_no, rn.base_reg_no, rn.disp as i16, rt.num_bits).into()
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},
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@ -1024,7 +1045,12 @@ mod tests {
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#[test]
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fn test_ldr() {
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check_bytes("40010058", |cb| ldr(cb, X0, 10));
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check_bytes("6a696cf8", |cb| ldr(cb, X10, X11, X12));
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}
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#[test]
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fn test_ldr_literal() {
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check_bytes("40010058", |cb| ldr_literal(cb, X0, 10));
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}
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#[test]
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@ -84,13 +84,66 @@ impl Assembler
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/// have no memory operands.
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fn arm64_split(mut self) -> Assembler
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{
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/// When we're attempting to load a memory address into a register, the
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/// displacement must fit into the maximum number of bits for an Op::Add
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/// immediate. If it doesn't, we have to load the displacement into a
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/// register first.
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fn split_lea_operand(asm: &mut Assembler, opnd: Opnd) -> Opnd {
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match opnd {
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Opnd::Mem(Mem { base, disp, num_bits }) => {
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if disp >= 0 && ShiftedImmediate::try_from(disp as u64).is_ok() {
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asm.lea(opnd)
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} else {
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let disp = asm.load(Opnd::Imm(disp.into()));
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let reg = match base {
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MemBase::Reg(reg_no) => Opnd::Reg(Reg { reg_no, num_bits }),
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MemBase::InsnOut(idx) => Opnd::InsnOut { idx, num_bits }
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};
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asm.add(reg, disp)
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}
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},
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_ => unreachable!("Op::Lea only accepts Opnd::Mem operands.")
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}
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}
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/// When you're storing a register into a memory location or loading a
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/// memory location into a register, the displacement from the base
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/// register of the memory location must fit into 9 bits. If it doesn't,
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/// then we need to load that memory address into a register first.
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fn split_memory_address(asm: &mut Assembler, opnd: Opnd) -> Opnd {
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match opnd {
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Opnd::Mem(mem) => {
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if mem_disp_fits_bits(mem.disp) {
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opnd
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} else {
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let base = split_lea_operand(asm, opnd);
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Opnd::mem(64, base, 0)
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}
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},
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_ => unreachable!("Can only split memory addresses.")
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}
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}
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/// Any memory operands you're sending into an Op::Load instruction need
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/// to be split in case their displacement doesn't fit into 9 bits.
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fn split_load_operand(asm: &mut Assembler, opnd: Opnd) -> Opnd {
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match opnd {
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Opnd::Mem(_) => {
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let split_opnd = split_memory_address(asm, opnd);
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asm.load(split_opnd)
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},
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_ => asm.load(opnd)
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}
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}
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/// Operands that take the place of bitmask immediates must follow a
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/// certain encoding. In this function we ensure that those operands
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/// do follow that encoding, and if they don't then we load them first.
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fn split_bitmask_immediate(asm: &mut Assembler, opnd: Opnd) -> Opnd {
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match opnd {
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Opnd::Reg(_) | Opnd::InsnOut { .. } => opnd,
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Opnd::Mem(_) => asm.load(opnd),
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Opnd::Mem(_) => split_load_operand(asm, opnd),
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Opnd::Imm(imm) => {
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if imm <= 0 {
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asm.load(opnd)
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@ -116,7 +169,8 @@ impl Assembler
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fn split_shifted_immediate(asm: &mut Assembler, opnd: Opnd) -> Opnd {
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match opnd {
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Opnd::Reg(_) | Opnd::InsnOut { .. } => opnd,
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Opnd::Mem(_) | Opnd::Imm(_) => asm.load(opnd),
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Opnd::Mem(_) => split_load_operand(asm, opnd),
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Opnd::Imm(_) => asm.load(opnd),
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Opnd::UImm(uimm) => {
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if ShiftedImmediate::try_from(uimm).is_ok() {
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opnd
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@ -128,24 +182,6 @@ impl Assembler
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}
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}
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/// When you're storing a register into a memory location, the
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/// displacement from the base register of the memory location must fit
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/// into 9 bits. If it doesn't, then we need to load that memory address
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/// into a register first.
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fn split_store(asm: &mut Assembler, opnd: Opnd) -> Opnd {
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match opnd {
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Opnd::Mem(mem) => {
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if imm_fits_bits(mem.disp.into(), 9) {
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opnd
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} else {
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let base = asm.lea(opnd);
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Opnd::mem(64, base, 0)
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}
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},
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_ => unreachable!("Can only store memory addresses.")
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}
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}
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self.forward_pass(|asm, index, op, opnds, target, text, pos_marker, original_opnds| {
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// Load all Value operands into registers that aren't already a part
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// of Load instructions.
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@ -172,7 +208,7 @@ impl Assembler
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asm.add(reg_opnd, opnd1);
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},
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_ => {
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let opnd0 = asm.load(opnds[0]);
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let opnd0 = split_load_operand(asm, opnds[0]);
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let opnd1 = split_shifted_immediate(asm, opnds[1]);
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asm.add(opnd0, opnd1);
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}
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@ -189,7 +225,7 @@ impl Assembler
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asm.push_insn(op, vec![reg_opnd, opnd1], target, text, pos_marker);
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},
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_ => {
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let opnd0 = asm.load(opnds[0]);
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let opnd0 = split_load_operand(asm, opnds[0]);
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let opnd1 = split_bitmask_immediate(asm, opnds[1]);
|
||||
asm.push_insn(op, vec![opnd0, opnd1], target, text, pos_marker);
|
||||
}
|
||||
|
|
@ -204,7 +240,7 @@ impl Assembler
|
|||
// Note: the iteration order is reversed to avoid corrupting x0,
|
||||
// which is both the return value and first argument register
|
||||
for (idx, opnd) in opnds.into_iter().enumerate().rev() {
|
||||
let value = asm.load(opnd);
|
||||
let value = split_load_operand(asm, opnd);
|
||||
asm.mov(C_ARG_OPNDS[idx], value);
|
||||
}
|
||||
|
||||
|
|
@ -215,16 +251,15 @@ impl Assembler
|
|||
Op::Cmp => {
|
||||
let opnd0 = match opnds[0] {
|
||||
Opnd::Reg(_) | Opnd::InsnOut { .. } => opnds[0],
|
||||
_ => asm.load(opnds[0])
|
||||
_ => split_load_operand(asm, opnds[0])
|
||||
};
|
||||
|
||||
let opnd1 = split_shifted_immediate(asm, opnds[1]);
|
||||
|
||||
asm.push_insn(op, vec![opnd0, opnd1], target, text, pos_marker);
|
||||
asm.cmp(opnd0, opnd1);
|
||||
},
|
||||
Op::CRet => {
|
||||
if opnds[0] != Opnd::Reg(C_RET_REG) {
|
||||
let value = asm.load(opnds[0]);
|
||||
let value = split_load_operand(asm, opnds[0]);
|
||||
asm.mov(C_RET_OPND, value);
|
||||
}
|
||||
asm.cret(C_RET_OPND);
|
||||
|
|
@ -234,7 +269,7 @@ impl Assembler
|
|||
let new_opnds = opnds.into_iter().map(|opnd| {
|
||||
match opnd {
|
||||
Opnd::Reg(_) | Opnd::InsnOut { .. } => opnd,
|
||||
_ => asm.load(opnd)
|
||||
_ => split_load_operand(asm, opnd)
|
||||
}
|
||||
}).collect();
|
||||
|
||||
|
|
@ -243,7 +278,7 @@ impl Assembler
|
|||
Op::IncrCounter => {
|
||||
// We'll use LDADD later which only works with registers
|
||||
// ... Load pointer into register
|
||||
let counter_addr = asm.lea(opnds[0]);
|
||||
let counter_addr = split_lea_operand(asm, opnds[0]);
|
||||
|
||||
// Load immediates into a register
|
||||
let addend = match opnds[1] {
|
||||
|
|
@ -255,12 +290,15 @@ impl Assembler
|
|||
},
|
||||
Op::JmpOpnd => {
|
||||
if let Opnd::Mem(_) = opnds[0] {
|
||||
let opnd0 = asm.load(opnds[0]);
|
||||
let opnd0 = split_load_operand(asm, opnds[0]);
|
||||
asm.jmp_opnd(opnd0);
|
||||
} else {
|
||||
asm.jmp_opnd(opnds[0]);
|
||||
}
|
||||
},
|
||||
Op::Load => {
|
||||
split_load_operand(asm, opnds[0]);
|
||||
},
|
||||
Op::LoadSExt => {
|
||||
match opnds[0] {
|
||||
// We only want to sign extend if the operand is a
|
||||
|
|
@ -295,7 +333,7 @@ impl Assembler
|
|||
// we'll use the normal mov instruction.
|
||||
match opnds[0] {
|
||||
Opnd::Mem(_) => {
|
||||
let opnd0 = split_store(asm, opnds[0]);
|
||||
let opnd0 = split_memory_address(asm, opnds[0]);
|
||||
asm.store(opnd0, value);
|
||||
},
|
||||
Opnd::Reg(_) => {
|
||||
|
|
@ -308,7 +346,7 @@ impl Assembler
|
|||
// The value that is being negated must be in a register, so
|
||||
// if we get anything else we need to load it first.
|
||||
let opnd0 = match opnds[0] {
|
||||
Opnd::Mem(_) => asm.load(opnds[0]),
|
||||
Opnd::Mem(_) => split_load_operand(asm, opnds[0]),
|
||||
_ => opnds[0]
|
||||
};
|
||||
|
||||
|
|
@ -318,13 +356,13 @@ impl Assembler
|
|||
// The displacement for the STUR instruction can't be more
|
||||
// than 9 bits long. If it's longer, we need to load the
|
||||
// memory address into a register first.
|
||||
let opnd0 = split_store(asm, opnds[0]);
|
||||
let opnd0 = split_memory_address(asm, opnds[0]);
|
||||
|
||||
// The value being stored must be in a register, so if it's
|
||||
// not already one we'll load it first.
|
||||
let opnd1 = match opnds[1] {
|
||||
Opnd::Reg(_) | Opnd::InsnOut { .. } => opnds[1],
|
||||
_ => asm.load(opnds[1])
|
||||
_ => split_load_operand(asm, opnds[1])
|
||||
};
|
||||
|
||||
asm.store(opnd0, opnd1);
|
||||
|
|
@ -332,19 +370,18 @@ impl Assembler
|
|||
Op::Sub => {
|
||||
let opnd0 = match opnds[0] {
|
||||
Opnd::Reg(_) | Opnd::InsnOut { .. } => opnds[0],
|
||||
_ => asm.load(opnds[0])
|
||||
_ => split_load_operand(asm, opnds[0])
|
||||
};
|
||||
|
||||
let opnd1 = split_shifted_immediate(asm, opnds[1]);
|
||||
|
||||
asm.push_insn(op, vec![opnd0, opnd1], target, text, pos_marker);
|
||||
asm.sub(opnd0, opnd1);
|
||||
},
|
||||
Op::Test => {
|
||||
// The value being tested must be in a register, so if it's
|
||||
// not already one we'll load it first.
|
||||
let opnd0 = match opnds[0] {
|
||||
Opnd::Reg(_) | Opnd::InsnOut { .. } => opnds[0],
|
||||
_ => asm.load(opnds[0])
|
||||
_ => split_load_operand(asm, opnds[0])
|
||||
};
|
||||
|
||||
// The second value must be either a register or an
|
||||
|
|
@ -352,7 +389,6 @@ impl Assembler
|
|||
// immediate. If it's not one of those, we'll need to load
|
||||
// it first.
|
||||
let opnd1 = split_bitmask_immediate(asm, opnds[1]);
|
||||
|
||||
asm.test(opnd0, opnd1);
|
||||
},
|
||||
_ => {
|
||||
|
|
@ -611,7 +647,7 @@ impl Assembler
|
|||
// references to GC'd Value operands. If the value
|
||||
// being loaded is a heap object, we'll report that
|
||||
// back out to the gc_offsets list.
|
||||
ldr(cb, insn.out.into(), 2);
|
||||
ldr_literal(cb, insn.out.into(), 2);
|
||||
b(cb, A64Opnd::new_imm(1 + (SIZEOF_VALUE as i64) / 4));
|
||||
cb.write_bytes(&value.as_u64().to_le_bytes());
|
||||
|
||||
|
|
@ -901,6 +937,42 @@ mod tests {
|
|||
asm.compile_with_num_regs(&mut cb, 1);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_emit_load_mem_disp_fits_into_load() {
|
||||
let (mut asm, mut cb) = setup_asm();
|
||||
|
||||
let opnd = asm.load(Opnd::mem(64, SP, 0));
|
||||
asm.store(Opnd::mem(64, SP, 0), opnd);
|
||||
asm.compile_with_num_regs(&mut cb, 1);
|
||||
|
||||
// Assert that two instructions were written: LDUR and STUR.
|
||||
assert_eq!(8, cb.get_write_pos());
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_emit_load_mem_disp_fits_into_add() {
|
||||
let (mut asm, mut cb) = setup_asm();
|
||||
|
||||
let opnd = asm.load(Opnd::mem(64, SP, 1 << 10));
|
||||
asm.store(Opnd::mem(64, SP, 0), opnd);
|
||||
asm.compile_with_num_regs(&mut cb, 1);
|
||||
|
||||
// Assert that three instructions were written: ADD, LDUR, and STUR.
|
||||
assert_eq!(12, cb.get_write_pos());
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_emit_load_mem_disp_does_not_fit_into_add() {
|
||||
let (mut asm, mut cb) = setup_asm();
|
||||
|
||||
let opnd = asm.load(Opnd::mem(64, SP, 1 << 12 | 1));
|
||||
asm.store(Opnd::mem(64, SP, 0), opnd);
|
||||
asm.compile_with_num_regs(&mut cb, 1);
|
||||
|
||||
// Assert that three instructions were written: MOVZ, ADD, LDUR, and STUR.
|
||||
assert_eq!(16, cb.get_write_pos());
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn test_emit_or() {
|
||||
let (mut asm, mut cb) = setup_asm();
|
||||
|
|
|
|||
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