From b988ae3a06506a4361ab5cbd51da5992268fb713 Mon Sep 17 00:00:00 2001
From: Dmitry Ukolov <udmitry@mail.ru>
Date: Fri, 14 Jun 2024 02:55:01 +0400
Subject: [PATCH] RJIT: Fixed and/or reg+disp32 operations (#10856)

Fixed RJIT `and reg+disp32` and `or reg+disp32` operation.
---
 bootstraptest/test_rjit.rb    | 22 ++++++++++++++++++++++
 lib/ruby_vm/rjit/assembler.rb | 20 ++++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/bootstraptest/test_rjit.rb b/bootstraptest/test_rjit.rb
index e123f35160..4c8cd26dff 100644
--- a/bootstraptest/test_rjit.rb
+++ b/bootstraptest/test_rjit.rb
@@ -29,6 +29,28 @@ assert_equal 'bar', %q{
   bar(Struct.new(:bar).new(:bar))
 }
 
+# AND with offset  DISP32
+assert_equal '2', %q{
+  def foo
+    a = 6;
+    b = {a: 1, b: 1, c: 1, d: 1, e: 1,  f: 1, g: 1, h: a&3}
+    b[:h]
+  end
+
+  foo
+}
+
+# OR with offset DISP32
+assert_equal '6', %q{
+  def foo
+    a = 4;
+    b = {a: 1, b: 1, c: 1, d: 1, e: 1,  f: 1, g: 1, h: a|2}
+    b[:h]
+  end
+
+  foo
+}
+
 # kwargs default w/ checkkeyword + locals (which shouldn't overwrite unspecified_bits)
 assert_equal '1', %q{
   def foo(bar: 1.to_s)
diff --git a/lib/ruby_vm/rjit/assembler.rb b/lib/ruby_vm/rjit/assembler.rb
index 645072d11b..fc3a98e122 100644
--- a/lib/ruby_vm/rjit/assembler.rb
+++ b/lib/ruby_vm/rjit/assembler.rb
@@ -152,6 +152,16 @@ module RubyVM::RJIT
           mod_rm: ModRM[mod: Mod01, reg: dst_reg, rm: src_reg],
           disp: imm8(src_disp),
         )
+        # AND r64, r/m64 (Mod 10: [reg]+disp32)
+        in [R64 => dst_reg, QwordPtr[R64 => src_reg, IMM32 => src_disp]]
+          # REX.W + 23 /r
+          # RM: Operand 1: ModRM:reg (r, w), Operand 2: ModRM:r/m (r)
+          insn(
+            prefix: REX_W,
+            opcode: 0x23,
+            mod_rm: ModRM[mod: Mod10, reg: dst_reg, rm: src_reg],
+            disp: imm32(src_disp),
+            )
       end
     end
 
@@ -736,6 +746,16 @@ module RubyVM::RJIT
           mod_rm: ModRM[mod: Mod01, reg: dst_reg, rm: src_reg],
           disp: imm8(src_disp),
         )
+        # OR r64, r/m64 (Mod 10: [reg]+disp32)
+        in [R64 => dst_reg, QwordPtr[R64 => src_reg, IMM32 => src_disp]]
+          # REX.W + 0B /r
+          # RM: Operand 1: ModRM:reg (r, w), Operand 2: ModRM:r/m (r)
+          insn(
+            prefix: REX_W,
+            opcode: 0x0b,
+            mod_rm: ModRM[mod: Mod10, reg: dst_reg, rm: src_reg],
+            disp: imm32(src_disp),
+            )
       end
     end