зеркало из https://github.com/github/ruby.git
Fixes for AArch64 (https://github.com/Shopify/ruby/pull/338)
* Better splitting for Op::Add, Op::Sub, and Op::Cmp * Split stores if the displacement is too large * Use a shifted immediate argument * Split all places where shifted immediates are used * Add more tests to the cirrus workflow
This commit is contained in:
Kevin Newton
Takashi Kokubun
Родитель
96303342e4
Коммит
f593b2c6db
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@ -140,6 +140,7 @@ yjit_task:
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bootstraptest/test_flow.rb \
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bootstraptest/test_fork.rb \
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bootstraptest/test_gc.rb \
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bootstraptest/test_io.rb \
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bootstraptest/test_jump.rb \
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bootstraptest/test_literal_suffix.rb \
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bootstraptest/test_load.rb \
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@ -147,7 +148,9 @@ yjit_task:
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bootstraptest/test_massign.rb \
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bootstraptest/test_method.rb \
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bootstraptest/test_objectspace.rb \
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bootstraptest/test_proc.rb \
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bootstraptest/test_string.rb \
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bootstraptest/test_struct.rb \
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bootstraptest/test_yjit_new_backend.rb
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bootstraptest/test_yjit_rust_port.rb
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# full_build_script: make -j
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@ -4,9 +4,11 @@
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mod bitmask_imm;
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mod condition;
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mod sf;
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mod shifted_imm;
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mod sys_reg;
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pub use bitmask_imm::BitmaskImmediate;
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pub use condition::Condition;
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pub use sf::Sf;
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pub use shifted_imm::ShiftedImmediate;
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pub use sys_reg::SystemRegister;
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@ -0,0 +1,75 @@
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/// How much to shift the immediate by.
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pub enum Shift {
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LSL0 = 0b0, // no shift
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LSL12 = 0b1 // logical shift left by 12 bits
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}
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/// Some instructions accept a 12-bit immediate that has an optional shift
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/// attached to it. This allows encoding larger values than just fit into 12
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/// bits. We attempt to encode those here. If the values are too large we have
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/// to bail out.
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pub struct ShiftedImmediate {
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shift: Shift,
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value: u16
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}
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impl TryFrom<u64> for ShiftedImmediate {
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type Error = ();
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/// Attempt to convert a u64 into a BitmaskImm.
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fn try_from(value: u64) -> Result<Self, Self::Error> {
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let mut current = value;
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if current < 2_u64.pow(12) {
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return Ok(ShiftedImmediate { shift: Shift::LSL0, value: current as u16 });
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}
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if (current & (2_u64.pow(12) - 1) == 0) && ((current >> 12) < 2_u64.pow(12)) {
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return Ok(ShiftedImmediate { shift: Shift::LSL12, value: (current >> 12) as u16 });
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}
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Err(())
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}
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}
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impl From<ShiftedImmediate> for u32 {
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/// Encode a bitmask immediate into a 32-bit value.
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fn from(imm: ShiftedImmediate) -> Self {
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0
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| (((imm.shift as u32) & 1) << 12)
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| (imm.value as u32)
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}
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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#[test]
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fn test_no_shift() {
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let value = 256;
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let result = ShiftedImmediate::try_from(value);
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assert!(matches!(result, Ok(ShiftedImmediate { shift: Shift::LSL0, value })));
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}
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#[test]
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fn test_maximum_no_shift() {
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let value = (1 << 12) - 1;
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let result = ShiftedImmediate::try_from(value);
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assert!(matches!(result, Ok(ShiftedImmediate { shift: Shift::LSL0, value })));
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}
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#[test]
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fn test_with_shift() {
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let result = ShiftedImmediate::try_from(256 << 12);
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assert!(matches!(result, Ok(ShiftedImmediate { shift: Shift::LSL12, value: 256 })));
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}
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#[test]
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fn test_unencodable() {
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let result = ShiftedImmediate::try_from((256 << 12) + 1);
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assert!(matches!(result, Err(())));
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}
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}
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@ -1,4 +1,4 @@
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use super::super::arg::Sf;
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use super::super::arg::{Sf, ShiftedImmediate};
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/// The operation being performed by this instruction.
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enum Op {
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@ -12,12 +12,6 @@ enum S {
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UpdateFlags = 0b1
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}
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/// How much to shift the immediate by.
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enum Shift {
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LSL0 = 0b0, // no shift
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LSL12 = 0b1 // logical shift left by 12 bits
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}
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/// The struct that represents an A64 data processing -- immediate instruction
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/// that can be encoded.
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///
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@ -35,11 +29,8 @@ pub struct DataImm {
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/// The register number of the first operand register.
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rn: u8,
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/// The value of the immediate.
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imm12: u16,
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/// How much to shift the immediate by.
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shift: Shift,
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imm: ShiftedImmediate,
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/// Whether or not to update the flags when this instruction is performed.
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s: S,
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@ -54,64 +45,32 @@ pub struct DataImm {
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impl DataImm {
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/// ADD (immediate)
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/// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ADD--immediate---Add--immediate--?lang=en
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pub fn add(rd: u8, rn: u8, imm12: u16, num_bits: u8) -> Self {
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Self {
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rd,
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rn,
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imm12,
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shift: Shift::LSL0,
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s: S::LeaveFlags,
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op: Op::Add,
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sf: num_bits.into()
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}
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pub fn add(rd: u8, rn: u8, imm: ShiftedImmediate, num_bits: u8) -> Self {
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Self { rd, rn, imm, s: S::LeaveFlags, op: Op::Add, sf: num_bits.into() }
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}
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/// ADDS (immediate, set flags)
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/// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ADDS--immediate---Add--immediate---setting-flags-?lang=en
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pub fn adds(rd: u8, rn: u8, imm12: u16, num_bits: u8) -> Self {
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Self {
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rd,
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rn,
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imm12,
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shift: Shift::LSL0,
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s: S::UpdateFlags,
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op: Op::Add,
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sf: num_bits.into()
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}
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pub fn adds(rd: u8, rn: u8, imm: ShiftedImmediate, num_bits: u8) -> Self {
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Self { rd, rn, imm, s: S::UpdateFlags, op: Op::Add, sf: num_bits.into() }
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}
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/// CMP (immediate)
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/// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/CMP--immediate---Compare--immediate---an-alias-of-SUBS--immediate--?lang=en
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pub fn cmp(rn: u8, imm12: u16, num_bits: u8) -> Self {
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Self::subs(31, rn, imm12, num_bits)
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pub fn cmp(rn: u8, imm: ShiftedImmediate, num_bits: u8) -> Self {
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Self::subs(31, rn, imm, num_bits)
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}
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/// SUB (immediate)
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/// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/SUB--immediate---Subtract--immediate--?lang=en
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pub fn sub(rd: u8, rn: u8, imm12: u16, num_bits: u8) -> Self {
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Self {
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rd,
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rn,
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imm12,
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shift: Shift::LSL0,
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s: S::LeaveFlags,
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op: Op::Sub,
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sf: num_bits.into()
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}
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pub fn sub(rd: u8, rn: u8, imm: ShiftedImmediate, num_bits: u8) -> Self {
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Self { rd, rn, imm, s: S::LeaveFlags, op: Op::Sub, sf: num_bits.into() }
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}
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/// SUBS (immediate, set flags)
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/// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/SUBS--immediate---Subtract--immediate---setting-flags-?lang=en
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pub fn subs(rd: u8, rn: u8, imm12: u16, num_bits: u8) -> Self {
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Self {
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rd,
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rn,
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imm12,
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shift: Shift::LSL0,
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s: S::UpdateFlags,
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op: Op::Sub,
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sf: num_bits.into()
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}
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pub fn subs(rd: u8, rn: u8, imm: ShiftedImmediate, num_bits: u8) -> Self {
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Self { rd, rn, imm, s: S::UpdateFlags, op: Op::Sub, sf: num_bits.into() }
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}
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}
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@ -121,7 +80,7 @@ const FAMILY: u32 = 0b1000;
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impl From<DataImm> for u32 {
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/// Convert an instruction into a 32-bit value.
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fn from(inst: DataImm) -> Self {
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let imm12 = (inst.imm12 as u32) & ((1 << 12) - 1);
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let imm: u32 = inst.imm.into();
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0
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| ((inst.sf as u32) << 31)
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@ -129,8 +88,7 @@ impl From<DataImm> for u32 {
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| ((inst.s as u32) << 29)
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| (FAMILY << 25)
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| (1 << 24)
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| ((inst.shift as u32) << 22)
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| (imm12 << 10)
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| (imm << 10)
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| ((inst.rn as u32) << 5)
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| inst.rd as u32
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}
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@ -150,35 +108,35 @@ mod tests {
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#[test]
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fn test_add() {
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let inst = DataImm::add(0, 1, 7, 64);
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let inst = DataImm::add(0, 1, 7.try_into().unwrap(), 64);
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let result: u32 = inst.into();
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assert_eq!(0x91001c20, result);
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}
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#[test]
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fn test_adds() {
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let inst = DataImm::adds(0, 1, 7, 64);
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let inst = DataImm::adds(0, 1, 7.try_into().unwrap(), 64);
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let result: u32 = inst.into();
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assert_eq!(0xb1001c20, result);
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}
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#[test]
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fn test_cmp() {
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let inst = DataImm::cmp(0, 7, 64);
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let inst = DataImm::cmp(0, 7.try_into().unwrap(), 64);
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let result: u32 = inst.into();
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assert_eq!(0xf1001c1f, result);
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}
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#[test]
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fn test_sub() {
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let inst = DataImm::sub(0, 1, 7, 64);
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let inst = DataImm::sub(0, 1, 7.try_into().unwrap(), 64);
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let result: u32 = inst.into();
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assert_eq!(0xd1001c20, result);
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}
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#[test]
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fn test_subs() {
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let inst = DataImm::subs(0, 1, 7, 64);
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let inst = DataImm::subs(0, 1, 7.try_into().unwrap(), 64);
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let result: u32 = inst.into();
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assert_eq!(0xf1001c20, result);
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}
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@ -41,18 +41,16 @@ pub fn add(cb: &mut CodeBlock, rd: A64Opnd, rn: A64Opnd, rm: A64Opnd) {
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},
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(A64Opnd::Reg(rd), A64Opnd::Reg(rn), A64Opnd::UImm(uimm12)) => {
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assert!(rd.num_bits == rn.num_bits, "rd and rn must be of the same size.");
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assert!(uimm_fits_bits(uimm12, 12), "The immediate operand must be 12 bits or less.");
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DataImm::add(rd.reg_no, rn.reg_no, uimm12 as u16, rd.num_bits).into()
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DataImm::add(rd.reg_no, rn.reg_no, uimm12.try_into().unwrap(), rd.num_bits).into()
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},
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(A64Opnd::Reg(rd), A64Opnd::Reg(rn), A64Opnd::Imm(imm12)) => {
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assert!(rd.num_bits == rn.num_bits, "rd and rn must be of the same size.");
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assert!(imm_fits_bits(imm12, 12), "The immediate operand must be 12 bits or less.");
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if imm12 < 0 {
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DataImm::sub(rd.reg_no, rn.reg_no, -imm12 as u16, rd.num_bits).into()
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DataImm::sub(rd.reg_no, rn.reg_no, (-imm12 as u64).try_into().unwrap(), rd.num_bits).into()
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} else {
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DataImm::add(rd.reg_no, rn.reg_no, imm12 as u16, rd.num_bits).into()
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DataImm::add(rd.reg_no, rn.reg_no, (imm12 as u64).try_into().unwrap(), rd.num_bits).into()
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}
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},
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_ => panic!("Invalid operand combination to add instruction."),
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@ -74,18 +72,16 @@ pub fn adds(cb: &mut CodeBlock, rd: A64Opnd, rn: A64Opnd, rm: A64Opnd) {
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},
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(A64Opnd::Reg(rd), A64Opnd::Reg(rn), A64Opnd::UImm(imm12)) => {
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assert!(rd.num_bits == rn.num_bits, "rd and rn must be of the same size.");
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assert!(uimm_fits_bits(imm12, 12), "The immediate operand must be 12 bits or less.");
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DataImm::adds(rd.reg_no, rn.reg_no, imm12 as u16, rd.num_bits).into()
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DataImm::adds(rd.reg_no, rn.reg_no, imm12.try_into().unwrap(), rd.num_bits).into()
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},
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(A64Opnd::Reg(rd), A64Opnd::Reg(rn), A64Opnd::Imm(imm12)) => {
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assert!(rd.num_bits == rn.num_bits, "rd and rn must be of the same size.");
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assert!(imm_fits_bits(imm12, 12), "The immediate operand must be 12 bits or less.");
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if imm12 < 0 {
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DataImm::subs(rd.reg_no, rn.reg_no, -imm12 as u16, rd.num_bits).into()
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DataImm::subs(rd.reg_no, rn.reg_no, (-imm12 as u64).try_into().unwrap(), rd.num_bits).into()
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} else {
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DataImm::adds(rd.reg_no, rn.reg_no, imm12 as u16, rd.num_bits).into()
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DataImm::adds(rd.reg_no, rn.reg_no, (imm12 as u64).try_into().unwrap(), rd.num_bits).into()
|
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}
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},
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_ => panic!("Invalid operand combination to adds instruction."),
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|
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@ -272,9 +268,7 @@ pub fn cmp(cb: &mut CodeBlock, rn: A64Opnd, rm: A64Opnd) {
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DataReg::cmp(rn.reg_no, rm.reg_no, rn.num_bits).into()
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},
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(A64Opnd::Reg(rn), A64Opnd::UImm(imm12)) => {
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assert!(uimm_fits_bits(imm12, 12), "The immediate operand must be 12 bits or less.");
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|
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DataImm::cmp(rn.reg_no, imm12 as u16, rn.num_bits).into()
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DataImm::cmp(rn.reg_no, imm12.try_into().unwrap(), rn.num_bits).into()
|
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},
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_ => panic!("Invalid operand combination to cmp instruction."),
|
||||
};
|
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|
|
@ -477,12 +471,12 @@ pub fn mov(cb: &mut CodeBlock, rd: A64Opnd, rm: A64Opnd) {
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(A64Opnd::Reg(A64Reg { reg_no: 31, num_bits: 64 }), A64Opnd::Reg(rm)) => {
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assert!(rm.num_bits == 64, "Expected rm to be 64 bits");
|
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|
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DataImm::add(31, rm.reg_no, 0, 64).into()
|
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DataImm::add(31, rm.reg_no, 0.try_into().unwrap(), 64).into()
|
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},
|
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(A64Opnd::Reg(rd), A64Opnd::Reg(A64Reg { reg_no: 31, num_bits: 64 })) => {
|
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assert!(rd.num_bits == 64, "Expected rd to be 64 bits");
|
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|
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DataImm::add(rd.reg_no, 31, 0, 64).into()
|
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DataImm::add(rd.reg_no, 31, 0.try_into().unwrap(), 64).into()
|
||||
},
|
||||
(A64Opnd::Reg(rd), A64Opnd::Reg(rm)) => {
|
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assert!(rd.num_bits == rm.num_bits, "Expected registers to be the same size");
|
||||
|
|
@ -713,18 +707,16 @@ pub fn sub(cb: &mut CodeBlock, rd: A64Opnd, rn: A64Opnd, rm: A64Opnd) {
|
|||
},
|
||||
(A64Opnd::Reg(rd), A64Opnd::Reg(rn), A64Opnd::UImm(uimm12)) => {
|
||||
assert!(rd.num_bits == rn.num_bits, "rd and rn must be of the same size.");
|
||||
assert!(uimm_fits_bits(uimm12, 12), "The immediate operand must be 12 bits or less.");
|
||||
|
||||
DataImm::sub(rd.reg_no, rn.reg_no, uimm12 as u16, rd.num_bits).into()
|
||||
DataImm::sub(rd.reg_no, rn.reg_no, uimm12.try_into().unwrap(), rd.num_bits).into()
|
||||
},
|
||||
(A64Opnd::Reg(rd), A64Opnd::Reg(rn), A64Opnd::Imm(imm12)) => {
|
||||
assert!(rd.num_bits == rn.num_bits, "rd and rn must be of the same size.");
|
||||
assert!(imm_fits_bits(imm12, 12), "The immediate operand must be 12 bits or less.");
|
||||
|
||||
if imm12 < 0 {
|
||||
DataImm::add(rd.reg_no, rn.reg_no, -imm12 as u16, rd.num_bits).into()
|
||||
DataImm::add(rd.reg_no, rn.reg_no, (-imm12 as u64).try_into().unwrap(), rd.num_bits).into()
|
||||
} else {
|
||||
DataImm::sub(rd.reg_no, rn.reg_no, imm12 as u16, rd.num_bits).into()
|
||||
DataImm::sub(rd.reg_no, rn.reg_no, (imm12 as u64).try_into().unwrap(), rd.num_bits).into()
|
||||
}
|
||||
},
|
||||
_ => panic!("Invalid operand combination to sub instruction."),
|
||||
|
|
@ -746,18 +738,16 @@ pub fn subs(cb: &mut CodeBlock, rd: A64Opnd, rn: A64Opnd, rm: A64Opnd) {
|
|||
},
|
||||
(A64Opnd::Reg(rd), A64Opnd::Reg(rn), A64Opnd::UImm(uimm12)) => {
|
||||
assert!(rd.num_bits == rn.num_bits, "rd and rn must be of the same size.");
|
||||
assert!(uimm_fits_bits(uimm12, 12), "The immediate operand must be 12 bits or less.");
|
||||
|
||||
DataImm::subs(rd.reg_no, rn.reg_no, uimm12 as u16, rd.num_bits).into()
|
||||
DataImm::subs(rd.reg_no, rn.reg_no, uimm12.try_into().unwrap(), rd.num_bits).into()
|
||||
},
|
||||
(A64Opnd::Reg(rd), A64Opnd::Reg(rn), A64Opnd::Imm(imm12)) => {
|
||||
assert!(rd.num_bits == rn.num_bits, "rd and rn must be of the same size.");
|
||||
assert!(imm_fits_bits(imm12, 12), "The immediate operand must be 12 bits or less.");
|
||||
|
||||
if imm12 < 0 {
|
||||
DataImm::adds(rd.reg_no, rn.reg_no, -imm12 as u16, rd.num_bits).into()
|
||||
DataImm::adds(rd.reg_no, rn.reg_no, (-imm12 as u64).try_into().unwrap(), rd.num_bits).into()
|
||||
} else {
|
||||
DataImm::subs(rd.reg_no, rn.reg_no, imm12 as u16, rd.num_bits).into()
|
||||
DataImm::subs(rd.reg_no, rn.reg_no, (imm12 as u64).try_into().unwrap(), rd.num_bits).into()
|
||||
}
|
||||
},
|
||||
_ => panic!("Invalid operand combination to subs instruction."),
|
||||
|
|
|
|||
|
|
@ -81,7 +81,10 @@ impl Assembler
|
|||
/// have no memory operands.
|
||||
fn arm64_split(mut self) -> Assembler
|
||||
{
|
||||
fn load_bitmask_immediate(asm: &mut Assembler, opnd: Opnd) -> Opnd {
|
||||
/// Operands that take the place of bitmask immediates must follow a
|
||||
/// certain encoding. In this function we ensure that those operands
|
||||
/// do follow that encoding, and if they don't then we load them first.
|
||||
fn split_bitmask_immediate(asm: &mut Assembler, opnd: Opnd) -> Opnd {
|
||||
match opnd {
|
||||
Opnd::Reg(_) | Opnd::InsnOut { .. } => opnd,
|
||||
Opnd::Mem(_) => asm.load(opnd),
|
||||
|
|
@ -105,6 +108,41 @@ impl Assembler
|
|||
}
|
||||
}
|
||||
|
||||
/// Operands that take the place of a shifted immediate must fit within
|
||||
/// a certain size. If they don't then we need to load them first.
|
||||
fn split_shifted_immediate(asm: &mut Assembler, opnd: Opnd) -> Opnd {
|
||||
match opnd {
|
||||
Opnd::Reg(_) | Opnd::InsnOut { .. } => opnd,
|
||||
Opnd::Mem(_) | Opnd::Imm(_) => asm.load(opnd),
|
||||
Opnd::UImm(uimm) => {
|
||||
if ShiftedImmediate::try_from(uimm).is_ok() {
|
||||
opnd
|
||||
} else {
|
||||
asm.load(opnd)
|
||||
}
|
||||
},
|
||||
Opnd::None | Opnd::Value(_) => unreachable!()
|
||||
}
|
||||
}
|
||||
|
||||
/// When you're storing a register into a memory location, the
|
||||
/// displacement from the base register of the memory location must fit
|
||||
/// into 9 bits. If it doesn't, then we need to load that memory address
|
||||
/// into a register first.
|
||||
fn split_store(asm: &mut Assembler, opnd: Opnd) -> Opnd {
|
||||
match opnd {
|
||||
Opnd::Mem(mem) => {
|
||||
if imm_fits_bits(mem.disp.into(), 9) {
|
||||
opnd
|
||||
} else {
|
||||
let base = asm.lea(opnd);
|
||||
Opnd::mem(64, base, 0)
|
||||
}
|
||||
},
|
||||
_ => unreachable!("Can only store memory addresses.")
|
||||
}
|
||||
}
|
||||
|
||||
self.forward_pass(|asm, index, op, opnds, target, text, pos_marker| {
|
||||
// Load all Value operands into registers that aren't already a part
|
||||
// of Load instructions.
|
||||
|
|
@ -120,22 +158,20 @@ impl Assembler
|
|||
};
|
||||
|
||||
match op {
|
||||
Op::Add | Op::Sub => {
|
||||
// Check if one of the operands is a register. If it is,
|
||||
// then we'll make that the first operand.
|
||||
Op::Add => {
|
||||
match (opnds[0], opnds[1]) {
|
||||
(Opnd::Mem(_), Opnd::Mem(_)) => {
|
||||
let opnd0 = asm.load(opnds[0]);
|
||||
let opnd1 = asm.load(opnds[1]);
|
||||
asm.push_insn(op, vec![opnd0, opnd1], target, text, pos_marker);
|
||||
(Opnd::Reg(_) | Opnd::InsnOut { .. }, Opnd::Reg(_) | Opnd::InsnOut { .. }) => {
|
||||
asm.add(opnds[0], opnds[1]);
|
||||
},
|
||||
(mem_opnd @ Opnd::Mem(_), other_opnd) |
|
||||
(other_opnd, mem_opnd @ Opnd::Mem(_)) => {
|
||||
let opnd0 = asm.load(mem_opnd);
|
||||
asm.push_insn(op, vec![opnd0, other_opnd], target, text, pos_marker);
|
||||
(reg_opnd @ (Opnd::Reg(_) | Opnd::InsnOut { .. }), other_opnd) |
|
||||
(other_opnd, reg_opnd @ (Opnd::Reg(_) | Opnd::InsnOut { .. })) => {
|
||||
let opnd1 = split_shifted_immediate(asm, other_opnd);
|
||||
asm.add(reg_opnd, opnd1);
|
||||
},
|
||||
_ => {
|
||||
asm.push_insn(op, opnds, target, text, pos_marker);
|
||||
let opnd0 = asm.load(opnds[0]);
|
||||
let opnd1 = split_shifted_immediate(asm, opnds[1]);
|
||||
asm.add(opnd0, opnd1);
|
||||
}
|
||||
}
|
||||
},
|
||||
|
|
@ -146,12 +182,12 @@ impl Assembler
|
|||
},
|
||||
(reg_opnd @ Opnd::Reg(_), other_opnd) |
|
||||
(other_opnd, reg_opnd @ Opnd::Reg(_)) => {
|
||||
let opnd1 = load_bitmask_immediate(asm, other_opnd);
|
||||
let opnd1 = split_bitmask_immediate(asm, other_opnd);
|
||||
asm.and(reg_opnd, opnd1);
|
||||
},
|
||||
_ => {
|
||||
let opnd0 = asm.load(opnds[0]);
|
||||
let opnd1 = load_bitmask_immediate(asm, opnds[1]);
|
||||
let opnd1 = split_bitmask_immediate(asm, opnds[1]);
|
||||
asm.and(opnd0, opnd1);
|
||||
}
|
||||
}
|
||||
|
|
@ -173,6 +209,16 @@ impl Assembler
|
|||
// just performs the call.
|
||||
asm.ccall(target.unwrap().unwrap_fun_ptr(), vec![]);
|
||||
},
|
||||
Op::Cmp => {
|
||||
let opnd0 = match opnds[0] {
|
||||
Opnd::Reg(_) | Opnd::InsnOut { .. } => opnds[0],
|
||||
_ => asm.load(opnds[0])
|
||||
};
|
||||
|
||||
let opnd1 = split_shifted_immediate(asm, opnds[1]);
|
||||
|
||||
asm.push_insn(op, vec![opnd0, opnd1], target, text, pos_marker);
|
||||
},
|
||||
Op::CRet => {
|
||||
if opnds[0] != Opnd::Reg(C_RET_REG) {
|
||||
let value = asm.load(opnds[0]);
|
||||
|
|
@ -238,15 +284,20 @@ impl Assembler
|
|||
// register or an immediate that can be encoded as a
|
||||
// bitmask immediate. Otherwise, we'll need to split the
|
||||
// move into multiple instructions.
|
||||
_ => load_bitmask_immediate(asm, opnds[1])
|
||||
_ => split_bitmask_immediate(asm, opnds[1])
|
||||
};
|
||||
|
||||
// If we're attempting to load into a memory operand, then
|
||||
// we'll switch over to the store instruction. Otherwise
|
||||
// we'll use the normal mov instruction.
|
||||
match opnds[0] {
|
||||
Opnd::Mem(_) => asm.store(opnds[0], value),
|
||||
_ => asm.mov(opnds[0], value)
|
||||
Opnd::Mem(_) => {
|
||||
let opnd0 = split_store(asm, opnds[0]);
|
||||
asm.store(opnd0, value);
|
||||
},
|
||||
_ => {
|
||||
asm.mov(opnds[0], value);
|
||||
}
|
||||
};
|
||||
},
|
||||
Op::Not => {
|
||||
|
|
@ -260,6 +311,11 @@ impl Assembler
|
|||
asm.not(opnd0);
|
||||
},
|
||||
Op::Store => {
|
||||
// The displacement for the STUR instruction can't be more
|
||||
// than 9 bits long. If it's longer, we need to load the
|
||||
// memory address into a register first.
|
||||
let opnd0 = split_store(asm, opnds[0]);
|
||||
|
||||
// The value being stored must be in a register, so if it's
|
||||
// not already one we'll load it first.
|
||||
let opnd1 = match opnds[1] {
|
||||
|
|
@ -267,7 +323,17 @@ impl Assembler
|
|||
_ => asm.load(opnds[1])
|
||||
};
|
||||
|
||||
asm.store(opnds[0], opnd1);
|
||||
asm.store(opnd0, opnd1);
|
||||
},
|
||||
Op::Sub => {
|
||||
let opnd0 = match opnds[0] {
|
||||
Opnd::Reg(_) | Opnd::InsnOut { .. } => opnds[0],
|
||||
_ => asm.load(opnds[0])
|
||||
};
|
||||
|
||||
let opnd1 = split_shifted_immediate(asm, opnds[1]);
|
||||
|
||||
asm.push_insn(op, vec![opnd0, opnd1], target, text, pos_marker);
|
||||
},
|
||||
Op::Test => {
|
||||
// The value being tested must be in a register, so if it's
|
||||
|
|
@ -281,7 +347,7 @@ impl Assembler
|
|||
// unsigned immediate that can be encoded as a bitmask
|
||||
// immediate. If it's not one of those, we'll need to load
|
||||
// it first.
|
||||
let opnd1 = load_bitmask_immediate(asm, opnds[1]);
|
||||
let opnd1 = split_bitmask_immediate(asm, opnds[1]);
|
||||
|
||||
asm.test(opnd0, opnd1);
|
||||
},
|
||||
|
|
@ -454,18 +520,15 @@ impl Assembler
|
|||
cb.add_comment(&insn.text.as_ref().unwrap());
|
||||
}
|
||||
},
|
||||
|
||||
Op::Label => {
|
||||
cb.write_label(insn.target.unwrap().unwrap_label_idx());
|
||||
},
|
||||
|
||||
// Report back the current position in the generated code
|
||||
Op::PosMarker => {
|
||||
let pos = cb.get_write_ptr();
|
||||
let pos_marker_fn = insn.pos_marker.as_ref().unwrap();
|
||||
pos_marker_fn(pos);
|
||||
}
|
||||
|
||||
Op::BakeString => {
|
||||
let str = insn.text.as_ref().unwrap();
|
||||
for byte in str.as_bytes() {
|
||||
|
|
|
|||
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