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arm64/arm64asm: fix the wrong shifted register offset go assembler syntax 

The current Go assembler encodes "MOVB R4, (R2)(R6)" as "44682638"
and encodes "MOVB R4, (R2)(R6<<0)" as "44782638", but the current
Go disassembler returns the same Go syntax "MOVB R4, (R3)(R6) for
the above two binarys. To match the assembler, this patch fixes the
wrong shifted register go syntax.

The fixed Go syntax:
  strb w4, [x2, x6, lsl #0]  ->   MOVB R4, (R2)(R6<<0)
  strb w4, [x2, x6]          ->   MOVB R4, (R2)(R6)

Change-Id: I60d4cdf1c04511891268efe510a18291fe0c0da6
Reviewed-on: https://go-review.googlesource.com/c/arch/+/214358
Run-TryBot: fannie zhang <Fannie.Zhang@arm.com>
TryBot-Result: Go Bot <gobot@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Trust: fannie zhang <Fannie.Zhang@arm.com>
This commit is contained in:
fanzha02 2020-01-08 11:14:57 +00:00 коммит произвёл fannie zhang
Родитель 52c3e6f60c
Коммит 377592649d
3 изменённых файлов: 40 добавлений и 20 удалений
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10
arm64/arm64asm/inst.go
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@ -538,10 +538,12 @@ type MemExtend struct {
Extend ExtShift
// Amount indicates the index shift amount (but also see ShiftMustBeZero field below).
Amount uint8
// ShiftMustBeZero is set to true when the shift amount must be 0, even if the
// Amount field is not 0. In GNU syntax, a #0 shift amount is printed if Amount
// is not 0 but ShiftMustBeZero is true; #0 is not printed if Amount is 0 and
// ShiftMustBeZero is true. Both cases represent shift by 0 bit.
// Refer to ARM reference manual, for byte load/store(register), the index
// shift amount must be 0, encoded in "S" as 0 if omitted, or as 1 if present.
// a.ShiftMustBeZero is set true indicates the index shift amount must be 0.
// In GNU syntax, a #0 shift amount is printed if Amount is 1 but ShiftMustBeZero
// is true; #0 is not printed if Amount is 0 and ShiftMustBeZero is true.
// Both cases represent shift by 0 bit.
ShiftMustBeZero bool
}

14
arm64/arm64asm/plan9x.go
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@ -595,14 +595,18 @@ func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg
}
if a.Extend == lsl {
// Refer to ARM reference manual, for byte load/store(register), the index
// shift amount must be 0, encoded in "S" as 0 if omitted, or as 1 if present.
// a.Amount indicates the index shift amount, encoded in "S" field.
// a.ShiftMustBeZero is set true when the index shift amount must be 0,
// even if the a.Amount field is not 0.
// When a.ShiftMustBeZero is ture, GNU syntax prints #0 shift amount if
// "S" equals to 1, or does not print #0 shift amount if "S" equals to 0.
// Go syntax should never print a zero index shift amount.
// a.ShiftMustBeZero is set true indicates the index shift amount must be 0.
// When a.ShiftMustBeZero is true, GNU syntax prints "[Xn, Xm lsl #0]" if "S"
// equals to 1, or prints "[Xn, Xm]" if "S" equals to 0.
if a.Amount != 0 && !a.ShiftMustBeZero {
index = fmt.Sprintf("(%s<<%d)", indexreg, a.Amount)
} else if a.ShiftMustBeZero && a.Amount == 1 {
// When a.ShiftMustBeZero is ture, Go syntax prints "(Rm<<0)" if "a.Amount"
// equals to 1.
index = fmt.Sprintf("(%s<<0)", indexreg)
} else {
index = fmt.Sprintf("(%s)", indexreg)
}

36
arm64/arm64asm/testdata/plan9cases.txt поставляемый
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@ -137,7 +137,7 @@ daeb66f8| MOVD (R30)(R6.SXTX), R26
8ca74238| MOVBU.P 42(R28), R12
4e5c5e38| MOVBU.W -27(R2), R14
03936d39| MOVBU 2916(R24), R3
577a6e38| MOVBU (R18)(R14), R23
577a6e38| MOVBU (R18)(R14<<0), R23
adb54678| MOVHU.P 107(R13), R13
820f4c78| MOVHU.W 192(R28), R2
92787579| MOVHU 6844(R4), R18
@ -147,7 +147,7 @@ fb478238| MOVB.P 36(RSP), R27
18ee9438| MOVB.W -178(R16), R24
16b9c639| MOVBW 430(R8), R22
37958f39| MOVB 997(R9), R23
af7ae238| MOVBW (R21)(R2), R15
af7ae238| MOVBW (R21)(R2<<0), R15
1568fa38| MOVBW (R0)(R26), R21
744bbf38| MOVB (R27)(ZR.UXTW), R20
f069a538| MOVB (R15)(R5), R16
@ -696,7 +696,7 @@ f5c3547d| MOVD 2656(RSP), V21
8e8a7bbd| FMOVS 15240(R20), F14
8e3c7afd| FMOVD 29816(R4), F14
f2aeff3d| MOVD 65200(R23), V18
1d78793c| MOVD (R0)(R25), V29
1d78793c| MOVD (R0)(R25<<0), V29
b8f15d3c| VLDUR -33(R13), V24
95635c7c| VLDUR -58(R28), V21
27d046bc| VLDUR 109(R1), V7
@ -1143,7 +1143,7 @@ e1cd51b9| MOVWU 4556(R15), R1
0c554b38| MOVBU.P 181(R8), R12
054f5938| MOVBU.W -108(R24), R5
1f206539| MOVBU 2376(R0), ZR
73796a38| MOVBU (R11)(R10), R19
73796a38| MOVBU (R11)(R10<<0), R19
a8b74f78| MOVHU.P 251(R29), R8
021e5e78| MOVHU.W -31(R16), R2
ec126b79| MOVHU 5512(R23), R12
@ -1155,7 +1155,7 @@ eaf6c238| MOVBW.P 47(R23), R10
7d74c039| MOVBW 29(R3), R29
7d1f8539| MOVB 327(R27), R29
225bff38| MOVBW (R25)(ZR.UXTW), R2
6a7bed38| MOVBW (R27)(R13), R10
6a7bed38| MOVBW (R27)(R13<<0), R10
0f69b538| MOVB (R8)(R21), R15
c796cc78| MOVHW.P 201(R22), R7
50268e78| MOVH.P 226(R18), R16
@ -1701,7 +1701,7 @@ f5885e7d| MOVD 3908(R7), V21
0cc4e93d| MOVD 42768(R0), V12
e1c4211c| FMOVS 69159(PC), F1
2071c35c| FMOVD -124023(PC), F0
ae79703c| MOVD (R13)(R16), V14
ae79703c| MOVD (R13)(R16<<0), V14
38fb67bc| FMOVS (R25)(R7.SXTX<<2), F24
3e6b6dfc| FMOVD (R25)(R13), F30
a278ff3c| MOVD (R5)(ZR<<4), V2
@ -1925,7 +1925,7 @@ d46e39bd| FMOVS F20, 14700(R22)
b84f30fd| FMOVD F24, 24728(R29)
3cee993d| MOVD V28, 26544(R17)
4348293c| MOVD V3, (R2)(R9.UXTW)
ed7b253c| MOVD V13, (RSP)(R5)
ed7b253c| MOVD V13, (RSP)(R5<<0)
8fc9357c| MOVD V15, (R12)(R21.SXTW)
87f832bc| FMOVS F7, (R4)(R18.SXTX<<2)
f1ea38fc| FMOVD F17, (R23)(R24.SXTX)
@ -2164,7 +2164,7 @@ b63e8038| MOVB.W 3(R21), R22
4491c939| MOVBW 612(R10), R4
497e8039| MOVB 31(R18), R9
7d6bf638| MOVBW (R27)(R22), R29
e578ba38| MOVB (R7)(R26), R5
e578ba38| MOVB (R7)(R26<<0), R5
9f06ca78| MOVHW.P 160(R20), ZR
15c59d78| MOVH.P -36(R8), R21
c07fd278| MOVHW.W -217(R30), R0
@ -2309,7 +2309,7 @@ d21508f8| MOVD.P R18, 129(R14)
1b441b38| MOVB.P R27, -76(R0)
d69c0f38| MOVB.W R22, 249(R6)
b7ce0d39| MOVB R23, 883(R21)
2b7b3938| MOVB R11, (R25)(R25)
2b7b3938| MOVB R11, (R25)(R25<<0)
4e771d78| MOVH.P R14, -41(R26)
64cc0b78| MOVH.W R4, 188(R3)
07b90279| MOVH R7, 348(R8)
@ -2940,7 +2940,7 @@ d41d13bc| FMOVS.W F20, -207(R14)
409503fd| FMOVD F0, 1832(R10)
58a1963d| MOVD V24, 23168(R10)
51c8253c| MOVD V17, (R2)(R5.SXTW)
967b313c| MOVD V22, (R28)(R17)
967b313c| MOVD V22, (R28)(R17<<0)
b4683e7c| MOVD V20, (R5)(R30)
64d9a33c| MOVD V4, (R11)(R3.SXTW<<4)
e5e1143c| MOVD V5, -178(R15)
@ -3950,7 +3950,7 @@ f0e5357d| MOVD V16, 6898(R15)
aeb813fd| FMOVD F14, 10096(R5)
2cc4943d| MOVD V12, 21264(R1)
e2f8263c| MOVD V2, (R7)(R6.SXTX)
1d79373c| MOVD V29, (R8)(R23)
1d79373c| MOVD V29, (R8)(R23<<0)
bc70003c| MOVD V28, 7(R5)
7190157c| MOVD V17, -167(R3)
073309bc| FMOVS F7, 147(R24)
@ -4562,3 +4562,17 @@ bd00639e| UCVTFD R5, F29
0b3c030e| VMOV V0.B[1], R11
2c3c0e0e| VMOV V1.H[3], R12
d7061a6f| VUSHR $6, V22.H8, V23.H8
44f82638| MOVB R4, (R2)(R6.SXTX)
44e82638| MOVB R4, (R2)(R6.SXTX)
44682638| MOVB R4, (R2)(R6)
44782638| MOVB R4, (R2)(R6<<0)
44e8a638| MOVB (R2)(R6.SXTX), R4
44f8a638| MOVB (R2)(R6.SXTX), R4
4468a638| MOVB (R2)(R6), R4
4478a638| MOVB (R2)(R6<<0), R4
44e86638| MOVBU (R2)(R6.SXTX), R4
44f86638| MOVBU (R2)(R6.SXTX), R4
44686638| MOVBU (R2)(R6), R4
44786638| MOVBU (R2)(R6<<0), R4
ae7bbe38| MOVB (R29)(R30<<0), R14
ae6bbe38| MOVB (R29)(R30), R14