diff --git a/ppc64/pp64.csv b/ppc64/pp64.csv
index c5e4e2d..fdcff5f 100644
--- a/ppc64/pp64.csv
+++ b/ppc64/pp64.csv
@@ -1007,7 +1007,6 @@
 #"Decorated Storage Notify X-form","dsn RA,RB","31@0|///@6|RA@11|RB@16|483@21|/@31|",""
 #"External Control In Word Indexed X-form","eciwx RT,RA,RB","31@0|RT@6|RA@11|RB@16|310@21|/@31|",""
 #"External Control Out Word Indexed X-form","ecowx RS,RA,RB","31@0|RS@6|RA@11|RB@16|438@21|/@31|",""
-"System Call SC-form","sc LEV","17@0|///@6|///@11|///@16|LEV@20|///@27|1@30|/@31|",""
 "Return from Interrupt Doubleword XL-form","rfid","19@0|///@6|///@11|///@16|18@21|/@31|",""
 "Return From Interrupt Doubleword Hypervisor XL-form","hrfid","19@0|///@6|///@11|///@16|274@21|/@31|",""
 #"Doze XL-form","doze","19@0|///@6|///@11|///@16|402@21|/@31|",""
@@ -1024,8 +1023,6 @@
 "Store Doubleword Caching Inhibited Indexed X-form","stdcix RS,RA,RB","31@0|RS@6|RA@11|RB@16|1013@21|/@31|",""
 #"Transaction Reclaim X-form","treclaim. RA","31@0|///@6|RA@11|///@16|942@21|1@31|",""
 #"Transaction Recheckpoint X-form","trechkpt.","31@0|///@6|///@11|///@16|1006@21|1@31|",""
-"Move To Special Purpose Register XFX-form","mtspr SPR,RS","31@0|RS@6|spr@11|467@21|/@31|",""
-"Move From Special Purpose Register XFX-form","mfspr RT,SPR","31@0|RT@6|spr@11|339@21|/@31|",""
 "Move To MSR X-form","mtmsr RS,L","31@0|RS@6|///@11|L@15|///@16|146@21|/@31|",""
 "Move To MSR Doubleword X-form","mtmsrd RS,L","31@0|RS@6|///@11|L@15|///@16|178@21|/@31|",""
 "Move From MSR X-form","mfmsr RT","31@0|RT@6|///@11|///@16|83@21|/@31|",""
@@ -1048,21 +1045,16 @@
 "Message Send Privileged X-form","msgsndp RB","31@0|///@6|///@11|RB@16|142@21|/@31|",""
 "Message Clear Privileged X-form","msgclrp RB","31@0|///@6|///@11|RB@16|174@21|/@31|",""
 #"Move To Thread Management Register XFX-form","mttmr TMR,RS","31@0|RS@6|tmr@11|494@21|/@31|",""
-"System Call SC-form","sc LEV","17@0|///@6|///@11|///@16|LEV@20|///@27|1@30|/@31|",""
 #"Return From Interrupt XL-form","rfi","19@0|///@6|///@11|///@16|50@21|/@31|",""
 #"Return From Critical Interrupt XL-form","rfci","19@0|///@6|///@11|///@16|51@21|/@31|",""
 #"Return From Debug Interrupt X-form","rfdi|[Category: Embedded.Enhanced Debug]","19@0|///@6|///@11|///@16|39@21|/@31|",""
 #"Return From Machine Check Interrupt XL-form","rfmci","19@0|///@6|///@11|///@16|38@21|/@31|",""
 #"Return From Guest Interrupt XL-form","rfgi [Category:Embedded.Hypervisor]","19@0|///@6|///@11|///@16|102@21|/@31|",""
 #"Embedded Hypervisor Privilege XL-form","ehpriv OC [Category: Embedded.Hypervisor]","31@0|OC@6|270@21|/@31|",""
-"Move To Special Purpose Register XFX-form","mtspr SPR,RS","31@0|RS@6|spr@11|467@21|/@31|",""
-"Move From Special Purpose Register XFX-form","mfspr RT,SPR","31@0|RT@6|spr@11|339@21|/@31|",""
 #"Move To Device Control Register XFX-form","mtdcr DCRN,RS|[Category: Embedded.Device Control]","31@0|RS@6|dcr@11|451@21|/@31|",""
 #"Move To Device Control Register Indexed X-form","mtdcrx RA,RS|[Category: Embedded.Device Control]","31@0|RS@6|RA@11|///@16|387@21|/@31|",""
 #"Move From Device Control Register XFX-form","mfdcr RT,DCRN|[Category: Embedded.Device Control]","31@0|RT@6|dcr@11|323@21|/@31|",""
 #"Move From Device Control Register Indexed X-form","mfdcrx RT,RA|[Category: Embedded.Device Control]","31@0|RT@6|RA@11|///@16|259@21|/@31|",""
-"Move To MSR X-form","mtmsr RS,L","31@0|RS@6|///@11|L@15|///@16|146@21|/@31|",""
-"Move From MSR X-form","mfmsr RT","31@0|RT@6|///@11|///@16|83@21|/@31|",""
 #"Write MSR External Enable X-form","wrtee RS","31@0|RS@6|///@11|///@16|131@21|/@31|",""
 #"Write MSR External Enable Immediate X-form","wrteei E","31@0|///@6|///@11|E@16|///@17|163@21|/@31|",""
 #"Load Byte by External Process ID Indexed X-form","lbepx RT,RA,RB","31@0|RT@6|RA@11|RB@16|95@21|/@31|",""
@@ -1100,11 +1092,8 @@
 #"TLB Search Indexed X-form","tlbsx RA,RB","31@0|///@6|RA@11|RB@16|914@21|/@31|",""
 #"TLB Search and Reserve Indexed X-form","tlbsrx. RA,RB [Category: Embedded.TLB Write|Conditional]","31@0|///@6|RA@11|RB@16|850@21|1@31|",""
 #"TLB Read Entry X-form","tlbre","31@0|///@6|///@11|///@16|946@21|/@31|",""
-"TLB Synchronize X-form","tlbsync","31@0|///@6|///@11|///@16|566@21|/@31|",""
 #"TLB Write Entry X-form","tlbwe","31@0|///@6|///@11|///@16|978@21|/@31|",""
 #"Debugger Notify Halt XFX-form","dnh DUI,DUIS","19@0|DUI@6|DUIS@11|198@21|/@31|",""
-"Message Send X-form","msgsnd RB","31@0|///@6|///@11|RB@16|206@21|/@31|",""
-"Message Clear X-form","msgclr RB","31@0|///@6|///@11|RB@16|238@21|/@31|",""
 #"Data Cache Invalidate X-form","dci CT","31@0|/@6|CT@7|///@11|///@16|454@21|/@31|",""
 #"Instruction Cache Invalidate X-form","ici CT","31@0|/@6|CT@7|///@11|///@16|966@21|/@31|",""
 #"Data Cache Read X-form","dcread RT,RA,RB","31@0|RT@6|RA@11|RB@16|486@21|/@31|",""
@@ -1234,14 +1223,8 @@
 "Multiply-Add Low Doubleword VA-form","maddld RT,RA,RB,RC","4@0|RT@6|RA@11|RB@16|RC@21|51@26|",""
 "Compare Ranged Byte X-form","cmprb BF,L,RA,RB","31@0|BF@6|/@9|L@10|RA@11|RB@16|192@21|/@31|",""
 "Compare Equal Byte X-form","cmpeqb BF,RA,RB","31@0|BF@6|//@9|RA@11|RB@16|224@21|/@31|",""
-"Bit Permute Doubleword X-form","bpermd RA,RS,RB","31@0|RS@6|RA@11|RB@16|252@21|/@31|",""
 "Extend Sign Word and Shift Left Immediate XS-form","extswsli RA,RS,SH (Rc=0)|extswsli. RA,RS,SH (Rc=1)","31@0|RS@6|RA@11|sh@16|445@21|sh@30|Rc@31|",""
-"Move From VSR Doubleword X-form","mfvsrd RA,XS","31@0|S@6|RA@11|///@16|51@21|SX@31|",""
 "Move From VSR Lower Doubleword X-form","mfvsrld RA,XS","31@0|S@6|RA@11|///@16|307@21|SX@31|",""
-"Move From VSR Word and Zero X-form","mfvsrwz RA,XS","31@0|S@6|RA@11|///@16|115@21|SX@31|",""
-"Move To VSR Doubleword X-form","mtvsrd XT,RA","31@0|T@6|RA@11|///@16|179@21|TX@31|",""
-"Move To VSR Word Algebraic X-form","mtvsrwa XT,RA","31@0|T@6|RA@11|///@16|211@21|TX@31|",""
-"Move To VSR Word and Zero X-form","mtvsrwz XT,RA","31@0|T@6|RA@11|///@16|243@21|TX@31|",""
 "Move To VSR Double Doubleword X-form","mtvsrdd XT,RA,RB","31@0|T@6|RA@11|RB@16|435@21|TX@31|",""
 "Move To VSR Word & Splat X-form","mtvsrws XT,RA","31@0|T@6|RA@11|///@16|403@21|TX@31|",""
 "Move to CR from XER Extended X-form","mcrxrx BF","31@0|BF@6|//@9|///@11|///@16|576@21|/@31|",""
diff --git a/ppc64/ppc64asm/tables.go b/ppc64/ppc64asm/tables.go
index 97f648d..a725694 100644
--- a/ppc64/ppc64asm/tables.go
+++ b/ppc64/ppc64asm/tables.go
@@ -4606,8 +4606,6 @@ var instFormats = [...]instFormat{
 		[5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
 	{RFEBB, 0xfc0007fe, 0x4c000124, 0x3fff001, // Return from Event Based Branch XL-form (rfebb S)
 		[5]*argField{ap_ImmUnsigned_20_20}},
-	{SC, 0xfc000002, 0x44000002, 0x3fff01d, // System Call SC-form (sc LEV)
-		[5]*argField{ap_ImmUnsigned_20_26}},
 	{RFID, 0xfc0007fe, 0x4c000024, 0x3fff801, // Return from Interrupt Doubleword XL-form (rfid)
 		[5]*argField{}},
 	{HRFID, 0xfc0007fe, 0x4c000224, 0x3fff801, // Return From Interrupt Doubleword Hypervisor XL-form (hrfid)
@@ -4628,10 +4626,6 @@ var instFormats = [...]instFormat{
 		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{STDCIX, 0xfc0007fe, 0x7c0007ea, 0x1, // Store Doubleword Caching Inhibited Indexed X-form (stdcix RS,RA,RB)
 		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
-	{MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS)
-		[5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
-	{MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1, // Move From Special Purpose Register XFX-form (mfspr RT,SPR)
-		[5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
 	{MTMSR, 0xfc0007fe, 0x7c000124, 0x1ef801, // Move To MSR X-form (mtmsr RS,L)
 		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}},
 	{MTMSRD, 0xfc0007fe, 0x7c000164, 0x1ef801, // Move To MSR Doubleword X-form (mtmsrd RS,L)
@@ -4664,22 +4658,6 @@ var instFormats = [...]instFormat{
 		[5]*argField{ap_Reg_16_20}},
 	{MSGCLRP, 0xfc0007fe, 0x7c00015c, 0x3ff0001, // Message Clear Privileged X-form (msgclrp RB)
 		[5]*argField{ap_Reg_16_20}},
-	{SC, 0xfc000002, 0x44000002, 0x3fff01d, // System Call SC-form (sc LEV)
-		[5]*argField{ap_ImmUnsigned_20_26}},
-	{MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS)
-		[5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
-	{MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1, // Move From Special Purpose Register XFX-form (mfspr RT,SPR)
-		[5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
-	{MTMSR, 0xfc0007fe, 0x7c000124, 0x1ef801, // Move To MSR X-form (mtmsr RS,L)
-		[5]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}},
-	{MFMSR, 0xfc0007fe, 0x7c0000a6, 0x1ff801, // Move From MSR X-form (mfmsr RT)
-		[5]*argField{ap_Reg_6_10}},
-	{TLBSYNC, 0xfc0007fe, 0x7c00046c, 0x3fff801, // TLB Synchronize X-form (tlbsync)
-		[5]*argField{}},
-	{MSGSND, 0xfc0007fe, 0x7c00019c, 0x3ff0001, // Message Send X-form (msgsnd RB)
-		[5]*argField{ap_Reg_16_20}},
-	{MSGCLR, 0xfc0007fe, 0x7c0001dc, 0x3ff0001, // Message Clear X-form (msgclr RB)
-		[5]*argField{ap_Reg_16_20}},
 	{ADDEX, 0xfc0001fe, 0x7c000154, 0x1, // Add Extended using alternate carry bit Z23-form (addex RT,RA,RB,CY)
 		[5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_21_22}},
 	{DARN, 0xfc0007fe, 0x7c0005e6, 0x1cf801, // Deliver A Random Number X-form (darn RT,L)
@@ -4694,24 +4672,12 @@ var instFormats = [...]instFormat{
 		[5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{CMPEQB, 0xfc0007fe, 0x7c0001c0, 0x600001, // Compare Equal Byte X-form (cmpeqb BF,RA,RB)
 		[5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
-	{BPERMD, 0xfc0007fe, 0x7c0001f8, 0x1, // Bit Permute Doubleword X-form (bpermd RA,RS,RB)
-		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
 	{EXTSWSLI, 0xfc0007fd, 0x7c0006f4, 0x0, // Extend Sign Word and Shift Left Immediate XS-form (extswsli RA,RS,SH)
 		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
 	{EXTSWSLICC, 0xfc0007fd, 0x7c0006f5, 0x0, // Extend Sign Word and Shift Left Immediate XS-form (extswsli. RA,RS,SH)
 		[5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
-	{MFVSRD, 0xfc0007fe, 0x7c000066, 0xf800, // Move From VSR Doubleword X-form (mfvsrd RA,XS)
-		[5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
 	{MFVSRLD, 0xfc0007fe, 0x7c000266, 0xf800, // Move From VSR Lower Doubleword X-form (mfvsrld RA,XS)
 		[5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
-	{MFVSRWZ, 0xfc0007fe, 0x7c0000e6, 0xf800, // Move From VSR Word and Zero X-form (mfvsrwz RA,XS)
-		[5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
-	{MTVSRD, 0xfc0007fe, 0x7c000166, 0xf800, // Move To VSR Doubleword X-form (mtvsrd XT,RA)
-		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
-	{MTVSRWA, 0xfc0007fe, 0x7c0001a6, 0xf800, // Move To VSR Word Algebraic X-form (mtvsrwa XT,RA)
-		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
-	{MTVSRWZ, 0xfc0007fe, 0x7c0001e6, 0xf800, // Move To VSR Word and Zero X-form (mtvsrwz XT,RA)
-		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
 	{MTVSRDD, 0xfc0007fe, 0x7c000366, 0x0, // Move To VSR Double Doubleword X-form (mtvsrdd XT,RA,RB)
 		[5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
 	{MTVSRWS, 0xfc0007fe, 0x7c000326, 0xf800, // Move To VSR Word & Splat X-form (mtvsrws XT,RA)