arm/armasm: Improve Plan 9 syntax decoding
The arm disassembler can not decode many instructions to
correct Plan 9 syntax.
This patch fixes 3 major issues.
1. Change memory addresses in PLD/PLI/SWP/STREX/LDREX to the correct
Plan 9 syntax (in accordance with MOVW/MOVB/MOVH). For example,
[rx] -> (Rx)
[rx, #imm] -> imm(Rx)
[rx, ry, lsl #imm] -> (Rx)(Ry<<imm)
2. Apply the Plan 9 syntax naming rule to more instructions. Such as,
VMRS -> MOVW
VMSR -> MOVW
XTB -> MOVBS
XTHU -> MOVHU
XTH -> MOVHS
XTBU -> MOVBU
3. Improve FP instructions decoding.
3.1 instruction name: VADD.F32 -> ADDF, VSUB.F64 -> SUBD, ...
3.2 register name: S0 -> F0, D0 -> F0, S2 -> F1, D1 -> F1, ...
Many test cases are also changed.
Change-Id: I5f8ac0e82c6edec2f4bdc4db58f6bcbab40d299a
Reviewed-on: https://go-review.googlesource.com/85455
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
7d04a2ea6b