chacha20: extend ppc64le support to ppc64
This requires fixing an incorrect save of the counter. It is a word value. It happens to work on LE because length is limited to u32. Refactor the constant table to load correctly independent of byte ordering. Add byte order swapping where output needs converted to LE ordering for storage. Change-Id: Ic7e09bd1c769bb77dd6e817f5a8639ba765f4c0f Reviewed-on: https://go-review.googlesource.com/c/crypto/+/614297 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Archana Ravindar <aravinda@redhat.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
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Родитель
6c21748958
Коммит
b61b08db44
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@ -2,7 +2,7 @@
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// Use of this source code is governed by a BSD-style
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// license that can be found in the LICENSE file.
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//go:build (!arm64 && !s390x && !ppc64le) || !gc || purego
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//go:build (!arm64 && !s390x && !ppc64 && !ppc64le) || !gc || purego
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package chacha20
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package chacha20
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@ -2,7 +2,7 @@
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// Use of this source code is governed by a BSD-style
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// license that can be found in the LICENSE file.
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//go:build gc && !purego
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//go:build gc && !purego && (ppc64 || ppc64le)
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package chacha20
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package chacha20
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@ -19,7 +19,7 @@
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// The differences in this and the original implementation are
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// The differences in this and the original implementation are
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// due to the calling conventions and initialization of constants.
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// due to the calling conventions and initialization of constants.
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//go:build gc && !purego
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//go:build gc && !purego && (ppc64 || ppc64le)
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#include "textflag.h"
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#include "textflag.h"
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@ -36,32 +36,68 @@
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// for VPERMXOR
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// for VPERMXOR
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#define MASK R18
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#define MASK R18
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DATA consts<>+0x00(SB)/8, $0x3320646e61707865
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DATA consts<>+0x00(SB)/4, $0x61707865
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DATA consts<>+0x08(SB)/8, $0x6b20657479622d32
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DATA consts<>+0x04(SB)/4, $0x3320646e
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DATA consts<>+0x10(SB)/8, $0x0000000000000001
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DATA consts<>+0x08(SB)/4, $0x79622d32
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DATA consts<>+0x18(SB)/8, $0x0000000000000000
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DATA consts<>+0x0c(SB)/4, $0x6b206574
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DATA consts<>+0x20(SB)/8, $0x0000000000000004
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DATA consts<>+0x10(SB)/4, $0x00000001
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DATA consts<>+0x28(SB)/8, $0x0000000000000000
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DATA consts<>+0x14(SB)/4, $0x00000000
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DATA consts<>+0x30(SB)/8, $0x0a0b08090e0f0c0d
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DATA consts<>+0x18(SB)/4, $0x00000000
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DATA consts<>+0x38(SB)/8, $0x0203000106070405
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DATA consts<>+0x1c(SB)/4, $0x00000000
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DATA consts<>+0x40(SB)/8, $0x090a0b080d0e0f0c
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DATA consts<>+0x20(SB)/4, $0x00000004
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DATA consts<>+0x48(SB)/8, $0x0102030005060704
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DATA consts<>+0x24(SB)/4, $0x00000000
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DATA consts<>+0x50(SB)/8, $0x6170786561707865
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DATA consts<>+0x28(SB)/4, $0x00000000
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DATA consts<>+0x58(SB)/8, $0x6170786561707865
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DATA consts<>+0x2c(SB)/4, $0x00000000
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DATA consts<>+0x60(SB)/8, $0x3320646e3320646e
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DATA consts<>+0x30(SB)/4, $0x0e0f0c0d
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DATA consts<>+0x68(SB)/8, $0x3320646e3320646e
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DATA consts<>+0x34(SB)/4, $0x0a0b0809
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DATA consts<>+0x70(SB)/8, $0x79622d3279622d32
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DATA consts<>+0x38(SB)/4, $0x06070405
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DATA consts<>+0x78(SB)/8, $0x79622d3279622d32
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DATA consts<>+0x3c(SB)/4, $0x02030001
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DATA consts<>+0x80(SB)/8, $0x6b2065746b206574
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DATA consts<>+0x40(SB)/4, $0x0d0e0f0c
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DATA consts<>+0x88(SB)/8, $0x6b2065746b206574
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DATA consts<>+0x44(SB)/4, $0x090a0b08
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DATA consts<>+0x90(SB)/8, $0x0000000100000000
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DATA consts<>+0x48(SB)/4, $0x05060704
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DATA consts<>+0x98(SB)/8, $0x0000000300000002
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DATA consts<>+0x4c(SB)/4, $0x01020300
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DATA consts<>+0xa0(SB)/8, $0x5566774411223300
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DATA consts<>+0x50(SB)/4, $0x61707865
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DATA consts<>+0xa8(SB)/8, $0xddeeffcc99aabb88
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DATA consts<>+0x54(SB)/4, $0x61707865
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DATA consts<>+0xb0(SB)/8, $0x6677445522330011
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DATA consts<>+0x58(SB)/4, $0x61707865
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DATA consts<>+0xb8(SB)/8, $0xeeffccddaabb8899
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DATA consts<>+0x5c(SB)/4, $0x61707865
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DATA consts<>+0x60(SB)/4, $0x3320646e
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DATA consts<>+0x64(SB)/4, $0x3320646e
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DATA consts<>+0x68(SB)/4, $0x3320646e
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DATA consts<>+0x6c(SB)/4, $0x3320646e
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DATA consts<>+0x70(SB)/4, $0x79622d32
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DATA consts<>+0x74(SB)/4, $0x79622d32
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DATA consts<>+0x78(SB)/4, $0x79622d32
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DATA consts<>+0x7c(SB)/4, $0x79622d32
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DATA consts<>+0x80(SB)/4, $0x6b206574
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DATA consts<>+0x84(SB)/4, $0x6b206574
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DATA consts<>+0x88(SB)/4, $0x6b206574
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DATA consts<>+0x8c(SB)/4, $0x6b206574
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DATA consts<>+0x90(SB)/4, $0x00000000
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DATA consts<>+0x94(SB)/4, $0x00000001
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DATA consts<>+0x98(SB)/4, $0x00000002
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DATA consts<>+0x9c(SB)/4, $0x00000003
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DATA consts<>+0xa0(SB)/4, $0x11223300
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DATA consts<>+0xa4(SB)/4, $0x55667744
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DATA consts<>+0xa8(SB)/4, $0x99aabb88
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DATA consts<>+0xac(SB)/4, $0xddeeffcc
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DATA consts<>+0xb0(SB)/4, $0x22330011
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DATA consts<>+0xb4(SB)/4, $0x66774455
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DATA consts<>+0xb8(SB)/4, $0xaabb8899
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DATA consts<>+0xbc(SB)/4, $0xeeffccdd
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GLOBL consts<>(SB), RODATA, $0xc0
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GLOBL consts<>(SB), RODATA, $0xc0
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#ifdef GOARCH_ppc64
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#define BE_XXBRW_INIT() \
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LVSL (R0)(R0), V24 \
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VSPLTISB $3, V25 \
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VXOR V24, V25, V24 \
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#define BE_XXBRW(vr) VPERM vr, vr, V24, vr
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#else
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#define BE_XXBRW_INIT()
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#define BE_XXBRW(vr)
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#endif
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//func chaCha20_ctr32_vsx(out, inp *byte, len int, key *[8]uint32, counter *uint32)
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//func chaCha20_ctr32_vsx(out, inp *byte, len int, key *[8]uint32, counter *uint32)
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TEXT ·chaCha20_ctr32_vsx(SB),NOSPLIT,$64-40
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TEXT ·chaCha20_ctr32_vsx(SB),NOSPLIT,$64-40
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MOVD out+0(FP), OUT
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MOVD out+0(FP), OUT
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@ -94,6 +130,8 @@ TEXT ·chaCha20_ctr32_vsx(SB),NOSPLIT,$64-40
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// Clear V27
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// Clear V27
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VXOR V27, V27, V27
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VXOR V27, V27, V27
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BE_XXBRW_INIT()
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// V28
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// V28
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LXVW4X (CONSTBASE)(R11), VS60
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LXVW4X (CONSTBASE)(R11), VS60
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@ -299,6 +337,11 @@ loop_vsx:
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VADDUWM V8, V18, V8
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VADDUWM V8, V18, V8
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VADDUWM V12, V19, V12
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VADDUWM V12, V19, V12
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BE_XXBRW(V0)
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BE_XXBRW(V4)
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BE_XXBRW(V8)
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BE_XXBRW(V12)
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CMPU LEN, $64
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CMPU LEN, $64
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BLT tail_vsx
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BLT tail_vsx
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@ -327,6 +370,11 @@ loop_vsx:
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VADDUWM V9, V18, V8
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VADDUWM V9, V18, V8
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VADDUWM V13, V19, V12
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VADDUWM V13, V19, V12
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BE_XXBRW(V0)
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BE_XXBRW(V4)
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BE_XXBRW(V8)
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BE_XXBRW(V12)
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CMPU LEN, $64
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CMPU LEN, $64
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BLT tail_vsx
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BLT tail_vsx
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LXVW4X (INP)(R8), VS60
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LXVW4X (INP)(R8), VS60
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LXVW4X (INP)(R9), VS61
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LXVW4X (INP)(R9), VS61
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LXVW4X (INP)(R10), VS62
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LXVW4X (INP)(R10), VS62
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VXOR V27, V0, V27
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VXOR V27, V0, V27
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VXOR V28, V4, V28
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VXOR V28, V4, V28
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VXOR V29, V8, V29
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VXOR V29, V8, V29
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VXOR V30, V12, V30
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VXOR V30, V12, V30
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VADDUWM V10, V18, V8
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VADDUWM V10, V18, V8
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VADDUWM V14, V19, V12
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VADDUWM V14, V19, V12
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BE_XXBRW(V0)
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BE_XXBRW(V4)
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BE_XXBRW(V8)
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BE_XXBRW(V12)
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CMPU LEN, $64
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CMPU LEN, $64
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BLT tail_vsx
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BLT tail_vsx
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VADDUWM V11, V18, V8
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VADDUWM V11, V18, V8
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VADDUWM V15, V19, V12
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VADDUWM V15, V19, V12
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BE_XXBRW(V0)
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BE_XXBRW(V4)
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BE_XXBRW(V8)
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BE_XXBRW(V12)
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CMPU LEN, $64
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CMPU LEN, $64
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BLT tail_vsx
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BLT tail_vsx
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done_vsx:
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done_vsx:
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// Increment counter by number of 64 byte blocks
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// Increment counter by number of 64 byte blocks
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MOVD (CNT), R14
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MOVWZ (CNT), R14
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ADD BLOCKS, R14
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ADD BLOCKS, R14
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MOVD R14, (CNT)
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MOVWZ R14, (CNT)
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RET
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RET
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tail_vsx:
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tail_vsx:
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