93 строки
4.3 KiB
Diff
93 строки
4.3 KiB
Diff
From 1c4b8fb30aa4262238260b5eedd33aa4a33423c8 Mon Sep 17 00:00:00 2001
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From: Vlad Buslov <vladbu@nvidia.com>
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Date: Thu, 26 May 2022 19:42:04 +0300
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Subject: [PATCH 1/9] net/mlx5: Bridge, refactor groups sizes and indices
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Following patches in the series introduce additional flow groups for QinQ
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support. With increased number of groups it becomes cumbersome to calculate
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groups sizes as fractions of the table size. Instead, manually define sizes
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of specific group types and ensure that totals are still correct by static
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assertions. Having specific table size is important for firmware resource
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management.
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This commit doesn't change functionality.
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Signed-off-by: Vlad Buslov <vladbu@nvidia.com>
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Reviewed-by: Roi Dayan <roid@nvidia.com>
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Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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Change-Id: I20a472caa0f8e93da4b215891c855e79e2af4032
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---
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.../ethernet/mellanox/mlx5/core/esw/bridge.c | 41 +++++++++++++------
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1 file changed, 29 insertions(+), 12 deletions(-)
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diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/bridge.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/bridge.c
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index 05e08cec5a8c..6547b848242a 100644
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--- a/drivers/net/ethernet/mellanox/mlx5/core/esw/bridge.c
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+++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/bridge.c
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@@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
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/* Copyright (c) 2021 Mellanox Technologies. */
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+#include <linux/build_bug.h>
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#include <linux/list.h>
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#include <linux/notifier.h>
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#include <net/netevent.h>
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@@ -12,26 +13,42 @@
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#define CREATE_TRACE_POINTS
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#include "diag/bridge_tracepoint.h"
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-#define MLX5_ESW_BRIDGE_INGRESS_TABLE_SIZE 64000
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+#define MLX5_ESW_BRIDGE_INGRESS_TABLE_VLAN_GRP_SIZE 16000
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+#define MLX5_ESW_BRIDGE_INGRESS_TABLE_UNTAGGED_GRP_SIZE 32000
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#define MLX5_ESW_BRIDGE_INGRESS_TABLE_VLAN_GRP_IDX_FROM 0
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-#define MLX5_ESW_BRIDGE_INGRESS_TABLE_VLAN_GRP_IDX_TO (MLX5_ESW_BRIDGE_INGRESS_TABLE_SIZE / 4 - 1)
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-#define MLX5_ESW_BRIDGE_INGRESS_TABLE_FILTER_GRP_IDX_FROM \
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+#define MLX5_ESW_BRIDGE_INGRESS_TABLE_VLAN_GRP_IDX_TO \
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+ (MLX5_ESW_BRIDGE_INGRESS_TABLE_VLAN_GRP_SIZE - 1)
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+#define MLX5_ESW_BRIDGE_INGRESS_TABLE_FILTER_GRP_IDX_FROM \
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(MLX5_ESW_BRIDGE_INGRESS_TABLE_VLAN_GRP_IDX_TO + 1)
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-#define MLX5_ESW_BRIDGE_INGRESS_TABLE_FILTER_GRP_IDX_TO \
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- (MLX5_ESW_BRIDGE_INGRESS_TABLE_SIZE / 2 - 1)
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-#define MLX5_ESW_BRIDGE_INGRESS_TABLE_MAC_GRP_IDX_FROM \
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+#define MLX5_ESW_BRIDGE_INGRESS_TABLE_FILTER_GRP_IDX_TO \
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+ (MLX5_ESW_BRIDGE_INGRESS_TABLE_FILTER_GRP_IDX_FROM + \
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+ MLX5_ESW_BRIDGE_INGRESS_TABLE_VLAN_GRP_SIZE - 1)
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+#define MLX5_ESW_BRIDGE_INGRESS_TABLE_MAC_GRP_IDX_FROM \
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(MLX5_ESW_BRIDGE_INGRESS_TABLE_FILTER_GRP_IDX_TO + 1)
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-#define MLX5_ESW_BRIDGE_INGRESS_TABLE_MAC_GRP_IDX_TO (MLX5_ESW_BRIDGE_INGRESS_TABLE_SIZE - 1)
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-
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-#define MLX5_ESW_BRIDGE_EGRESS_TABLE_SIZE 64000
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+#define MLX5_ESW_BRIDGE_INGRESS_TABLE_MAC_GRP_IDX_TO \
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+ (MLX5_ESW_BRIDGE_INGRESS_TABLE_MAC_GRP_IDX_FROM + \
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+ MLX5_ESW_BRIDGE_INGRESS_TABLE_UNTAGGED_GRP_SIZE - 1)
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+#define MLX5_ESW_BRIDGE_INGRESS_TABLE_SIZE \
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+ (MLX5_ESW_BRIDGE_INGRESS_TABLE_MAC_GRP_IDX_TO + 1)
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+static_assert(MLX5_ESW_BRIDGE_INGRESS_TABLE_SIZE == 64000);
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+
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+#define MLX5_ESW_BRIDGE_EGRESS_TABLE_VLAN_GRP_SIZE 32000
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+#define MLX5_ESW_BRIDGE_EGRESS_TABLE_MAC_GRP_SIZE (32000 - 1)
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#define MLX5_ESW_BRIDGE_EGRESS_TABLE_VLAN_GRP_IDX_FROM 0
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-#define MLX5_ESW_BRIDGE_EGRESS_TABLE_VLAN_GRP_IDX_TO (MLX5_ESW_BRIDGE_EGRESS_TABLE_SIZE / 2 - 1)
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+#define MLX5_ESW_BRIDGE_EGRESS_TABLE_VLAN_GRP_IDX_TO \
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+ (MLX5_ESW_BRIDGE_EGRESS_TABLE_VLAN_GRP_SIZE - 1)
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#define MLX5_ESW_BRIDGE_EGRESS_TABLE_MAC_GRP_IDX_FROM \
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(MLX5_ESW_BRIDGE_EGRESS_TABLE_VLAN_GRP_IDX_TO + 1)
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-#define MLX5_ESW_BRIDGE_EGRESS_TABLE_MAC_GRP_IDX_TO (MLX5_ESW_BRIDGE_EGRESS_TABLE_SIZE - 2)
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+#define MLX5_ESW_BRIDGE_EGRESS_TABLE_MAC_GRP_IDX_TO \
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+ (MLX5_ESW_BRIDGE_EGRESS_TABLE_MAC_GRP_IDX_FROM + \
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+ MLX5_ESW_BRIDGE_EGRESS_TABLE_MAC_GRP_SIZE - 1)
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#define MLX5_ESW_BRIDGE_EGRESS_TABLE_MISS_GRP_IDX_FROM \
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(MLX5_ESW_BRIDGE_EGRESS_TABLE_MAC_GRP_IDX_TO + 1)
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-#define MLX5_ESW_BRIDGE_EGRESS_TABLE_MISS_GRP_IDX_TO (MLX5_ESW_BRIDGE_EGRESS_TABLE_SIZE - 1)
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+#define MLX5_ESW_BRIDGE_EGRESS_TABLE_MISS_GRP_IDX_TO \
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+ MLX5_ESW_BRIDGE_EGRESS_TABLE_MISS_GRP_IDX_FROM
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+#define MLX5_ESW_BRIDGE_EGRESS_TABLE_SIZE \
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+ (MLX5_ESW_BRIDGE_EGRESS_TABLE_MISS_GRP_IDX_TO + 1)
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+static_assert(MLX5_ESW_BRIDGE_EGRESS_TABLE_SIZE == 64000);
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#define MLX5_ESW_BRIDGE_SKIP_TABLE_SIZE 0
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--
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2.21.3
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