214 строки
7.1 KiB
Diff
214 строки
7.1 KiB
Diff
From 51d89fa01da8a845bd3705ce1bdb918e62cdc9f1 Mon Sep 17 00:00:00 2001
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From: Maor Gottlieb <maorg@nvidia.com>
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Date: Tue, 13 Jul 2021 15:30:45 +0300
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Subject: [PATCH 07/22] net/mlx5: Lag, set match mask according to the traffic
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type bitmap
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Set the related bits in the match definer mask according to the
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TT mapping.
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This mask will be used to create the match definers.
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Signed-off-by: Maor Gottlieb <maorg@nvidia.com>
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Reviewed-by: Mark Bloch <mbloch@nvidia.com>
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Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
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---
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.../mellanox/mlx5/core/lag/port_sel.c | 182 ++++++++++++++++++
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1 file changed, 182 insertions(+)
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diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c
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index 7b4ad49c8438..6095f1049bdb 100644
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--- a/drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c
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+++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c
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@@ -4,6 +4,188 @@
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#include <linux/netdevice.h>
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#include "lag.h"
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+static int mlx5_lag_set_definer_inner(u32 *match_definer_mask,
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+ enum mlx5_traffic_types tt)
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+{
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+ int format_id;
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+ u8 *ipv6;
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+
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+ switch (tt) {
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+ case MLX5_TT_IPV4_UDP:
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+ case MLX5_TT_IPV4_TCP:
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+ format_id = 23;
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+ MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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+ inner_l4_sport);
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+ MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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+ inner_l4_dport);
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+ MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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+ inner_ip_src_addr);
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+ MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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+ inner_ip_dest_addr);
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+ break;
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+ case MLX5_TT_IPV4:
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+ format_id = 23;
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+ MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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+ inner_l3_type);
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+ MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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+ inner_dmac_47_16);
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+ MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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+ inner_dmac_15_0);
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+ MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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+ inner_smac_47_16);
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+ MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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+ inner_smac_15_0);
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+ MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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+ inner_ip_src_addr);
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+ MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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+ inner_ip_dest_addr);
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+ break;
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+ case MLX5_TT_IPV6_TCP:
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+ case MLX5_TT_IPV6_UDP:
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+ format_id = 31;
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+ MLX5_SET_TO_ONES(match_definer_format_31, match_definer_mask,
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+ inner_l4_sport);
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+ MLX5_SET_TO_ONES(match_definer_format_31, match_definer_mask,
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+ inner_l4_dport);
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+ ipv6 = MLX5_ADDR_OF(match_definer_format_31, match_definer_mask,
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+ inner_ip_dest_addr);
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+ memset(ipv6, 0xff, 16);
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+ ipv6 = MLX5_ADDR_OF(match_definer_format_31, match_definer_mask,
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+ inner_ip_src_addr);
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+ memset(ipv6, 0xff, 16);
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+ break;
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+ case MLX5_TT_IPV6:
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+ format_id = 32;
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+ ipv6 = MLX5_ADDR_OF(match_definer_format_32, match_definer_mask,
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+ inner_ip_dest_addr);
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+ memset(ipv6, 0xff, 16);
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+ ipv6 = MLX5_ADDR_OF(match_definer_format_32, match_definer_mask,
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+ inner_ip_src_addr);
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+ memset(ipv6, 0xff, 16);
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+ MLX5_SET_TO_ONES(match_definer_format_32, match_definer_mask,
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+ inner_dmac_47_16);
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+ MLX5_SET_TO_ONES(match_definer_format_32, match_definer_mask,
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+ inner_dmac_15_0);
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+ MLX5_SET_TO_ONES(match_definer_format_32, match_definer_mask,
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+ inner_smac_47_16);
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+ MLX5_SET_TO_ONES(match_definer_format_32, match_definer_mask,
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+ inner_smac_15_0);
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+ break;
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+ default:
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+ format_id = 23;
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+ MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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+ inner_l3_type);
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+ MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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+ inner_dmac_47_16);
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+ MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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+ inner_dmac_15_0);
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+ MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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+ inner_smac_47_16);
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+ MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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+ inner_smac_15_0);
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+ break;
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+ }
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+
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+ return format_id;
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+}
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+
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+static int mlx5_lag_set_definer(u32 *match_definer_mask,
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+ enum mlx5_traffic_types tt, bool tunnel,
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+ enum netdev_lag_hash hash)
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+{
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+ int format_id;
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+ u8 *ipv6;
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+
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+ if (tunnel)
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+ return mlx5_lag_set_definer_inner(match_definer_mask, tt);
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+
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+ switch (tt) {
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+ case MLX5_TT_IPV4_UDP:
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+ case MLX5_TT_IPV4_TCP:
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+ format_id = 22;
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+ MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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+ outer_l4_sport);
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+ MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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+ outer_l4_dport);
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+ MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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+ outer_ip_src_addr);
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+ MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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+ outer_ip_dest_addr);
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+ break;
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+ case MLX5_TT_IPV4:
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+ format_id = 22;
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+ MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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+ outer_l3_type);
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+ MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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+ outer_dmac_47_16);
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+ MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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+ outer_dmac_15_0);
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+ MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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+ outer_smac_47_16);
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+ MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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+ outer_smac_15_0);
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+ MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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+ outer_ip_src_addr);
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+ MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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+ outer_ip_dest_addr);
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+ break;
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+ case MLX5_TT_IPV6_TCP:
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+ case MLX5_TT_IPV6_UDP:
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+ format_id = 29;
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+ MLX5_SET_TO_ONES(match_definer_format_29, match_definer_mask,
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+ outer_l4_sport);
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+ MLX5_SET_TO_ONES(match_definer_format_29, match_definer_mask,
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+ outer_l4_dport);
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+ ipv6 = MLX5_ADDR_OF(match_definer_format_29, match_definer_mask,
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+ outer_ip_dest_addr);
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+ memset(ipv6, 0xff, 16);
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+ ipv6 = MLX5_ADDR_OF(match_definer_format_29, match_definer_mask,
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+ outer_ip_src_addr);
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+ memset(ipv6, 0xff, 16);
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+ break;
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+ case MLX5_TT_IPV6:
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+ format_id = 30;
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+ ipv6 = MLX5_ADDR_OF(match_definer_format_30, match_definer_mask,
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+ outer_ip_dest_addr);
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+ memset(ipv6, 0xff, 16);
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+ ipv6 = MLX5_ADDR_OF(match_definer_format_30, match_definer_mask,
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+ outer_ip_src_addr);
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+ memset(ipv6, 0xff, 16);
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+ MLX5_SET_TO_ONES(match_definer_format_30, match_definer_mask,
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+ outer_dmac_47_16);
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+ MLX5_SET_TO_ONES(match_definer_format_30, match_definer_mask,
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+ outer_dmac_15_0);
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+ MLX5_SET_TO_ONES(match_definer_format_30, match_definer_mask,
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+ outer_smac_47_16);
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+ MLX5_SET_TO_ONES(match_definer_format_30, match_definer_mask,
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+ outer_smac_15_0);
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+ break;
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+ default:
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+ format_id = 0;
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+ MLX5_SET_TO_ONES(match_definer_format_0, match_definer_mask,
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+ outer_smac_47_16);
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+ MLX5_SET_TO_ONES(match_definer_format_0, match_definer_mask,
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+ outer_smac_15_0);
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+
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+ if (hash == NETDEV_LAG_HASH_VLAN_SRCMAC) {
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+ MLX5_SET_TO_ONES(match_definer_format_0,
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+ match_definer_mask,
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+ outer_first_vlan_vid);
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+ break;
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+ }
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+
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+ MLX5_SET_TO_ONES(match_definer_format_0, match_definer_mask,
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+ outer_ethertype);
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+ MLX5_SET_TO_ONES(match_definer_format_0, match_definer_mask,
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+ outer_dmac_47_16);
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+ MLX5_SET_TO_ONES(match_definer_format_0, match_definer_mask,
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+ outer_dmac_15_0);
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+ break;
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+ }
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+
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+ return format_id;
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+}
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+
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static void set_tt_map(struct mlx5_lag_port_sel *port_sel,
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enum netdev_lag_hash hash)
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{
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--
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2.25.1
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