enabling cross-compile of the cntk sources for arm64 devices.
This commit replaces implementations of functions based on sse with a non-sse version and updates the makefile such that SSE_FLAGS can be overriden when compiling for non-Intel architectures.
This commit is contained in:
Friedel van Megen
Родитель
279b25680c
Коммит
a183815dd1
9
Makefile
9
Makefile
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@ -67,13 +67,18 @@ endif
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# The mpic++ wrapper only adds MPI specific flags to the g++ command line.
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# The actual compiler/linker flags added can be viewed by running 'mpic++ --showme:compile' and 'mpic++ --showme:link'
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CXX = mpic++
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SSE_FLAGS = -msse4.1 -mssse3
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# Settings for ARM64 architectures that use a crosscompiler on a host machine.
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#CXX = aarch64-linux-gnu-g++
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#SSE_FLAGS =
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SOURCEDIR:= Source
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INCLUDEPATH:= $(addprefix $(SOURCEDIR)/, Common/Include CNTKv2LibraryDll CNTKv2LibraryDll/API Math CNTK ActionsLib ComputationNetworkLib SGDLib SequenceTrainingLib CNTK/BrainScript Readers/ReaderLib)
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# COMMON_FLAGS include settings that are passed both to NVCC and C++ compilers.
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COMMON_FLAGS:= -D_POSIX_SOURCE -D_XOPEN_SOURCE=600 -D__USE_XOPEN2K -std=c++11
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CPPFLAGS:=
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CXXFLAGS:= -msse4.1 -mssse3 -std=c++0x -fopenmp -fpermissive -fPIC -Werror -fcheck-new
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CPPFLAGS:=
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CXXFLAGS:= $(SSE_FLAGS) -std=c++0x -fopenmp -fpermissive -fPIC -Werror -fcheck-new
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LIBPATH:=
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LIBS:=
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LDFLAGS:=
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@ -11,7 +11,12 @@
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#include <intrin.h> // for intrinsics
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#endif
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#ifdef __unix__
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#if !defined(__aarch64__)
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#include <x86intrin.h>
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#else
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#define _mm_free(p) free(p)
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#define _mm_malloc(a, b) malloc(a)
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#endif
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#endif
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namespace msra { namespace math {
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@ -27,6 +32,155 @@ namespace msra { namespace math {
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// newer ones: (seems no single list available)
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// ===========================================================================
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// The code in this file implements a float4 vector based on the SSE intrinsics available on Intel platforms.
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// Since we don't have SSE on ARM64 (NEON has similar functionality but is not identical) we cannot
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// use the SSE implementation on ARM64.
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// TODO: In the future, we should provide a NEON based implementation instead.
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#if defined(__aarch64__)
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typedef struct __m128_t
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{
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float f[4];
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}__m128;
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static __m128 ZERO_M128 = {0,0,0,0};
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static __m128 _mm_setzero_ps()
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{
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return ZERO_M128;
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}
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static void _mm_store_ss(float *a, const __m128 &b)
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{
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*a = b.f[0];
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}
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static __m128 _mm_load1_ps(const float *a)
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{
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__m128 result = {(float)*a, (float)*a, (float)*a, (float)*a};
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return result;
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}
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static __m128 _mm_sub_ps(const __m128 &a, const __m128 &b)
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{
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__m128 result = {
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a.f[0] - b.f[0],
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a.f[1] - b.f[1],
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a.f[2] - b.f[2],
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a.f[3] - b.f[3] };
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return result;
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}
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static __m128 _mm_and_ps(const __m128 &a, const __m128 &b)
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{
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__m128 result = {
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(float)((int)(a.f[0]) & (int)(b.f[0])),
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(float)((int)(a.f[1]) & (int)(b.f[1])),
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(float)((int)(a.f[2]) & (int)(b.f[2])),
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(float)((int)(a.f[3]) & (int)(b.f[3])) };
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return result;
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}
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static __m128 _mm_or_ps(const __m128 &a, const __m128 &b)
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{
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__m128 result = {
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(float)((int)(a.f[0]) | (int)(b.f[0])),
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(float)((int)(a.f[1]) | (int)(b.f[1])),
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(float)((int)(a.f[2]) | (int)(b.f[2])),
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(float)((int)(a.f[3]) | (int)(b.f[3])) };
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return result;
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}
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static __m128 _mm_add_ps(const __m128 &a, const __m128 &b)
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{
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__m128 result = {
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a.f[0] + b.f[0],
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a.f[1] + b.f[1],
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a.f[2] + b.f[2],
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a.f[3] + b.f[3] };
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return result;
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}
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static __m128 _mm_mul_ps(const __m128 &a, const __m128 &b)
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{
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__m128 result = {
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a.f[0] * b.f[0],
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a.f[1] * b.f[1],
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a.f[2] * b.f[2],
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a.f[3] * b.f[3] };
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return result;
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}
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static __m128 _mm_div_ps(const __m128 &a, const __m128 &b)
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{
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__m128 result = {
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a.f[0] / b.f[0],
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a.f[1] / b.f[1],
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a.f[2] / b.f[2],
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a.f[3] / b.f[3] };
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return result;
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}
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static __m128 _mm_hadd_ps(const __m128 &a, const __m128 &b)
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{
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__m128 result = {
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a.f[0] + a.f[1],
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a.f[2] + a.f[3],
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b.f[0] + b.f[1],
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b.f[2] + b.f[3] };
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return result;
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}
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static __m128 _mm_cmpge_ps(const __m128 &a, const __m128 &b)
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{
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__m128 result = {
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a.f[0] >= b.f[0] ? 1.0f : 0.0f,
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a.f[1] >= b.f[1] ? 1.0f : 0.0f,
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a.f[2] >= b.f[2] ? 1.0f : 0.0f,
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a.f[3] >= b.f[3] ? 1.0f : 0.0f };
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return result;
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}
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static __m128 _mm_cmple_ps(const __m128 &a, const __m128 &b)
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{
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__m128 result = {
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a.f[0] <= b.f[0] ? 1.0f : 0.0f,
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a.f[1] <= b.f[1] ? 1.0f : 0.0f,
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a.f[2] <= b.f[2] ? 1.0f : 0.0f,
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a.f[3] <= b.f[3] ? 1.0f : 0.0f };
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return result;
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}
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#define _MM_TRANSPOSE4_PS( c1, c2, c3, c4 ) \
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{ \
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float4 t1, t2, t3, t4; \
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\
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t1.v.f[0] = c1.v.f[0]; \
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t1.v.f[1] = c2.v.f[0]; \
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t1.v.f[2] = c3.v.f[0]; \
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t1.v.f[3] = c4.v.f[0]; \
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\
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t2.v.f[0] = c1.v.f[1]; \
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t2.v.f[1] = c2.v.f[1]; \
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t2.v.f[2] = c3.v.f[1]; \
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t2.v.f[3] = c4.v.f[1]; \
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\
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t3.v.f[0] = c1.v.f[2]; \
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t3.v.f[1] = c2.v.f[2]; \
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t3.v.f[2] = c3.v.f[2]; \
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t3.v.f[3] = c4.v.f[2]; \
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\
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t4.v.f[0] = c1.v.f[3]; \
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t4.v.f[1] = c2.v.f[3]; \
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t4.v.f[2] = c3.v.f[3]; \
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t4.v.f[3] = c4.v.f[3]; \
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\
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c1 = t1; \
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c2 = t2; \
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c3 = t3; \
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c4 = t4; \
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}
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#define _mm_prefetch(a, b)
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#endif
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class float4
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{
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__m128 v; // value
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@ -3,6 +3,14 @@
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// Licensed under the MIT license. See LICENSE.md file in the project root for full licence information.
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//
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#include "stdafx.h"
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// This class implements a block handler based on the SSE intrinsics available on intel platforms.
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// Since we don't have SSE on ARM64 (NEON has similar functionality but is not identical) we cannot
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// use the BlockHandlerSSE implementation no ARM64.
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// Therefore, exclude the implementation on ARM64 builds for now.
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// TODO: In the future, we should provide a NEON based implementation instead.
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#if !defined(__aarch64__)
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#include <xmmintrin.h>
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#include <emmintrin.h>
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#include <tmmintrin.h>
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@ -30,3 +38,5 @@ int BlockHandlerSSE::RowToColOffsetRewrittenB(int col, int kOffset, int blockSiz
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}}}
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#endif
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