[spirv] Translate intrinsic msad4 function. (#808)
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Ehsan
GitHub
Родитель
9745b0d55c
Коммит
998bab9dea
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@ -256,6 +256,18 @@ public:
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/// is created; otherwise an OpMemoryBarrier is created.
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void createBarrier(uint32_t exec, uint32_t memory, uint32_t semantics);
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/// \brief Creates an OpBitFieldInsert SPIR-V instruction for the given
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/// arguments.
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uint32_t createBitFieldInsert(uint32_t resultType, uint32_t base,
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uint32_t insert, uint32_t offset,
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uint32_t count);
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/// \brief Creates an OpBitFieldUExtract or OpBitFieldSExtract SPIR-V
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/// instruction for the given arguments.
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uint32_t createBitFieldExtract(uint32_t resultType, uint32_t base,
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uint32_t offset, uint32_t count,
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bool isSigned);
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/// \brief Creates an OpEmitVertex instruction.
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void createEmitVertex();
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@ -563,6 +563,32 @@ void ModuleBuilder::createBarrier(uint32_t execution, uint32_t memory,
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insertPoint->appendInstruction(std::move(constructSite));
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}
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uint32_t ModuleBuilder::createBitFieldExtract(uint32_t resultType,
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uint32_t base, uint32_t offset,
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uint32_t count, bool isSigned) {
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assert(insertPoint && "null insert point");
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uint32_t resultId = theContext.takeNextId();
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if (isSigned)
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instBuilder.opBitFieldSExtract(resultType, resultId, base, offset, count);
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else
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instBuilder.opBitFieldUExtract(resultType, resultId, base, offset, count);
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instBuilder.x();
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insertPoint->appendInstruction(std::move(constructSite));
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return resultId;
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}
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uint32_t ModuleBuilder::createBitFieldInsert(uint32_t resultType, uint32_t base,
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uint32_t insert, uint32_t offset,
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uint32_t count) {
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assert(insertPoint && "null insert point");
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uint32_t resultId = theContext.takeNextId();
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instBuilder
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.opBitFieldInsert(resultType, resultId, base, insert, offset, count)
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.x();
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insertPoint->appendInstruction(std::move(constructSite));
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return resultId;
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}
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void ModuleBuilder::createEmitVertex() {
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assert(insertPoint && "null insert point");
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instBuilder.opEmitVertex().x();
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@ -4317,6 +4317,9 @@ SpirvEvalInfo SPIRVEmitter::processIntrinsicCallExpr(const CallExpr *callExpr) {
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case hlsl::IntrinsicOp::IOP_modf:
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retVal = processIntrinsicModf(callExpr);
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break;
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case hlsl::IntrinsicOp::IOP_msad4:
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retVal = processIntrinsicMsad4(callExpr);
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break;
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case hlsl::IntrinsicOp::IOP_sign: {
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if (isFloatOrVecMatOfFloatType(callExpr->getArg(0)->getType()))
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retVal = processIntrinsicFloatSign(callExpr);
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@ -4547,6 +4550,170 @@ SPIRVEmitter::processIntrinsicInterlockedMethod(const CallExpr *expr,
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return 0;
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}
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uint32_t SPIRVEmitter::processIntrinsicMsad4(const CallExpr *callExpr) {
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emitWarning("msad4 intrinsic function is emulated using many SPIR-V "
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"instructions due to lack of direct SPIR-V equivalent",
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callExpr->getExprLoc());
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// Compares a 4-byte reference value and an 8-byte source value and
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// accumulates a vector of 4 sums. Each sum corresponds to the masked sum
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// of absolute differences of a different byte alignment between the
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// reference value and the source value.
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// If we have:
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// uint v0; // reference
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// uint2 v1; // source
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// uint4 v2; // accum
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// uint4 o0; // result of msad4
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// uint4 r0, t0; // temporary values
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//
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// Then msad4(v0, v1, v2) translates to the following SM5 assembly according
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// to fxc:
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// Step 1:
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// ushr r0.xyz, v1.xxxx, l(8, 16, 24, 0)
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// Step 2:
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// [result], [ width ], [ offset ], [ insert ], [ base ]
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// bfi t0.yzw, l(0, 8, 16, 24), l(0, 24, 16, 8), v1.yyyy , r0.xxyz
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// mov t0.x, v1.x
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// Step 3:
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// msad o0.xyzw, v0.xxxx, t0.xyzw, v2.xyzw
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const uint32_t glsl = theBuilder.getGLSLExtInstSet();
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const auto boolType = theBuilder.getBoolType();
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const auto intType = theBuilder.getInt32Type();
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const auto uintType = theBuilder.getUint32Type();
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const auto uint4Type = theBuilder.getVecType(uintType, 4);
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const uint32_t reference = doExpr(callExpr->getArg(0));
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const uint32_t source = doExpr(callExpr->getArg(1));
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const uint32_t accum = doExpr(callExpr->getArg(2));
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const auto uint0 = theBuilder.getConstantUint32(0);
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const auto uint8 = theBuilder.getConstantUint32(8);
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const auto uint16 = theBuilder.getConstantUint32(16);
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const auto uint24 = theBuilder.getConstantUint32(24);
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// Step 1.
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const uint32_t v1x = theBuilder.createCompositeExtract(uintType, source, {0});
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// r0.x = v1xS8 = v1.x shifted by 8 bits
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uint32_t v1xS8 = theBuilder.createBinaryOp(spv::Op::OpShiftLeftLogical,
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uintType, v1x, uint8);
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// r0.y = v1xS16 = v1.x shifted by 16 bits
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uint32_t v1xS16 = theBuilder.createBinaryOp(spv::Op::OpShiftLeftLogical,
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uintType, v1x, uint16);
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// r0.z = v1xS24 = v1.x shifted by 24 bits
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uint32_t v1xS24 = theBuilder.createBinaryOp(spv::Op::OpShiftLeftLogical,
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uintType, v1x, uint24);
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// Step 2.
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// Do bfi 3 times. DXIL bfi is equivalent to SPIR-V OpBitFieldInsert.
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const uint32_t v1y = theBuilder.createCompositeExtract(uintType, source, {1});
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// Note that t0.x = v1.x, nothing we need to do for that.
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const uint32_t t0y =
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theBuilder.createBitFieldInsert(uintType, /*base*/ v1xS8, /*insert*/ v1y,
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/*offset*/ uint24,
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/*width*/ uint8);
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const uint32_t t0z =
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theBuilder.createBitFieldInsert(uintType, /*base*/ v1xS16, /*insert*/ v1y,
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/*offset*/ uint16,
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/*width*/ uint16);
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const uint32_t t0w =
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theBuilder.createBitFieldInsert(uintType, /*base*/ v1xS24, /*insert*/ v1y,
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/*offset*/ uint8,
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/*width*/ uint24);
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// Step 3. MSAD (Masked Sum of Absolute Differences)
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// Now perform MSAD four times.
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// Need to mimic this algorithm in SPIR-V!
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//
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// UINT msad( UINT ref, UINT src, UINT accum )
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// {
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// for (UINT i = 0; i < 4; i++)
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// {
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// BYTE refByte, srcByte, absDiff;
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//
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// refByte = (BYTE)(ref >> (i * 8));
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// if (!refByte)
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// {
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// continue;
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// }
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//
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// srcByte = (BYTE)(src >> (i * 8));
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// if (refByte >= srcByte)
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// {
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// absDiff = refByte - srcByte;
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// }
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// else
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// {
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// absDiff = srcByte - refByte;
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// }
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//
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// // The recommended overflow behavior for MSAD is
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// // to do a 32-bit saturate. This is not
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// // required, however, and wrapping is allowed.
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// // So from an application point of view,
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// // overflow behavior is undefined.
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// if (UINT_MAX - accum < absDiff)
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// {
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// accum = UINT_MAX;
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// break;
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// }
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// accum += absDiff;
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// }
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//
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// return accum;
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// }
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llvm::SmallVector<uint32_t, 4> result;
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const uint32_t accum0 =
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theBuilder.createCompositeExtract(uintType, accum, {0});
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const uint32_t accum1 =
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theBuilder.createCompositeExtract(uintType, accum, {1});
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const uint32_t accum2 =
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theBuilder.createCompositeExtract(uintType, accum, {2});
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const uint32_t accum3 =
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theBuilder.createCompositeExtract(uintType, accum, {3});
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const llvm::SmallVector<uint32_t, 4> sources = {v1x, t0y, t0z, t0w};
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llvm::SmallVector<uint32_t, 4> accums = {accum0, accum1, accum2, accum3};
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llvm::SmallVector<uint32_t, 4> refBytes;
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llvm::SmallVector<uint32_t, 4> signedRefBytes;
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llvm::SmallVector<uint32_t, 4> isRefByteZero;
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for (uint32_t i = 0; i < 4; ++i) {
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refBytes.push_back(theBuilder.createBitFieldExtract(
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uintType, reference, /*offset*/ theBuilder.getConstantUint32(i * 8),
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/*count*/ uint8, /*isSigned*/ false));
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signedRefBytes.push_back(
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theBuilder.createUnaryOp(spv::Op::OpBitcast, intType, refBytes.back()));
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isRefByteZero.push_back(theBuilder.createBinaryOp(
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spv::Op::OpIEqual, boolType, refBytes.back(), uint0));
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}
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for (uint32_t msadNum = 0; msadNum < 4; ++msadNum) {
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for (uint32_t byteCount = 0; byteCount < 4; ++byteCount) {
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// 'count' is always 8 because we are extracting 8 bits out of 32.
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const uint32_t srcByte = theBuilder.createBitFieldExtract(
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uintType, sources[msadNum],
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/*offset*/ theBuilder.getConstantUint32(8 * byteCount),
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/*count*/ uint8, /*isSigned*/ false);
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const uint32_t signedSrcByte =
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theBuilder.createUnaryOp(spv::Op::OpBitcast, intType, srcByte);
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const uint32_t sub = theBuilder.createBinaryOp(
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spv::Op::OpISub, intType, signedRefBytes[byteCount], signedSrcByte);
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const uint32_t absSub = theBuilder.createExtInst(
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intType, glsl, GLSLstd450::GLSLstd450SAbs, {sub});
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const uint32_t diff = theBuilder.createSelect(
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uintType, isRefByteZero[byteCount], uint0,
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theBuilder.createUnaryOp(spv::Op::OpBitcast, uintType, absSub));
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// As pointed out by the DXIL reference above, it is *not* required to
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// saturate the output to UINT_MAX in case of overflow. Wrapping around is
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// also allowed. For simplicity, we will wrap around at this point.
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accums[msadNum] = theBuilder.createBinaryOp(spv::Op::OpIAdd, uintType,
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accums[msadNum], diff);
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}
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}
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return theBuilder.createCompositeConstruct(uint4Type, accums);
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}
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uint32_t SPIRVEmitter::processIntrinsicModf(const CallExpr *callExpr) {
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// Signature is: ret modf(x, ip)
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// [in] x: the input floating-point value.
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@ -290,6 +290,9 @@ private:
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/// Processes the 'modf' intrinsic function.
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uint32_t processIntrinsicModf(const CallExpr *);
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/// Processes the 'msad4' intrinsic function.
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uint32_t processIntrinsicMsad4(const CallExpr *);
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/// Processes the 'mul' intrinsic function.
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uint32_t processIntrinsicMul(const CallExpr *);
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@ -0,0 +1,190 @@
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// Run: %dxc -T vs_6_0 -E main
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// CHECK: [[glsl:%\d+]] = OpExtInstImport "GLSL.std.450"
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uint4 main(uint reference : REF, uint2 source :SOURCE, uint4 accum : ACCUM) : MSAD_RESULT
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{
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// CHECK: [[ref:%\d+]] = OpLoad %uint %reference
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// CHECK-NEXT: [[src:%\d+]] = OpLoad %v2uint %source
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// CHECK-NEXT: [[accum:%\d+]] = OpLoad %v4uint %accum
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// CHECK-NEXT: [[src0:%\d+]] = OpCompositeExtract %uint [[src]] 0
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// CHECK-NEXT: [[src0s8:%\d+]] = OpShiftLeftLogical %uint [[src0]] %uint_8
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// CHECK-NEXT: [[src0s16:%\d+]] = OpShiftLeftLogical %uint [[src0]] %uint_16
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// CHECK-NEXT: [[src0s24:%\d+]] = OpShiftLeftLogical %uint [[src0]] %uint_24
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// CHECK-NEXT: [[src1:%\d+]] = OpCompositeExtract %uint [[src]] 1
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// CHECK-NEXT: [[bfi0:%\d+]] = OpBitFieldInsert %uint [[src0s8]] [[src1]] %uint_24 %uint_8
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// CHECK-NEXT: [[bfi1:%\d+]] = OpBitFieldInsert %uint [[src0s16]] [[src1]] %uint_16 %uint_16
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// CHECK-NEXT: [[bfi2:%\d+]] = OpBitFieldInsert %uint [[src0s24]] [[src1]] %uint_8 %uint_24
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// CHECK-NEXT: [[accum0:%\d+]] = OpCompositeExtract %uint [[accum]] 0
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// CHECK-NEXT: [[accum1:%\d+]] = OpCompositeExtract %uint [[accum]] 1
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// CHECK-NEXT: [[accum2:%\d+]] = OpCompositeExtract %uint [[accum]] 2
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// CHECK-NEXT: [[accum3:%\d+]] = OpCompositeExtract %uint [[accum]] 3
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// Now perforoming MSAD four times
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// CHECK-NEXT: [[refByte0:%\d+]] = OpBitFieldUExtract %uint [[ref]] %uint_0 %uint_8
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// CHECK-NEXT: [[intRefByte0:%\d+]] = OpBitcast %int [[refByte0]]
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// CHECK-NEXT: [[isRefByte0Zero:%\d+]] = OpIEqual %bool [[refByte0]] %uint_0
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// CHECK-NEXT: [[refByte1:%\d+]] = OpBitFieldUExtract %uint [[ref]] %uint_8 %uint_8
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// CHECK-NEXT: [[intRefByte1:%\d+]] = OpBitcast %int [[refByte1]]
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// CHECK-NEXT: [[isRefByte1Zero:%\d+]] = OpIEqual %bool [[refByte1]] %uint_0
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// CHECK-NEXT: [[refByte2:%\d+]] = OpBitFieldUExtract %uint [[ref]] %uint_16 %uint_8
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// CHECK-NEXT: [[intRefByte2:%\d+]] = OpBitcast %int [[refByte2]]
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// CHECK-NEXT: [[isRefByte2Zero:%\d+]] = OpIEqual %bool [[refByte2]] %uint_0
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// CHECK-NEXT: [[refByte3:%\d+]] = OpBitFieldUExtract %uint [[ref]] %uint_24 %uint_8
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// CHECK-NEXT: [[intRefByte3:%\d+]] = OpBitcast %int [[refByte3]]
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// CHECK-NEXT: [[isRefByte3Zero:%\d+]] = OpIEqual %bool [[refByte3]] %uint_0
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// MSAD 0 Byte 0
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// CHECK-NEXT: [[src0Byte0:%\d+]] = OpBitFieldUExtract %uint [[src0]] %uint_0 %uint_8
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// CHECK-NEXT: [[intSrc0Byte0:%\d+]] = OpBitcast %int [[src0Byte0]]
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// CHECK-NEXT: [[sub0:%\d+]] = OpISub %int [[intRefByte0]] [[intSrc0Byte0]]
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// CHECK-NEXT: [[absSub0:%\d+]] = OpExtInst %int [[glsl]] SAbs [[sub0]]
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// CHECK-NEXT: [[uintAbsSub0:%\d+]] = OpBitcast %uint [[absSub0]]
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// CHECK-NEXT: [[diff0:%\d+]] = OpSelect %uint [[isRefByte0Zero]] %uint_0 [[uintAbsSub0]]
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// CHECK-NEXT: [[accum0PlusDiff0:%\d+]] = OpIAdd %uint [[accum0]] [[diff0]]
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// MSAD 0 Byte 1
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// CHECK-NEXT: [[src0Byte1:%\d+]] = OpBitFieldUExtract %uint [[src0]] %uint_8 %uint_8
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// CHECK-NEXT: [[intSrc0Byte1:%\d+]] = OpBitcast %int [[src0Byte1]]
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// CHECK-NEXT: [[sub1:%\d+]] = OpISub %int [[intRefByte1]] [[intSrc0Byte1]]
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// CHECK-NEXT: [[absSub1:%\d+]] = OpExtInst %int [[glsl]] SAbs [[sub1]]
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// CHECK-NEXT: [[uintAbsSub1:%\d+]] = OpBitcast %uint [[absSub1]]
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// CHECK-NEXT: [[diff1:%\d+]] = OpSelect %uint [[isRefByte1Zero]] %uint_0 [[uintAbsSub1]]
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// CHECK-NEXT: [[accum0PlusDiff01:%\d+]] = OpIAdd %uint [[accum0PlusDiff0]] [[diff1]]
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// MSAD 0 Byte 2
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// CHECK-NEXT: [[src0Byte2:%\d+]] = OpBitFieldUExtract %uint [[src0]] %uint_16 %uint_8
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// CHECK-NEXT: [[intSrc0Byte2:%\d+]] = OpBitcast %int [[src0Byte2]]
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// CHECK-NEXT: [[sub2:%\d+]] = OpISub %int [[intRefByte2]] [[intSrc0Byte2]]
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// CHECK-NEXT: [[absSub2:%\d+]] = OpExtInst %int [[glsl]] SAbs [[sub2]]
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// CHECK-NEXT: [[uintAbsSub2:%\d+]] = OpBitcast %uint [[absSub2]]
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// CHECK-NEXT: [[diff2:%\d+]] = OpSelect %uint [[isRefByte2Zero]] %uint_0 [[uintAbsSub2]]
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// CHECK-NEXT: [[accum0PlusDiff012:%\d+]] = OpIAdd %uint [[accum0PlusDiff01]] [[diff2]]
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// MSAD 0 Byte 3
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// CHECK-NEXT: [[src0Byte3:%\d+]] = OpBitFieldUExtract %uint [[src0]] %uint_24 %uint_8
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// CHECK-NEXT: [[intSrc0Byte3:%\d+]] = OpBitcast %int [[src0Byte3]]
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// CHECK-NEXT: [[sub3:%\d+]] = OpISub %int [[intRefByte3]] [[intSrc0Byte3]]
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// CHECK-NEXT: [[absSub3:%\d+]] = OpExtInst %int [[glsl]] SAbs [[sub3]]
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// CHECK-NEXT: [[uintAbsSub3:%\d+]] = OpBitcast %uint [[absSub3]]
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// CHECK-NEXT: [[diff3:%\d+]] = OpSelect %uint [[isRefByte3Zero]] %uint_0 [[uintAbsSub3]]
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// CHECK-NEXT: [[accum0PlusDiff0123:%\d+]] = OpIAdd %uint [[accum0PlusDiff012]] [[diff3]]
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// MSAD 1 Byte 0
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// CHECK-NEXT: [[src1Byte0:%\d+]] = OpBitFieldUExtract %uint [[bfi0]] %uint_0 %uint_8
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// CHECK-NEXT: [[intSrc1Byte0:%\d+]] = OpBitcast %int [[src1Byte0]]
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// CHECK-NEXT: [[sub0:%\d+]] = OpISub %int [[intRefByte0]] [[intSrc1Byte0]]
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// CHECK-NEXT: [[absSub0:%\d+]] = OpExtInst %int [[glsl]] SAbs [[sub0]]
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// CHECK-NEXT: [[uintAbsSub0:%\d+]] = OpBitcast %uint [[absSub0]]
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// CHECK-NEXT: [[diff0:%\d+]] = OpSelect %uint [[isRefByte0Zero]] %uint_0 [[uintAbsSub0]]
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// CHECK-NEXT: [[accum1PlusDiff0:%\d+]] = OpIAdd %uint [[accum1]] [[diff0]]
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// MSAD 1 Byte 1
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// CHECK-NEXT: [[src1Byte1:%\d+]] = OpBitFieldUExtract %uint [[bfi0]] %uint_8 %uint_8
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// CHECK-NEXT: [[intSrc1Byte1:%\d+]] = OpBitcast %int [[src1Byte1]]
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// CHECK-NEXT: [[sub1:%\d+]] = OpISub %int [[intRefByte1]] [[intSrc1Byte1]]
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// CHECK-NEXT: [[absSub1:%\d+]] = OpExtInst %int [[glsl]] SAbs [[sub1]]
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// CHECK-NEXT: [[uintAbsSub1:%\d+]] = OpBitcast %uint [[absSub1]]
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// CHECK-NEXT: [[diff1:%\d+]] = OpSelect %uint [[isRefByte1Zero]] %uint_0 [[uintAbsSub1]]
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// CHECK-NEXT: [[accum1PlusDiff01:%\d+]] = OpIAdd %uint [[accum1PlusDiff0]] [[diff1]]
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// MSAD 1 Byte 2
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// CHECK-NEXT: [[src1Byte2:%\d+]] = OpBitFieldUExtract %uint [[bfi0]] %uint_16 %uint_8
|
||||
// CHECK-NEXT: [[intSrc1Byte2:%\d+]] = OpBitcast %int [[src1Byte2]]
|
||||
// CHECK-NEXT: [[sub2:%\d+]] = OpISub %int [[intRefByte2]] [[intSrc1Byte2]]
|
||||
// CHECK-NEXT: [[absSub2:%\d+]] = OpExtInst %int [[glsl]] SAbs [[sub2]]
|
||||
// CHECK-NEXT: [[uintAbsSub2:%\d+]] = OpBitcast %uint [[absSub2]]
|
||||
// CHECK-NEXT: [[diff2:%\d+]] = OpSelect %uint [[isRefByte2Zero]] %uint_0 [[uintAbsSub2]]
|
||||
// CHECK-NEXT: [[accum1PlusDiff012:%\d+]] = OpIAdd %uint [[accum1PlusDiff01]] [[diff2]]
|
||||
|
||||
// MSAD 1 Byte 3
|
||||
// CHECK-NEXT: [[src1Byte3:%\d+]] = OpBitFieldUExtract %uint [[bfi0]] %uint_24 %uint_8
|
||||
// CHECK-NEXT: [[intSrc1Byte3:%\d+]] = OpBitcast %int [[src1Byte3]]
|
||||
// CHECK-NEXT: [[sub3:%\d+]] = OpISub %int [[intRefByte3]] [[intSrc1Byte3]]
|
||||
// CHECK-NEXT: [[absSub3:%\d+]] = OpExtInst %int [[glsl]] SAbs [[sub3]]
|
||||
// CHECK-NEXT: [[uintAbsSub3:%\d+]] = OpBitcast %uint [[absSub3]]
|
||||
// CHECK-NEXT: [[diff3:%\d+]] = OpSelect %uint [[isRefByte3Zero]] %uint_0 [[uintAbsSub3]]
|
||||
// CHECK-NEXT: [[accum1PlusDiff0123:%\d+]] = OpIAdd %uint [[accum1PlusDiff012]] [[diff3]]
|
||||
|
||||
|
||||
// MSAD 2 Byte 0
|
||||
// CHECK-NEXT: [[src2Byte0:%\d+]] = OpBitFieldUExtract %uint [[bfi1]] %uint_0 %uint_8
|
||||
// CHECK-NEXT: [[intSrc2Byte0:%\d+]] = OpBitcast %int [[src2Byte0]]
|
||||
// CHECK-NEXT: [[sub0:%\d+]] = OpISub %int [[intRefByte0]] [[intSrc2Byte0]]
|
||||
// CHECK-NEXT: [[absSub0:%\d+]] = OpExtInst %int [[glsl]] SAbs [[sub0]]
|
||||
// CHECK-NEXT: [[uintAbsSub0:%\d+]] = OpBitcast %uint [[absSub0]]
|
||||
// CHECK-NEXT: [[diff0:%\d+]] = OpSelect %uint [[isRefByte0Zero]] %uint_0 [[uintAbsSub0]]
|
||||
// CHECK-NEXT: [[accum2PlusDiff0:%\d+]] = OpIAdd %uint [[accum2]] [[diff0]]
|
||||
|
||||
// MSAD 2 Byte 1
|
||||
// CHECK-NEXT: [[src2Byte1:%\d+]] = OpBitFieldUExtract %uint [[bfi1]] %uint_8 %uint_8
|
||||
// CHECK-NEXT: [[intSrc2Byte1:%\d+]] = OpBitcast %int [[src2Byte1]]
|
||||
// CHECK-NEXT: [[sub1:%\d+]] = OpISub %int [[intRefByte1]] [[intSrc2Byte1]]
|
||||
// CHECK-NEXT: [[absSub1:%\d+]] = OpExtInst %int [[glsl]] SAbs [[sub1]]
|
||||
// CHECK-NEXT: [[uintAbsSub1:%\d+]] = OpBitcast %uint [[absSub1]]
|
||||
// CHECK-NEXT: [[diff1:%\d+]] = OpSelect %uint [[isRefByte1Zero]] %uint_0 [[uintAbsSub1]]
|
||||
// CHECK-NEXT: [[accum2PlusDiff01:%\d+]] = OpIAdd %uint [[accum2PlusDiff0]] [[diff1]]
|
||||
|
||||
// MSAD 2 Byte 2
|
||||
// CHECK-NEXT: [[src2Byte2:%\d+]] = OpBitFieldUExtract %uint [[bfi1]] %uint_16 %uint_8
|
||||
// CHECK-NEXT: [[intSrc2Byte2:%\d+]] = OpBitcast %int [[src2Byte2]]
|
||||
// CHECK-NEXT: [[sub2:%\d+]] = OpISub %int [[intRefByte2]] [[intSrc2Byte2]]
|
||||
// CHECK-NEXT: [[absSub2:%\d+]] = OpExtInst %int [[glsl]] SAbs [[sub2]]
|
||||
// CHECK-NEXT: [[uintAbsSub2:%\d+]] = OpBitcast %uint [[absSub2]]
|
||||
// CHECK-NEXT: [[diff2:%\d+]] = OpSelect %uint [[isRefByte2Zero]] %uint_0 [[uintAbsSub2]]
|
||||
// CHECK-NEXT: [[accum2PlusDiff012:%\d+]] = OpIAdd %uint [[accum2PlusDiff01]] [[diff2]]
|
||||
|
||||
// MSAD 2 Byte 3
|
||||
// CHECK-NEXT: [[src2Byte3:%\d+]] = OpBitFieldUExtract %uint [[bfi1]] %uint_24 %uint_8
|
||||
// CHECK-NEXT: [[intSrc2Byte3:%\d+]] = OpBitcast %int [[src2Byte3]]
|
||||
// CHECK-NEXT: [[sub3:%\d+]] = OpISub %int [[intRefByte3]] [[intSrc2Byte3]]
|
||||
// CHECK-NEXT: [[absSub3:%\d+]] = OpExtInst %int [[glsl]] SAbs [[sub3]]
|
||||
// CHECK-NEXT: [[uintAbsSub3:%\d+]] = OpBitcast %uint [[absSub3]]
|
||||
// CHECK-NEXT: [[diff3:%\d+]] = OpSelect %uint [[isRefByte3Zero]] %uint_0 [[uintAbsSub3]]
|
||||
// CHECK-NEXT: [[accum2PlusDiff0123:%\d+]] = OpIAdd %uint [[accum2PlusDiff012]] [[diff3]]
|
||||
|
||||
|
||||
// MSAD 3 Byte 0
|
||||
// CHECK-NEXT: [[src3Byte0:%\d+]] = OpBitFieldUExtract %uint [[bfi2]] %uint_0 %uint_8
|
||||
// CHECK-NEXT: [[intSrc3Byte0:%\d+]] = OpBitcast %int [[src3Byte0]]
|
||||
// CHECK-NEXT: [[sub0:%\d+]] = OpISub %int [[intRefByte0]] [[intSrc3Byte0]]
|
||||
// CHECK-NEXT: [[absSub0:%\d+]] = OpExtInst %int [[glsl]] SAbs [[sub0]]
|
||||
// CHECK-NEXT: [[uintAbsSub0:%\d+]] = OpBitcast %uint [[absSub0]]
|
||||
// CHECK-NEXT: [[diff0:%\d+]] = OpSelect %uint [[isRefByte0Zero]] %uint_0 [[uintAbsSub0]]
|
||||
// CHECK-NEXT: [[accum3PlusDiff0:%\d+]] = OpIAdd %uint [[accum3]] [[diff0]]
|
||||
|
||||
// MSAD 3 Byte 1
|
||||
// CHECK-NEXT: [[src3Byte1:%\d+]] = OpBitFieldUExtract %uint [[bfi2]] %uint_8 %uint_8
|
||||
// CHECK-NEXT: [[intSrc3Byte1:%\d+]] = OpBitcast %int [[src3Byte1]]
|
||||
// CHECK-NEXT: [[sub1:%\d+]] = OpISub %int [[intRefByte1]] [[intSrc3Byte1]]
|
||||
// CHECK-NEXT: [[absSub1:%\d+]] = OpExtInst %int [[glsl]] SAbs [[sub1]]
|
||||
// CHECK-NEXT: [[uintAbsSub1:%\d+]] = OpBitcast %uint [[absSub1]]
|
||||
// CHECK-NEXT: [[diff1:%\d+]] = OpSelect %uint [[isRefByte1Zero]] %uint_0 [[uintAbsSub1]]
|
||||
// CHECK-NEXT: [[accum3PlusDiff01:%\d+]] = OpIAdd %uint [[accum3PlusDiff0]] [[diff1]]
|
||||
|
||||
// MSAD 3 Byte 2
|
||||
// CHECK-NEXT: [[src3Byte2:%\d+]] = OpBitFieldUExtract %uint [[bfi2]] %uint_16 %uint_8
|
||||
// CHECK-NEXT: [[intSrc3Byte2:%\d+]] = OpBitcast %int [[src3Byte2]]
|
||||
// CHECK-NEXT: [[sub2:%\d+]] = OpISub %int [[intRefByte2]] [[intSrc3Byte2]]
|
||||
// CHECK-NEXT: [[absSub2:%\d+]] = OpExtInst %int [[glsl]] SAbs [[sub2]]
|
||||
// CHECK-NEXT: [[uintAbsSub2:%\d+]] = OpBitcast %uint [[absSub2]]
|
||||
// CHECK-NEXT: [[diff2:%\d+]] = OpSelect %uint [[isRefByte2Zero]] %uint_0 [[uintAbsSub2]]
|
||||
// CHECK-NEXT: [[accum3PlusDiff012:%\d+]] = OpIAdd %uint [[accum3PlusDiff01]] [[diff2]]
|
||||
|
||||
// MSAD 3 Byte 3
|
||||
// CHECK-NEXT: [[src3Byte3:%\d+]] = OpBitFieldUExtract %uint [[bfi2]] %uint_24 %uint_8
|
||||
// CHECK-NEXT: [[intSrc3Byte3:%\d+]] = OpBitcast %int [[src3Byte3]]
|
||||
// CHECK-NEXT: [[sub3:%\d+]] = OpISub %int [[intRefByte3]] [[intSrc3Byte3]]
|
||||
// CHECK-NEXT: [[absSub3:%\d+]] = OpExtInst %int [[glsl]] SAbs [[sub3]]
|
||||
// CHECK-NEXT: [[uintAbsSub3:%\d+]] = OpBitcast %uint [[absSub3]]
|
||||
// CHECK-NEXT: [[diff3:%\d+]] = OpSelect %uint [[isRefByte3Zero]] %uint_0 [[uintAbsSub3]]
|
||||
// CHECK-NEXT: [[accum3PlusDiff0123:%\d+]] = OpIAdd %uint [[accum3PlusDiff012]] [[diff3]]
|
||||
|
||||
// CHECK-NEXT: {{%\d+}} = OpCompositeConstruct %v4uint [[accum0PlusDiff0123]] [[accum1PlusDiff0123]] [[accum2PlusDiff0123]] [[accum3PlusDiff0123]]
|
||||
|
||||
uint4 result = msad4(reference, source, accum);
|
||||
return result;
|
||||
}
|
||||
|
|
@ -776,6 +776,7 @@ TEST_F(FileTest, IntrinsicsLit) { runFileTest("intrinsics.lit.hlsl"); }
|
|||
TEST_F(FileTest, IntrinsicsModf) { runFileTest("intrinsics.modf.hlsl"); }
|
||||
TEST_F(FileTest, IntrinsicsMad) { runFileTest("intrinsics.mad.hlsl"); }
|
||||
TEST_F(FileTest, IntrinsicsMax) { runFileTest("intrinsics.max.hlsl"); }
|
||||
TEST_F(FileTest, IntrinsicsMsad4) { runFileTest("intrinsics.msad4.hlsl"); }
|
||||
TEST_F(FileTest, IntrinsicsNormalize) {
|
||||
runFileTest("intrinsics.normalize.hlsl");
|
||||
}
|
||||
|
|
|
|||
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