Граф коммитов

823 Коммитов

Автор SHA1 Сообщение Дата
Marcelo Lopez Ruiz 1fea2b7162
Adds support for basic SRV resources and some help to dndxc. (#1160)
Add an optional extended description…
2018-03-21 16:18:05 -07:00
Lei Zhang 01fb45c865
[spirv] Unify checks for skipping struct fields in layout (#1164) 2018-03-21 15:44:22 -04:00
Lei Zhang d6dfe83f0a
[spirv] Skip cbuffer/tbuffer when creating $Globals (#1162) 2018-03-21 12:48:20 -04:00
Lei Zhang 4cfcdf3239
[spirv] Emit single store for cross-storage-class composite types (#1158)
Previously we emit a store for each sub-element, which is not
friendly to SPIR-V transformations. This commit converted that
into first constructing a temporary value of the target storage
class, and the store once.
2018-03-21 10:55:43 -04:00
Lei Zhang 9b0167be56
[spirv] Add support for :packoffset() (#1156) 2018-03-20 12:18:31 -04:00
Xiang Li a489c2ec25
Transform mad(a, 0, b) into b. (#1150) 2018-03-19 18:04:56 -07:00
Lei Zhang 0d8a15a61a
[spirv] Better reflection support via new extensions (#1111)
This commit uses the HlslCounterBufferGOOGLE decoration to link
the main RW/Append/Consume StructuredBuffer with its associated
counter buffer. It also uses HLSLSemanticGOOGLE to decorate
stage IO variables with their semantic strings from the source code.
2018-03-17 13:05:31 -04:00
Young Kim f174990c6e
Fix checking LoadInput for GetAttributeAtVertex for no Opt (#1149) 2018-03-17 08:45:46 -07:00
Lei Zhang cfd787a18e
[spirv] Cull RHS of shift operations (#1148)
In SPIR-V, if shifting a value by an amount that is greater than
the value's bitwidth, the result is undefined.

FXC and DXC/DXIL performs a bitwise and over the RHS of the shift
operation to only consider its (n - 1) least significant bits,
where n is the bitwidth of LHS.
2018-03-16 20:19:20 -04:00
Ehsan be8c74dd4f
[spirv] Booleans do not have a physical layout. (#1140)
* [spirv] Booleans do not have a physical layout.

Addresses issue #1136.
2018-03-16 17:58:08 -04:00
Grant 18138ff8cf Handle more complex addressing modes (#1147)
Fix HoistConstantArray pass to recognize more complex load & store patterns.

Previously it was expecting no nesting and just a simple list of GetElementPtr's that fed loads or stores. Now it can accept a tree (DAG) of GetElementPtrs that feed leaf node loads or stores.
These patterns cannot be directly derived from HLSL, however they can occur due to previous optimizations that transform the array accesses (like a partial CSE or similar).
2018-03-16 14:29:36 -07:00
Lei Zhang 5d557ccb34
[spirv] Revamp matrix majorness handling (#1144)
Previously we use an additional parameter to translateType()
to convey the matrix majorness info. It causes lots of type
inconsistency issue.

Now the majorness info is queried directly from the QualType.
This should be more robust.
2018-03-16 15:15:28 -04:00
Lei Zhang f6f79e744d
[spirv] Emit OpSource debug instruction (#1145) 2018-03-16 13:40:00 -04:00
Lei Zhang e3662ff353
[spirv] Collect global non-resource variables into $Globals (#1138)
This commit changes the behavior of how to handle externally-visiable
non-resource-type stand-alone variables. Previously they are emitted
as stand-alone SPIR-V variables. Now they are grouped into a cbuffer
that named as $Globals. This is more aligned with how DirectX handles
them.
2018-03-14 11:15:14 -04:00
Lei Zhang c133d935eb
[spirv] Support SM6.0 wave ops using Vulkan 1.1 (#1118)
Support promoting to SPIR-V 1.3 when necessary

Support SM6.0 wave query and vote ops

* WaveIsFirstLane
* WaveGetLaneCount
* WaveGetLaneIndex
* WaveActiveAnyTrue
* WaveActiveAllTrue
* WaveActiveBallot

Support SM6.0 wave reduction ops

* WaveActiveAllEqual
* WaveActiveCountBits
* WaveActiveSum
* WaveActiveProduct
* WaveActiveBitAnd
* WaveActiveBitOr
* WaveActiveBitXor
* WaveActiveMin
* WaveActiveMax

Support SM6.0 wave scan/prefix ops

* WavePrefixSum
* WavePrefixProduct
* WavePrefixCountBits

Support SM6.0 wave broadcast ops

* WaveReadLaneAt
* WaveReadLaneFirst

Support SM6.0 quad-wide shuffle ops

*  QuadReadAcrossX
*  QuadReadAcrossY
*  QuadReadAcrossDiagonal
*  QuadReadLaneAt
2018-03-13 15:24:48 -04:00
Helena Kotas 20353da208
Fix anonymous struct cbuffer (#1134)
Anonymous structures were not added to $Globals because they are
not externally visible.

Fixes #1075: dxcompiler drops anonymous struct cbuffer
2018-03-13 12:23:22 -07:00
Xiang Li d66d48721f
Set default input control point count to 1. (#1135) 2018-03-13 11:06:30 -07:00
Lei Zhang c859bb040f
[spirv] Support SPV_KHR_shader_draw_parameters (#1127)
Added support for the following SPIR-V builtins exposed in
SPV_KHR_shader_draw_parameters:
* BaseVertex
* BaseInstance
* DrawIndex
2018-03-13 10:07:54 -04:00
Tex Riddell 9beafa70b4
Skip deadInsts in SimpleTransformForHLDXIR to prevent AV (#1129) 2018-03-12 12:59:32 -07:00
Tex Riddell c842450dfd
DxcOpts: init flags, FileCheckerTest: fix error handling for ReadDxcOpts. (#1126) 2018-03-12 12:57:03 -07:00
Lei Zhang 70990344ed
[spirv] Implement relaxed layout for vector types (#1092)
Based on GLSL std140/std430 layout rules, relaxed layout allows
using vector's element type's alignment as the vector types's
alignment, so that we can pack a float value and a float3 value
tightly. This is the default right now.

Also add an option, -fvk-use-glsl-layout, to turn off the relaxed
layout for vectors and use conventional GLSL std140/std430 layout
rules.
2018-03-12 10:21:54 -04:00
Xiang Li 277bb0bce3
Use memcpy when cast cbuffer constant into static global. (#1125) 2018-03-08 22:34:46 -08:00
Ehsan fc771d1046
[spirv] Non-literal 'literal float' as initializer (#1122)
Handle FlatConversion for cases such as:
```
S myS = (S)(1.0/0.0);
```
These cases result in an initializer of type 'literal float', even
though the initializer is *not* a FloatingLiteral!
2018-03-08 11:41:38 -05:00
Lei Zhang d34e2654f4
[spirv] Remove accidentally added empty test file (#1120) 2018-03-08 09:13:50 -05:00
Young Kim fc2cbbd4ce
revert cosh test tolerance value for float32 (#1119) 2018-03-07 17:49:51 -08:00
Lei Zhang 307c860193
[spirv] Consider majorness when accessing matrix in cbuffer (#1116)
Moved majorness info into SpirvEvalInfo so that we can translate
type correctly based on it. This affects accessing matrices inside
cbuffer; otherwise, we will have wrong type for the matrix field
loaded out of a cbuffer.

Fixes https://github.com/Microsoft/DirectXShaderCompiler/issues/1112
2018-03-07 14:14:45 -05:00
Lei Zhang 89bc301735
[spirv] Refresh external projects for SPIR-V 1.3 (#1117) 2018-03-07 14:07:48 -05:00
Young Kim a71140cdaa
Relax hcos tolerance range (#1114) 2018-03-06 17:33:32 -08:00
Young Kim 7895e40376
Fix div denorm ftz (#1113) 2018-03-06 17:33:24 -08:00
Ehsan b02d940813
[spirv] Don't emit Float16 capability. (#1109)
Capability Float16 is not allowed by Vulkan 1.0 specification.
SPV_AMD_gpu_shader_half_float should be used if 16bit floats are used.
2018-03-06 11:25:20 -05:00
Lei Zhang c1ea245a16
[spirv] Add support for WaveReadLineFirst() (#1106) 2018-03-01 15:48:09 -05:00
Ehsan 8d5d976674
[spirv] Take bitwidth into account when casting (#1105) 2018-03-01 12:22:05 -05:00
Young Kim 81ecfef34b
Fix denorm preserve division with high value of denominator (#1093) 2018-03-01 07:41:10 -08:00
Lei Zhang c8970cdf6b
[spirv] Ignore static when seeing both static and groupshared (#1101) 2018-02-28 12:12:13 -05:00
Lei Zhang ca077c9b1f
[spirv] Fix type mismatch for compound assignment (#1104)
Compound assignments don't have the proper AST nodes to implicitly
casting LHS and RHS to the same type. But it has an API called
getComputationLHSType() to tell us what the LHS are expected to
convert to when doing the computation. We need to take into
consideration of that information when CodeGen'ing compound
assignments.
2018-02-28 12:11:58 -05:00
Xiang Li 3873af6750
Support addrspacecast when flatten global variable. (#1103) 2018-02-27 17:16:58 -08:00
Ehsan 93ba5ed95f
[spirv] Non-floating point matrix layout. (#1097) 2018-02-27 14:06:32 -05:00
Xiang Li 19616e53b5 Revert "Support addrspacecast when flatten global variable."
This reverts commit d74ff8a97d.
2018-02-27 10:59:48 -08:00
Xiang Li d74ff8a97d Support addrspacecast when flatten global variable. 2018-02-27 10:55:35 -08:00
Lei Zhang 7b7510b2c5
[spirv] Fix location assignment for composite stage IO types (#1098)
Scalars and vectors typically take only one location. But matrices
and composite types take multiple sequential locations.
2018-02-27 10:30:22 -05:00
Lei Zhang 1e410c0b54
[spirv] Do not assign descriptors to Workgroup variables (#1100)
Also fix missing row-major-ness for external matrices that need
struct wrapping.
2018-02-27 10:23:00 -05:00
Lei Zhang 552b5cc8a2
[spirv] Support 64bit types during resource calculation (#1099)
Fixes https://github.com/Microsoft/DirectXShaderCompiler/issues/1094
2018-02-27 10:21:59 -05:00
Jeff Noyle 8e3451b82d
Allow debug name to be added or removed (#1079)
* Allow debug name to be added or removed

* Add unit test

* change test name
2018-02-26 17:18:05 -08:00
Lei Zhang 4221a698e1
[spirv] Support WaveGetLaneCount() and WaveGetLaneIndex() (#1077)
They are translated into SPIR-V builtin varibles. The translation
requires the SPV_KHR_shader_ballot extension.
2018-02-21 10:34:01 -05:00
Tex Riddell 97a1b6bbee
Fix leak in dxc /recompile (#1085) 2018-02-20 19:05:01 -08:00
Xiang Li cda6c52875
Save signature debug info to alloca. (#1087) 2018-02-20 18:44:04 -08:00
Xiang Li 4156aaf280
Check row and col on resultTy after CombineDimensions. (#1086) 2018-02-20 18:00:40 -08:00
Young Kim faafc68222
set test as blocked for invalid shader model test (#1061) 2018-02-20 12:34:36 -08:00
Young Kim 3a77648684
Fix argument passing for tertiary denorm mode (#1078) 2018-02-20 12:33:49 -08:00
Xiang Li 21c251a391
Choose i32 as result type for select used by binary operator. (#1080)
* Choose i32 as result type for case like ((P.x < -P.w) ? 3 : 9) | ((P.y < -P.z) ? 5 : 3).

* Use lowest precision for literal integer for binary operator.
2018-02-20 10:31:11 -08:00