зеркало из https://github.com/microsoft/STL.git
112 строки
3.5 KiB
C++
112 строки
3.5 KiB
C++
// xatomic.h internal header
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// Copyright (c) Microsoft Corporation.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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#pragma once
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#ifndef _XATOMIC_H
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#define _XATOMIC_H
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#include <yvals.h>
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#if _STL_COMPILER_PREPROCESSOR
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#include <intrin0.h>
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#include <type_traits>
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#pragma pack(push, _CRT_PACKING)
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#pragma warning(push, _STL_WARNING_LEVEL)
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#pragma warning(disable : _STL_DISABLED_WARNINGS)
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_STL_DISABLE_CLANG_WARNINGS
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#pragma push_macro("new")
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#undef new
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// Interlocked intrinsic mapping for _nf/_acq/_rel
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#if defined(_M_CEE_PURE) || defined(_M_IX86) || defined(_M_X64)
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#define _INTRIN_RELAXED(x) x
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#define _INTRIN_ACQUIRE(x) x
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#define _INTRIN_RELEASE(x) x
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#define _INTRIN_ACQ_REL(x) x
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#define _YIELD_PROCESSOR()
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#elif defined(_M_ARM) || defined(_M_ARM64)
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#define _INTRIN_RELAXED(x) _CONCAT(x, _nf)
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#define _INTRIN_ACQUIRE(x) _CONCAT(x, _acq)
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#define _INTRIN_RELEASE(x) _CONCAT(x, _rel)
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// We don't have interlocked intrinsics for acquire-release ordering, even on
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// ARM32/ARM64, so fall back to sequentially consistent.
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#define _INTRIN_ACQ_REL(x) x
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#define _YIELD_PROCESSOR() __yield()
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#else // ^^^ ARM32/ARM64 / unsupported hardware vvv
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#error Unsupported hardware
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#endif // hardware
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#define _MT_INCR(x) _INTRIN_RELAXED(_InterlockedIncrement)(reinterpret_cast<volatile long*>(&x))
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#define _MT_DECR(x) _INTRIN_ACQ_REL(_InterlockedDecrement)(reinterpret_cast<volatile long*>(&x))
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#if defined(_M_CEE_PURE) || defined(_M_IX86) || defined(_M_X64)
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#define _ISO_VOLATILE_LOAD32(_Storage) (*_Atomic_address_as<const long>(_Storage))
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#elif defined(_M_ARM) || defined(_M_ARM64)
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#define _ISO_VOLATILE_LOAD32(_Storage) __iso_volatile_load32(_Atomic_address_as<const int>(_Storage))
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#else // ^^^ ARM32/ARM64 / unsupported hardware vvv
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#error Unsupported hardware
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#endif // hardware
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_STD_BEGIN
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#if _HAS_CXX20
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// ENUM CLASS memory_order
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enum class memory_order : int {
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relaxed,
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consume,
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acquire,
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release,
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acq_rel,
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seq_cst,
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// LWG-3268
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memory_order_relaxed = relaxed,
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memory_order_consume = consume,
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memory_order_acquire = acquire,
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memory_order_release = release,
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memory_order_acq_rel = acq_rel,
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memory_order_seq_cst = seq_cst
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};
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inline constexpr memory_order memory_order_relaxed = memory_order::relaxed;
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inline constexpr memory_order memory_order_consume = memory_order::consume;
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inline constexpr memory_order memory_order_acquire = memory_order::acquire;
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inline constexpr memory_order memory_order_release = memory_order::release;
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inline constexpr memory_order memory_order_acq_rel = memory_order::acq_rel;
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inline constexpr memory_order memory_order_seq_cst = memory_order::seq_cst;
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#else // _HAS_CXX20
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// ENUM memory_order
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enum memory_order {
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memory_order_relaxed,
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memory_order_consume,
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memory_order_acquire,
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memory_order_release,
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memory_order_acq_rel,
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memory_order_seq_cst
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};
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#endif // _HAS_CXX20
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using _Atomic_counter_t = unsigned long;
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// FUNCTION TEMPLATE _Atomic_address_as
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template <class _Integral, class _Ty>
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_NODISCARD volatile _Integral* _Atomic_address_as(_Ty& _Source) noexcept {
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// gets a pointer to the argument as an integral type (to pass to intrinsics)
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static_assert(is_integral_v<_Integral>, "Tried to reinterpret memory as non-integral");
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return &reinterpret_cast<volatile _Integral&>(_Source);
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}
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_STD_END
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#pragma pop_macro("new")
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_STL_RESTORE_CLANG_WARNINGS
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#pragma warning(pop)
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#pragma pack(pop)
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#endif // _STL_COMPILER_PREPROCESSOR
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#endif // _XATOMIC_H
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