Add FPGA files
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qiluo-msft
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<header>
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<!-- ISE source project file created by Project Navigator. -->
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<!-- -->
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<!-- This file contains project source information including a list of -->
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<!-- project source files, project and process properties. This file, -->
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<!-- along with the project source files, is sufficient to open and -->
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<!-- implement in ISE Project Navigator. -->
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<!-- -->
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<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
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</header>
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<version xil_pn:ise_version="12.3" xil_pn:schema_version="2"/>
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<files>
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<file xil_pn:name="../../../rtl/Sora_RCB.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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<association xil_pn:name="Implementation"/>
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||||
</file>
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||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/Clock_module_FRL.v" xil_pn:type="FILE_VERILOG">
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||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
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||||
</file>
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||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/completer_pkt_gen.v" xil_pn:type="FILE_VERILOG">
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||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
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||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/completion_timeout.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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||||
<association xil_pn:name="Implementation"/>
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||||
</file>
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<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/dma_ddr2_if.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
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||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/edge_detect.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
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||||
</file>
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||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/firmware_ctrl_wrapper.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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<association xil_pn:name="Implementation"/>
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</file>
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<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/internal_dma_ctrl.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
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||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/non_posted_pkt_builder.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
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||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/non_posted_pkt_gen.v" xil_pn:type="FILE_VERILOG">
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||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
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||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/non_posted_pkt_slicer.v" xil_pn:type="FILE_VERILOG">
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||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/pcie_dma_wrapper.v" xil_pn:type="FILE_VERILOG">
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||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/pending_comp_ram_32x1.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/performance_counter.v" xil_pn:type="FILE_VERILOG">
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||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
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||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/performance_counters.v" xil_pn:type="FILE_VERILOG"/>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/posted_pkt_builder.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/posted_pkt_gen_sora.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/read_req_wrapper.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/register_table.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/rising_edge_detect.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/rx_engine.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/rx_mem_data_fsm.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/rx_trn_data_fsm.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/rx_trn_monitor.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/tag_generator.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/transfer_controller.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/tx_engine.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/tx_trn_sm.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/CRC8_gen.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_BIT_ALIGN_MACHINE.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_BYTE_Alignment.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_count_to_16x.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_COUNT_TO_64.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_count_to_128.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_CRC_gen.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_DDR_8TO1_16CHAN_RX.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_LED_Clock.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_OSERDES.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_OSERDES_MSG.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_RESOURCE_SHARING_CONTROL.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_RX.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_RX_Data_FIFO_8bit.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_RX_MSG.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_RX_OneDataChannel.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_RXMSG_ACK_Decoder.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_RXMSG_Byte_Alignment.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_TrainingPattern.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_TX.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_TX_MSG.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/Sora_FRL_RCB.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/Sora_FRL_STATUS_decoder.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/Sora_FRL_STATUS_encoder.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../ip_cores/coregen_memories/a64_64_distram_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../ip_cores/coregen_memories/a64_128_distram_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../ip_cores/coregen_memories/data_trn_dma_write_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../ip_cores/coregen_memories/data_trn_mem_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../ip_cores/coregen_memories/dualport_32x32_compram.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../ip_cores/coregen_memories/egress_addr_cntrl_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../ip_cores/coregen_memories/Egress_data_FIFO.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../ip_cores/coregen_memories/ingress_addr_cntrl_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../ip_cores/coregen_memories/ingress_data_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../ip_cores/coregen_memories/RX_data_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../ip_cores/coregen_memories/RX_TS_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../ip_cores/coregen_memories/TX_MSG_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../ip_cores/coregen_memories/xfer_trn_mem_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../ip_cores/coregen_DCMs/DCM_200MI_133MO_176MO.xaw" xil_pn:type="FILE_XAW">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../ip_cores/coregen_DCMs/PLL_200MI_200MO.xaw" xil_pn:type="FILE_XAW">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../ip_cores/pcie_endpoint_plus_x8_250/endpoint_blk_plus_v1_9.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/posted_pkt_scheduler_4radios.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/TX_controller_noloss.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="Sora_RCB_FRL_x4_plus_133MDDR_RCBv1.1.3_pciev1.14.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../ip_cores/ddr2_memory_interface/rtl/mem_interface_top.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../ip_cores/pcie_endpoint_plus_x8_250/endpoint_blk_plus_v1_14.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/old/RCB_FRL_data_check.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/old/RCB_FRL_fifo_MSG.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../../ip_cores/coregen_memories/RCB_FRL_RX_Data_FIFO_onechannel.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector virtex5" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String)" xil_pn:value="f5941f72eacd3436792975408cbaafb70826328b2fd6e20d0826328bb598eefd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Busy" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Configuration Pin CS" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Configuration Pin DIn" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Configuration Pin RdWr" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cores Search Directories" xil_pn:value="../../../ip_cores/coregen_memories|../../../ip_cores/pcie_endpoint_plus_x8_250" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc5vlx110t" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Virtex5" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Continue on Impossible" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fallback Reconfiguration" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Generate Detailed Package Parasitics" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|Sora_RCB" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../rtl/Sora_RCB.v" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Sora_RCB" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="JTAG to System Monitor Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="Soft" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="All" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macro Search Path" xil_pn:value="../../../ip_cores/coregen_memories|../../../ip_cores/pcie_endpoint_plus_x8_250|../../../ip_cores/coregen_DCMs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="50" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="On" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="400" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Speed" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="Sora_RCB" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="ff1136" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Continue on Impossible" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Sora_RCB_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="Sora_RCB_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Sora_RCB_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Sora_RCB_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Distributed" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Distributed" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retiming" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SelectMAP Abort Sequence" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-1" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Constraints File" xil_pn:value="pcie_dma_top.xcf" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/12.3/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Include Directories" xil_pn:value="../../../rtl|../../../rtl/pcie_userapp_wrapper/pcie_dma_engine" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events) virtex5" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value virtex5" xil_pn:value="0x000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="SoraRCB" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-11-30T17:32:33" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BBAC7ED072DF4461B16794091A62D8FA" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings>
|
||||
<binding xil_pn:location="/Sora_RCB" xil_pn:name="Sora_RCB_FRL_x4_plus_133MDDR_RCBv1.1.3_pciev1.14.ucf"/>
|
||||
</bindings>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
<file xil_pn:name="../../../rtl/pcie_userapp_wrapper/pcie_dma_engine/Sora_config.v" xil_pn:type="FILE_VERILOG"/>
|
||||
<file xil_pn:name="../../../rtl/PCIe_setting.v" xil_pn:type="FILE_VERILOG"/>
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,165 @@
|
|||
###############################################################################
|
||||
## 2007-2008 Xilinx, Inc. All Rights Reserved.
|
||||
## Confidential and proprietary information of Xilinx, Inc.
|
||||
###############################################################################
|
||||
## ____ ____
|
||||
## / /\/ /
|
||||
## /___/ \ / Vendor: Xilinx
|
||||
## \ \ \/ Version: 1.0
|
||||
## \ \ Filename: pcie_dma_top.xcf
|
||||
## / / Date Last Modified: Apr. 1st, 2008
|
||||
## /___/ /\ Date Created: Apr. 1st, 2008
|
||||
## \ \ / \
|
||||
## \___\/\___\
|
||||
##
|
||||
## Device: Virtex-5 LXT
|
||||
## Purpose: Endpoint Block Plus to DDR2 DMA Initiator XST User Constraints File
|
||||
## Reference: XAPP859
|
||||
## Revision History:
|
||||
## Rev 1.0 - First created, Kraig Lund, Apr. 1 2008.
|
||||
###############################################################################
|
||||
################################################################################
|
||||
# Define Device, Package, and Speed Grade
|
||||
################################################################################
|
||||
#
|
||||
# CONFIG PART = XC5VLX50T-FF1136 ;
|
||||
#
|
||||
################################################################################
|
||||
|
||||
# Timing specifications common to all board/chip
|
||||
|
||||
NET "trn_clk_c" TNM_NET = "USR_PCIE_CLK";
|
||||
#TIMESPEC "TS_USR_PCIE_CLK" = PERIOD "USR_PCIE_CLK" 4 ns HIGH 50 %;
|
||||
TIMESPEC "TS_USR_PCIE_CLK" = PERIOD "USR_PCIE_CLK" 8 ns HIGH 50 %;
|
||||
|
||||
NET "SYS_CLK_P" TNM_NET = "SYS_CLK";
|
||||
#TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 4 ns HIGH 50 %;
|
||||
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 8 ns HIGH 50 %;
|
||||
|
||||
NET "trn_clk_c" TNM_NET = "TRN_CLK";
|
||||
#TIMESPEC "TS_TRN_CLK" = PERIOD "TRN_CLK" 4 ns HIGH 50 %;
|
||||
TIMESPEC "TS_TRN_CLK" = PERIOD "TRN_CLK" 8 ns HIGH 50 %;
|
||||
|
||||
## Multi-cycle paths
|
||||
#Multi-cycle paths for tx_trn_sm adder/subtractor
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/rx_trn_monitor_inst/dma*_div8_reg*" TNM=FFS "TNM_DMARDIV8_REG_SRC";
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/rx_trn_monitor_inst/dma*_div8_now*" TNM=FFS "TNM_DMARDIV8_NOW_SRC";
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/rx_trn_monitor_inst/addsub_state*" TNM=FFS "TNM_RADDSUB_STATE_SRC";
|
||||
TIMEGRP "DMARDIV8_2X_SRC" = "TNM_DMARDIV8_REG_SRC" "TNM_DMARDIV8_NOW_SRC" "TNM_RADDSUB_STATE_SRC";
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/rx_trn_monitor_inst/dma*_div8_reg_new*" TNM=FFS "TNM_DMARDIV8_REGNEW_DEST";
|
||||
TIMESPEC "TS_DMARDIV8_2X" = FROM "DMARDIV8_2X_SRC" TO "TNM_DMARDIV8_REGNEW_DEST" "TS_TRN_CLK"*2;
|
||||
|
||||
# Jiansong: disabled
|
||||
#Multi-cycle paths for tx_trn_sm adder/subtractor
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/tx_trn_sm_inst/dma*_div8_reg*" TNM=FFS "TNM_DMAWDIV8_REG_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/tx_trn_sm_inst/dma*_div8_now*" TNM=FFS "TNM_DMAWDIV8_NOW_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/tx_trn_sm_inst/addsub_state*" TNM=FFS "TNM_WADDSUB_STATE_SRC";
|
||||
#TIMEGRP "DMAWDIV8_2X_SRC" = "TNM_DMAWDIV8_REG_SRC" "TNM_DMAWDIV8_NOW_SRC" "TNM_WADDSUB_STATE_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/tx_trn_sm_inst/dma*_div8_reg_new*" TNM=FFS "TNM_DMAWDIV8_REGNEW_DEST";
|
||||
#TIMESPEC "TS_DMAWDIV8_2X" = FROM "DMAWDIV8_2X_SRC" TO "TNM_DMAWDIV8_REGNEW_DEST" "TS_TRN_CLK"*2;
|
||||
|
||||
# Jiansong: disabled
|
||||
#Multi-cycle paths for posted slicer adder
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/posted_pkt_gen_inst/posted_pkt_slicer_inst/four_kb_xfer*" TNM=FFS "TNM_PFKB_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/posted_pkt_gen_inst/posted_pkt_slicer_inst/dma*_reg*" TNM=FFS "TNM_PDMAREG_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/posted_pkt_gen_inst/posted_pkt_slicer_inst/state*" TNM=FFS "TNM_PSTATE_SRC";
|
||||
#TIMEGRP "POSTED_2X_SRC" = "TNM_PFKB_SRC" "TNM_PDMAREG_SRC" "TNM_PSTATE_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/posted_pkt_gen_inst/posted_pkt_slicer_inst/dma*_new*" TNM=FFS "TNM_PDMANEW_DEST";
|
||||
#TIMESPEC "TS_POSTED_2X" = FROM "POSTED_2X_SRC" TO "TNM_PDMANEW_DEST" "TS_TRN_CLK"*2;
|
||||
|
||||
# Jiansong: modified
|
||||
#Multi-cycle paths for non-posted slicer adder#INST "pcie_dma_wrapper_inst/tx_engine_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/four_kb_xfer*" TNM=FFS "TNM_NFKB_SRC";
|
||||
INST "pcie_dma_wrapper_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/four_kb_xfer*" TNM=FFS "TNM_NFKB_SRC";
|
||||
INST "pcie_dma_wrapper_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/dma*_reg*" TNM=FFS "TNM_NDMAREG_SRC";
|
||||
INST "pcie_dma_wrapper_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/state*" TNM=FFS "TNM_NSTATE_SRC";
|
||||
TIMEGRP "NONPOSTED_2X_SRC" = "TNM_NFKB_SRC" "TNM_NDMAREG_SRC" "TNM_NSTATE_SRC";
|
||||
INST "pcie_dma_wrapper_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/dma*_new*" TNM=FFS "TNM_NDMANEW_DEST";
|
||||
TIMESPEC "TS_NONPOSTED_2X" = FROM "NONPOSTED_2X_SRC" TO "TNM_NDMANEW_DEST" "TS_TRN_CLK"*2;
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/four_kb_xfer*" TNM=FFS "TNM_NFKB_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/dma*_reg*" TNM=FFS "TNM_NDMAREG_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/state*" TNM=FFS "TNM_NSTATE_SRC";
|
||||
#TIMEGRP "NONPOSTED_2X_SRC" = "TNM_NFKB_SRC" "TNM_NDMAREG_SRC" "TNM_NSTATE_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/dma*_new*" TNM=FFS "TNM_NDMANEW_DEST";
|
||||
#TIMESPEC "TS_NONPOSTED_2X" = FROM "NONPOSTED_2X_SRC" TO "TNM_NDMANEW_DEST" "TS_TRN_CLK"*2;
|
||||
|
||||
# Jiansong: added for poset_packet_scheduler
|
||||
# Multi-cycle paths for posted scheduler adder
|
||||
#INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_inst/RXBuf*" TNM=FFS "TNM_NRXB_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_inst/dmawad_now1*" TNM=FFS "TNM_NDWNW_SRC";
|
||||
#TIMEGRP "POSTED_2X_SRC" = "TNM_NRXB_SRC" "TNM_NDWNW_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_inst/dmawad_next*" TNM=FFS "TNM_NDWNT_DEST";
|
||||
#TIMESPEC "TS_POSTED_2X" = FROM "POSTED_2X_SRC" TO "TNM_NDWNT_DEST" "TS_TRN_CLK"*2;
|
||||
|
||||
# Jiansong: added for poset_packet_scheduler_4radios
|
||||
# Multi-cycle paths for posted scheduler adder
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_4radios_inst/RXBuf_1st*" TNM=FFS "TNM_NRXB_SRC";
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_4radios_inst/dmawad_now1_1st*" TNM=FFS "TNM_NDWNW_SRC";
|
||||
TIMEGRP "POSTED_2X_SRC" = "TNM_NRXB_SRC" "TNM_NDWNW_SRC";
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_4radios_inst/dmawad_next_1st*" TNM=FFS "TNM_NDWNT_DEST";
|
||||
TIMESPEC "TS_POSTED_2X" = FROM "POSTED_2X_SRC" TO "TNM_NDWNT_DEST" "TS_TRN_CLK"*2;
|
||||
|
||||
# Jiansong: added for poset_packet_scheduler_4radios
|
||||
# Multi-cycle paths for posted scheduler adder
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_4radios_inst/RXBuf_2nd*" TNM=FFS "TNM_NRXB_SRC_2nd";
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_4radios_inst/dmawad_now1_2nd*" TNM=FFS "TNM_NDWNW_SRC_2nd";
|
||||
TIMEGRP "POSTED_2X_SRC_2nd" = "TNM_NRXB_SRC_2nd" "TNM_NDWNW_SRC_2nd";
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_4radios_inst/dmawad_next_2nd*" TNM=FFS "TNM_NDWNT_DEST_2nd";
|
||||
TIMESPEC "TS_POSTED_2X_2nd" = FROM "POSTED_2X_SRC_2nd" TO "TNM_NDWNT_DEST_2nd" "TS_TRN_CLK"*2;
|
||||
|
||||
# Jiansong: added for poset_packet_scheduler_4radios
|
||||
# Multi-cycle paths for posted scheduler adder
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_4radios_inst/RXBuf_3rd*" TNM=FFS "TNM_NRXB_SRC_3rd";
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_4radios_inst/dmawad_now1_3rd*" TNM=FFS "TNM_NDWNW_SRC_3rd";
|
||||
TIMEGRP "POSTED_2X_SRC_3rd" = "TNM_NRXB_SRC_3rd" "TNM_NDWNW_SRC_3rd";
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_4radios_inst/dmawad_next_3rd*" TNM=FFS "TNM_NDWNT_DEST_3rd";
|
||||
TIMESPEC "TS_POSTED_2X_3rd" = FROM "POSTED_2X_SRC_3rd" TO "TNM_NDWNT_DEST_3rd" "TS_TRN_CLK"*2;
|
||||
|
||||
# Jiansong: added for poset_packet_scheduler_4radios
|
||||
# Multi-cycle paths for posted scheduler adder
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_4radios_inst/RXBuf_4th*" TNM=FFS "TNM_NRXB_SRC_4th";
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_4radios_inst/dmawad_now1_4th*" TNM=FFS "TNM_NDWNW_SRC_4th";
|
||||
TIMEGRP "POSTED_2X_SRC_4th" = "TNM_NRXB_SRC_4th" "TNM_NDWNW_SRC_4th";
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_4radios_inst/dmawad_next_4th*" TNM=FFS "TNM_NDWNT_DEST_4th";
|
||||
TIMESPEC "TS_POSTED_2X_4th" = FROM "POSTED_2X_SRC_4th" TO "TNM_NDWNT_DEST_4th" "TS_TRN_CLK"*2;
|
||||
|
||||
# Jiansong: modified
|
||||
# Multi-cycle paths for large xfers shim adder
|
||||
#INST "pcie_dma_wrapper_inst/transfer_controller_inst/state_1*" TNM=FFS "TNM_STATE_1_SRC";
|
||||
INST "pcie_dma_wrapper_inst/transfer_controller_inst/state_3*" TNM=FFS "TNM_STATE_3_SRC";
|
||||
INST "pcie_dma_wrapper_inst/transfer_controller_inst/dma*_now*" TNM=FFS "TNM_DMANOW_SRC";
|
||||
#TIMEGRP "LARGE_XFER_2X_SRC" = "TNM_STATE_1_SRC" "TNM_STATE_3_SRC" "TNM_DMANOW_SRC";
|
||||
TIMEGRP "LARGE_XFER_2X_SRC" = "TNM_STATE_3_SRC" "TNM_DMANOW_SRC";
|
||||
INST "pcie_dma_wrapper_inst/transfer_controller_inst/dma*_next*" TNM=FFS "TNM_DMANEXT_DEST";
|
||||
TIMESPEC "TS_DMAREG_DMANEXT" = FROM "LARGE_XFER_2X_SRC" TO "TNM_DMANEXT_DEST" "TS_TRN_CLK"*2;
|
||||
|
||||
# Jiansong: added
|
||||
# Multi-cycle paths for large xfers shim adder
|
||||
INST "pcie_dma_wrapper_inst/TX_controller_inst/TX_state_1*" TNM=FFS "TNM_TX_STATE_1_SRC";
|
||||
INST "pcie_dma_wrapper_inst/TX_controller_inst/TX_*_now*" TNM=FFS "TNM_TXNOW_SRC";
|
||||
TIMEGRP "TX_LARGE_XFER_2X_SRC" = "TNM_TX_STATE_1_SRC" "TNM_TXNOW_SRC";
|
||||
INST "pcie_dma_wrapper_inst/TX_controller_inst/TX_*_next*" TNM=FFS "TNM_TXNEXT_DEST";
|
||||
TIMESPEC "TS_TXREG_TXNEXT" = FROM "TX_LARGE_XFER_2X_SRC" TO "TNM_TXNEXT_DEST" "TS_TRN_CLK"*2;
|
||||
|
||||
# Jiansong: added, used for WARP radio register version
|
||||
# Multi-cycle paths from radio module to host registers
|
||||
# INST "WARP_Radio_module_inst/host_*" TNM=FFS "TNM_RADIOHOST_SRC";
|
||||
# TIMEGRP "RADIO_WARP_SRC" = "TNM_RADIOHOST_SRC";
|
||||
# INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/WARP_*" TNM=FFS "TNM_WARP_DEST";
|
||||
# TIMESPEC "TS_RADIO_INTERFACE" = FROM "RADIO_WARP_SRC" TO "TNM_WARP_DEST" "TS_TRN_CLK"*3;
|
||||
|
||||
# Jiansong: added, used for SORA radio register version
|
||||
# Multi-cycle paths from radio module to host registers
|
||||
# INST "Sora_Radio_Interpretation_for_WARP_inst/host_*" TNM=FFS "TNM_ABS_RADIOHOST_SRC";
|
||||
# TIMEGRP "ABS_RADIO_SORA_SRC" = "TNM_ABS_RADIOHOST_SRC";
|
||||
# INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/SORA_*" TNM=FFS "TNM_ABS_SORA_DEST";
|
||||
# TIMESPEC "TS_ABS_RADIO_INTERFACE" = FROM "ABS_RADIO_SORA_SRC" TO "TNM_ABS_SORA_DEST" "TS_TRN_CLK"*3;
|
||||
|
||||
#Tig'ed nets - these are static signals
|
||||
NET "trn_lnk_up_n_c" TIG;
|
||||
NET "phy_init_initialization_done" TIG;
|
||||
|
||||
INST "max_read_req_reg*" TIG;
|
||||
INST "max_pay_size_reg*" TIG;
|
||||
INST "pcie_id_reg*" TIG;
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
XILINX-XDB 0.1 STUB 0.1 ASCII
|
||||
XILINX-XDM V1.4e
|
||||
$8;x5>6239$;95;40/1044=6;2;%9:5>0/3-46><9?-cJ=H?3:3427=6P:19<=<42308607<<<1>"=>?7:CQGMQNR8=0M_YU_NLO]ZEF[JKOECIPCMI2<>GU_SUDBAWPCMIJJZC_\LXEMA?:;@PT^ZIIDPUH@FGA_WCOQ@7e3HX\VRAALX]GGHYT_@^HDD@H_BNH55=FZ^PTCCBV_EFQ[F6682KY[WQ@NM[\@ATXK8;:7L\XZ^MMH\YCL[UH@F?9;@PT^ZIIDPUOH_QJDFGNKAC6>2KY[WQ@NM[\@ATXNEC[JAA_139BVR\XGGFRSIJ]_HLJP41<I[]QSB@CY^FGVZTB[L^_U]K>5:CQS_YHFESTJOQJXUGQJDJ6:2KY[WQ@NM[\MKUSWG_F=h5NRVX\KKJ^WCC_XH\PPJ0SOZHHFFCXI<l4ASUY[JHKQV@BXYK]_TK\JJHHAZO:;6O]W[]LJI_XZLIDBKGH_QKMW43<I[]QSB@CY^PFW@RXDFMBO<<4ASUY[JHKQVXNXL\HEU3;?DTPRVEE@TQYAMKG[A@TWDEOIl5NSRM@[ROS@o1J[WQLLJ@VBQ_WM8;=7LYU_BNHFP@SQYO:SCAJDHV27>GPRVIGGRAZTQWW[Q_WMj1J[WQILNUW]UC?3H]QS]O]Te9BS_YTQG^CXBAC4:@VBB2<KEA;46MCK1]AQCc<KEA;SO[IG^KMWQ><KEA;SB[[6:AOO4>7>2IGG?9?5:AOO7^?3JF@>U?7049@HN?7=2IGGIX6;BNH@SYE]Ol0OAEKV^@VBBYNFZ^h7NBDDW]GMSOCM01H@FJY_NWW1>EKCOH37NBDFC]JJ0=DDBLS46MCKGZ2<5?<KEAMTRLZFg9@HN@_WK_MKRGASUa8GIMAPVNBZDJJe:AOOC^XE\F_E]BV9:AOOC^XG\^>7NBDIO32?FJLAGUOE[GKE^@Z[7><KEABBRGAc:AOOLHXXLXBCIk4CMIJJZUUKV^R\H?=;BNHKPRXXAKXIR]GIGV`?FJLWOONHOOLK89@KHKN\]OO;6M]E@VF@3?<L3%fuiky/GRDE*~fxy2>5R]`r`]eqij(phz{487Psnpb[454Emny#k~ha.ks[fiumz%hckheo]GGHu(LJGT>=>BI^307HIX9><FC#vnw49GEABU<2NH@F94DBO\EAPd3MIFSLJY_HLPP45<LJGTMXZ@C@NJFWGSAFD:86JLM^RFVCIUEHDHIRC@DD18@@Hc3MOXGHYPAEHVWQ753MLXSK\JQTGMG\YJGMO97IGn;ENO[DHCWOR:>6JCL^DQATSBFJSTABJJ2:FL0>BULP;>7I[[Y^AZGICXKFXYINZFOO18@RC03MU]MA[Ja:DBGQIUQV@M96HNLRG:?CDX[F_YOHm4FDGGFDELWK_M56HFN^WMMQU?3OE^XR][R`9EKPRX]GC__l5IOTV\RDJRM=1CEJF>;H:8MKRBZGKG=<5EIUVFVZOIX\^TXT^J6:NLEACC>2FDOFKKa:NLGNCCWF__56CNX^QSA@B43DBQ;6CPV@NVA2=IM]]D^F:4NNLF5>I33FNO^55@PQMPMQCe3YBJ_HQ\HHDW=>VNFAKXNX]n;QKMMVAILLN37]GAWHFWL==WZ@G_U]K>0:RQKUYWAGCXMNZFVD78TVEKC?1[_IAAE59SW@H?3YYBBNJJC29QWQ0<ZZ^TECl4SHEF\QCUFHFj7^GB_EGUMFC13ZCEKAKl;RVBVQSWW^KBXo5\YOAKVJHH]Z;97^W\TDO\W\HD@[EECX]<;UMS0>RU]L20Y^KPBTDD=>STMVH^JJ]:;WKFS41<^@X_IU;m;YCT[SCU[@EE=i5WIMKM\(^CJ):%=-][UC"3*4&F[JCB?6V\T79[`gYNl8:0TicPM`hlvScu{`ee==5Wdl]Nmkiu^lxxeb`:;Z294X0<S90:9P;4[185Y1=fz~p87imb7:tfvljhok1}i}foo"2*5763qi>zav:0u/2bc76;?wKL}:=;AB{0d<A2?0:w^:6:869=2<6;;2m:54=d177k>a281e5=4;;%:f>=e<uZ>364:5968277>a>109h=9n;R4;><2=1>0:??6i6981`5c23Z>364:5968277>a>109h<?k;R4;><2=1>0:??6i6981`4243Z>364:5968277>a>109h<;<;e;7>5<628qX84464;;4>4550o<36?j?559uP=?=83;1=7otS5;9=1<>?3;8>5h98;0g402<j1?1<7>54;cx `<>=2.9:779;%04><><,;214i5+8c86?g2b290:47>50z&43?2c3-l1?>5+118;5>"6:38j7)?n:938 4d=;2.:;79>;%30>7g<,8>1>h5+1481e>"6>3=97)?7:19'5<<?;2.:i7;k;%3e>0b<,;:19i5+468;?!512=1/?h4m;%1e>d=#<;0>h6*;4;f8 13=>?1/8;49f:&7b?>13-?;6;l4$409<1=#=:0=86*:6;47?!3>21<0(8l53:&6g?0<,<o1:;5+6185g>"1:3<h7)8<:69'22<192.=h7m4$6194>"?:3?o7)68:9:8 47=12.997;:;%02>32<,1:14l5+1e82?!7d2;1b8<4?:%55><7<,>214;54i2:94?"0>33:7)97:948?l2e290/;;463:&41?>13-=?6584;h77>5<#??02>6*85;:5?!1321<07d;n:18'33<>92.<9769;:k65?6=,><15<5+748;2>=n<j0;6)99:838 23=0?10e:j50;&42??63-=36584;h5a>5<#??02=6*85;:5?>o0k3:1(:85909'30<?>21b;44?:%55><7<,>?14;54o3c94?"0>33:7)97:948 75=:01/>94:f:9l77<72-==64?4;n0f>5<#??02=65`2g83>!1120;07b=<:18'33<>92.<4769;%00>7?<3f9;6=4+778:5>=h;80;6)99:838?j5f290/;;461:&4<?>13-886?74;n1a>5<#??02=65`5983>!1120;07b;8:18'33<>:2.<8769;:m5=?6=,><15<5+798;2>=h?h0;6)99:838?xd5k3:1>7>50z&43?4>3`<>6=4+778:5>"0032=76a80;29 20=181/;5476:9~f63=8381<7>t$6596<=n><0;6)99:838 2>=0?10c:>50;&42??63-=36584;|`0`?6=:3:1<v*87;0:?l02290/;;461:&4<?>132e<<7>5$649=4=#?103:65rs5194?7|5=o18<5+7g851>{t;00;6?u24d80<>;5k3=;7)<=:3f8yv1b290:w0:j:6f8 2`=><1v?l50;0x91c=:h16>n495:p71<72;q68h4<3:?01?023ty8o7>52z?7a?5f349o6;;4}r4b>5<6s4>n6;74$6d935=z{:=1<7?t=27935=#?o0<<6s|4183>4}:;m0<<6*8f;53?xu5l3:1<v*8f;53?x{i:l0;6<urn3d94?7|ug9;6=4>{|l05?6=9rwe??4?:0y~j65=83;pqc=;:182xh4=3:1=vsa3783>4}zf:=1<7?t}|~DEE|<;0258;=e6CDG}7uIJ[wpNO
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
XILINX-XDB 0.1 STUB 0.1 ASCII
|
||||
XILINX-XDM V1.4e
|
||||
$6cx5>6239$;<=640/23456702:%=?</nr784+37881::6??.1233>77&8$;?>5>011865663=?09#>?069BVFNPAS;=7L\XZ^MMH\YDDBCE=RXNLTG22>GU_SUDBAWPCMIJJ7YQIE_N==5NRVX\KKJ^WJF@_HB>a:CQS_YHFESTICOMLD]@HNIR\MIF=95NRVX\KKJ^WOCE=R[AIUQ20>GU_SUDBAWPFHL1[PHN\Z;j7L\XZ^MMH\YWDEUMN^\L_BNHKPR6l2KY[WQ@NM[\TIJXNKYYORMCKNWW@FK6?2KY[WQ@NM[\V@EHFOCLS]GAS0c8EWQ]WFDGUR\JF^HJPQCUW\DBX^h4AVX\GIME]O^R\H?>7:CT^ZEKC@D:SD@_UU]AQC@BZ8>0MZTPCMIJJ4YTZJUBNXHH169BS_YDDBCE>RGAPTV\FP@AM[;?7LYU_BNHMK4X[[ITEO[IGb9BS_YADF]_U]K7;@UY[UGU\8k0MZTPPMN\AVRXB@^_I_QLLJMVP5b<I^PT_T@[HUMLH<=EIGN\EIZG4:@VBB><KEAMNIMB149@HN@ELJG+{dzgotv#FP@@?2IGGKLFN99@HN@EG\^:96MCKG@LQQ&pa}bdyy.MUGE24>EKCOHDYYQLLJDAMKb<KEAMNB[[_LWOP`=DDBLICXZPPICPA3=DDBCE=45LLJKM5ZOIl2IGGD@>_QGQMJB13JF@EC<k;BNHMK4XXLXBCI64CMIJJVCK?2IGGB[[0c9@HNIR\9UIYK?>;BNHKPR7WK_MKRGASUg8GIMH]]:THDXFDD31?FJLG\^;SI[[Y^AZGICe3JF@CXZ?_NWW`>EKCF__<R^GARG4?FJLG\^:;6MCKNWW62=DDBE^X>94CMILQQ203JF@CXZ:a:AOOJSSLJG;m6MCKNWW@FK6i2IGGB[[DBO1e>EKCF__HNC<a:AOOJSSLJG?m6MCKNWW@FK212IDA@G[TDF`?FIJXLDXMYG@N69@V@GSMM=:7I4SmxffrY@WOHVsm}~758]PkwgX`~c~ljfo^nlkudfkbVsm}~758]pkwgX9:9Fhi|SfqebXlvXkfxnQm`rdefjZBDEzV[@AQ=01OJ[767EF$smz;4D@FGV1=CKEA87IKA2:FJ`>BN^JF@SIGYIEG1?AI33MXOU>5KWD78BDJTM81B:6B@AEGG2>JHKBOOm6B@CJGG[JSS;2GCV:5AEUULVN7<G01D\YGBI[GG=>VNFAKXNX]n;QKMMVAILLN37]GAIRT@G==WAG]BHYF8;QNO[DBQk2ZG@ROKV^KMWQ><X[CFXT^J119SVJVXX@DB_LM[IWG1?UUf3[OMSGG[TDP0?WCK;2XXX;5]SU]JJg=TANOSXH\AAM48WLH@DL;97^W\TDO\W\HD@[EECX]<;UMS0>RU]L20Y^KPBTDD=>STMVH^JJ]:;WKFS4d<PH]TZH\\INL2`>^ND@DS!UJM 1,2$VRRJ):%=-O\CHK0?]US>2RonRGk119[`hYJiceyZh||inl24>^ceVGbbb|Yesqjkk3<S90;Q;5T0;36Y0=\83>V86o}w{58`fkXxef<7{k}immdf>pbzzcdb-?!0008|f3qdq?;x hi1015)4{GHy9=7MNw448E>1<6sZ>?6:;5798277>aj=0:856:{o53>4=i?80?7)8i:7f8yV252>?1;54>33:ef1<6<h8h7^;?:6793=<6;;2mn94>64:e?V252>?1;54>33:ef1<6>?9?7i9::182>4}T<=0<9797:011<cd328>3485yT7`94?7=93<p_9:57484<?74:1li87?;8978f31=83:1>78t$b842>"6k3=<7)?k:6;8 4`=>l1/:n48;c7`>5<6k3:1<v*:d;7a?!b=12.n655+f;78 46=<l1/=<4:3:&26?343-;86?84$06966=#9<0?i6*>6;7e?!472<<0(?m5b:&1a?0<,:91m6*<6;38 62=<2.??789;%6b>0=#:10j7)<6:19'25<53-<26;o4$0;90`=#9k0=46*>8;46?!7f2??0(<k53:k1e?6=,<k1;?5+5d85<>=n:m0;6);n:608 0>=>11/9h498:9j61<72-?j6:<4$4g92==<a;l1<7*:a;51?!3>2?20(8k56998m34=83.>m79=;%7f>3><3`>=6=4+5`840>"203<37);8:7:8?l2>290/9l483:&6<?0?3-?<6;64;h6g>5<#=h0<>6*:8;4;?>o303:1(8o5739'1=<1021b8:4?:%7b>24<,<21:554i7394?"2i3=97);7:7:8 0c=>110c>>50;&6e?153-?n6;64$05964=<g:=1<7*:a;51?>i403:1(8o57398k6?=83.>m79=;:m0e?6=,<k1;?54o2`94?"2i3=976a=5;29 0g=?;1/9h498:9l14<72-?j6:<4$4g92==<g=i1<7*:a;51?>i3j3:1(8o5729'12<1021d?n4?:%7b>24<3f9o6=4+5`846>=h;l0;6);n:608?j5a290/9l482:9l05<72-?j6:<4;n62>5<#=h0<>65`2383>!3f2>807pl<2;296?6=8r.>h7<>;h6e>5<#=h0<>6*:e;4;?>i2=3:1(8o5739'1`<1021v?l50;3x90e=:h1/:94;f:p62<72;q69n4=4:?6g?423ty=?7>51z?6g?053-<?69h4}r12>5<5s4?h6>>4=2090c=z{<81<7?t=4a914=#>=0>96s|3483>4}:;;0>96*94;76?x{i:h0;6<urn3`94?7|ug8h6=4>{|l1`?6=9rwe>h4?:0y~j7`=83;pqpsr@AAx73<d?l:;i5?r@A@x4xFGXrwKL
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
# Date: Wed Jul 08 14:34:38 2009
|
||||
SET addpads = False
|
||||
SET asysymbol = False
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = False
|
||||
SET designentry = Verilog
|
||||
SET device = xc5vlx50t
|
||||
SET devicefamily = virtex5
|
||||
SET flowvendor = Other
|
||||
SET formalverification = False
|
||||
SET foundationsym = False
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = ff1136
|
||||
SET removerpms = False
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -1
|
||||
SET verilogsim = True
|
||||
SET vhdlsim = False
|
||||
SET workingdirectory = D:\mydev\FPGA\xapp859_sora\fpga\ip_cores\coregen_DCMs\tmp
|
||||
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
##############################################################
|
||||
##############################################################
|
||||
##############################################################
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET createndf = false
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET workingdirectory = ./tmp/
|
||||
SET designentry = Verilog
|
||||
SET BusFormat = BusFormatAngleBracketNotRipped
|
||||
SET devicefamily = virtex5
|
||||
SET device = xc5vlx110t
|
||||
SET package = ff1136
|
||||
SET speedgrade = -1
|
||||
SET FlowVendor = Foundation_ISE
|
||||
SET VerilogSim = True
|
||||
SET VHDLSim = True
|
||||
SELECT Fifo_Generator family Xilinx,_Inc. 4.4
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=false
|
||||
CSET component_name=Egress_data_FIFO
|
||||
CSET data_count=false
|
||||
CSET data_count_width=11
|
||||
CSET disable_timing_violations=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=2
|
||||
CSET empty_threshold_negate_value=7
|
||||
CSET enable_ecc=false
|
||||
CSET enable_int_clk=false
|
||||
CSET fifo_implementation=Common_Clock_Block_RAM
|
||||
CSET full_flags_reset_value=1
|
||||
CSET full_threshold_assert_value=1024
|
||||
CSET full_threshold_negate_value=1023
|
||||
CSET input_data_width=128
|
||||
CSET input_depth=2048
|
||||
CSET output_data_width=128
|
||||
CSET output_depth=2048
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET performance_options=Standard_FIFO
|
||||
CSET programmable_empty_type=Multiple_Programmable_Empty_Threshold_Constants
|
||||
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=11
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=false
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=11
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
##############################################################
|
||||
##############################################################
|
||||
##############################################################
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET createndf = false
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET workingdirectory = ./tmp/
|
||||
SET designentry = Verilog
|
||||
SET BusFormat = BusFormatAngleBracketNotRipped
|
||||
SET devicefamily = virtex5
|
||||
SET device = xc5vlx110t
|
||||
SET package = ff1136
|
||||
SET speedgrade = -1
|
||||
SET FlowVendor = Foundation_ISE
|
||||
SET VerilogSim = True
|
||||
SET VHDLSim = True
|
||||
SELECT Fifo_Generator family Xilinx,_Inc. 6.2
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=false
|
||||
CSET component_name=FromDDR_addr_cntrl_fifo
|
||||
CSET data_count=false
|
||||
CSET data_count_width=5
|
||||
CSET disable_timing_violations=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=2
|
||||
CSET empty_threshold_negate_value=3
|
||||
CSET enable_ecc=false
|
||||
CSET enable_int_clk=false
|
||||
CSET enable_reset_synchronization=true
|
||||
CSET fifo_implementation=Common_Clock_Block_RAM
|
||||
CSET full_flags_reset_value=0
|
||||
CSET full_threshold_assert_value=30
|
||||
CSET full_threshold_negate_value=29
|
||||
CSET inject_dbit_error=false
|
||||
CSET inject_sbit_error=false
|
||||
CSET input_data_width=32
|
||||
CSET input_depth=32
|
||||
CSET output_data_width=32
|
||||
CSET output_depth=32
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET performance_options=Standard_FIFO
|
||||
CSET programmable_empty_type=No_Programmable_Empty_Threshold
|
||||
CSET programmable_full_type=No_Programmable_Full_Threshold
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=5
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=false
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=5
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 12.2
|
||||
# Date: Mon Dec 24 07:15:39 2012
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Advanced
|
||||
SET device = xc5vlx50t
|
||||
SET devicefamily = virtex5
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = ff1136
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -1
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = true
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Fifo_Generator family Xilinx,_Inc. 6.2
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=false
|
||||
CSET component_name=RCB_FRL_RX_Data_FIFO_onechannel
|
||||
CSET data_count=false
|
||||
CSET data_count_width=7
|
||||
CSET disable_timing_violations=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=7
|
||||
CSET empty_threshold_negate_value=8
|
||||
CSET enable_ecc=false
|
||||
CSET enable_int_clk=false
|
||||
CSET enable_reset_synchronization=true
|
||||
CSET fifo_implementation=Common_Clock_Distributed_RAM
|
||||
CSET full_flags_reset_value=1
|
||||
CSET full_threshold_assert_value=126
|
||||
CSET full_threshold_negate_value=125
|
||||
CSET inject_dbit_error=false
|
||||
CSET inject_sbit_error=false
|
||||
CSET input_data_width=8
|
||||
CSET input_depth=128
|
||||
CSET output_data_width=8
|
||||
CSET output_depth=128
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET performance_options=Standard_FIFO
|
||||
CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant
|
||||
CSET programmable_full_type=No_Programmable_Full_Threshold
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=7
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=false
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=7
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: 827246ed
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
##############################################################
|
||||
##############################################################
|
||||
##############################################################
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET createndf = false
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET workingdirectory = ./tmp/
|
||||
SET designentry = Verilog
|
||||
SET BusFormat = BusFormatAngleBracketNotRipped
|
||||
SET devicefamily = virtex5
|
||||
SET device = xc5vlx50t
|
||||
SET package = ff1136
|
||||
SET speedgrade = -1
|
||||
SET FlowVendor = Foundation_ISE
|
||||
SET VerilogSim = True
|
||||
SET VHDLSim = True
|
||||
SELECT Fifo_Generator family Xilinx,_Inc. 4.4
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=false
|
||||
CSET component_name=RX_TS_fifo
|
||||
CSET data_count=false
|
||||
CSET data_count_width=9
|
||||
CSET disable_timing_violations=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=2
|
||||
CSET empty_threshold_negate_value=3
|
||||
CSET enable_ecc=false
|
||||
CSET enable_int_clk=false
|
||||
CSET fifo_implementation=Independent_Clocks_Block_RAM
|
||||
CSET full_flags_reset_value=1
|
||||
CSET full_threshold_assert_value=509
|
||||
CSET full_threshold_negate_value=508
|
||||
CSET input_data_width=32
|
||||
CSET input_depth=512
|
||||
CSET output_data_width=32
|
||||
CSET output_depth=512
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET performance_options=Standard_FIFO
|
||||
CSET programmable_empty_type=No_Programmable_Empty_Threshold
|
||||
CSET programmable_full_type=No_Programmable_Full_Threshold
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=9
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=false
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=9
|
||||
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version K.39
|
||||
# Date: Wed Apr 21 08:07:09 2010
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = False
|
||||
SET asysymbol = True
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = False
|
||||
SET designentry = VHDL
|
||||
SET device = xc5vlx50t
|
||||
SET devicefamily = virtex5
|
||||
SET flowvendor = Foundation_iSE
|
||||
SET formalverification = False
|
||||
SET foundationsym = False
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = ff1136
|
||||
SET removerpms = False
|
||||
SET simulationfiles = Structural
|
||||
SET speedgrade = -1
|
||||
SET verilogsim = True
|
||||
SET vhdlsim = True
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Fifo_Generator family Xilinx,_Inc. 4.4
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=false
|
||||
CSET component_name=RX_data_fifo
|
||||
CSET data_count=false
|
||||
CSET data_count_width=10
|
||||
CSET disable_timing_violations=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=13
|
||||
CSET empty_threshold_negate_value=14
|
||||
CSET enable_ecc=false
|
||||
CSET enable_int_clk=false
|
||||
CSET fifo_implementation=Independent_Clocks_Block_RAM
|
||||
CSET full_flags_reset_value=0
|
||||
CSET full_threshold_assert_value=1021
|
||||
CSET full_threshold_negate_value=1020
|
||||
CSET input_data_width=32
|
||||
CSET input_depth=1024
|
||||
CSET output_data_width=64
|
||||
CSET output_depth=512
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET performance_options=Standard_FIFO
|
||||
CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant
|
||||
CSET programmable_full_type=No_Programmable_Full_Threshold
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=9
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=false
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=10
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: 1d62a76c
|
||||
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
##############################################################
|
||||
##############################################################
|
||||
##############################################################
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET createndf = false
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET workingdirectory = ./tmp/
|
||||
SET designentry = Verilog
|
||||
SET BusFormat = BusFormatAngleBracketNotRipped
|
||||
SET devicefamily = virtex5
|
||||
SET device = xc5vlx110t
|
||||
SET package = ff1136
|
||||
SET speedgrade = -1
|
||||
SET FlowVendor = Foundation_ISE
|
||||
SET VerilogSim = True
|
||||
SET VHDLSim = True
|
||||
SELECT Fifo_Generator family Xilinx,_Inc. 4.4
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=false
|
||||
CSET component_name=TX_MSG_fifo
|
||||
CSET data_count=false
|
||||
CSET data_count_width=9
|
||||
CSET disable_timing_violations=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=2
|
||||
CSET empty_threshold_negate_value=3
|
||||
CSET enable_ecc=false
|
||||
CSET enable_int_clk=false
|
||||
CSET fifo_implementation=Independent_Clocks_Block_RAM
|
||||
CSET full_flags_reset_value=1
|
||||
CSET full_threshold_assert_value=500
|
||||
CSET full_threshold_negate_value=499
|
||||
CSET input_data_width=40
|
||||
CSET input_depth=512
|
||||
CSET output_data_width=40
|
||||
CSET output_depth=512
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET performance_options=Standard_FIFO
|
||||
CSET programmable_empty_type=No_Programmable_Empty_Threshold
|
||||
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=9
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=false
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=9
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
##############################################################
|
||||
##############################################################
|
||||
##############################################################
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET createndf = false
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET workingdirectory = ./tmp/
|
||||
SET designentry = Verilog
|
||||
SET BusFormat = BusFormatAngleBracketNotRipped
|
||||
SET devicefamily = virtex5
|
||||
SET device = xc5vlx110t
|
||||
SET package = ff1136
|
||||
SET speedgrade = -1
|
||||
SET FlowVendor = Foundation_ISE
|
||||
SET VerilogSim = True
|
||||
SET VHDLSim = True
|
||||
SELECT Fifo_Generator family Xilinx,_Inc. 6.2
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=true
|
||||
CSET component_name=ToFRL_data_fifo
|
||||
CSET data_count=false
|
||||
CSET data_count_width=12
|
||||
CSET disable_timing_violations=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=7
|
||||
CSET empty_threshold_negate_value=8
|
||||
CSET enable_ecc=false
|
||||
CSET enable_int_clk=false
|
||||
CSET enable_reset_synchronization=true
|
||||
CSET fifo_implementation=Independent_Clocks_Block_RAM
|
||||
CSET full_flags_reset_value=1
|
||||
CSET full_threshold_assert_value=1980
|
||||
CSET full_threshold_negate_value=1979
|
||||
CSET inject_dbit_error=false
|
||||
CSET inject_sbit_error=false
|
||||
CSET input_data_width=128
|
||||
CSET input_depth=4096
|
||||
CSET output_data_width=32
|
||||
CSET output_depth=16384
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET performance_options=Standard_FIFO
|
||||
CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant
|
||||
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=14
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=false
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=12
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version K.39
|
||||
# Date: Wed Apr 21 08:34:04 2010
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = False
|
||||
SET asysymbol = True
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = False
|
||||
SET designentry = Verilog
|
||||
SET device = xc5vlx50t
|
||||
SET devicefamily = virtex5
|
||||
SET flowvendor = Foundation_iSE
|
||||
SET formalverification = False
|
||||
SET foundationsym = False
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = ff1136
|
||||
SET removerpms = False
|
||||
SET simulationfiles = Structural
|
||||
SET speedgrade = -1
|
||||
SET verilogsim = True
|
||||
SET vhdlsim = False
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Fifo_Generator family Xilinx,_Inc. 4.3
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=false
|
||||
CSET component_name=a64_128_distram_fifo
|
||||
CSET data_count=false
|
||||
CSET data_count_width=7
|
||||
CSET disable_timing_violations=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=2
|
||||
CSET empty_threshold_negate_value=3
|
||||
CSET enable_ecc=false
|
||||
CSET enable_int_clk=false
|
||||
CSET fifo_implementation=Common_Clock_Distributed_RAM
|
||||
CSET full_flags_reset_value=1
|
||||
CSET full_threshold_assert_value=126
|
||||
CSET full_threshold_negate_value=125
|
||||
CSET input_data_width=64
|
||||
CSET input_depth=128
|
||||
CSET output_data_width=64
|
||||
CSET output_depth=128
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET performance_options=Standard_FIFO
|
||||
CSET programmable_empty_type=No_Programmable_Empty_Threshold
|
||||
CSET programmable_full_type=No_Programmable_Full_Threshold
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=7
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=false
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=7
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: 4f5f05ca
|
||||
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version K.39
|
||||
# Date: Wed Apr 21 08:35:00 2010
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = False
|
||||
SET asysymbol = True
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = False
|
||||
SET designentry = Verilog
|
||||
SET device = xc5vlx50t
|
||||
SET devicefamily = virtex5
|
||||
SET flowvendor = Foundation_iSE
|
||||
SET formalverification = False
|
||||
SET foundationsym = False
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = ff1136
|
||||
SET removerpms = False
|
||||
SET simulationfiles = Structural
|
||||
SET speedgrade = -1
|
||||
SET verilogsim = True
|
||||
SET vhdlsim = False
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Fifo_Generator family Xilinx,_Inc. 4.3
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=false
|
||||
CSET component_name=a64_64_distram_fifo
|
||||
CSET data_count=false
|
||||
CSET data_count_width=6
|
||||
CSET disable_timing_violations=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=2
|
||||
CSET empty_threshold_negate_value=3
|
||||
CSET enable_ecc=false
|
||||
CSET enable_int_clk=false
|
||||
CSET fifo_implementation=Common_Clock_Distributed_RAM
|
||||
CSET full_flags_reset_value=1
|
||||
CSET full_threshold_assert_value=62
|
||||
CSET full_threshold_negate_value=61
|
||||
CSET input_data_width=64
|
||||
CSET input_depth=64
|
||||
CSET output_data_width=64
|
||||
CSET output_depth=64
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET performance_options=Standard_FIFO
|
||||
CSET programmable_empty_type=No_Programmable_Empty_Threshold
|
||||
CSET programmable_full_type=No_Programmable_Full_Threshold
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=6
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=false
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=6
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: 8da9da97
|
||||
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version K.39
|
||||
# Date: Wed Apr 21 08:00:31 2010
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = False
|
||||
SET asysymbol = True
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = False
|
||||
SET designentry = VHDL
|
||||
SET device = xc5vlx50t
|
||||
SET devicefamily = virtex5
|
||||
SET flowvendor = Foundation_iSE
|
||||
SET formalverification = False
|
||||
SET foundationsym = False
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = ff1136
|
||||
SET removerpms = False
|
||||
SET simulationfiles = Structural
|
||||
SET speedgrade = -1
|
||||
SET verilogsim = True
|
||||
SET vhdlsim = True
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Fifo_Generator family Xilinx,_Inc. 4.4
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=false
|
||||
CSET component_name=data_trn_dma_write_fifo
|
||||
CSET data_count=false
|
||||
CSET data_count_width=9
|
||||
CSET disable_timing_violations=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=2
|
||||
CSET empty_threshold_negate_value=3
|
||||
CSET enable_ecc=false
|
||||
CSET enable_int_clk=false
|
||||
CSET fifo_implementation=Common_Clock_Block_RAM
|
||||
CSET full_flags_reset_value=0
|
||||
CSET full_threshold_assert_value=480
|
||||
CSET full_threshold_negate_value=479
|
||||
CSET input_data_width=64
|
||||
CSET input_depth=512
|
||||
CSET output_data_width=64
|
||||
CSET output_depth=512
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET performance_options=Standard_FIFO
|
||||
CSET programmable_empty_type=No_Programmable_Empty_Threshold
|
||||
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=9
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=false
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=9
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: 3a08a743
|
||||
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version K.39
|
||||
# Date: Wed Apr 21 08:01:18 2010
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = False
|
||||
SET asysymbol = True
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = False
|
||||
SET designentry = VHDL
|
||||
SET device = xc5vlx50t
|
||||
SET devicefamily = virtex5
|
||||
SET flowvendor = Foundation_iSE
|
||||
SET formalverification = False
|
||||
SET foundationsym = False
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = ff1136
|
||||
SET removerpms = False
|
||||
SET simulationfiles = Structural
|
||||
SET speedgrade = -1
|
||||
SET verilogsim = True
|
||||
SET vhdlsim = True
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Fifo_Generator family Xilinx,_Inc. 4.3
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=false
|
||||
CSET component_name=data_trn_mem_fifo
|
||||
CSET data_count=false
|
||||
CSET data_count_width=10
|
||||
CSET disable_timing_violations=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=2
|
||||
CSET empty_threshold_negate_value=3
|
||||
CSET enable_ecc=false
|
||||
CSET enable_int_clk=false
|
||||
CSET fifo_implementation=Independent_Clocks_Block_RAM
|
||||
CSET full_flags_reset_value=1
|
||||
CSET full_threshold_assert_value=1021
|
||||
CSET full_threshold_negate_value=1020
|
||||
CSET input_data_width=64
|
||||
CSET input_depth=1024
|
||||
CSET output_data_width=128
|
||||
CSET output_depth=512
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET performance_options=Standard_FIFO
|
||||
CSET programmable_empty_type=No_Programmable_Empty_Threshold
|
||||
CSET programmable_full_type=No_Programmable_Full_Threshold
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=9
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=false
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=10
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: 3efab682
|
||||
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version K.39
|
||||
# Date: Wed Apr 21 08:02:08 2010
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = False
|
||||
SET asysymbol = True
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = False
|
||||
SET designentry = VHDL
|
||||
SET device = xc5vlx50t
|
||||
SET devicefamily = virtex5
|
||||
SET flowvendor = Foundation_iSE
|
||||
SET formalverification = False
|
||||
SET foundationsym = False
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = ff1136
|
||||
SET removerpms = False
|
||||
SET simulationfiles = Structural
|
||||
SET speedgrade = -1
|
||||
SET verilogsim = True
|
||||
SET vhdlsim = True
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Distributed_Memory_Generator family Xilinx,_Inc. 3.4
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET ce_overrides=ce_overrides_sync_controls
|
||||
CSET coefficient_file=no_coe_file_loaded
|
||||
CSET common_output_ce=false
|
||||
CSET common_output_clk=false
|
||||
CSET component_name=dualport_32x32_compram
|
||||
CSET data_width=32
|
||||
CSET default_data=0
|
||||
CSET default_data_radix=16
|
||||
CSET depth=32
|
||||
CSET dual_port_address=non_registered
|
||||
CSET dual_port_output_clock_enable=false
|
||||
CSET input_clock_enable=false
|
||||
CSET input_options=non_registered
|
||||
CSET memory_type=dual_port_ram
|
||||
CSET output_options=non_registered
|
||||
CSET pipeline_stages=0
|
||||
CSET qualify_we_with_i_ce=false
|
||||
CSET reset_qdpo=false
|
||||
CSET reset_qspo=false
|
||||
CSET single_port_output_clock_enable=false
|
||||
CSET sync_reset_qdpo=false
|
||||
CSET sync_reset_qspo=false
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: badf2081
|
||||
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
##############################################################
|
||||
##############################################################
|
||||
##############################################################
|
||||
SET designentry = Verilog
|
||||
SET BusFormat = BusFormatAngleBracketNotRipped
|
||||
SET devicefamily = virtex5
|
||||
SET device = xc5vlx110t
|
||||
SET package = ff1136
|
||||
SET speedgrade = -1
|
||||
SET FlowVendor = Foundation_ISE
|
||||
SET VerilogSim = True
|
||||
SET VHDLSim = True
|
||||
SELECT Fifo_Generator family Xilinx,_Inc. 4.4
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=false
|
||||
CSET component_name=egress_addr_cntrl_fifo
|
||||
CSET data_count=false
|
||||
CSET data_count_width=4
|
||||
CSET disable_timing_violations=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=2
|
||||
CSET empty_threshold_negate_value=3
|
||||
CSET enable_ecc=false
|
||||
CSET enable_int_clk=false
|
||||
CSET fifo_implementation=Independent_Clocks_Distributed_RAM
|
||||
CSET full_flags_reset_value=1
|
||||
CSET full_threshold_assert_value=13
|
||||
CSET full_threshold_negate_value=12
|
||||
CSET input_data_width=32
|
||||
CSET input_depth=16
|
||||
CSET output_data_width=32
|
||||
CSET output_depth=16
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET performance_options=Standard_FIFO
|
||||
CSET programmable_empty_type=No_Programmable_Empty_Threshold
|
||||
CSET programmable_full_type=No_Programmable_Full_Threshold
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=4
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=false
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=4
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
##############################################################
|
||||
##############################################################
|
||||
##############################################################
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET createndf = false
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET workingdirectory = ./tmp/
|
||||
SET designentry = Verilog
|
||||
SET BusFormat = BusFormatAngleBracketNotRipped
|
||||
SET devicefamily = virtex5
|
||||
SET device = xc5vlx50t
|
||||
SET package = ff1136
|
||||
SET speedgrade = -1
|
||||
SET FlowVendor = Foundation_ISE
|
||||
SET VerilogSim = True
|
||||
SET VHDLSim = True
|
||||
SELECT Fifo_Generator family Xilinx,_Inc. 4.4
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=false
|
||||
CSET component_name=ingress_addr_cntrl_fifo
|
||||
CSET data_count=false
|
||||
CSET data_count_width=7
|
||||
CSET disable_timing_violations=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=2
|
||||
CSET empty_threshold_negate_value=3
|
||||
CSET enable_ecc=false
|
||||
CSET enable_int_clk=false
|
||||
CSET fifo_implementation=Independent_Clocks_Distributed_RAM
|
||||
CSET full_flags_reset_value=1
|
||||
CSET full_threshold_assert_value=64
|
||||
CSET full_threshold_negate_value=63
|
||||
CSET input_data_width=32
|
||||
CSET input_depth=128
|
||||
CSET output_data_width=32
|
||||
CSET output_depth=128
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET performance_options=Standard_FIFO
|
||||
CSET programmable_empty_type=No_Programmable_Empty_Threshold
|
||||
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=7
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=false
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=7
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
##############################################################
|
||||
##############################################################
|
||||
##############################################################
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET createndf = false
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET workingdirectory = ./tmp/
|
||||
SET designentry = Verilog
|
||||
SET BusFormat = BusFormatAngleBracketNotRipped
|
||||
SET devicefamily = virtex5
|
||||
SET device = xc5vlx110t
|
||||
SET package = ff1136
|
||||
SET speedgrade = -1
|
||||
SET FlowVendor = Foundation_ISE
|
||||
SET VerilogSim = True
|
||||
SET VHDLSim = True
|
||||
SELECT Fifo_Generator family Xilinx,_Inc. 4.4
|
||||
CSET almost_empty_flag=true
|
||||
CSET almost_full_flag=false
|
||||
CSET component_name=ingress_data_fifo
|
||||
CSET data_count=false
|
||||
CSET data_count_width=9
|
||||
CSET disable_timing_violations=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=256
|
||||
CSET empty_threshold_negate_value=257
|
||||
CSET enable_ecc=false
|
||||
CSET enable_int_clk=false
|
||||
CSET fifo_implementation=Independent_Clocks_Block_RAM
|
||||
CSET full_flags_reset_value=0
|
||||
CSET full_threshold_assert_value=450
|
||||
CSET full_threshold_negate_value=449
|
||||
CSET input_data_width=128
|
||||
CSET input_depth=512
|
||||
CSET output_data_width=128
|
||||
CSET output_depth=512
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET performance_options=Standard_FIFO
|
||||
CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant
|
||||
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=9
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=false
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=9
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version K.39
|
||||
# Date: Wed Apr 21 08:09:03 2010
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = False
|
||||
SET asysymbol = True
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = False
|
||||
SET designentry = VHDL
|
||||
SET device = xc5vlx50t
|
||||
SET devicefamily = virtex5
|
||||
SET flowvendor = Foundation_iSE
|
||||
SET formalverification = False
|
||||
SET foundationsym = False
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = ff1136
|
||||
SET removerpms = False
|
||||
SET simulationfiles = Structural
|
||||
SET speedgrade = -1
|
||||
SET verilogsim = True
|
||||
SET vhdlsim = True
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Fifo_Generator family Xilinx,_Inc. 4.3
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET almost_empty_flag=false
|
||||
CSET almost_full_flag=false
|
||||
CSET component_name=xfer_trn_mem_fifo
|
||||
CSET data_count=false
|
||||
CSET data_count_width=7
|
||||
CSET disable_timing_violations=false
|
||||
CSET dout_reset_value=0
|
||||
CSET empty_threshold_assert_value=2
|
||||
CSET empty_threshold_negate_value=3
|
||||
CSET enable_ecc=false
|
||||
CSET enable_int_clk=false
|
||||
CSET fifo_implementation=Common_Clock_Distributed_RAM
|
||||
CSET full_flags_reset_value=1
|
||||
CSET full_threshold_assert_value=126
|
||||
CSET full_threshold_negate_value=125
|
||||
CSET input_data_width=34
|
||||
CSET input_depth=128
|
||||
CSET output_data_width=34
|
||||
CSET output_depth=128
|
||||
CSET overflow_flag=false
|
||||
CSET overflow_sense=Active_High
|
||||
CSET performance_options=Standard_FIFO
|
||||
CSET programmable_empty_type=No_Programmable_Empty_Threshold
|
||||
CSET programmable_full_type=No_Programmable_Full_Threshold
|
||||
CSET read_clock_frequency=1
|
||||
CSET read_data_count=false
|
||||
CSET read_data_count_width=7
|
||||
CSET reset_pin=true
|
||||
CSET reset_type=Asynchronous_Reset
|
||||
CSET underflow_flag=false
|
||||
CSET underflow_sense=Active_High
|
||||
CSET use_dout_reset=true
|
||||
CSET use_embedded_registers=false
|
||||
CSET use_extra_logic=false
|
||||
CSET valid_flag=false
|
||||
CSET valid_sense=Active_High
|
||||
CSET write_acknowledge_flag=false
|
||||
CSET write_acknowledge_sense=Active_High
|
||||
CSET write_clock_frequency=1
|
||||
CSET write_data_count=false
|
||||
CSET write_data_count_width=7
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: 447276d9
|
||||
|
||||
|
|
@ -0,0 +1,233 @@
|
|||
//*****************************************************************************
|
||||
// Copyright (c) 2006 Xilinx, Inc.
|
||||
// This design is confidential and proprietary of Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
//*****************************************************************************
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version: $Name: i+IP+125372 $
|
||||
// \ \ Application: MIG
|
||||
// / / Filename: mem_interface_top.v
|
||||
// /___/ /\ Date Last Modified: $Date: 2007/04/18 13:49:32 $
|
||||
// \ \ / \ Date Created: Wed Aug 16 2006
|
||||
// \___\/\___\
|
||||
//
|
||||
//Device: Virtex-5
|
||||
//Design Name: DDR2
|
||||
//Purpose:
|
||||
// Top-level module. Simple model for what the user might use
|
||||
// Typically, the user will only instantiate MEM_INTERFACE_TOP in their
|
||||
// code, and generate all the other infrastructure and backend logic
|
||||
// separately. This module serves both as an example, and allows the user
|
||||
// to synthesize a self-contained design, which they can use to test their
|
||||
// hardware.
|
||||
// In addition to the memory controller, the module instantiates:
|
||||
// 1. Clock generation/distribution, reset logic
|
||||
// 2. IDELAY control block
|
||||
// 3. Synthesizable testbench - used to model user's backend logic
|
||||
//Reference:
|
||||
//Revision History:
|
||||
//*****************************************************************************
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module mem_interface_top #
|
||||
(
|
||||
parameter BANK_WIDTH = 3, // # of memory bank addr bits
|
||||
parameter CKE_WIDTH = 1, // # of memory clock enable outputs
|
||||
parameter CLK_WIDTH = 1, // # of clock outputs
|
||||
parameter COL_WIDTH = 10, // # of memory column bits
|
||||
parameter CS_NUM = 1, // # of separate memory chip selects
|
||||
parameter CS_WIDTH = 1, // # of total memory chip selects
|
||||
parameter CS_BITS = 0, // set to log2(CS_NUM) (rounded up)
|
||||
parameter DM_WIDTH = 9, // # of data mask bits
|
||||
parameter DQ_WIDTH = 72, // # of data width
|
||||
parameter DQ_PER_DQS = 8, // # of DQ data bits per strobe
|
||||
parameter DQS_WIDTH = 9, // # of DQS strobes
|
||||
parameter DQ_BITS = 7, // set to log2(DQS_WIDTH*DQ_PER_DQS)
|
||||
parameter DQS_BITS = 4, // set to log2(DQS_WIDTH)
|
||||
parameter ODT_WIDTH = 1, // # of memory on-die term enables
|
||||
parameter ROW_WIDTH = 14, // # of memory row and # of addr bits
|
||||
parameter ADDITIVE_LAT = 0, // additive write latency
|
||||
parameter BURST_LEN = 4, // burst length (in double words)
|
||||
parameter BURST_TYPE = 0, // burst type (=0 seq; =1 interleaved)
|
||||
parameter CAS_LAT = 3, // CAS latency
|
||||
parameter ECC_ENABLE = 0, // enable ECC (=1 enable)
|
||||
parameter MULTI_BANK_EN = 1, // Keeps multiple banks open. (= 1 enable)
|
||||
parameter ODT_TYPE = 0, // ODT (=0(none),=1(75),=2(150),=3(50))
|
||||
parameter REDUCE_DRV = 0, // reduced strength mem I/O (=1 yes)
|
||||
parameter REG_ENABLE = 1, // registered addr/ctrl (=1 yes)
|
||||
parameter TREFI_NS = 7800, // auto refresh interval (uS)
|
||||
parameter TRAS = 40000, // active->precharge delay
|
||||
parameter TRCD = 15000, // active->read/write delay
|
||||
parameter TRFC = 127500, // refresh->refresh, refresh->active delay
|
||||
parameter TRP = 15000, // precharge->command delay
|
||||
parameter TRTP = 7500, // read->precharge delay
|
||||
parameter TWR = 15000, // used to determine write->precharge
|
||||
parameter TWTR = 10000, // write->read delay
|
||||
parameter IDEL_HIGH_PERF = "TRUE", // # initial # taps for DQ IDELAY
|
||||
parameter SIM_ONLY = 0, // = 1 to skip SDRAM power up delay
|
||||
parameter CLK_PERIOD = 5000, // Core/Memory clock period (in ps)
|
||||
parameter RST_ACT_LOW = 1, // =1 for active low reset, =0 for active high
|
||||
parameter DLL_FREQ_MODE = "HIGH" // DCM Frequency range
|
||||
)
|
||||
(
|
||||
inout [DQ_WIDTH-1:0] ddr2_dq,
|
||||
output [ROW_WIDTH-1:0] ddr2_a,
|
||||
output [BANK_WIDTH-1:0] ddr2_ba,
|
||||
output ddr2_ras_n,
|
||||
output ddr2_cas_n,
|
||||
output ddr2_we_n,
|
||||
output [CS_WIDTH-1:0] ddr2_cs_n,
|
||||
output [ODT_WIDTH-1:0] ddr2_odt,
|
||||
output [CKE_WIDTH-1:0] ddr2_cke,
|
||||
output ddr2_reset_n,
|
||||
output [DM_WIDTH-1:0] ddr2_dm,
|
||||
//// input sys_clk_p,
|
||||
//// input sys_clk_n,
|
||||
input sys_clk,
|
||||
input clk200_p,
|
||||
input clk200_n,
|
||||
/// Jiansong: 200MHz clock output
|
||||
output clk200_o,
|
||||
input sys_rst_n,
|
||||
output phy_init_done,
|
||||
output rst0_tb,
|
||||
output clk0_tb,
|
||||
output app_wdf_afull,
|
||||
output app_af_afull,
|
||||
output rd_data_valid,
|
||||
input app_wdf_wren,
|
||||
input app_af_wren,
|
||||
input [30:0] app_af_addr,
|
||||
input [2:0] app_af_cmd,
|
||||
output [(2*DQ_WIDTH)-1:0] rd_data_fifo_out,
|
||||
input [(2*DQ_WIDTH)-1:0] app_wdf_data,
|
||||
input [(2*DM_WIDTH)-1:0] app_wdf_mask_data,
|
||||
inout [DQS_WIDTH-1:0] ddr2_dqs,
|
||||
inout [DQS_WIDTH-1:0] ddr2_dqs_n,
|
||||
output [CLK_WIDTH-1:0] ddr2_ck,
|
||||
output [CLK_WIDTH-1:0] ddr2_ck_n
|
||||
);
|
||||
|
||||
wire rst0;
|
||||
wire rst90;
|
||||
wire rst200;
|
||||
wire clk0;
|
||||
wire clk90;
|
||||
wire clk200;
|
||||
wire idelay_ctrl_rdy;
|
||||
|
||||
//***************************************************************************
|
||||
assign rst0_tb = rst0;
|
||||
assign clk0_tb = clk0;
|
||||
assign ddr2_reset_n= ~rst0;
|
||||
|
||||
/// Jiansong:
|
||||
assign clk200_o = clk200;
|
||||
|
||||
mem_interface_top_idelay_ctrl u_idelay_ctrl
|
||||
(
|
||||
.rst200(rst200),
|
||||
.clk200(clk200),
|
||||
.idelay_ctrl_rdy(idelay_ctrl_rdy)
|
||||
);
|
||||
|
||||
mem_interface_top_infrastructure #
|
||||
(
|
||||
.CLK_PERIOD(CLK_PERIOD),
|
||||
.RST_ACT_LOW(RST_ACT_LOW),
|
||||
.DLL_FREQ_MODE(DLL_FREQ_MODE)
|
||||
)
|
||||
u_infrastructure
|
||||
(
|
||||
//// .sys_clk_p(sys_clk_p),
|
||||
//// .sys_clk_n(sys_clk_n),
|
||||
.sys_clk(sys_clk),
|
||||
.clk200_p(clk200_p),
|
||||
.clk200_n(clk200_n),
|
||||
.sys_rst_n(sys_rst_n),
|
||||
.rst0(rst0),
|
||||
.rst90(rst90),
|
||||
.rst200(rst200),
|
||||
.clk0(clk0),
|
||||
.clk90(clk90),
|
||||
.clk200(clk200),
|
||||
.idelay_ctrl_rdy(idelay_ctrl_rdy)
|
||||
);
|
||||
|
||||
mem_interface_top_ddr2_top_0 #
|
||||
(
|
||||
.BANK_WIDTH(BANK_WIDTH),
|
||||
.CKE_WIDTH(CKE_WIDTH),
|
||||
.CLK_WIDTH(CLK_WIDTH),
|
||||
.COL_WIDTH(COL_WIDTH),
|
||||
.CS_NUM(CS_NUM),
|
||||
.CS_WIDTH(CS_WIDTH),
|
||||
.CS_BITS(CS_BITS),
|
||||
.DM_WIDTH(DM_WIDTH),
|
||||
.DQ_WIDTH(DQ_WIDTH),
|
||||
.DQ_PER_DQS(DQ_PER_DQS),
|
||||
.DQS_WIDTH(DQS_WIDTH),
|
||||
.DQ_BITS(DQ_BITS),
|
||||
.DQS_BITS(DQS_BITS),
|
||||
.ODT_WIDTH(ODT_WIDTH),
|
||||
.ROW_WIDTH(ROW_WIDTH),
|
||||
.ADDITIVE_LAT(ADDITIVE_LAT),
|
||||
.BURST_LEN(BURST_LEN),
|
||||
.BURST_TYPE(BURST_TYPE),
|
||||
.CAS_LAT(CAS_LAT),
|
||||
.ECC_ENABLE(ECC_ENABLE),
|
||||
.MULTI_BANK_EN(MULTI_BANK_EN),
|
||||
.ODT_TYPE(ODT_TYPE),
|
||||
.REDUCE_DRV(REDUCE_DRV),
|
||||
.REG_ENABLE(REG_ENABLE),
|
||||
.TREFI_NS(TREFI_NS),
|
||||
.TRAS(TRAS),
|
||||
.TRCD(TRCD),
|
||||
.TRFC(TRFC),
|
||||
.TRP(TRP),
|
||||
.TRTP(TRTP),
|
||||
.TWR(TWR),
|
||||
.TWTR(TWTR),
|
||||
.IDEL_HIGH_PERF(IDEL_HIGH_PERF),
|
||||
.SIM_ONLY(SIM_ONLY),
|
||||
.CLK_PERIOD(CLK_PERIOD)
|
||||
)
|
||||
u_ddr2_top_0
|
||||
(
|
||||
.ddr2_dq(ddr2_dq),
|
||||
.ddr2_a(ddr2_a),
|
||||
.ddr2_ba(ddr2_ba),
|
||||
.ddr2_ras_n(ddr2_ras_n),
|
||||
.ddr2_cas_n(ddr2_cas_n),
|
||||
.ddr2_we_n(ddr2_we_n),
|
||||
.ddr2_cs_n(ddr2_cs_n),
|
||||
.ddr2_odt(ddr2_odt),
|
||||
.ddr2_cke(ddr2_cke),
|
||||
.ddr2_dm(ddr2_dm),
|
||||
.phy_init_done(phy_init_done),
|
||||
.rst0(rst0),
|
||||
.rst90(rst90),
|
||||
.clk0(clk0),
|
||||
.clk90(clk90),
|
||||
.app_wdf_afull(app_wdf_afull),
|
||||
.app_af_afull(app_af_afull),
|
||||
.rd_data_valid(rd_data_valid),
|
||||
.app_wdf_wren(app_wdf_wren),
|
||||
.app_af_wren(app_af_wren),
|
||||
.app_af_addr(app_af_addr),
|
||||
.app_af_cmd(app_af_cmd),
|
||||
.rd_data_fifo_out(rd_data_fifo_out),
|
||||
.app_wdf_data(app_wdf_data),
|
||||
.app_wdf_mask_data(app_wdf_mask_data),
|
||||
.ddr2_dqs(ddr2_dqs),
|
||||
.ddr2_dqs_n(ddr2_dqs_n),
|
||||
.ddr2_ck(ddr2_ck),
|
||||
.ddr2_ck_n(ddr2_ck_n)
|
||||
);
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 12.3
|
||||
# Date: Fri Jun 14 07:19:03 2013
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Advanced
|
||||
SET device = xc5vlx110t
|
||||
SET devicefamily = virtex5
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = ff1136
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -1
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = true
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Endpoint_Block_Plus_for_PCI_Express family Xilinx,_Inc. 1.14
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET acceptable_l0_latency=No_limit
|
||||
CSET acceptable_l1_latency=No_limit
|
||||
CSET advanced_flow_control_credit=Header_Credit
|
||||
CSET aux_max_current=0mA
|
||||
CSET bar0_64bit=false
|
||||
CSET bar0_enabled=true
|
||||
CSET bar0_prefetchable=false
|
||||
CSET bar0_scale=Kilobytes
|
||||
CSET bar0_size=16
|
||||
CSET bar0_type=Memory
|
||||
CSET bar0_value=FFFFC000
|
||||
CSET bar1_64bit=false
|
||||
CSET bar1_enabled=false
|
||||
CSET bar1_prefetchable=false
|
||||
CSET bar1_scale=Kilobytes
|
||||
CSET bar1_size=64
|
||||
CSET bar1_type=IO
|
||||
CSET bar1_value=00000000
|
||||
CSET bar2_64bit=false
|
||||
CSET bar2_enabled=false
|
||||
CSET bar2_prefetchable=false
|
||||
CSET bar2_scale=Kilobytes
|
||||
CSET bar2_size=64
|
||||
CSET bar2_type=IO
|
||||
CSET bar2_value=00000000
|
||||
CSET bar3_64bit=false
|
||||
CSET bar3_enabled=false
|
||||
CSET bar3_prefetchable=false
|
||||
CSET bar3_scale=Kilobytes
|
||||
CSET bar3_size=64
|
||||
CSET bar3_type=IO
|
||||
CSET bar3_value=00000000
|
||||
CSET bar4_64bit=false
|
||||
CSET bar4_enabled=false
|
||||
CSET bar4_prefetchable=false
|
||||
CSET bar4_scale=Kilobytes
|
||||
CSET bar4_size=64
|
||||
CSET bar4_type=IO
|
||||
CSET bar4_value=00000000
|
||||
CSET bar5_enabled=false
|
||||
CSET bar5_prefetchable=false
|
||||
CSET bar5_scale=Kilobytes
|
||||
CSET bar5_size=64
|
||||
CSET bar5_type=IO
|
||||
CSET bar5_value=00000000
|
||||
CSET capabilities_register=0001
|
||||
CSET capability_version=1
|
||||
CSET cardbus_cis_pointer=00000000
|
||||
CSET class_code_base=0B
|
||||
CSET class_code_interface=00
|
||||
CSET class_code_sub=40
|
||||
CSET class_code_value=0B4000
|
||||
CSET component_name=endpoint_blk_plus_v1_14
|
||||
CSET d0_pme_support=false
|
||||
CSET d0_power_consumed=0
|
||||
CSET d0_power_consumed_factor=0
|
||||
CSET d0_power_dissipated=0
|
||||
CSET d0_power_dissipated_factor=0
|
||||
CSET d1_pme_support=false
|
||||
CSET d1_power_consumed=0
|
||||
CSET d1_power_consumed_factor=0
|
||||
CSET d1_power_dissipated=0
|
||||
CSET d1_power_dissipated_factor=0
|
||||
CSET d1_support=false
|
||||
CSET d2_pme_support=false
|
||||
CSET d2_power_consumed=0
|
||||
CSET d2_power_consumed_factor=0
|
||||
CSET d2_power_dissipated=0
|
||||
CSET d2_power_dissipated_factor=0
|
||||
CSET d2_support=false
|
||||
CSET d3_power_consumed=0
|
||||
CSET d3_power_consumed_factor=0
|
||||
CSET d3_power_dissipated=0
|
||||
CSET d3_power_dissipated_factor=0
|
||||
CSET d3cold_pme_support=false
|
||||
CSET d3hot_pme_support=false
|
||||
CSET device_capabilities_register=00000FC2
|
||||
CSET device_id=4250
|
||||
CSET device_port_type=PCI_Express_Endpoint_device
|
||||
CSET device_specific_initialization=false
|
||||
CSET enable_aspm_l1_support=false
|
||||
CSET enable_slot_clock_cfg=true
|
||||
CSET expansion_rom_bar=FFF00001
|
||||
CSET expansion_rom_enabled=true
|
||||
CSET expansion_rom_scale=Megabytes
|
||||
CSET expansion_rom_size=1
|
||||
CSET force_no_scrambling=false
|
||||
CSET gt_debug_ports=false
|
||||
CSET interface_freq=125_default
|
||||
CSET lane_width=X4
|
||||
CSET link_capabilities_register=0003F441
|
||||
CSET max_payload_size=512_bytes
|
||||
CSET maximum_link_speed=1
|
||||
CSET maximum_link_width=4
|
||||
CSET msi=1_vector
|
||||
CSET reference_freq=100
|
||||
CSET revision_id=02
|
||||
CSET subsystem_id=4250
|
||||
CSET subsystem_vendor_id=10EE
|
||||
CSET trim_tlp_digest=false
|
||||
CSET tx_buf_diff_ctrl=800
|
||||
CSET tx_diff_boost=true
|
||||
CSET tx_diff_ctrl=800
|
||||
CSET tx_pre_emphasis=52
|
||||
CSET vendor_id=10EE
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: 6bd0aaf5
|
||||
|
|
@ -0,0 +1,118 @@
|
|||
##############################################################
|
||||
##############################################################
|
||||
##############################################################
|
||||
SET designentry = Verilog
|
||||
SET BusFormat = BusFormatAngleBracketNotRipped
|
||||
SET devicefamily = virtex5
|
||||
SET device = xc5vlx50t
|
||||
SET package = ff1136
|
||||
SET speedgrade = -1
|
||||
SET FlowVendor = Foundation_ISE
|
||||
SET VerilogSim = True
|
||||
SET VHDLSim = True
|
||||
SELECT Endpoint_Block_Plus_for_PCI_Express family Xilinx,_Inc. 1.8
|
||||
CSET acceptable_l0_latency=No_limit
|
||||
CSET acceptable_l1_latency=No_limit
|
||||
CSET advanced_flow_control_credit=Header_Credit
|
||||
CSET aux_max_current=0mA
|
||||
CSET bar0_64bit=false
|
||||
CSET bar0_enabled=true
|
||||
CSET bar0_prefetchable=false
|
||||
CSET bar0_scale=Kilobytes
|
||||
CSET bar0_size=16
|
||||
CSET bar0_type=Memory
|
||||
CSET bar0_value=FFFFC000
|
||||
CSET bar1_64bit=false
|
||||
CSET bar1_enabled=false
|
||||
CSET bar1_prefetchable=false
|
||||
CSET bar1_scale=Kilobytes
|
||||
CSET bar1_size=64
|
||||
CSET bar1_type=IO
|
||||
CSET bar1_value=00000000
|
||||
CSET bar2_64bit=false
|
||||
CSET bar2_enabled=false
|
||||
CSET bar2_prefetchable=false
|
||||
CSET bar2_scale=Kilobytes
|
||||
CSET bar2_size=64
|
||||
CSET bar2_type=IO
|
||||
CSET bar2_value=00000000
|
||||
CSET bar3_64bit=false
|
||||
CSET bar3_enabled=false
|
||||
CSET bar3_prefetchable=false
|
||||
CSET bar3_scale=Kilobytes
|
||||
CSET bar3_size=64
|
||||
CSET bar3_type=IO
|
||||
CSET bar3_value=00000000
|
||||
CSET bar4_64bit=false
|
||||
CSET bar4_enabled=false
|
||||
CSET bar4_prefetchable=false
|
||||
CSET bar4_scale=Kilobytes
|
||||
CSET bar4_size=64
|
||||
CSET bar4_type=IO
|
||||
CSET bar4_value=00000000
|
||||
CSET bar5_enabled=false
|
||||
CSET bar5_prefetchable=false
|
||||
CSET bar5_scale=Kilobytes
|
||||
CSET bar5_size=64
|
||||
CSET bar5_type=IO
|
||||
CSET bar5_value=00000000
|
||||
CSET capabilities_register=0001
|
||||
CSET capability_version=1
|
||||
CSET cardbus_cis_pointer=00000000
|
||||
CSET class_code_base=0B
|
||||
CSET class_code_interface=00
|
||||
CSET class_code_sub=40
|
||||
CSET class_code_value=0B4000
|
||||
CSET component_name=endpoint_blk_plus_v1_8
|
||||
CSET d0_pme_support=true
|
||||
CSET d0_power_consumed=0
|
||||
CSET d0_power_consumed_factor=0
|
||||
CSET d0_power_dissipated=0
|
||||
CSET d0_power_dissipated_factor=0
|
||||
CSET d1_pme_support=false
|
||||
CSET d1_power_consumed=0
|
||||
CSET d1_power_consumed_factor=0
|
||||
CSET d1_power_dissipated=0
|
||||
CSET d1_power_dissipated_factor=0
|
||||
CSET d1_support=false
|
||||
CSET d2_pme_support=false
|
||||
CSET d2_power_consumed=0
|
||||
CSET d2_power_consumed_factor=0
|
||||
CSET d2_power_dissipated=0
|
||||
CSET d2_power_dissipated_factor=0
|
||||
CSET d2_support=false
|
||||
CSET d3_power_consumed=0
|
||||
CSET d3_power_consumed_factor=0
|
||||
CSET d3_power_dissipated=0
|
||||
CSET d3_power_dissipated_factor=0
|
||||
CSET d3cold_pme_support=false
|
||||
CSET d3hot_pme_support=false
|
||||
CSET device_capabilities_register=00000FC2
|
||||
CSET device_id=4250
|
||||
CSET device_port_type=PCI_Express_Endpoint_device
|
||||
CSET device_specific_initialization=false
|
||||
CSET enable_aspm_l1_support=false
|
||||
CSET enable_slot_clock_cfg=true
|
||||
CSET expansion_rom_bar=00000000
|
||||
CSET expansion_rom_enabled=false
|
||||
CSET expansion_rom_scale=Megabytes
|
||||
CSET expansion_rom_size=1
|
||||
CSET force_no_scrambling=false
|
||||
CSET gt_debug_ports=false
|
||||
CSET interface_freq=250_default
|
||||
CSET lane_width=X8
|
||||
CSET link_capabilities_register=0003F481
|
||||
CSET max_payload_size=512_bytes
|
||||
CSET maximum_link_speed=1
|
||||
CSET maximum_link_width=8
|
||||
CSET msi=1_vector
|
||||
CSET reference_freq=100
|
||||
CSET revision_id=02
|
||||
CSET subsystem_id=4250
|
||||
CSET subsystem_vendor_id=10EE
|
||||
CSET trim_tlp_digest=false
|
||||
CSET tx_diff_boost=true
|
||||
CSET tx_diff_ctrl=800
|
||||
CSET tx_pre_emphasis=3
|
||||
CSET vendor_id=10EE
|
||||
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
##############################################################
|
||||
##############################################################
|
||||
##############################################################
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET createndf = false
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET workingdirectory = ./tmp/
|
||||
SET designentry = Verilog
|
||||
SET BusFormat = BusFormatAngleBracketNotRipped
|
||||
SET devicefamily = virtex5
|
||||
SET device = xc5vlx110t
|
||||
SET package = ff1136
|
||||
SET speedgrade = -1
|
||||
SET FlowVendor = Foundation_ISE
|
||||
SET VerilogSim = True
|
||||
SET VHDLSim = True
|
||||
SELECT Endpoint_Block_Plus_for_PCI_Express family Xilinx,_Inc. 1.9
|
||||
CSET acceptable_l0_latency=No_limit
|
||||
CSET acceptable_l1_latency=No_limit
|
||||
CSET advanced_flow_control_credit=Header_Credit
|
||||
CSET aux_max_current=0mA
|
||||
CSET bar0_64bit=false
|
||||
CSET bar0_enabled=true
|
||||
CSET bar0_prefetchable=false
|
||||
CSET bar0_scale=Kilobytes
|
||||
CSET bar0_size=16
|
||||
CSET bar0_type=Memory
|
||||
CSET bar0_value=FFFFC000
|
||||
CSET bar1_64bit=false
|
||||
CSET bar1_enabled=false
|
||||
CSET bar1_prefetchable=false
|
||||
CSET bar1_scale=Kilobytes
|
||||
CSET bar1_size=64
|
||||
CSET bar1_type=IO
|
||||
CSET bar1_value=00000000
|
||||
CSET bar2_64bit=false
|
||||
CSET bar2_enabled=false
|
||||
CSET bar2_prefetchable=false
|
||||
CSET bar2_scale=Kilobytes
|
||||
CSET bar2_size=64
|
||||
CSET bar2_type=IO
|
||||
CSET bar2_value=00000000
|
||||
CSET bar3_64bit=false
|
||||
CSET bar3_enabled=false
|
||||
CSET bar3_prefetchable=false
|
||||
CSET bar3_scale=Kilobytes
|
||||
CSET bar3_size=64
|
||||
CSET bar3_type=IO
|
||||
CSET bar3_value=00000000
|
||||
CSET bar4_64bit=false
|
||||
CSET bar4_enabled=false
|
||||
CSET bar4_prefetchable=false
|
||||
CSET bar4_scale=Kilobytes
|
||||
CSET bar4_size=64
|
||||
CSET bar4_type=IO
|
||||
CSET bar4_value=00000000
|
||||
CSET bar5_enabled=false
|
||||
CSET bar5_prefetchable=false
|
||||
CSET bar5_scale=Kilobytes
|
||||
CSET bar5_size=64
|
||||
CSET bar5_type=IO
|
||||
CSET bar5_value=00000000
|
||||
CSET capabilities_register=0001
|
||||
CSET capability_version=1
|
||||
CSET cardbus_cis_pointer=00000000
|
||||
CSET class_code_base=0B
|
||||
CSET class_code_interface=00
|
||||
CSET class_code_sub=40
|
||||
CSET class_code_value=0B4000
|
||||
CSET component_name=endpoint_blk_plus_v1_9
|
||||
CSET d0_pme_support=true
|
||||
CSET d0_power_consumed=0
|
||||
CSET d0_power_consumed_factor=0
|
||||
CSET d0_power_dissipated=0
|
||||
CSET d0_power_dissipated_factor=0
|
||||
CSET d1_pme_support=false
|
||||
CSET d1_power_consumed=0
|
||||
CSET d1_power_consumed_factor=0
|
||||
CSET d1_power_dissipated=0
|
||||
CSET d1_power_dissipated_factor=0
|
||||
CSET d1_support=false
|
||||
CSET d2_pme_support=false
|
||||
CSET d2_power_consumed=0
|
||||
CSET d2_power_consumed_factor=0
|
||||
CSET d2_power_dissipated=0
|
||||
CSET d2_power_dissipated_factor=0
|
||||
CSET d2_support=false
|
||||
CSET d3_power_consumed=0
|
||||
CSET d3_power_consumed_factor=0
|
||||
CSET d3_power_dissipated=0
|
||||
CSET d3_power_dissipated_factor=0
|
||||
CSET d3cold_pme_support=false
|
||||
CSET d3hot_pme_support=false
|
||||
CSET device_capabilities_register=00000FC2
|
||||
CSET device_id=4250
|
||||
CSET device_port_type=PCI_Express_Endpoint_device
|
||||
CSET device_specific_initialization=false
|
||||
CSET enable_aspm_l1_support=false
|
||||
CSET enable_slot_clock_cfg=true
|
||||
CSET expansion_rom_bar=FFF00001
|
||||
CSET expansion_rom_enabled=true
|
||||
CSET expansion_rom_scale=Megabytes
|
||||
CSET expansion_rom_size=1
|
||||
CSET force_no_scrambling=false
|
||||
CSET gt_debug_ports=false
|
||||
CSET interface_freq=125_default
|
||||
CSET lane_width=X4
|
||||
CSET link_capabilities_register=0003F441
|
||||
CSET max_payload_size=512_bytes
|
||||
CSET maximum_link_speed=1
|
||||
CSET maximum_link_width=4
|
||||
CSET msi=1_vector
|
||||
CSET reference_freq=100
|
||||
CSET revision_id=02
|
||||
CSET subsystem_id=4250
|
||||
CSET subsystem_vendor_id=10EE
|
||||
CSET trim_tlp_digest=false
|
||||
CSET tx_diff_boost=true
|
||||
CSET tx_diff_ctrl=800
|
||||
CSET tx_pre_emphasis=52
|
||||
CSET vendor_id=10EE
|
||||
|
||||
|
|
@ -0,0 +1 @@
|
|||
Xilinx files (mainly IP_cores) are removed to avoid potential licensing issue. The \ip_cores folder only contains necessary configuration files for customizing the IP cores. Please generate your own IP cores using Xilinx core generater. If you need help on this, you can try to contact V3best.
|
||||
|
|
@ -0,0 +1,135 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 01/05/2010
|
||||
// Design Name:
|
||||
// Module Name: parameters for Sora's PCIe configuration
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//////////////////////////////////////
|
||||
//////// PCIe settings ///////////////
|
||||
//////////////////////////////////////
|
||||
|
||||
`ifdef sora_simulation
|
||||
`define BOARDx08 1
|
||||
`else
|
||||
`define BOARDx04 1
|
||||
`endif
|
||||
|
||||
`ifdef BOARDx01
|
||||
|
||||
`define PCI_EXP_EP endpoint_blk_plus_v1_5
|
||||
`define XILINX_PCI_EXP_EP xilinx_pci_exp_1_lane_ep
|
||||
`define PCI_EXP_LINK_WIDTH 1
|
||||
|
||||
`endif // BOARDx01
|
||||
|
||||
`ifdef BOARDx04
|
||||
|
||||
`define PCI_EXP_EP endpoint_blk_plus_v1_5
|
||||
`define XILINX_PCI_EXP_EP xilinx_pci_exp_4_lane_ep
|
||||
`define PCI_EXP_LINK_WIDTH 4
|
||||
|
||||
`endif // BOARDx04
|
||||
|
||||
`ifdef BOARDx08
|
||||
|
||||
`define PCI_EXP_EP endpoint_blk_plus_v1_5
|
||||
`define XILINX_PCI_EXP_EP xilinx_pci_exp_8_lane_ep
|
||||
`define PCI_EXP_LINK_WIDTH 8
|
||||
|
||||
`endif // BOARDx08
|
||||
|
||||
`define PCI_EXP_EP_INST ep
|
||||
|
||||
//-------------------------------------------------------
|
||||
// Config File Module
|
||||
//-------------------------------------------------------
|
||||
|
||||
`define PCI_EXP_CFG pci_exp_cfg
|
||||
|
||||
`define PCI_EXP_CFG_INST pci_exp_cfg
|
||||
|
||||
//-------------------------------------------------------
|
||||
// Transaction (TRN) Interface
|
||||
//-------------------------------------------------------
|
||||
|
||||
`define PCI_EXP_TRN_DATA_WIDTH 64
|
||||
`define PCI_EXP_TRN_REM_WIDTH 8
|
||||
`define PCI_EXP_TRN_BUF_AV_WIDTH 4
|
||||
|
||||
`define PCI_EXP_TRN_BAR_HIT_WIDTH 7
|
||||
`define PCI_EXP_TRN_FC_HDR_WIDTH 8
|
||||
`define PCI_EXP_TRN_FC_DATA_WIDTH 12
|
||||
|
||||
//-------------------------------------------------------
|
||||
// Application Stub Module
|
||||
//-------------------------------------------------------
|
||||
|
||||
`define PCI_EXP_APP pci_exp_64b_app
|
||||
|
||||
//-------------------------------------------------------
|
||||
// Configuration (CFG) Interface
|
||||
//-------------------------------------------------------
|
||||
|
||||
`define PCI_EXP_CFG_DATA_WIDTH 32
|
||||
`define PCI_EXP_CFG_ADDR_WIDTH 10
|
||||
`define PCI_EXP_CFG_BUSNUM_WIDTH 8
|
||||
`define PCI_EXP_CFG_DEVNUM_WIDTH 5
|
||||
`define PCI_EXP_CFG_FUNNUM_WIDTH 3
|
||||
`define PCI_EXP_CFG_CPLHDR_WIDTH 48
|
||||
`define PCI_EXP_CFG_CAP_WIDTH 16
|
||||
`define PCI_EXP_CFG_CFG_WIDTH 1024
|
||||
`define PCI_EXP_CFG_WIDTH 1024
|
||||
`define PCI_EXP_LNK_STATE_WIDTH 3
|
||||
|
||||
`define PCI_EXP_CFG_BUSNUM_WIDTH 8
|
||||
`define PCI_EXP_CFG_DEVNUM_WIDTH 5
|
||||
`define PCI_EXP_CFG_FUNNUM_WIDTH 3
|
||||
`define PCI_EXP_CFG_DSN_WIDTH 64
|
||||
`define PCI_EXP_EP_OUI 24'h000A35
|
||||
`define PCI_EXP_EP_DSN_1 {{8'h1},`PCI_EXP_EP_OUI}
|
||||
`define PCI_EXP_EP_DSN_2 32'h00000001
|
||||
|
||||
//////////////////////////////////////
|
||||
//////// PCIe settings ///////////////
|
||||
//////////////////////////////////////
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,85 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 17:00:10 11/17/2012
|
||||
// Design Name:
|
||||
// Module Name: CRC8_gen
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module CRC8_gen(
|
||||
input [47:0] D,
|
||||
output [7:0] NewCRC
|
||||
);
|
||||
|
||||
assign NewCRC[0] = D[46] ^ D[42] ^ D[41] ^ D[37] ^ D[36] ^ D[35] ^ D[34] ^
|
||||
D[33] ^ D[31] ^ D[30] ^ D[29] ^ D[27] ^ D[26] ^ D[24] ^
|
||||
D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
|
||||
D[8] ^ D[7] ^ D[6] ^ D[3] ^ D[1] ^ D[0];
|
||||
assign NewCRC[1] = D[47] ^ D[43] ^ D[42] ^ D[38] ^ D[37] ^ D[36] ^ D[35] ^
|
||||
D[34] ^ D[32] ^ D[31] ^ D[30] ^ D[28] ^ D[27] ^ D[25] ^
|
||||
D[21] ^ D[19] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^
|
||||
D[9] ^ D[8] ^ D[7] ^ D[4] ^ D[2] ^ D[1];
|
||||
assign NewCRC[2] = D[46] ^ D[44] ^ D[43] ^ D[42] ^ D[41] ^ D[39] ^ D[38] ^
|
||||
D[34] ^ D[32] ^ D[30] ^ D[28] ^ D[27] ^ D[24] ^ D[22] ^
|
||||
D[19] ^ D[14] ^ D[13] ^ D[10] ^ D[9] ^ D[7] ^ D[6] ^
|
||||
D[5] ^ D[2] ^ D[1] ^ D[0];
|
||||
assign NewCRC[3] = D[47] ^ D[45] ^ D[44] ^ D[43] ^ D[42] ^ D[40] ^ D[39] ^
|
||||
D[35] ^ D[33] ^ D[31] ^ D[29] ^ D[28] ^ D[25] ^ D[23] ^
|
||||
D[20] ^ D[15] ^ D[14] ^ D[11] ^ D[10] ^ D[8] ^ D[7] ^
|
||||
D[6] ^ D[3] ^ D[2] ^ D[1];
|
||||
assign NewCRC[4] = D[45] ^ D[44] ^ D[43] ^ D[42] ^ D[40] ^ D[37] ^ D[35] ^
|
||||
D[33] ^ D[32] ^ D[31] ^ D[27] ^ D[21] ^ D[20] ^ D[18] ^
|
||||
D[17] ^ D[14] ^ D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[6] ^
|
||||
D[4] ^ D[2] ^ D[1] ^ D[0];
|
||||
assign NewCRC[5] = D[46] ^ D[45] ^ D[44] ^ D[43] ^ D[41] ^ D[38] ^ D[36] ^
|
||||
D[34] ^ D[33] ^ D[32] ^ D[28] ^ D[22] ^ D[21] ^ D[19] ^
|
||||
D[18] ^ D[15] ^ D[14] ^ D[13] ^ D[12] ^ D[10] ^ D[7] ^
|
||||
D[5] ^ D[3] ^ D[2] ^ D[1];
|
||||
assign NewCRC[6] = D[47] ^ D[45] ^ D[44] ^ D[41] ^ D[39] ^ D[36] ^ D[31] ^
|
||||
D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[23] ^ D[22] ^ D[19] ^
|
||||
D[18] ^ D[17] ^ D[11] ^ D[7] ^ D[4] ^ D[2] ^ D[1] ^
|
||||
D[0];
|
||||
assign NewCRC[7] = D[45] ^ D[41] ^ D[40] ^ D[36] ^ D[35] ^ D[34] ^ D[33] ^
|
||||
D[32] ^ D[30] ^ D[29] ^ D[28] ^ D[26] ^ D[25] ^ D[23] ^
|
||||
D[19] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^ D[12] ^
|
||||
D[7] ^ D[6] ^ D[5] ^ D[2] ^ D[0];
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,107 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version : 12.2
|
||||
// \ \ Application : xaw2verilog
|
||||
// / / Filename : DCM_FRL.v
|
||||
// /___/ /\ Timestamp : 10/19/2012 11:30:08
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
//Command: xaw2verilog -st D:\\Mydev\firmwareTFS\FPGA\MIMOv1\rtl\pcie_userapp_wrapper\Sora_Fast_Radio_Link\DCM\.\DCM_FRL.xaw D:\\Mydev\firmwareTFS\FPGA\MIMOv1\rtl\pcie_userapp_wrapper\Sora_Fast_Radio_Link\DCM\.\DCM_FRL
|
||||
//Design Name: DCM_FRL
|
||||
//Device: xc5vlx50t-1ff1136
|
||||
//
|
||||
// Module DCM_FRL
|
||||
// Generated by Xilinx Architecture Wizard
|
||||
// Written for synthesis tool: XST
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module DCM_FRL(CLKIN_IN,
|
||||
RST_IN,
|
||||
CLKDV_OUT,
|
||||
CLK0_OUT,
|
||||
LOCKED_OUT);
|
||||
|
||||
input CLKIN_IN;
|
||||
input RST_IN;
|
||||
output CLKDV_OUT;
|
||||
output CLK0_OUT;
|
||||
output LOCKED_OUT;
|
||||
|
||||
wire CLKDV_BUF;
|
||||
wire CLKFB_IN;
|
||||
wire CLK0_BUF;
|
||||
wire GND_BIT;
|
||||
wire [6:0] GND_BUS_7;
|
||||
wire [15:0] GND_BUS_16;
|
||||
|
||||
assign GND_BIT = 0;
|
||||
assign GND_BUS_7 = 7'b0000000;
|
||||
assign GND_BUS_16 = 16'b0000000000000000;
|
||||
assign CLK0_OUT = CLKFB_IN;
|
||||
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
|
||||
.O(CLKDV_OUT));
|
||||
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
|
||||
.O(CLKFB_IN));
|
||||
DCM_ADV #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(4.0), .CLKFX_DIVIDE(1),
|
||||
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"), .CLKIN_PERIOD(4.464),
|
||||
.CLKOUT_PHASE_SHIFT("NONE"), .DCM_AUTOCALIBRATION("TRUE"),
|
||||
.DCM_PERFORMANCE_MODE("MAX_SPEED"),
|
||||
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("HIGH"),
|
||||
.DLL_FREQUENCY_MODE("HIGH"), .DUTY_CYCLE_CORRECTION("TRUE"),
|
||||
.FACTORY_JF(16'hF0F0), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE"),
|
||||
.SIM_DEVICE("VIRTEX5") ) DCM_ADV_INST (.CLKFB(CLKFB_IN),
|
||||
.CLKIN(CLKIN_IN),
|
||||
.DADDR(GND_BUS_7[6:0]),
|
||||
.DCLK(GND_BIT),
|
||||
.DEN(GND_BIT),
|
||||
.DI(GND_BUS_16[15:0]),
|
||||
.DWE(GND_BIT),
|
||||
.PSCLK(GND_BIT),
|
||||
.PSEN(GND_BIT),
|
||||
.PSINCDEC(GND_BIT),
|
||||
.RST(RST_IN),
|
||||
.CLKDV(CLKDV_BUF),
|
||||
.CLKFX(),
|
||||
.CLKFX180(),
|
||||
.CLK0(CLK0_BUF),
|
||||
.CLK2X(),
|
||||
.CLK2X180(),
|
||||
.CLK90(),
|
||||
.CLK180(),
|
||||
.CLK270(),
|
||||
.DO(),
|
||||
.DRDY(),
|
||||
.LOCKED(LOCKED_OUT),
|
||||
.PSDONE());
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
XILINX-XDB 0.1 STUB 0.1 ASCII
|
||||
XILINX-XDM V1.6e
|
||||
$9gx4>7<881:86?=.3:853!oN9L;>6?W3:0104=3=2>%8;:8;@P@LRO]9>1J^ZTPOONZ[FGTKHNBBJQLLJ3;?DTPRVEE@TQLLJKM[@^SM[DJ@<;4ASUY[JHKQVIGGD@PV@NVA4d<I[]QSB@CY^F@IZUPA]ICECIPCMI24>GU_SUDBAWPDEP\G5773HX\VRAALX]G@WYD98;0M_YU_NLO]ZBCZVIGG<84ASUY[JHKQVNO^RKKGDOL@@713HX\VRAALX]G@WYAD@ZM@B^>2:CQS_YHFESTHI\PIOKW52=FZ^PTCCBV_EFQ[WCTM]^R\H?:;@PT^ZIIDPUMNRKWTDPMEI753HX\VRAALX]JJVRXF\G:;6O]W[]LJI_XZLIDBKGH_QKMW43<I[]QSB@CY^PFW@RXDFMBO<<4ASUY[JHKQVXNXL\HEU3;?DTPRVEE@TQYAMKG[A@TWDEOIl5NSRM@[ROS@o1J[WQLLJ@VBQ_WM8;=7LYU_BNHFP@SQYO:SCAJDHV27>GPRVIGGRAZTQWW[Q_WMj1J[WQILNUW]UC?3H]QS]O]Te9BS_YTQG^CXBAC4:@VBB2<KEA;46MCK1]AQCc<KEA;SO[IG^KMWQ><KEA;SB[[6:AOO4>7>2IGG?9?5:AOO7^?3JF@>U?7049@HN?7=2IGGIX6;BNH@SYE]Ol0OAEKV^@VBBYNFZ^h7NBDDW]GMSOCM01H@FJY_NWW1>EKCOH37NBDFC]JJ0=DDBLS46MCKGZ2<5e<KEAMTRJFVHFFa>EKCORTAXB[IQNZ1>EKC@D:=6MCKHL\@LPNLLUIUR<7;BNHMKYNFj1H@FGA_QGQMJBb3JF@ECQ\RB]W]UC6:2IGGB[[_QJBW@YT@@L_o6MCK^DFAADFKB30OBCBIUVF@2=DZLK_II8>;E8_XHcmVmecxasgWBVZAXNKWADC@v0^qpiZwk`oTy~k}aqr\swgwxlxW_b|n_GcppZTfl`eT@d`d\EANX+ZCKDUM^A wav78@DBCZ=1OOAE8;EAN[DBQk2NHAROKV^KMWQ743MIFSL[[OBCOMGTF\@EE=95KCL]SAW@HZDKEOHQBOEG0?ACIl2NN_FKX_@FIQVR6:2NM_RH]EPWFJF_XEFNN>6JF3:FOH44<LEFTJ_K^UDL@]ZKHLL80HB:4DSFZ50=C]]STOTMCE^ALVWCD\@EE?6JXE69G[SGK]Lk0JLM[OS[\NC3<NHFXI45IB^QLQWEBk2LNIILNCJ]AQC?<N@DTYCG[S99EKPRX[]Xj7KAZT^WMMQUf3OE^XRXNLTG7?MO@@81B46GATDPMEI763CC_XH\PIORVPZR^XL<0@BMDEEc8HJELMMUDYY74M@Z\WUCBL:1FDW94M^TBHPC03GO_[B\D4:LLJ@7<G=1DHI\7;NRSKVOSMk1[DL]J_RJJBQ?<X@DCM^LZS`9SMKOTOGNNH55_IOUJ@QN?3YXBAYW_E028TWIWWYCEE^OLTHTF1>VTKEA=7]]KOOG7?UUBF11[_D@LDDA0?WUS>2XXXRGAb:QJC@^SM[DJ@l5\IL]GASODM?1XECICEb9PPDTS]YU\MDZm;R[MGMTHFF_X=?5\YRVFIZU^FJBYCCAZS29WKU2<\[_N46[\E^@VBB?<]ZOTNXHHS49UM@Q6?2\B^YKW5c9[ERYQM[YBCC?k;YKOMK^*PMH+<#?/SUWA$5(6(HYHED=4XRV5?]beW@n:<6Vkm^ObnjtQm{ybcc??;Yfn[Hoig{\n~~g`n49X4?6Z>2Q;6<;R5:Y3>3[33hx|v>5kcl58r`tndfmi7{k}shmm$4(7981so8xcx42w)4`a989=qMN369CD}272O096<u\3g8;=?>d2898<8lm:9261~h?<3;0b5;56:&;7?>63tY8i766:9a95657=kh14=h?;e::>5<628qX?k479;:`>4548<hi65>:5:tW3`<7280:65u\3g8;=?>d2898<8lm:9261>d0i3:1<7=58z&:>=g<,8l14o5+218;`>"593297)6?:29a01<72821<7>t$7a906=#i38h7)l5779'`?443-;>6:84$0496>"6:3<=7)k5229'b?403-;;6?=4$03922=#9:0:7)?;:6:8 41==:1/=54:3:&2=?343-9o685+2g84?!522;1/?;48;%1;>05<,:k146*<b;7`?!5d2?>0(9;57c9'03<182.?4796;%6:>0g<,=i19l5+4g84f>"29380(8<54:&60?3d3-?=6;?4$4:924=#=00;7);k:458 34=?2.=47?4$65916=#?j0<h6*l:79'5`<3j2.:m7;n;%56>2`<a:=1<7*9b;:5?!0c2>h07d=>:18'2g<?>2.=h79m;:k75?6=,?h1455+6`84f>"113=i76g;a;29 3d=0>1/:l48b:&5=?1e32c><7>5$7`9<3=#>h0<n65f4683>!0e21<0(;o57c98m14=83.=n769;%4b>2d<3`=96=4+6c8;2>"1l3=i76g80;29 3d=0?1/:l48b:9j34<72-<i6584$7c93g=<a?o1<7*9b;:5?!0f2>h07b<<:18'2g<?>2.=h79m;%3`>74<,8n19854o3`94?"1j32=76a=7;29 3d=0?10c?650;&5f?>132e9o7>5$7`9<3=#>m0<n6*>c;01?>i513:1(;l58798k7g=83.=n769;:m07?6=,?h14;54o2694?"1j32=76a;e;29 3d=0?10c9j50;&5f?>03-<26:l4;n7f>5<#>k03:6*9d;5a?>i1n3:1(;l58798yg4229096=4?{%4`>74<a<h1<7*9b;:5?!0c2>h07b8::18'2g<?>2.=h79m;:a6`<72;0;6=u+6b816>o2j3:1(;l5879'2a<0j21d:84?:%4a>=0<,?n1;o54}r1:>5<6s4>?6>94$6691g=z{:81<7<t=56974=::<0=96*>b;05?xu0;3:1=v3;4;51?!132<h0q~<;:1818232;901?;55c9~w7b=838p19:52b9>6`<2j2wx9k4?:0y>01<2m2.<878:;|q04?6=9r79i78:;%57>33<uz8=6=4?{%57>33<utd9;7>51zm6=<728qvb?750;3xyk4f290:wp`=b;295~{i:j0;6<urn3f94?7|ug8n6=4>{|~yEFDs:=14?mi947eyEFEs9wKL]ur@A
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
# Generated by Xilinx Architecture Wizard
|
||||
# --- UCF Template Only ---
|
||||
# Cut and paste these attributes into the project's UCF file, if desired
|
||||
INST DCM_ADV_INST CLK_FEEDBACK = 1X;
|
||||
INST DCM_ADV_INST CLKDV_DIVIDE = 4.0;
|
||||
INST DCM_ADV_INST CLKFX_DIVIDE = 1;
|
||||
INST DCM_ADV_INST CLKFX_MULTIPLY = 4;
|
||||
INST DCM_ADV_INST CLKIN_DIVIDE_BY_2 = FALSE;
|
||||
INST DCM_ADV_INST CLKIN_PERIOD = 4.464;
|
||||
INST DCM_ADV_INST CLKOUT_PHASE_SHIFT = NONE;
|
||||
INST DCM_ADV_INST DCM_AUTOCALIBRATION = TRUE;
|
||||
INST DCM_ADV_INST DCM_PERFORMANCE_MODE = MAX_SPEED;
|
||||
INST DCM_ADV_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
|
||||
INST DCM_ADV_INST DFS_FREQUENCY_MODE = HIGH;
|
||||
INST DCM_ADV_INST DLL_FREQUENCY_MODE = HIGH;
|
||||
INST DCM_ADV_INST DUTY_CYCLE_CORRECTION = TRUE;
|
||||
INST DCM_ADV_INST FACTORY_JF = F0F0;
|
||||
INST DCM_ADV_INST PHASE_SHIFT = 0;
|
||||
INST DCM_ADV_INST STARTUP_WAIT = FALSE;
|
||||
INST DCM_ADV_INST SIM_DEVICE = VIRTEX5;
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
# Output products list for <DCM_FRL>
|
||||
DCM_FRL_flist.txt
|
||||
DCM_FRL_readme.txt
|
||||
DCM_FRL_xmdf.tcl
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
# The package naming convention is <core_name>_xmdf
|
||||
package provide DCM_FRL_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::DCM_FRL_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::DCM_FRL_xmdf::xmdfInit { instance } {
|
||||
# Variable containg name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name DCM_FRL
|
||||
}
|
||||
# ::DCM_FRL_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::DCM_FRL_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be magically
|
||||
# available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path DCM_FRL_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module DCM_FRL
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
|
|
@ -0,0 +1,506 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Summary:
|
||||
//
|
||||
// The BIT_ALIGN_MACHINE module analyzes the data input of a single channel
|
||||
// to determine the optimal clock/data relationship for that channel. By
|
||||
// dynamically changing the delay of the data channel (with respect to the
|
||||
// sampling clock), the machine places the sampling point at the center of
|
||||
// the data eye.
|
||||
//
|
||||
//----------------------------------------------------------------
|
||||
|
||||
module RCB_FRL_BIT_ALIGN_MACHINE (
|
||||
input RXCLKDIV,
|
||||
input [7:0] RXDATA,
|
||||
input RST,
|
||||
input USE_BITSLIP,
|
||||
input SAP,
|
||||
output reg INC,
|
||||
output reg ICE,
|
||||
output reg BITSLIP,
|
||||
output DATA_ALIGNED
|
||||
);
|
||||
|
||||
reg COUNT;
|
||||
reg UD;
|
||||
reg STORE;
|
||||
reg STORE_DATA_PREV;
|
||||
reg COUNT_SAMPLE;
|
||||
reg UD_SAMPLE;
|
||||
reg [4:0] CURRENT_STATE;
|
||||
reg [4:0] NEXT_STATE;
|
||||
|
||||
wire [6:0] COUNT_VALUE;
|
||||
wire [6:0] HALF_DATA_EYE;
|
||||
wire [7:0] RXDATA_PREV;
|
||||
wire [6:0] COUNT_VALUE_SAMPLE;
|
||||
wire [6:0] CVS;
|
||||
wire [6:0] CVS_ADJUSTED;
|
||||
wire [7:0] CHECK_PATTERN;
|
||||
|
||||
RCB_FRL_count_to_128 machine_counter_total(
|
||||
.clk(RXCLKDIV),
|
||||
.rst(RST),
|
||||
.count(COUNT_SAMPLE),
|
||||
.ud(UD_SAMPLE),
|
||||
.counter_value(COUNT_VALUE_SAMPLE)
|
||||
);
|
||||
|
||||
RCB_FRL_count_to_128 machine_counter(
|
||||
.clk(RXCLKDIV),
|
||||
.rst(RST),
|
||||
.count(COUNT),
|
||||
.ud(UD),
|
||||
.counter_value(COUNT_VALUE)
|
||||
);
|
||||
|
||||
RCB_FRL_seven_bit_reg_w_ce tap_reserve(
|
||||
.Q(CVS),
|
||||
.CLK(RXCLKDIV),
|
||||
.CE(STORE),
|
||||
.D(COUNT_VALUE),
|
||||
.RST(RST)
|
||||
);
|
||||
|
||||
FDR count_reg(.Q(DATA_ALIGNED), .C(RXCLKDIV), .D(DATA_ALIGNEDx), .R(RST));
|
||||
|
||||
//STORE ENTIRE DATA BUS FOR COMPARISON AFTER CHANGING DELAY
|
||||
FDRE bit0(.Q(RXDATA_PREV[0]), .C(RXCLKDIV), .CE(STORE_DATA_PREV), .D(RXDATA[0]), .R(RST));
|
||||
FDRE bit1(.Q(RXDATA_PREV[1]), .C(RXCLKDIV), .CE(STORE_DATA_PREV), .D(RXDATA[1]), .R(RST));
|
||||
FDRE bit2(.Q(RXDATA_PREV[2]), .C(RXCLKDIV), .CE(STORE_DATA_PREV), .D(RXDATA[2]), .R(RST));
|
||||
FDRE bit3(.Q(RXDATA_PREV[3]), .C(RXCLKDIV), .CE(STORE_DATA_PREV), .D(RXDATA[3]), .R(RST));
|
||||
FDRE bit4(.Q(RXDATA_PREV[4]), .C(RXCLKDIV), .CE(STORE_DATA_PREV), .D(RXDATA[4]), .R(RST));
|
||||
FDRE bit5(.Q(RXDATA_PREV[5]), .C(RXCLKDIV), .CE(STORE_DATA_PREV), .D(RXDATA[5]), .R(RST));
|
||||
FDRE bit6(.Q(RXDATA_PREV[6]), .C(RXCLKDIV), .CE(STORE_DATA_PREV), .D(RXDATA[6]), .R(RST));
|
||||
FDRE bit7(.Q(RXDATA_PREV[7]), .C(RXCLKDIV), .CE(STORE_DATA_PREV), .D(RXDATA[7]), .R(RST));
|
||||
|
||||
assign DATA_ALIGNEDx = (~CURRENT_STATE[4] & ~CURRENT_STATE[3] & CURRENT_STATE[2] & CURRENT_STATE[1] & CURRENT_STATE[0]);
|
||||
//assign CHECK_PATTERN = 8'b11010010;
|
||||
assign CHECK_PATTERN = 8'h5c; // training pattern for spartan6
|
||||
//CVS IS A SNAPSHOT OF THE TAP COUNTER. IT'S VALUE IS THE SIZE OF THE DATA VALID WINDOW
|
||||
//OUR INTENTION IS TO DECREMENT THE DELAY TO 1/2 THIS VALUE TO BE AT THE CENTER OF THE EYE.
|
||||
//SINCE IT MAY BE POSSIBLE TO HAVE AN ODD COUNTER VALUE, THE HALVED VALUE WILL BE A DECIMAL.
|
||||
//IN CASES WHERE CVS IS A DECIMAL, WE WILL ROUND UP. E.G CVS = 4.5, SO DECREMENT 5 TAPS.
|
||||
//CVS_ADJUSTED AND HALF_DATA_EYE ARE FINE TUNED ADJUSTMENTS FOR OPTIMAL OPERATION AT HIGH RATES
|
||||
|
||||
assign CVS_ADJUSTED = CVS - 1; //THE ALGORITHM COUNTS ONE TAP BEYOND EYE, MUST BE REMOVED
|
||||
assign HALF_DATA_EYE = {1'b0,CVS_ADJUSTED[6:1]} + CVS_ADJUSTED[0]; //THE CVS[0] FACTOR CAUSES A ROUND-UP
|
||||
|
||||
//CURRENT STATE LOGIC
|
||||
always@(posedge RXCLKDIV or posedge RST) begin
|
||||
if(RST == 1'b1) begin
|
||||
CURRENT_STATE = 5'b00000;
|
||||
end else begin
|
||||
CURRENT_STATE = NEXT_STATE;
|
||||
end
|
||||
end
|
||||
|
||||
//NEXT_STATE LOGIC
|
||||
always @(CURRENT_STATE or COUNT_VALUE or USE_BITSLIP or RXDATA or
|
||||
CHECK_PATTERN or RXDATA_PREV or COUNT_VALUE_SAMPLE or SAP or HALF_DATA_EYE) begin
|
||||
case(CURRENT_STATE)
|
||||
5'b00000: begin
|
||||
if (SAP == 1'b0) //RST STATE
|
||||
NEXT_STATE <= 5'b00001;
|
||||
else
|
||||
NEXT_STATE <= 5'b00000;
|
||||
end
|
||||
|
||||
5'b00001: begin //INITIAL STATE, SAMPLE TRAINING BIT
|
||||
if (RXDATA_PREV != RXDATA)
|
||||
NEXT_STATE <= 5'b01111;
|
||||
else
|
||||
NEXT_STATE <= 5'b01000;
|
||||
end
|
||||
|
||||
5'b01000: begin //CHECK SAMPLE TO SEE IF IT IS ON A TRANSITION
|
||||
if (RXDATA_PREV != RXDATA)
|
||||
NEXT_STATE <= 5'b01111;
|
||||
else if (COUNT_VALUE_SAMPLE > 7'b0001111)
|
||||
NEXT_STATE <= 5'b01011;
|
||||
else
|
||||
NEXT_STATE <= 5'b01000;
|
||||
end
|
||||
|
||||
5'b01111: begin //IF SAMPLED POINT IS TRANSITION, EDGE IS FOUND, SO INC DELAY TO EXIT TRANSITION
|
||||
NEXT_STATE <= 5'b01101;
|
||||
end
|
||||
|
||||
5'b01101: begin //WAIT 16 CYCLES WHILE APPLYING BITSLIP TO FIND CHECK_PATTERN
|
||||
if (COUNT_VALUE_SAMPLE > 7'b0001110)
|
||||
NEXT_STATE <= 5'b01111;
|
||||
else if (RXDATA == CHECK_PATTERN) //IF CHECK_PATTERN IS FOUND, WE ARE CLOSE TO END OF TRANSITION
|
||||
NEXT_STATE <= 5'b01100;
|
||||
else
|
||||
NEXT_STATE <= 5'b01101;
|
||||
end
|
||||
|
||||
5'b01100: begin //IDLE (NEEDED FOR COUNTER RESET BEFORE NEXT STATE)
|
||||
NEXT_STATE <= 5'b10000;
|
||||
end
|
||||
|
||||
5'b10000: begin //IDLE (NEEDED FOR STABILIZATION)
|
||||
NEXT_STATE <= 5'b00010;
|
||||
end
|
||||
|
||||
5'b00010: begin //CHECK SAMPLE AGAIN TO SEE IF WE HAVE EXITED TRANSITION
|
||||
if (COUNT_VALUE_SAMPLE < 7'b0000011) //ALLOW TIME FOR BITSLIP OP TO STABILIZE
|
||||
NEXT_STATE <= 5'b00010;
|
||||
else if (RXDATA_PREV != RXDATA)
|
||||
NEXT_STATE <= 5'b01111;
|
||||
else if (COUNT_VALUE_SAMPLE > 7'b1111110) //SCAN FOR STABILITY FOR 128 CYCLES
|
||||
NEXT_STATE <= 5'b01110;
|
||||
else
|
||||
NEXT_STATE <= 5'b00010;
|
||||
end
|
||||
|
||||
5'b01011: begin //INITIAL STATE WAS STABLE, SO INC ONCE TO SEARCH FOR TRANS
|
||||
NEXT_STATE <= 5'b00100;
|
||||
end
|
||||
|
||||
5'b00100: begin //WAIT 8 CYCLES, COMPARE RXDATA WITH PREVIOUS DATA
|
||||
if (COUNT_VALUE_SAMPLE < 7'b0000111)
|
||||
NEXT_STATE <= 5'b00100;
|
||||
else if(RXDATA_PREV != RXDATA)
|
||||
NEXT_STATE <= 5'b01111;
|
||||
else
|
||||
NEXT_STATE <= 5'b01011;
|
||||
end
|
||||
|
||||
5'b01110: begin //DATA IS STABLE AFTER FINDING 1ST TRANS, COUNT 1 TO INCLUDE LAST INC
|
||||
NEXT_STATE <= 5'b01001;
|
||||
end
|
||||
|
||||
5'b01001: begin //INC ONCE TO LOOK FOR 2ND TRANS
|
||||
NEXT_STATE <= 5'b00011;
|
||||
end
|
||||
|
||||
5'b00011: begin //WAIT 8 CYCLES, COMPARE RXDATA WITH PREVIOUS DATA
|
||||
if (COUNT_VALUE_SAMPLE < 7'b0000111)
|
||||
NEXT_STATE <= 5'b00011;
|
||||
else if(RXDATA_PREV != RXDATA)
|
||||
NEXT_STATE <= 5'b10010;
|
||||
else
|
||||
NEXT_STATE <= 5'b01001;
|
||||
end
|
||||
|
||||
5'b10010: begin //IDLE (NEEDED FOR COUNTER RESET BEFORE NEXT STATE)
|
||||
NEXT_STATE <= 5'b01010;
|
||||
end
|
||||
|
||||
5'b01010: begin //DECREMENT TO MIDDLE OF DATA EYE
|
||||
if (COUNT_VALUE_SAMPLE < HALF_DATA_EYE-1)
|
||||
NEXT_STATE <= 5'b01010;
|
||||
else
|
||||
NEXT_STATE <= 5'b00101;
|
||||
end
|
||||
|
||||
5'b00101: begin //SAMPLE PATTERN 16 TIMES TO SEE IF WORD ALIGNMENT NEEDED
|
||||
if(USE_BITSLIP == 1'b0)
|
||||
NEXT_STATE <= 5'b00111;
|
||||
else if(COUNT_VALUE < 7'h0F)
|
||||
NEXT_STATE <= 5'b00101;
|
||||
else if (RXDATA == CHECK_PATTERN)
|
||||
NEXT_STATE <= 5'b00111;
|
||||
else
|
||||
NEXT_STATE <= 5'b00110;
|
||||
end
|
||||
|
||||
5'b00110: begin //INITIATE 1 BITSLIP
|
||||
NEXT_STATE <= 5'b00101;
|
||||
end
|
||||
|
||||
5'b00111: begin
|
||||
if (SAP == 1'b0) //TRAINING COMPLETE FOR THIS CHANNEL
|
||||
NEXT_STATE <= 5'b00111;
|
||||
else
|
||||
NEXT_STATE <= 5'b00000;
|
||||
end
|
||||
|
||||
default: NEXT_STATE <= 5'b00000;
|
||||
endcase
|
||||
end
|
||||
|
||||
//OUTPUT LOGIC
|
||||
|
||||
always @(CURRENT_STATE)
|
||||
begin
|
||||
case(CURRENT_STATE)
|
||||
5'b00000: begin //RST STATE
|
||||
INC = 1'b0;
|
||||
ICE = 1'b0;
|
||||
COUNT = 1'b0;
|
||||
UD = 1'b0;
|
||||
STORE = 1'b0;
|
||||
STORE_DATA_PREV = 1'b1;
|
||||
BITSLIP = 1'b0;
|
||||
COUNT_SAMPLE = 1'b0;
|
||||
UD_SAMPLE = 1'b0;
|
||||
end
|
||||
|
||||
5'b00001: begin //INITIAL STATE, SAMPLE TRAINING BIT
|
||||
INC = 1'b0;
|
||||
ICE = 1'b0;
|
||||
COUNT = 1'b0;
|
||||
UD = 1'b0;
|
||||
STORE = 1'b0;
|
||||
STORE_DATA_PREV = 1'b1;
|
||||
BITSLIP = 1'b0;
|
||||
COUNT_SAMPLE = 1'b0;
|
||||
UD_SAMPLE = 1'b0;
|
||||
end
|
||||
|
||||
5'b01000: begin //CHECK SAMPLE TO SEE IF IT IS ON A TRANSITION
|
||||
INC = 1'b0;
|
||||
ICE = 1'b0;
|
||||
COUNT = 1'b0;
|
||||
UD = 1'b1;
|
||||
STORE = 1'b0;
|
||||
STORE_DATA_PREV = 1'b1;
|
||||
BITSLIP = 1'b0;
|
||||
COUNT_SAMPLE = 1'b1;
|
||||
UD_SAMPLE = 1'b1;
|
||||
end
|
||||
|
||||
5'b01111: begin //IF SAMPLED POINT IS TRANSITION, EDGE IS FOUND, SO INC DELAY TO EXIT TRANSITION
|
||||
INC = 1'b1;
|
||||
ICE = 1'b1;
|
||||
COUNT = 1'b0;
|
||||
UD = 1'b1;
|
||||
STORE = 1'b0;
|
||||
STORE_DATA_PREV = 1'b1;
|
||||
BITSLIP = 1'b0;
|
||||
COUNT_SAMPLE = 1'b0;
|
||||
UD_SAMPLE = 1'b0;
|
||||
end
|
||||
|
||||
5'b01101: begin //WAIT 16 CYCLES WHILE APPLYING BITSLIP TO FIND CHECK_PATTERN
|
||||
INC = 1'b0;
|
||||
ICE = 1'b0;
|
||||
COUNT = 1'b0;
|
||||
UD = 1'b1;
|
||||
STORE = 1'b0;
|
||||
STORE_DATA_PREV = 1'b1;
|
||||
BITSLIP = 1'b1;
|
||||
COUNT_SAMPLE = 1'b1;
|
||||
UD_SAMPLE = 1'b1;
|
||||
end
|
||||
|
||||
5'b01100: begin //IDLE (NEEDED FOR COUNTER RESET BEFORE NEXT STATE)
|
||||
INC = 1'b0;
|
||||
ICE = 1'b0;
|
||||
COUNT = 1'b0;
|
||||
UD = 1'b1;
|
||||
STORE = 1'b0;
|
||||
STORE_DATA_PREV = 1'b1;
|
||||
BITSLIP = 1'b0;
|
||||
COUNT_SAMPLE = 1'b0;
|
||||
UD_SAMPLE = 1'b0;
|
||||
end
|
||||
|
||||
5'b10000: begin //IDLE (NEEDED FOR STABILIZATION)
|
||||
INC = 1'b0;
|
||||
ICE = 1'b0;
|
||||
COUNT = 1'b0;
|
||||
UD = 1'b1;
|
||||
STORE = 1'b0;
|
||||
STORE_DATA_PREV = 1'b1;
|
||||
BITSLIP = 1'b0;
|
||||
COUNT_SAMPLE = 1'b0;
|
||||
UD_SAMPLE = 1'b0;
|
||||
end
|
||||
|
||||
5'b00010: begin //CHECK SAMPLE AGAIN TO SEE IF WE HAVE EXITED TRANSITION
|
||||
INC = 1'b0;
|
||||
ICE = 1'b0;
|
||||
COUNT = 1'b0;
|
||||
UD = 1'b1;
|
||||
STORE = 1'b0;
|
||||
STORE_DATA_PREV = 1'b1;
|
||||
BITSLIP = 1'b0;
|
||||
COUNT_SAMPLE = 1'b1;
|
||||
UD_SAMPLE = 1'b1;
|
||||
end
|
||||
|
||||
5'b01011: begin //INITIAL STATE WAS STABLE, SO INC ONCE TO SEARCH FOR TRANS
|
||||
INC = 1'b1;
|
||||
ICE = 1'b1;
|
||||
COUNT = 1'b0;
|
||||
UD = 1'b0;
|
||||
STORE = 1'b0;
|
||||
STORE_DATA_PREV = 1'b1;
|
||||
BITSLIP = 1'b0;
|
||||
COUNT_SAMPLE = 1'b0;
|
||||
UD_SAMPLE = 1'b0;
|
||||
end
|
||||
|
||||
5'b00100: begin //WAIT 8 CYCLES, COMPARE RXDATA WITH PREVIOUS DATA
|
||||
INC = 1'b0;
|
||||
ICE = 1'b0;
|
||||
COUNT = 1'b0;
|
||||
UD = 1'b0;
|
||||
STORE = 1'b0;
|
||||
STORE_DATA_PREV = 1'b0;
|
||||
BITSLIP = 1'b0;
|
||||
COUNT_SAMPLE = 1'b1;
|
||||
UD_SAMPLE = 1'b1;
|
||||
end
|
||||
|
||||
5'b01110: begin //DATA IS STABLE AFTER FINDING 1ST TRANS, COUNT 1 TO INCLUDE LAST INC
|
||||
INC = 1'b0;
|
||||
ICE = 1'b0;
|
||||
COUNT = 1'b1;
|
||||
UD = 1'b1;
|
||||
STORE = 1'b0;
|
||||
STORE_DATA_PREV = 1'b1;
|
||||
BITSLIP = 1'b0;
|
||||
COUNT_SAMPLE = 1'b0;
|
||||
UD_SAMPLE = 1'b0;
|
||||
end
|
||||
|
||||
5'b01001: begin //INC ONCE TO LOOK FOR 2ND TRANS
|
||||
INC = 1'b1;
|
||||
ICE = 1'b1;
|
||||
COUNT = 1'b1;
|
||||
UD = 1'b1;
|
||||
STORE = 1'b0;
|
||||
STORE_DATA_PREV = 1'b1;
|
||||
BITSLIP = 1'b0;
|
||||
COUNT_SAMPLE = 1'b0;
|
||||
UD_SAMPLE = 1'b0;
|
||||
end
|
||||
|
||||
5'b00011: begin //WAIT 8 CYCLES, COMPARE RXDATA WITH PREVIOUS DATA
|
||||
INC = 1'b0;
|
||||
ICE = 1'b0;
|
||||
COUNT = 1'b0;
|
||||
UD = 1'b1;
|
||||
STORE = 1'b1;
|
||||
STORE_DATA_PREV = 1'b0;
|
||||
BITSLIP = 1'b0;
|
||||
COUNT_SAMPLE = 1'b1;
|
||||
UD_SAMPLE = 1'b1;
|
||||
end
|
||||
|
||||
5'b10010: begin //IDLE (NEEDED FOR COUNTER RESET BEFORE NEXT STATE)
|
||||
INC = 1'b0;
|
||||
ICE = 1'b0;
|
||||
COUNT = 1'b0;
|
||||
UD = 1'b0;
|
||||
STORE = 1'b0;
|
||||
STORE_DATA_PREV = 1'b1;
|
||||
BITSLIP = 1'b0;
|
||||
COUNT_SAMPLE = 1'b0;
|
||||
UD_SAMPLE = 1'b0;
|
||||
end
|
||||
|
||||
5'b01010: begin //DECREMENT TO CENTER OF DATA EYE
|
||||
INC = 1'b0;
|
||||
ICE = 1'b1;
|
||||
COUNT = 1'b0;
|
||||
UD = 1'b0;
|
||||
STORE = 1'b0;
|
||||
STORE_DATA_PREV = 1'b1;
|
||||
BITSLIP = 1'b0;
|
||||
COUNT_SAMPLE = 1'b1;
|
||||
UD_SAMPLE = 1'b1;
|
||||
end
|
||||
|
||||
5'b00101: begin //SAMPLE PATTERN 16 TIMES TO SEE IF WORD ALIGNMENT NEEDED
|
||||
INC = 1'b0;
|
||||
ICE = 1'b0;
|
||||
COUNT = 1'b1;
|
||||
UD = 1'b1;
|
||||
STORE = 1'b0;
|
||||
STORE_DATA_PREV = 1'b1;
|
||||
BITSLIP = 1'b0;
|
||||
COUNT_SAMPLE = 1'b0;
|
||||
UD_SAMPLE = 1'b0;
|
||||
end
|
||||
|
||||
5'b00110: begin //INITIATE 1 BITSLIP
|
||||
INC = 1'b0;
|
||||
ICE = 1'b0;
|
||||
COUNT = 1'b0;
|
||||
UD = 1'b0;
|
||||
STORE = 1'b0;
|
||||
STORE_DATA_PREV = 1'b1;
|
||||
BITSLIP = 1'b1;
|
||||
COUNT_SAMPLE = 1'b0;
|
||||
UD_SAMPLE = 1'b0;
|
||||
end
|
||||
|
||||
5'b00111: begin //TRAINING COMPLETE ON THIS CHANNEL
|
||||
INC = 1'b0;
|
||||
ICE = 1'b0;
|
||||
COUNT = 1'b0;
|
||||
UD = 1'b0;
|
||||
STORE = 1'b0;
|
||||
STORE_DATA_PREV = 1'b1;
|
||||
BITSLIP = 1'b0;
|
||||
COUNT_SAMPLE = 1'b0;
|
||||
UD_SAMPLE = 1'b0;
|
||||
end
|
||||
|
||||
default: begin
|
||||
INC = 1'b0;
|
||||
ICE = 1'b0;
|
||||
COUNT = 1'b0;
|
||||
UD = 1'b0;
|
||||
STORE = 1'b0;
|
||||
STORE_DATA_PREV = 1'b1;
|
||||
BITSLIP = 1'b0;
|
||||
COUNT_SAMPLE = 1'b0;
|
||||
UD_SAMPLE = 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
`timescale 1 ns / 10 ps
|
||||
module RCB_FRL_seven_bit_reg_w_ce(Q, CLK, CE, D, RST);
|
||||
|
||||
input [6:0] D;
|
||||
input CLK, CE, RST;
|
||||
|
||||
output [6:0] Q;
|
||||
|
||||
FDRE bit0(.Q(Q[0]), .C(CLK), .CE(CE), .D(D[0]), .R(RST));
|
||||
FDRE bit1(.Q(Q[1]), .C(CLK), .CE(CE), .D(D[1]), .R(RST));
|
||||
FDRE bit2(.Q(Q[2]), .C(CLK), .CE(CE), .D(D[2]), .R(RST));
|
||||
FDRE bit3(.Q(Q[3]), .C(CLK), .CE(CE), .D(D[3]), .R(RST));
|
||||
FDRE bit4(.Q(Q[4]), .C(CLK), .CE(CE), .D(D[4]), .R(RST));
|
||||
FDRE bit5(.Q(Q[5]), .C(CLK), .CE(CE), .D(D[5]), .R(RST));
|
||||
FDRE bit6(.Q(Q[6]), .C(CLK), .CE(CE), .D(D[6]), .R(RST));
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,254 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 17:27:17 08/15/2011
|
||||
// Design Name:
|
||||
// Module Name: RCB_FRL_BYTE_Alignment
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
// Byte alignment and Sora-FRL packet decapsulation
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module RCB_FRL_BYTE_Alignment(
|
||||
input clk,
|
||||
input enable, //Active low reset
|
||||
input [7:0] data_in,
|
||||
|
||||
output reg data_valid,
|
||||
output reg [7:0] data_out
|
||||
);
|
||||
|
||||
// modified by zjs, 2009-3-9, none of the parameters are really used
|
||||
// parameter lock_pattern = 8'hf5; //Specifies the lock pattern
|
||||
// parameter pack_size = 100; // Current packet size
|
||||
// parameter word_size = 8; // Not currently used in code
|
||||
|
||||
// output lockk;
|
||||
|
||||
reg [7:0] data_reg1; //First register used to re-align the data
|
||||
reg [7:0] data_reg2; //Second register used to re-align the data
|
||||
reg [7:0] data_reg3; //Third register used to re-align the data
|
||||
reg [2:0] shift; //designate the bit shift value of the package
|
||||
reg lock; //if high, then the correct shift value has been found.
|
||||
reg [7:0] byte_count; //word count in packet
|
||||
reg [2:0] front_count;
|
||||
reg [7:0] data_out_tmp; //pipeline register
|
||||
// reg data_valid;
|
||||
|
||||
reg [7:0] frame_length;
|
||||
// reg [7:0] data_out; // output register
|
||||
|
||||
// wire end_pack = pack_size; // signifies end of packet
|
||||
|
||||
|
||||
|
||||
always @(negedge clk) //°′2éμ?μ???í·ê?3???3ì
|
||||
// always @(negedge clk) // timing broken to set data_valid flag
|
||||
begin
|
||||
if (!enable)begin
|
||||
data_out_tmp <= 8'h00; //test data_out_tmp <= 8'h00;
|
||||
//data_valid<=1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
//data_valid<=1'b1;
|
||||
case(shift) //Re-aligns the data depending on shift value
|
||||
3'h0 : data_out_tmp <= data_reg1;
|
||||
3'h1 : data_out_tmp <= ({data_reg1[6:0],data_in[7]});
|
||||
3'h2 : data_out_tmp <= ({data_reg1[5:0],data_in[7:6]});
|
||||
3'h3 : data_out_tmp <= ({data_reg1[4:0],data_in[7:5]});
|
||||
3'h4 : data_out_tmp <= ({data_reg1[3:0],data_in[7:4]});
|
||||
3'h5 : data_out_tmp <= ({data_reg1[2:0],data_in[7:3]});
|
||||
3'h6 : data_out_tmp <= ({data_reg1[1:0],data_in[7:2]});
|
||||
3'h7 : data_out_tmp <= ({data_reg1[0],data_in[7:1]});
|
||||
default : data_out_tmp <= data_reg1;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
// Word counter, counts words in packet
|
||||
always@(negedge clk) //??êy??3ì
|
||||
begin
|
||||
if(!enable || !lock) // Active low reset
|
||||
begin
|
||||
byte_count <= 0; //Initializes byte count
|
||||
front_count <= 0;
|
||||
//frame_length <= 0;
|
||||
end
|
||||
|
||||
if(lock)//lock data_valid
|
||||
begin
|
||||
byte_count <= byte_count + 1; //Increments the byte count to keep track of packet boundry
|
||||
front_count <= front_count+1;
|
||||
end
|
||||
end
|
||||
|
||||
// Data shift registers
|
||||
always @(negedge clk) //
|
||||
begin
|
||||
if(!enable)
|
||||
begin
|
||||
data_reg1 <= 8'h00; //Initializes the registers
|
||||
data_reg2 <= 8'h00;
|
||||
data_reg3 <= 8'h00;
|
||||
end
|
||||
else
|
||||
begin
|
||||
data_reg1 <= data_in; // Registers incoming data, shifts to compare registers
|
||||
data_reg2 <= data_reg1; // reg2 and reg3 are compare registers
|
||||
data_reg3 <= data_reg2;
|
||||
end
|
||||
end
|
||||
|
||||
// Search and validate
|
||||
|
||||
always @(negedge clk) //
|
||||
begin
|
||||
if(!enable) // if (!enable)
|
||||
begin
|
||||
lock <= 0;
|
||||
shift <= 0;
|
||||
data_out <= 8'h00; ///data_out <= 8'h00; //////
|
||||
data_valid <= 0;
|
||||
frame_length <= 0;
|
||||
end
|
||||
|
||||
else //else 1
|
||||
begin //
|
||||
//data_out <= 8'hff;
|
||||
if(!lock) //If not locked, search for lock pattern
|
||||
begin //begin search
|
||||
|
||||
// data_out <= data_reg2;
|
||||
/// temporarily added 64 into this
|
||||
|
||||
if(data_reg3 === 8'hf5 & data_reg2 === 8'h08/*8'h64*/) // modified by zjs, 2009-3-9
|
||||
// if(data_reg3 === 8'hf5 & data_reg2 === 8'h1D/*8'h64*/) // modified by zjs, 2009-3-9
|
||||
begin
|
||||
// data_out <= 8'hff;
|
||||
//data_valid <= 1;
|
||||
lock <= 1;
|
||||
shift <= 3'h0;
|
||||
end
|
||||
|
||||
else if({data_reg3[6:0],data_reg2[7]} === 8'hf5 & {data_reg2[6:0],data_reg1[7]} === 8'h08/*8'h64*/ )
|
||||
// else if({data_reg3[6:0],data_reg2[7]} === 8'hf5 & {data_reg2[6:0],data_reg1[7]} === 8'h1D/*8'h64*/ )
|
||||
begin
|
||||
lock <= 1;
|
||||
shift <= 3'h1;
|
||||
end
|
||||
|
||||
else if({data_reg3[5:0],data_reg2[7:6]} === 8'hf5 & {data_reg2[5:0],data_reg1[7:6]} === 8'h08/*8'h64*/)
|
||||
// else if({data_reg3[5:0],data_reg2[7:6]} === 8'hf5 & {data_reg2[5:0],data_reg1[7:6]} === 8'h1D/*8'h64*/)
|
||||
begin
|
||||
lock <= 1;
|
||||
shift <= 3'h2;
|
||||
end
|
||||
|
||||
else if({data_reg3[4:0],data_reg2[7:5]} === 8'hf5 & {data_reg2[4:0],data_reg1[7:5]} === 8'h08/*8'h64*/)
|
||||
// else if({data_reg3[4:0],data_reg2[7:5]} === 8'hf5 & {data_reg2[4:0],data_reg1[7:5]} === 8'h1D/*8'h64*/)
|
||||
begin
|
||||
lock <= 1;
|
||||
shift <= 3'h3;
|
||||
end
|
||||
|
||||
else if({data_reg3[3:0],data_reg2[7:4]} === 8'hf5 & {data_reg2[3:0],data_reg1[7:4]} === 8'h08/*8'h64*/)
|
||||
// else if({data_reg3[3:0],data_reg2[7:4]} === 8'hf5 & {data_reg2[3:0],data_reg1[7:4]} === 8'h1D/*8'h64*/)
|
||||
begin
|
||||
lock <= 1;
|
||||
shift <= 3'h4;
|
||||
end
|
||||
|
||||
else if({data_reg3[2:0],data_reg2[7:3]} === 8'hf5 & {data_reg2[2:0],data_reg1[7:3]} === 8'h08/*8'h64*/)
|
||||
// else if({data_reg3[2:0],data_reg2[7:3]} === 8'hf5 & {data_reg2[2:0],data_reg1[7:3]} === 8'h1D/*8'h64*/)
|
||||
begin
|
||||
lock <= 1;
|
||||
shift <= 3'h5;
|
||||
end
|
||||
|
||||
else if({data_reg3[1:0],data_reg2[7:2]} === 8'hf5 & {data_reg2[1:0],data_reg1[7:2]} === 8'h08/*8'h64*/)
|
||||
// else if({data_reg3[1:0],data_reg2[7:2]} === 8'hf5 & {data_reg2[1:0],data_reg1[7:2]} === 8'h1D/*8'h64*/)
|
||||
begin
|
||||
lock <= 1;
|
||||
shift <= 3'h6;
|
||||
end
|
||||
|
||||
else if({data_reg3[0],data_reg2[7:1]} === 8'hf5 & {data_reg2[0],data_reg1[7:1]} === 8'h08/*8'h64*/) //lock_pattern
|
||||
// else if({data_reg3[0],data_reg2[7:1]} === 8'hf5 & {data_reg2[0],data_reg1[7:1]} === 8'h1D/*8'h64*/) //lock_pattern
|
||||
begin
|
||||
lock <= 1;
|
||||
shift <= 3'h7;
|
||||
end
|
||||
|
||||
end //if (!lock) // end search
|
||||
|
||||
else if (lock)
|
||||
begin //Confirms that data is valid
|
||||
/* if( byte_count == 8'h00) //the frame head
|
||||
begin
|
||||
data_valid <= 0;
|
||||
data_out <= 8'hff; //output the frame head
|
||||
end
|
||||
else if(byte_count == 8'h01) //the frame length
|
||||
begin
|
||||
data_valid <= 0;
|
||||
data_out <= data_out_tmp;
|
||||
frame_length <= data_out_tmp;
|
||||
end*/
|
||||
// if(byte_count < 8) // modified by zjs, 2009-3-9
|
||||
if(byte_count < 29) // modified by zjs, 2009-3-9
|
||||
begin
|
||||
data_valid <= 1;
|
||||
data_out <= data_out_tmp;
|
||||
end
|
||||
else
|
||||
begin
|
||||
data_valid <= 0;
|
||||
lock <= 0;
|
||||
shift <= 0;
|
||||
frame_length <= 0;
|
||||
end
|
||||
end //end if(lock)
|
||||
|
||||
end //end else if(enable)
|
||||
end //end always
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 00:09:17 06/06/2009
|
||||
// Design Name:
|
||||
// Module Name: RCB_FRL_COUNT_TO_64
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module RCB_FRL_COUNT_TO_64(
|
||||
input clk,
|
||||
input rst,
|
||||
input count,
|
||||
input ud,
|
||||
output reg [5:0] counter_value /*synthesis syn_noprune = 1*/
|
||||
);
|
||||
|
||||
//This module counts up/down between 0 to 63
|
||||
|
||||
wire [5:0] counter_value_preserver;
|
||||
// reg [5:0] counter_value/*synthesis syn_noprune = 1*/;
|
||||
|
||||
always@(posedge clk or posedge rst) begin
|
||||
if(rst == 1'b1)
|
||||
counter_value = 6'h00;
|
||||
else begin
|
||||
case({count,ud})
|
||||
2'b00: counter_value = counter_value_preserver;
|
||||
2'b01: counter_value = counter_value_preserver;
|
||||
2'b10: counter_value = counter_value_preserver - 1;
|
||||
2'b11: counter_value = counter_value_preserver + 1;
|
||||
default: counter_value = 6'h00;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
assign counter_value_preserver = counter_value;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module RCB_FRL_CRC_gen ( D, NewCRC);
|
||||
|
||||
input [47:0] D;
|
||||
output [7:0] NewCRC;
|
||||
|
||||
|
||||
assign NewCRC[0] = D[46] ^ D[42] ^ D[41] ^ D[37] ^ D[36] ^ D[35] ^ D[34] ^
|
||||
D[33] ^ D[31] ^ D[30] ^ D[29] ^ D[27] ^ D[26] ^ D[24] ^
|
||||
D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
|
||||
D[8] ^ D[7] ^ D[6] ^ D[3] ^ D[1] ^ D[0];
|
||||
assign NewCRC[1] = D[47] ^ D[43] ^ D[42] ^ D[38] ^ D[37] ^ D[36] ^ D[35] ^
|
||||
D[34] ^ D[32] ^ D[31] ^ D[30] ^ D[28] ^ D[27] ^ D[25] ^
|
||||
D[21] ^ D[19] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^
|
||||
D[9] ^ D[8] ^ D[7] ^ D[4] ^ D[2] ^ D[1];
|
||||
assign NewCRC[2] = D[46] ^ D[44] ^ D[43] ^ D[42] ^ D[41] ^ D[39] ^ D[38] ^
|
||||
D[34] ^ D[32] ^ D[30] ^ D[28] ^ D[27] ^ D[24] ^ D[22] ^
|
||||
D[19] ^ D[14] ^ D[13] ^ D[10] ^ D[9] ^ D[7] ^ D[6] ^
|
||||
D[5] ^ D[2] ^ D[1] ^ D[0];
|
||||
assign NewCRC[3] = D[47] ^ D[45] ^ D[44] ^ D[43] ^ D[42] ^ D[40] ^ D[39] ^
|
||||
D[35] ^ D[33] ^ D[31] ^ D[29] ^ D[28] ^ D[25] ^ D[23] ^
|
||||
D[20] ^ D[15] ^ D[14] ^ D[11] ^ D[10] ^ D[8] ^ D[7] ^
|
||||
D[6] ^ D[3] ^ D[2] ^ D[1];
|
||||
assign NewCRC[4] = D[45] ^ D[44] ^ D[43] ^ D[42] ^ D[40] ^ D[37] ^ D[35] ^
|
||||
D[33] ^ D[32] ^ D[31] ^ D[27] ^ D[21] ^ D[20] ^ D[18] ^
|
||||
D[17] ^ D[14] ^ D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[6] ^
|
||||
D[4] ^ D[2] ^ D[1] ^ D[0];
|
||||
assign NewCRC[5] = D[46] ^ D[45] ^ D[44] ^ D[43] ^ D[41] ^ D[38] ^ D[36] ^
|
||||
D[34] ^ D[33] ^ D[32] ^ D[28] ^ D[22] ^ D[21] ^ D[19] ^
|
||||
D[18] ^ D[15] ^ D[14] ^ D[13] ^ D[12] ^ D[10] ^ D[7] ^
|
||||
D[5] ^ D[3] ^ D[2] ^ D[1];
|
||||
assign NewCRC[6] = D[47] ^ D[45] ^ D[44] ^ D[41] ^ D[39] ^ D[36] ^ D[31] ^
|
||||
D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[23] ^ D[22] ^ D[19] ^
|
||||
D[18] ^ D[17] ^ D[11] ^ D[7] ^ D[4] ^ D[2] ^ D[1] ^
|
||||
D[0];
|
||||
assign NewCRC[7] = D[45] ^ D[41] ^ D[40] ^ D[36] ^ D[35] ^ D[34] ^ D[33] ^
|
||||
D[32] ^ D[30] ^ D[29] ^ D[28] ^ D[26] ^ D[25] ^ D[23] ^
|
||||
D[19] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^ D[12] ^
|
||||
D[7] ^ D[6] ^ D[5] ^ D[2] ^ D[0];
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,359 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Summary:
|
||||
//
|
||||
// The DDR_8TO1_16CHAN_RX module contains logic for LVDS Receiver,
|
||||
// including 5 channels of LVDS data, one channel of LVDS clock, a clock/data
|
||||
// alignment algorithm, control circuit to share the alignment machine among
|
||||
// all 5 data channels, and tap counters that keep track of the IDELAY tap
|
||||
// setting of all data channels.
|
||||
//
|
||||
//----------------------------------------------------------------
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module RCB_FRL_DDR_8TO1_16CHAN_RX
|
||||
(
|
||||
input RXCLK,
|
||||
input RXCLKDIV,
|
||||
input RESET,
|
||||
input IDLY_RESET,
|
||||
|
||||
input [4:0] DATA_RX_P,
|
||||
input [4:0] DATA_RX_N,
|
||||
input INC_PAD,
|
||||
input DEC_PAD,
|
||||
input BITSLIP_PAD,
|
||||
|
||||
output [39:0] DATA_FROM_ISERDES,
|
||||
output [5:0] TAP_00,
|
||||
output [5:0] TAP_01,
|
||||
output [5:0] TAP_02,
|
||||
output [5:0] TAP_03,
|
||||
output [5:0] TAP_04,
|
||||
output [5:0] TAP_CLK,
|
||||
output TRAINING_DONE
|
||||
);
|
||||
|
||||
|
||||
wire [4:0] DATA_RX_BUF;
|
||||
wire [4:0] DATA_RX_IDLY;
|
||||
wire BITSLIP_FROM_MACHINE;
|
||||
wire ICE_FROM_MACHINE;
|
||||
wire INC_FROM_MACHINE;
|
||||
wire DATA_ALIGNED;
|
||||
wire [4:0] SHIFT1;
|
||||
wire [4:0] SHIFT2;
|
||||
wire [3:0] CHAN_SEL;
|
||||
|
||||
reg [4:0] INC_CAPTURE;
|
||||
reg [4:0] DEC_CAPTURE;
|
||||
reg [4:0] BITSLIP_CAPTURE;
|
||||
reg INC_PULSE;
|
||||
reg DEC_PULSE;
|
||||
reg BITSLIP_PULSE;
|
||||
reg [20:0] RESET_SM;
|
||||
reg [4:0] BITSLIP_TO_ISERDES;
|
||||
reg [4:0] ICE_TO_ISERDES;
|
||||
reg [4:0] INC_TO_ISERDES;
|
||||
reg [7:0] DATA_TO_MACHINE;
|
||||
|
||||
integer I;
|
||||
|
||||
assign INC_DELAY = INC_PULSE;
|
||||
assign ICE_DELAY = INC_PULSE || DEC_PULSE;
|
||||
assign TAP_CLK = 6'h01; //CLOCK DELAY IS NOT ADJUSTED IN THIS REFERENCE DESIGN
|
||||
|
||||
|
||||
//CHANNEL SELECT LOGIC TO SHARE ALIGNMENT MACHINE RESOURCES IN ROUND ROBIN FASHION
|
||||
always @(posedge RXCLKDIV) begin
|
||||
case (CHAN_SEL)
|
||||
4'b0000: begin
|
||||
DATA_TO_MACHINE <= DATA_FROM_ISERDES[7:0];
|
||||
INC_TO_ISERDES <= {15'b000000000000000, INC_FROM_MACHINE};
|
||||
ICE_TO_ISERDES <= {15'b000000000000000, ICE_FROM_MACHINE};
|
||||
BITSLIP_TO_ISERDES <= {15'b000000000000000, BITSLIP_FROM_MACHINE};
|
||||
end
|
||||
|
||||
4'b0001: begin
|
||||
DATA_TO_MACHINE <= DATA_FROM_ISERDES[15:8];
|
||||
INC_TO_ISERDES <= {14'b00000000000000, INC_FROM_MACHINE, 1'b0};
|
||||
ICE_TO_ISERDES <= {14'b00000000000000, ICE_FROM_MACHINE, 1'b0};
|
||||
BITSLIP_TO_ISERDES <= {14'b00000000000000, BITSLIP_FROM_MACHINE, 1'b0};
|
||||
end
|
||||
|
||||
4'b0010: begin
|
||||
DATA_TO_MACHINE <= DATA_FROM_ISERDES[23:16];
|
||||
INC_TO_ISERDES <= {13'b0000000000000, INC_FROM_MACHINE, 2'b00};
|
||||
ICE_TO_ISERDES <= {13'b0000000000000, ICE_FROM_MACHINE, 2'b00};
|
||||
BITSLIP_TO_ISERDES <= {13'b0000000000000, BITSLIP_FROM_MACHINE, 2'b00};
|
||||
end
|
||||
|
||||
4'b0011: begin
|
||||
DATA_TO_MACHINE <= DATA_FROM_ISERDES[31:24];
|
||||
INC_TO_ISERDES <= {12'b000000000000, INC_FROM_MACHINE, 3'b000};
|
||||
ICE_TO_ISERDES <= {12'b000000000000, ICE_FROM_MACHINE, 3'b000};
|
||||
BITSLIP_TO_ISERDES <= {12'b000000000000, BITSLIP_FROM_MACHINE, 3'b000};
|
||||
end
|
||||
4'b0100: begin
|
||||
DATA_TO_MACHINE <= DATA_FROM_ISERDES[39:32];
|
||||
INC_TO_ISERDES <= {11'b00000000000, INC_FROM_MACHINE, 4'b0000};
|
||||
ICE_TO_ISERDES <= {11'b00000000000, ICE_FROM_MACHINE, 4'b0000};
|
||||
BITSLIP_TO_ISERDES <= {11'b00000000000, BITSLIP_FROM_MACHINE, 4'b0000};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
//MACHINE THAT ALLOCATES BIT_ALIGN_MACHINE TO EACH OF THE 5 DATA CHANNELS, ONE AT A TIME
|
||||
RCB_FRL_RESOURCE_SHARING_CONTROL RCB_FRL_RESOURCE_SHARING_CONTROL_inst (
|
||||
.CLK (RXCLKDIV),
|
||||
.RST (RESET),
|
||||
.CHAN_SEL (CHAN_SEL),
|
||||
.START_ALIGN (START_ALIGN),
|
||||
.DATA_ALIGNED (DATA_ALIGNED),
|
||||
.ALL_CHANNELS_ALIGNED (TRAINING_DONE)
|
||||
);
|
||||
|
||||
//MACHINE THAT ADJUSTS DELAY OF A SINGLE DATA CHANNEL TO OPTIMIZE SAMPLING POINT
|
||||
RCB_FRL_BIT_ALIGN_MACHINE RCB_FRL_BIT_ALIGN_MACHINE_inst (
|
||||
.RXCLKDIV (RXCLKDIV),
|
||||
.RST (RESET||RESET_SM[15]),
|
||||
.RXDATA (DATA_TO_MACHINE),
|
||||
.USE_BITSLIP (1'b1),
|
||||
.SAP (START_ALIGN),
|
||||
.INC (INC_FROM_MACHINE),
|
||||
.ICE (ICE_FROM_MACHINE),
|
||||
.BITSLIP (BITSLIP_FROM_MACHINE),
|
||||
.DATA_ALIGNED (DATA_ALIGNED)
|
||||
);
|
||||
|
||||
//SHORTEN EACH EXTERNAL INC AND DEC PULSE TO ONE RXCLKDIV CYCLE
|
||||
always @(posedge RXCLKDIV) begin
|
||||
INC_CAPTURE[0] <= INC_PAD; //ASYNCHRONOUS ENTRY POINT
|
||||
DEC_CAPTURE[0] <= DEC_PAD;
|
||||
BITSLIP_CAPTURE[0] <= BITSLIP_PAD;
|
||||
begin
|
||||
for(I = 0; I <= 3 - 1; I = I + 1)
|
||||
begin
|
||||
INC_CAPTURE[I + 1] <= INC_CAPTURE[I]; //METASTABLE FLIP-FLOPS
|
||||
DEC_CAPTURE[I + 1] <= DEC_CAPTURE[I];
|
||||
BITSLIP_CAPTURE[I + 1] <= BITSLIP_CAPTURE[I];
|
||||
end
|
||||
end
|
||||
INC_PULSE <= INC_CAPTURE[2] & ~INC_CAPTURE[3]; //STABLE, SINGLE PULSE
|
||||
DEC_PULSE <= DEC_CAPTURE[2] & ~DEC_CAPTURE[3];
|
||||
BITSLIP_PULSE <= BITSLIP_CAPTURE[2] & ~BITSLIP_CAPTURE[3];
|
||||
end
|
||||
|
||||
//KEEP TRACK OF CURRENT TAP SETTING OF IDELAY IN DATA PATH OF CHANNELS 00-04
|
||||
RCB_FRL_COUNT_TO_64 TAP_COUNTER_00(
|
||||
.clk(RXCLKDIV),
|
||||
.rst(IDLY_RESET||RESET),
|
||||
.count(ICE_DELAY||ICE_TO_ISERDES[00]),
|
||||
.ud(INC_DELAY||INC_TO_ISERDES[00]),
|
||||
.counter_value(TAP_00)
|
||||
);
|
||||
RCB_FRL_COUNT_TO_64 TAP_COUNTER_01(
|
||||
.clk(RXCLKDIV),
|
||||
.rst(IDLY_RESET||RESET),
|
||||
.count(ICE_DELAY||ICE_TO_ISERDES[01]),
|
||||
.ud(INC_DELAY||INC_TO_ISERDES[01]),
|
||||
.counter_value(TAP_01)
|
||||
);
|
||||
RCB_FRL_COUNT_TO_64 TAP_COUNTER_02(
|
||||
.clk(RXCLKDIV),
|
||||
.rst(IDLY_RESET||RESET),
|
||||
.count(ICE_DELAY||ICE_TO_ISERDES[02]),
|
||||
.ud(INC_DELAY||INC_TO_ISERDES[02]),
|
||||
.counter_value(TAP_02)
|
||||
);
|
||||
RCB_FRL_COUNT_TO_64 TAP_COUNTER_03(
|
||||
.clk(RXCLKDIV),
|
||||
.rst(IDLY_RESET||RESET),
|
||||
.count(ICE_DELAY||ICE_TO_ISERDES[03]),
|
||||
.ud(INC_DELAY||INC_TO_ISERDES[03]),
|
||||
.counter_value(TAP_03)
|
||||
);
|
||||
RCB_FRL_COUNT_TO_64 TAP_COUNTER_04(
|
||||
.clk(RXCLKDIV),
|
||||
.rst(IDLY_RESET||RESET),
|
||||
.count(ICE_DELAY||ICE_TO_ISERDES[04]),
|
||||
.ud(INC_DELAY||INC_TO_ISERDES[04]),
|
||||
.counter_value(TAP_04)
|
||||
);
|
||||
|
||||
//CIRCUIT TO PRODUCE RESET DELAYED BY 20 CYCLES FOR BIT_ALIGN_MACHINE
|
||||
integer K;
|
||||
always @(posedge RXCLKDIV) begin
|
||||
RESET_SM[0] <= RESET;
|
||||
for(K = 0; K <= 20 - 1; K = K + 1) begin
|
||||
RESET_SM[K+1] <= RESET_SM[K];
|
||||
end
|
||||
end
|
||||
|
||||
//DATA INPUT BUFFERS
|
||||
IBUFDS #(.DIFF_TERM("FALSE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_00(.O(DATA_RX_BUF[00]), .I(DATA_RX_P[00]), .IB(DATA_RX_N[00]));
|
||||
IBUFDS #(.DIFF_TERM("FALSE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_01(.O(DATA_RX_BUF[01]), .I(DATA_RX_P[01]), .IB(DATA_RX_N[01]));
|
||||
IBUFDS #(.DIFF_TERM("FALSE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_02(.O(DATA_RX_BUF[02]), .I(DATA_RX_P[02]), .IB(DATA_RX_N[02]));
|
||||
IBUFDS #(.DIFF_TERM("FALSE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_03(.O(DATA_RX_BUF[03]), .I(DATA_RX_P[03]), .IB(DATA_RX_N[03]));
|
||||
IBUFDS #(.DIFF_TERM("FALSE"), .IOSTANDARD("LVDS_25")) RX_DATA_IN_04(.O(DATA_RX_BUF[04]), .I(DATA_RX_P[04]), .IB(DATA_RX_N[04]));
|
||||
|
||||
//INPUT DELAY IN DATA PATH
|
||||
IODELAY #(
|
||||
.IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .ODELAY_VALUE(0), .REFCLK_FREQUENCY(200.00),
|
||||
.HIGH_PERFORMANCE_MODE("TRUE"))
|
||||
IODELAY_RX_DATA_00 (
|
||||
.DATAOUT(DATA_RX_IDLY[00]), .IDATAIN(DATA_RX_BUF[00]), .ODATAIN(1'b0), .DATAIN(1'b0),
|
||||
.T(), .CE(ICE_DELAY||ICE_TO_ISERDES[00]), .INC(INC_DELAY||INC_TO_ISERDES[00]), .C(RXCLKDIV), .RST(IDLY_RESET||RESET));
|
||||
IODELAY #(
|
||||
.IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .ODELAY_VALUE(0), .REFCLK_FREQUENCY(200.00),
|
||||
.HIGH_PERFORMANCE_MODE("TRUE"))
|
||||
IODELAY_RX_DATA_01 (
|
||||
.DATAOUT(DATA_RX_IDLY[01]), .IDATAIN(DATA_RX_BUF[01]), .ODATAIN(1'b0), .DATAIN(1'b0),
|
||||
.T(), .CE(ICE_DELAY||ICE_TO_ISERDES[01]), .INC(INC_DELAY||INC_TO_ISERDES[01]), .C(RXCLKDIV), .RST(IDLY_RESET||RESET));
|
||||
IODELAY #(
|
||||
.IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .ODELAY_VALUE(0), .REFCLK_FREQUENCY(200.00),
|
||||
.HIGH_PERFORMANCE_MODE("TRUE"))
|
||||
IODELAY_RX_DATA_02 (
|
||||
.DATAOUT(DATA_RX_IDLY[02]), .IDATAIN(DATA_RX_BUF[02]), .ODATAIN(1'b0), .DATAIN(1'b0),
|
||||
.T(), .CE(ICE_DELAY||ICE_TO_ISERDES[02]), .INC(INC_DELAY||INC_TO_ISERDES[02]), .C(RXCLKDIV), .RST(IDLY_RESET||RESET));
|
||||
IODELAY #(
|
||||
.IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .ODELAY_VALUE(0), .REFCLK_FREQUENCY(200.00),
|
||||
.HIGH_PERFORMANCE_MODE("TRUE"))
|
||||
IODELAY_RX_DATA_03 (
|
||||
.DATAOUT(DATA_RX_IDLY[03]), .IDATAIN(DATA_RX_BUF[03]), .ODATAIN(1'b0), .DATAIN(1'b0),
|
||||
.T(), .CE(ICE_DELAY||ICE_TO_ISERDES[03]), .INC(INC_DELAY||INC_TO_ISERDES[03]), .C(RXCLKDIV), .RST(IDLY_RESET||RESET));
|
||||
IODELAY #(
|
||||
.IDELAY_TYPE("VARIABLE"), .IDELAY_VALUE(0), .ODELAY_VALUE(0), .REFCLK_FREQUENCY(200.00),
|
||||
.HIGH_PERFORMANCE_MODE("TRUE"))
|
||||
IODELAY_RX_DATA_04 (
|
||||
.DATAOUT(DATA_RX_IDLY[04]), .IDATAIN(DATA_RX_BUF[04]), .ODATAIN(1'b0), .DATAIN(1'b0),
|
||||
.T(), .CE(ICE_DELAY||ICE_TO_ISERDES[04]), .INC(INC_DELAY||INC_TO_ISERDES[04]), .C(RXCLKDIV), .RST(IDLY_RESET||RESET));
|
||||
|
||||
|
||||
//M ISERDES IN DATA PATH
|
||||
ISERDES_NODELAY #(
|
||||
.BITSLIP_ENABLE("TRUE"), .DATA_RATE("DDR"), .DATA_WIDTH(8), .INTERFACE_TYPE("NETWORKING"),
|
||||
.NUM_CE(1), .SERDES_MODE("MASTER")
|
||||
) ISERDES_RX_DATA_00(
|
||||
.Q1(DATA_FROM_ISERDES[000]), .Q2(DATA_FROM_ISERDES[001]), .Q3(DATA_FROM_ISERDES[002]),
|
||||
.Q4(DATA_FROM_ISERDES[003]), .Q5(DATA_FROM_ISERDES[004]), .Q6(DATA_FROM_ISERDES[005]),
|
||||
.SHIFTOUT1(SHIFT1[00]), .SHIFTOUT2(SHIFT2[00]), .BITSLIP(BITSLIP_PULSE||BITSLIP_TO_ISERDES[00]),
|
||||
.CE1(1'b1), .CE2(), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_IDLY[00]),
|
||||
.OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET)
|
||||
);
|
||||
ISERDES_NODELAY #(
|
||||
.BITSLIP_ENABLE("TRUE"), .DATA_RATE("DDR"), .DATA_WIDTH(8), .INTERFACE_TYPE("NETWORKING"),
|
||||
.NUM_CE(1), .SERDES_MODE("MASTER")
|
||||
) ISERDES_RX_DATA_01(
|
||||
.Q1(DATA_FROM_ISERDES[008]), .Q2(DATA_FROM_ISERDES[009]), .Q3(DATA_FROM_ISERDES[010]),
|
||||
.Q4(DATA_FROM_ISERDES[011]), .Q5(DATA_FROM_ISERDES[012]), .Q6(DATA_FROM_ISERDES[013]),
|
||||
.SHIFTOUT1(SHIFT1[01]), .SHIFTOUT2(SHIFT2[01]), .BITSLIP(BITSLIP_PULSE||BITSLIP_TO_ISERDES[01]),
|
||||
.CE1(1'b1), .CE2(), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_IDLY[01]),
|
||||
.OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET)
|
||||
);
|
||||
ISERDES_NODELAY #(
|
||||
.BITSLIP_ENABLE("TRUE"), .DATA_RATE("DDR"), .DATA_WIDTH(8), .INTERFACE_TYPE("NETWORKING"),
|
||||
.NUM_CE(1), .SERDES_MODE("MASTER")
|
||||
) ISERDES_RX_DATA_02(
|
||||
.Q1(DATA_FROM_ISERDES[016]), .Q2(DATA_FROM_ISERDES[017]), .Q3(DATA_FROM_ISERDES[018]),
|
||||
.Q4(DATA_FROM_ISERDES[019]), .Q5(DATA_FROM_ISERDES[020]), .Q6(DATA_FROM_ISERDES[021]),
|
||||
.SHIFTOUT1(SHIFT1[02]), .SHIFTOUT2(SHIFT2[02]), .BITSLIP(BITSLIP_PULSE||BITSLIP_TO_ISERDES[02]),
|
||||
.CE1(1'b1), .CE2(), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_IDLY[02]),
|
||||
.OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET)
|
||||
);
|
||||
ISERDES_NODELAY #(
|
||||
.BITSLIP_ENABLE("TRUE"), .DATA_RATE("DDR"), .DATA_WIDTH(8), .INTERFACE_TYPE("NETWORKING"),
|
||||
.NUM_CE(1), .SERDES_MODE("MASTER")
|
||||
) ISERDES_RX_DATA_03(
|
||||
.Q1(DATA_FROM_ISERDES[024]), .Q2(DATA_FROM_ISERDES[025]), .Q3(DATA_FROM_ISERDES[026]),
|
||||
.Q4(DATA_FROM_ISERDES[027]), .Q5(DATA_FROM_ISERDES[028]), .Q6(DATA_FROM_ISERDES[029]),
|
||||
.SHIFTOUT1(SHIFT1[03]), .SHIFTOUT2(SHIFT2[03]), .BITSLIP(BITSLIP_PULSE||BITSLIP_TO_ISERDES[03]),
|
||||
.CE1(1'b1), .CE2(), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_IDLY[03]),
|
||||
.OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET)
|
||||
);
|
||||
ISERDES_NODELAY #(
|
||||
.BITSLIP_ENABLE("TRUE"), .DATA_RATE("DDR"), .DATA_WIDTH(8), .INTERFACE_TYPE("NETWORKING"),
|
||||
.NUM_CE(1), .SERDES_MODE("MASTER")
|
||||
) ISERDES_RX_DATA_04(
|
||||
.Q1(DATA_FROM_ISERDES[032]), .Q2(DATA_FROM_ISERDES[033]), .Q3(DATA_FROM_ISERDES[034]),
|
||||
.Q4(DATA_FROM_ISERDES[035]), .Q5(DATA_FROM_ISERDES[036]), .Q6(DATA_FROM_ISERDES[037]),
|
||||
.SHIFTOUT1(SHIFT1[04]), .SHIFTOUT2(SHIFT2[04]), .BITSLIP(BITSLIP_PULSE||BITSLIP_TO_ISERDES[04]),
|
||||
.CE1(1'b1), .CE2(), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(DATA_RX_IDLY[04]),
|
||||
.OCLK(), .SHIFTIN1(), .SHIFTIN2(), .RST(RESET)
|
||||
);
|
||||
|
||||
//S ISERDES IN DATA PATH
|
||||
ISERDES_NODELAY #(
|
||||
.BITSLIP_ENABLE("TRUE"), .DATA_RATE("DDR"), .DATA_WIDTH(8), .INTERFACE_TYPE("NETWORKING"),
|
||||
.NUM_CE(1), .SERDES_MODE("SLAVE")
|
||||
) ISERDES_RX_DATA_00S(
|
||||
.Q1(), .Q2(), .Q3(DATA_FROM_ISERDES[006]), .Q4(DATA_FROM_ISERDES[007]), .Q5(), .Q6(),
|
||||
.SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(BITSLIP_PULSE||BITSLIP_TO_ISERDES[00]),
|
||||
.CE1(1'b1), .CE2(), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(), .OCLK(),
|
||||
.SHIFTIN1(SHIFT1[00]), .SHIFTIN2(SHIFT2[00]), .RST(RESET)
|
||||
);
|
||||
ISERDES_NODELAY #(
|
||||
.BITSLIP_ENABLE("TRUE"), .DATA_RATE("DDR"), .DATA_WIDTH(8), .INTERFACE_TYPE("NETWORKING"),
|
||||
.NUM_CE(1), .SERDES_MODE("SLAVE")
|
||||
) ISERDES_RX_DATA_01S(
|
||||
.Q1(), .Q2(), .Q3(DATA_FROM_ISERDES[014]), .Q4(DATA_FROM_ISERDES[015]), .Q5(), .Q6(),
|
||||
.SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(BITSLIP_PULSE||BITSLIP_TO_ISERDES[01]),
|
||||
.CE1(1'b1), .CE2(), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(), .OCLK(),
|
||||
.SHIFTIN1(SHIFT1[01]), .SHIFTIN2(SHIFT2[01]), .RST(RESET)
|
||||
);
|
||||
ISERDES_NODELAY #(
|
||||
.BITSLIP_ENABLE("TRUE"), .DATA_RATE("DDR"), .DATA_WIDTH(8), .INTERFACE_TYPE("NETWORKING"),
|
||||
.NUM_CE(1), .SERDES_MODE("SLAVE")
|
||||
) ISERDES_RX_DATA_02S(
|
||||
.Q1(), .Q2(), .Q3(DATA_FROM_ISERDES[022]), .Q4(DATA_FROM_ISERDES[023]), .Q5(), .Q6(),
|
||||
.SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(BITSLIP_PULSE||BITSLIP_TO_ISERDES[02]),
|
||||
.CE1(1'b1), .CE2(), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(), .OCLK(),
|
||||
.SHIFTIN1(SHIFT1[02]), .SHIFTIN2(SHIFT2[02]), .RST(RESET)
|
||||
);
|
||||
ISERDES_NODELAY #(
|
||||
.BITSLIP_ENABLE("TRUE"), .DATA_RATE("DDR"), .DATA_WIDTH(8), .INTERFACE_TYPE("NETWORKING"),
|
||||
.NUM_CE(1), .SERDES_MODE("SLAVE")
|
||||
) ISERDES_RX_DATA_03S(
|
||||
.Q1(), .Q2(), .Q3(DATA_FROM_ISERDES[030]), .Q4(DATA_FROM_ISERDES[031]), .Q5(), .Q6(),
|
||||
.SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(BITSLIP_PULSE||BITSLIP_TO_ISERDES[03]),
|
||||
.CE1(1'b1), .CE2(), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(), .OCLK(),
|
||||
.SHIFTIN1(SHIFT1[03]), .SHIFTIN2(SHIFT2[03]), .RST(RESET)
|
||||
);
|
||||
ISERDES_NODELAY #(
|
||||
.BITSLIP_ENABLE("TRUE"), .DATA_RATE("DDR"), .DATA_WIDTH(8), .INTERFACE_TYPE("NETWORKING"),
|
||||
.NUM_CE(1), .SERDES_MODE("SLAVE")
|
||||
) ISERDES_RX_DATA_04S(
|
||||
.Q1(), .Q2(), .Q3(DATA_FROM_ISERDES[038]), .Q4(DATA_FROM_ISERDES[039]), .Q5(), .Q6(),
|
||||
.SHIFTOUT1(), .SHIFTOUT2(), .BITSLIP(BITSLIP_PULSE||BITSLIP_TO_ISERDES[04]),
|
||||
.CE1(1'b1), .CE2(), .CLK(RXCLK), .CLKB(~RXCLK), .CLKDIV(RXCLKDIV), .D(), .OCLK(),
|
||||
.SHIFTIN1(SHIFT1[04]), .SHIFTIN2(SHIFT2[04]), .RST(RESET)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,137 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 03:04:50 02/19/2009
|
||||
// Design Name:
|
||||
// Module Name: RCB_FRL_LED_Clock
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module RCB_FRL_LED_Clock(Test_Clock_in, LED_Clock_out, RST);
|
||||
input Test_Clock_in;
|
||||
output LED_Clock_out;
|
||||
input RST;
|
||||
|
||||
reg[9:0] count1;
|
||||
reg[9:0] count2;
|
||||
reg[9:0] count3;
|
||||
reg LED_Clock_out_reg;
|
||||
|
||||
assign LED_Clock_out = LED_Clock_out_reg;
|
||||
|
||||
always @(posedge Test_Clock_in or posedge RST) begin
|
||||
if (RST) begin
|
||||
count1 <= 1'b0;
|
||||
count2 <= 1'b0;
|
||||
count3 <= 1'b0;
|
||||
LED_Clock_out_reg <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (count3 < 448) begin
|
||||
if (count2 < 1000) begin
|
||||
if (count1 < 1000)
|
||||
count1 <= count1 + 1'b1;
|
||||
else
|
||||
begin
|
||||
count1 <= 1'b0;
|
||||
count2 <= count2 + 1'b1;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
count2 <= 1'b0;
|
||||
count3 <= count3 + 1'b1;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
count3 <= 1'b0;
|
||||
LED_Clock_out_reg <= ~LED_Clock_out_reg;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module RCB_FRL_LED_Clock_DIV(Test_Clock_in, LED_Clock_out, RST);
|
||||
input Test_Clock_in;
|
||||
output LED_Clock_out;
|
||||
input RST;
|
||||
|
||||
reg[9:0] count1;
|
||||
reg[9:0] count2;
|
||||
reg[9:0] count3;
|
||||
reg LED_Clock_out_reg;
|
||||
|
||||
assign LED_Clock_out = LED_Clock_out_reg;
|
||||
|
||||
always @(posedge Test_Clock_in or posedge RST) begin
|
||||
if (RST) begin
|
||||
count1 <= 1'b0;
|
||||
count2 <= 1'b0;
|
||||
count3 <= 1'b0;
|
||||
LED_Clock_out_reg <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (count3 < 56) begin
|
||||
if (count2 < 1000) begin
|
||||
if (count1 < 1000)
|
||||
count1 <= count1 + 1'b1;
|
||||
else
|
||||
begin
|
||||
count1 <= 1'b0;
|
||||
count2 <= count2 + 1'b1;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
count2 <= 1'b0;
|
||||
count3 <= count3 + 1'b1;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
count3 <= 1'b0;
|
||||
LED_Clock_out_reg <= ~LED_Clock_out_reg;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module RCB_FRL_OSERDES(OQ, CLK, CLKDIV, DI, OCE, SR);
|
||||
|
||||
output OQ;
|
||||
input CLK, CLKDIV;
|
||||
input [7:0] DI;
|
||||
input OCE, SR;
|
||||
|
||||
wire SHIFT1, SHIFT2;
|
||||
|
||||
OSERDES OSERDES_inst1 (
|
||||
.OQ(OQ), // 1-bit data path output
|
||||
.SHIFTOUT1(), // 1-bit data expansion output
|
||||
.SHIFTOUT2(), // 1-bit data expansion output
|
||||
.TQ(), // 1-bit 3-state control output
|
||||
.CLK(CLK), // 1-bit clock input
|
||||
.CLKDIV(CLKDIV), // 1-bit divided clock input
|
||||
.D1(DI[7]), // 1-bit parallel data input
|
||||
.D2(DI[6]), // 1-bit parallel data input
|
||||
.D3(DI[5]), // 1-bit parallel data input
|
||||
.D4(DI[4]), // 1-bit parallel data input
|
||||
.D5(DI[3]), // 1-bit parallel data input
|
||||
.D6(DI[2]), // 1-bit parallel data input
|
||||
.OCE(OCE), // 1-bit clock enable input
|
||||
.REV(1'b0), // 1-bit reverse SR input
|
||||
.SHIFTIN1(SHIFT1), // 1-bit data expansion input
|
||||
.SHIFTIN2(SHIFT2), // 1-bit data expansion input
|
||||
.SR(SR), // 1-bit set/reset input
|
||||
.T1(), // 1-bit parallel 3-state input
|
||||
.T2(), // 1-bit parallel 3-state input
|
||||
.T3(), // 1-bit parallel 3-state input
|
||||
.T4(), // 1-bit parallel 3-state input
|
||||
.TCE(1'b1) // 1-bit 3-state signal clock enable input
|
||||
);
|
||||
defparam OSERDES_inst1.DATA_RATE_OQ = "DDR";
|
||||
defparam OSERDES_inst1.DATA_RATE_TQ = "DDR";
|
||||
defparam OSERDES_inst1.DATA_WIDTH = 8;
|
||||
defparam OSERDES_inst1.SERDES_MODE = "MASTER";
|
||||
defparam OSERDES_inst1.TRISTATE_WIDTH = 1;
|
||||
|
||||
OSERDES OSERDES_inst2 (
|
||||
.OQ(), // 1-bit data path output
|
||||
.SHIFTOUT1(SHIFT1), // 1-bit data expansion output
|
||||
.SHIFTOUT2(SHIFT2), // 1-bit data expansion output
|
||||
.TQ(), // 1-bit 3-state control output
|
||||
.CLK(CLK), // 1-bit clock input
|
||||
.CLKDIV(CLKDIV), // 1-bit divided clock input
|
||||
.D1(), // 1-bit parallel data input
|
||||
.D2(), // 1-bit parallel data input
|
||||
.D3(DI[1]), // 1-bit parallel data input
|
||||
.D4(DI[0]), // 1-bit parallel data input
|
||||
.D5(), // 1-bit parallel data input
|
||||
.D6(), // 1-bit parallel data input
|
||||
.OCE(OCE), // 1-bit clock enable input
|
||||
.REV(1'b0), // 1-bit reverse SR input
|
||||
.SHIFTIN1(), // 1-bit data expansion input
|
||||
.SHIFTIN2(), // 1-bit data expansion input
|
||||
.SR(SR), // 1-bit set/reset input
|
||||
.T1(), // 1-bit parallel 3-state input
|
||||
.T2(), // 1-bit parallel 3-state input
|
||||
.T3(), // 1-bit parallel 3-state input
|
||||
.T4(), // 1-bit parallel 3-state input
|
||||
.TCE(1'b1) // 1-bit 3-state signal clock enable input
|
||||
);
|
||||
defparam OSERDES_inst2.DATA_RATE_OQ = "DDR";
|
||||
defparam OSERDES_inst2.DATA_RATE_TQ = "DDR";
|
||||
defparam OSERDES_inst2.DATA_WIDTH = 8;
|
||||
defparam OSERDES_inst2.SERDES_MODE = "SLAVE";
|
||||
defparam OSERDES_inst2.TRISTATE_WIDTH = 1;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module RCB_FRL_OSERDES_MSG(OQ, clk, clkdiv, DI, OCE, SR);
|
||||
|
||||
output OQ;
|
||||
input clk, clkdiv;
|
||||
input [7:0] DI;
|
||||
input OCE, SR;
|
||||
|
||||
wire SHIFT1, SHIFT2;
|
||||
|
||||
OSERDES OSERDES_inst1 (
|
||||
.OQ(OQ), // 1-bit data path output
|
||||
.SHIFTOUT1(), // 1-bit data expansion output
|
||||
.SHIFTOUT2(), // 1-bit data expansion output
|
||||
.TQ(), // 1-bit 3-state control output
|
||||
.CLK(clk), // 1-bit clock input
|
||||
.CLKDIV(clkdiv), // 1-bit divided clock input
|
||||
.D1(DI[7]), // 1-bit parallel data input
|
||||
.D2(DI[6]), // 1-bit parallel data input
|
||||
.D3(DI[5]), // 1-bit parallel data input
|
||||
.D4(DI[4]), // 1-bit parallel data input
|
||||
.D5(DI[3]), // 1-bit parallel data input
|
||||
.D6(DI[2]), // 1-bit parallel data input
|
||||
.OCE(OCE), // 1-bit clock enable input
|
||||
.REV(1'b0), // 1-bit reverse SR input
|
||||
.SHIFTIN1(SHIFT1), // 1-bit data expansion input
|
||||
.SHIFTIN2(SHIFT2), // 1-bit data expansion input
|
||||
.SR(SR), // 1-bit set/reset input
|
||||
.T1(), // 1-bit parallel 3-state input
|
||||
.T2(), // 1-bit parallel 3-state input
|
||||
.T3(), // 1-bit parallel 3-state input
|
||||
.T4(), // 1-bit parallel 3-state input
|
||||
.TCE(1'b1) // 1-bit 3-state signal clock enable input
|
||||
);
|
||||
defparam OSERDES_inst1.DATA_RATE_OQ = "DDR";
|
||||
defparam OSERDES_inst1.DATA_RATE_TQ = "DDR";
|
||||
defparam OSERDES_inst1.DATA_WIDTH = 8;
|
||||
defparam OSERDES_inst1.SERDES_MODE = "MASTER";
|
||||
defparam OSERDES_inst1.TRISTATE_WIDTH = 1;
|
||||
|
||||
OSERDES OSERDES_inst2 (
|
||||
.OQ(), // 1-bit data path output
|
||||
.SHIFTOUT1(SHIFT1), // 1-bit data expansion output
|
||||
.SHIFTOUT2(SHIFT2), // 1-bit data expansion output
|
||||
.TQ(), // 1-bit 3-state control output
|
||||
.CLK(clk), // 1-bit clock input
|
||||
.CLKDIV(clkdiv), // 1-bit divided clock input
|
||||
.D1(), // 1-bit parallel data input
|
||||
.D2(), // 1-bit parallel data input
|
||||
.D3(DI[1]), // 1-bit parallel data input
|
||||
.D4(DI[0]), // 1-bit parallel data input
|
||||
.D5(), // 1-bit parallel data input
|
||||
.D6(), // 1-bit parallel data input
|
||||
.OCE(OCE), // 1-bit clock enable input
|
||||
.REV(1'b0), // 1-bit reverse SR input
|
||||
.SHIFTIN1(), // 1-bit data expansion input
|
||||
.SHIFTIN2(), // 1-bit data expansion input
|
||||
.SR(SR), // 1-bit set/reset input
|
||||
.T1(), // 1-bit parallel 3-state input
|
||||
.T2(), // 1-bit parallel 3-state input
|
||||
.T3(), // 1-bit parallel 3-state input
|
||||
.T4(), // 1-bit parallel 3-state input
|
||||
.TCE(1'b1) // 1-bit 3-state signal clock enable input
|
||||
);
|
||||
defparam OSERDES_inst2.DATA_RATE_OQ = "DDR";
|
||||
defparam OSERDES_inst2.DATA_RATE_TQ = "DDR";
|
||||
defparam OSERDES_inst2.DATA_WIDTH = 8;
|
||||
defparam OSERDES_inst2.SERDES_MODE = "SLAVE";
|
||||
defparam OSERDES_inst2.TRISTATE_WIDTH = 1;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,203 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Summary:
|
||||
//
|
||||
// The RESOURCE_SHARING_CONTROL module allocates the BIT_ALIGN_MACHINE
|
||||
// module to each of the 16 data channels of the interface. Each channel
|
||||
// must be aligned one at a time, such that the RESOURCE_SHARING_CONTROL module
|
||||
// must determine when training on a given channel is complete, and then
|
||||
// switch the context to the next channel.
|
||||
//
|
||||
//----------------------------------------------------------------
|
||||
|
||||
module RCB_FRL_RESOURCE_SHARING_CONTROL (
|
||||
input CLK,
|
||||
input RST,
|
||||
input DATA_ALIGNED,
|
||||
output [3:0] CHAN_SEL,
|
||||
output reg START_ALIGN,
|
||||
output ALL_CHANNELS_ALIGNED
|
||||
);
|
||||
|
||||
|
||||
wire [6:0] COUNT_VALUE;
|
||||
|
||||
reg UD_DELAY;
|
||||
reg COUNT_DELAY;
|
||||
reg COUNT_CHAN;
|
||||
reg [2:0] CS;
|
||||
reg [2:0] NS;
|
||||
|
||||
parameter INIT = 3'b000;
|
||||
parameter INC_CHAN_SEL = 3'b001;
|
||||
parameter WAIT_8 = 3'b010;
|
||||
parameter START_NEXT = 3'b011;
|
||||
parameter LAST_CHAN = 3'b100;
|
||||
parameter TRAIN_DONE = 3'b101;
|
||||
parameter IDLE = 3'b110;
|
||||
parameter START_LAST = 3'b111;
|
||||
|
||||
assign ALL_CHANNELS_ALIGNED = CS[2] & ~CS[1] & CS[0];
|
||||
|
||||
RCB_FRL_count_to_128 delay_counter(
|
||||
.clk(CLK),
|
||||
.rst(RST),
|
||||
.count(COUNT_DELAY),
|
||||
.ud(UD_DELAY),
|
||||
.counter_value(COUNT_VALUE)
|
||||
);
|
||||
|
||||
RCB_FRL_count_to_16x channel_counter(
|
||||
.clk(CLK),
|
||||
.rst(RST),
|
||||
.count(COUNT_CHAN),
|
||||
.counter_value(CHAN_SEL)
|
||||
);
|
||||
|
||||
//CURRENT STATE LOGIC
|
||||
always@(posedge CLK) begin
|
||||
if (RST == 1'b1)
|
||||
CS <= INIT;
|
||||
else
|
||||
CS <= NS;
|
||||
end
|
||||
|
||||
//NEXT_STATE LOGIC
|
||||
always @(CS or DATA_ALIGNED or COUNT_VALUE or CHAN_SEL) begin
|
||||
case (CS)
|
||||
INIT: begin
|
||||
if (COUNT_VALUE < 7'h08 || DATA_ALIGNED == 1'b0)
|
||||
NS <= INIT;
|
||||
else
|
||||
NS <= IDLE;
|
||||
end
|
||||
|
||||
IDLE: NS <= INC_CHAN_SEL;
|
||||
|
||||
INC_CHAN_SEL: NS <= WAIT_8;
|
||||
|
||||
WAIT_8: begin
|
||||
if (COUNT_VALUE < 7'h08)
|
||||
NS <= WAIT_8;
|
||||
else if (CHAN_SEL == 4'b0100)
|
||||
NS <= START_LAST;
|
||||
else
|
||||
NS <= START_NEXT;
|
||||
end
|
||||
|
||||
START_NEXT: NS <= INIT;
|
||||
|
||||
START_LAST: NS <= LAST_CHAN;
|
||||
|
||||
LAST_CHAN: begin
|
||||
if (COUNT_VALUE < 7'h08 || DATA_ALIGNED == 1'b0)
|
||||
NS <= LAST_CHAN;
|
||||
else
|
||||
NS <= TRAIN_DONE;
|
||||
end
|
||||
|
||||
TRAIN_DONE: NS <= TRAIN_DONE;
|
||||
|
||||
default: NS <= INIT;
|
||||
endcase
|
||||
end
|
||||
|
||||
//OUTPUT LOGIC
|
||||
always @(CS) begin
|
||||
case (CS)
|
||||
INIT: begin
|
||||
COUNT_CHAN <= 1'b0;
|
||||
COUNT_DELAY <= 1'b1;
|
||||
UD_DELAY <= 1'b1;
|
||||
START_ALIGN <= 1'b0;
|
||||
end
|
||||
|
||||
IDLE: begin
|
||||
COUNT_CHAN <= 1'b0;
|
||||
COUNT_DELAY <= 1'b0;
|
||||
UD_DELAY <= 1'b0;
|
||||
START_ALIGN <= 1'b0;
|
||||
end
|
||||
|
||||
INC_CHAN_SEL: begin
|
||||
COUNT_CHAN <= 1'b1;
|
||||
COUNT_DELAY <= 1'b0;
|
||||
UD_DELAY <= 1'b0;
|
||||
START_ALIGN <= 1'b0;
|
||||
end
|
||||
|
||||
WAIT_8: begin
|
||||
COUNT_CHAN <= 1'b0;
|
||||
COUNT_DELAY <= 1'b1;
|
||||
UD_DELAY <= 1'b1;
|
||||
START_ALIGN <= 1'b0;
|
||||
end
|
||||
|
||||
START_NEXT: begin
|
||||
COUNT_CHAN <= 1'b0;
|
||||
COUNT_DELAY <= 1'b0;
|
||||
UD_DELAY <= 1'b0;
|
||||
START_ALIGN <= 1'b1;
|
||||
end
|
||||
|
||||
START_LAST: begin
|
||||
COUNT_CHAN <= 1'b0;
|
||||
COUNT_DELAY <= 1'b0;
|
||||
UD_DELAY <= 1'b0;
|
||||
START_ALIGN <= 1'b1;
|
||||
end
|
||||
|
||||
LAST_CHAN: begin
|
||||
COUNT_CHAN <= 1'b0;
|
||||
COUNT_DELAY <= 1'b1;
|
||||
UD_DELAY <= 1'b1;
|
||||
START_ALIGN <= 1'b0;
|
||||
end
|
||||
|
||||
TRAIN_DONE: begin
|
||||
COUNT_CHAN <= 1'b0;
|
||||
COUNT_DELAY <= 1'b0;
|
||||
UD_DELAY <= 1'b0;
|
||||
START_ALIGN <= 1'b0;
|
||||
end
|
||||
|
||||
default: begin
|
||||
COUNT_CHAN <= 1'b1;
|
||||
COUNT_DELAY <= 1'b0;
|
||||
UD_DELAY <= 1'b0;
|
||||
START_ALIGN <= 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,165 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 11:19:11 02/11/2009
|
||||
// Design Name:
|
||||
// Module Name: RCB_FRL_RX
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
////////////////////
|
||||
module RCB_FRL_RX(
|
||||
input CLKDIV,
|
||||
input [31:0] DATA_IN,
|
||||
output [31:0] DATA_OUT,
|
||||
input RST,
|
||||
// input RDCLK,
|
||||
input RDEN,
|
||||
output ALMOSTEMPTY
|
||||
// output fifo_WREN
|
||||
);
|
||||
|
||||
wire [7:0] data_channel1;
|
||||
wire [7:0] data_channel2;
|
||||
wire [7:0] data_channel3;
|
||||
wire [7:0] data_channel4;
|
||||
|
||||
wire wren_channel1;
|
||||
wire wren_channel2;
|
||||
wire wren_channel3;
|
||||
wire wren_channel4;
|
||||
|
||||
wire pempty_channel1;
|
||||
wire pempty_channel2;
|
||||
wire pempty_channel3;
|
||||
wire pempty_channel4;
|
||||
|
||||
|
||||
assign ALMOSTEMPTY = pempty_channel1 | pempty_channel2 | pempty_channel3 | pempty_channel4;
|
||||
|
||||
|
||||
// four data channels, to do byte alignment and Sora-FRL packet decapsulation
|
||||
RCB_FRL_RX_OneDataChannel RCB_FRL_RX_Decapsulation_01_inst (
|
||||
.CLKDIV(CLKDIV), .DATA_IN(DATA_IN[7:0]), .RST(RST), .data_valid(wren_channel1),
|
||||
.data_out(data_channel1[7:0])
|
||||
);
|
||||
|
||||
RCB_FRL_RX_OneDataChannel RCB_FRL_RX_Decapsulation_02_inst (
|
||||
.CLKDIV(CLKDIV), .DATA_IN(DATA_IN[15:8]), .RST(RST), .data_valid(wren_channel2),
|
||||
.data_out(data_channel2[7:0])
|
||||
);
|
||||
|
||||
RCB_FRL_RX_OneDataChannel RCB_FRL_RX_Decapsulation_03_inst (
|
||||
.CLKDIV(CLKDIV), .DATA_IN(DATA_IN[23:16]), .RST(RST), .data_valid(wren_channel3),
|
||||
.data_out(data_channel3[7:0])
|
||||
);
|
||||
|
||||
RCB_FRL_RX_OneDataChannel RCB_FRL_RX_Decapsulation_04_inst (
|
||||
.CLKDIV(CLKDIV), .DATA_IN(DATA_IN[31:24]), .RST(RST), .data_valid(wren_channel4),
|
||||
.data_out(data_channel4[7:0])
|
||||
);
|
||||
|
||||
// assign fifo_WREN = wren_channel1 & wren_channel2 & wren_channel3 & wren_channel4;
|
||||
|
||||
// Four 8-bit data fifos for four data channels
|
||||
RCB_FRL_RX_Data_FIFO_onechannel RCB_FRL_RX_Data_FIFO_onechannel_inst1(
|
||||
.clk (CLKDIV),
|
||||
.rst (RST),
|
||||
.din (data_channel1[7:0]), // Bus [7 : 0]
|
||||
.wr_en (wren_channel1),
|
||||
.rd_en (RDEN),
|
||||
.dout (DATA_OUT[7:0]), // Bus [7 : 0]
|
||||
.full (),
|
||||
.empty (),
|
||||
.prog_empty (pempty_channel1)
|
||||
);
|
||||
RCB_FRL_RX_Data_FIFO_onechannel RCB_FRL_RX_Data_FIFO_onechannel_inst2(
|
||||
.clk (CLKDIV),
|
||||
.rst (RST),
|
||||
.din (data_channel2[7:0]), // Bus [7 : 0]
|
||||
.wr_en (wren_channel2),
|
||||
.rd_en (RDEN),
|
||||
.dout (DATA_OUT[15:8]), // Bus [7 : 0]
|
||||
.full (),
|
||||
.empty (),
|
||||
.prog_empty (pempty_channel2)
|
||||
);
|
||||
RCB_FRL_RX_Data_FIFO_onechannel RCB_FRL_RX_Data_FIFO_onechannel_inst3(
|
||||
.clk (CLKDIV),
|
||||
.rst (RST),
|
||||
.din (data_channel3[7:0]), // Bus [7 : 0]
|
||||
.wr_en (wren_channel3),
|
||||
.rd_en (RDEN),
|
||||
.dout (DATA_OUT[23:16]), // Bus [7 : 0]
|
||||
.full (),
|
||||
.empty (),
|
||||
.prog_empty (pempty_channel3)
|
||||
);
|
||||
RCB_FRL_RX_Data_FIFO_onechannel RCB_FRL_RX_Data_FIFO_onechannel_inst4(
|
||||
.clk (CLKDIV),
|
||||
.rst (RST),
|
||||
.din (data_channel4[7:0]), // Bus [7 : 0]
|
||||
.wr_en (wren_channel4),
|
||||
.rd_en (RDEN),
|
||||
.dout (DATA_OUT[31:24]), // Bus [7 : 0]
|
||||
.full (),
|
||||
.empty (),
|
||||
.prog_empty (pempty_channel4)
|
||||
);
|
||||
// RCB_FRL_RX_Data_FIFO_8bit RCB_FRL_RX_Data_FIFO_01_inst(
|
||||
// .ALMOSTEMPTY(pempty_channel1), .ALMOSTFULL(), .DO(DATA_OUT [7:0]), .EMPTY(), .FULL(),
|
||||
// .DI(data_channel1[7:0]), .RDCLK(RDCLK), .RDEN(RDEN), .WRCLK(CLKDIV), .WREN(wren_channel1), .RST(RST)
|
||||
// );
|
||||
//
|
||||
// RCB_FRL_RX_Data_FIFO_8bit RCB_FRL_RX_Data_FIFO_02_inst(
|
||||
// .ALMOSTEMPTY(pempty_channel2), .ALMOSTFULL(), .DO(DATA_OUT [15:8]), .EMPTY(), .FULL(),
|
||||
// .DI(data_channel2[7:0]), .RDCLK(RDCLK), .RDEN(RDEN), .WRCLK(CLKDIV), .WREN(wren_channel2), .RST(RST)
|
||||
// );
|
||||
//
|
||||
// RCB_FRL_RX_Data_FIFO_8bit RCB_FRL_RX_Data_FIFO_03_inst(
|
||||
// .ALMOSTEMPTY(pempty_channel3), .ALMOSTFULL(), .DO(DATA_OUT [23:16]), .EMPTY(), .FULL(),
|
||||
// .DI(data_channel3[7:0]), .RDCLK(RDCLK), .RDEN(RDEN), .WRCLK(CLKDIV), .WREN(wren_channel3), .RST(RST)
|
||||
// );
|
||||
//
|
||||
// RCB_FRL_RX_Data_FIFO_8bit RCB_FRL_RX_Data_FIFO_04_inst(
|
||||
// .ALMOSTEMPTY(pempty_channel4), .ALMOSTFULL(), .DO(DATA_OUT [31:24]), .EMPTY(), .FULL(),
|
||||
// .DI(data_channel4[7:0]), .RDCLK(RDCLK), .RDEN(RDEN), .WRCLK(CLKDIV), .WREN(wren_channel4), .RST(RST)
|
||||
// );
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,223 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 19:29:55 08/15/2011
|
||||
// Design Name:
|
||||
// Module Name: RCB_FRL_RXMSG_ACK_Decoder
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module RCB_FRL_RXMSG_ACK_Decoder(
|
||||
input clk,
|
||||
input enable, //Active low reset
|
||||
input [7:0] data_in,
|
||||
output reg CON_P,
|
||||
output reg CON_N
|
||||
);
|
||||
|
||||
// parameter lock_pattern = 8'hff ; //Specifies the lock pattern
|
||||
// parameter pack_size = 100; // Current packet size
|
||||
// parameter word_size = 8; // Not currently used in code
|
||||
|
||||
reg [7:0] data_reg1; //First register used to re-align the data
|
||||
reg [7:0] data_reg2; //Second register used to re-align the data
|
||||
reg [7:0] data_reg3; //Third register used to re-align the data
|
||||
reg [2:0] shift; //designate the bit shift value of the package
|
||||
reg lock; //if high, then the correct shift value has been found.
|
||||
reg [7:0] byte_count; //word count in packet
|
||||
reg [2:0] front_count;
|
||||
reg [7:0] data_out_tmp; //pipeline register
|
||||
reg data_valid;
|
||||
|
||||
reg [7:0] frame_length;
|
||||
reg [7:0] data_out; // output register
|
||||
reg data_correct;
|
||||
reg data_wrong;
|
||||
reg [39:0] data_all;
|
||||
|
||||
// wire end_pack = pack_size; // signifies end of packet
|
||||
|
||||
always @(negedge clk) // timing broken to set data_valid flag
|
||||
begin
|
||||
if (!enable)
|
||||
begin
|
||||
data_out_tmp <= 8'h00; //test
|
||||
end
|
||||
else
|
||||
begin
|
||||
case(shift) //Re-aligns the data depending on shift value
|
||||
3'h0 : data_out_tmp <= data_reg3;
|
||||
3'h1 : data_out_tmp <= ({data_reg3[6:0],data_reg2[7]});
|
||||
3'h2 : data_out_tmp <= ({data_reg3[5:0],data_reg2[7:6]});
|
||||
3'h3 : data_out_tmp <= ({data_reg3[4:0],data_reg2[7:5]});
|
||||
3'h4 : data_out_tmp <= ({data_reg3[3:0],data_reg2[7:4]});
|
||||
3'h5 : data_out_tmp <= ({data_reg3[2:0],data_reg2[7:3]});
|
||||
3'h6 : data_out_tmp <= ({data_reg3[1:0],data_reg2[7:2]});
|
||||
3'h7 : data_out_tmp <= ({data_reg3[0],data_reg2[7:1]});
|
||||
default : data_out_tmp <= data_reg3;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// Data shift registers
|
||||
always @(negedge clk) //
|
||||
begin
|
||||
if(!enable)
|
||||
begin
|
||||
data_reg1 <= 8'h00; //Initializes the registers
|
||||
data_reg2 <= 8'h00;
|
||||
data_reg3 <= 8'h00;
|
||||
end
|
||||
else
|
||||
begin
|
||||
data_reg1 <= data_in; // Registers incoming data, shifts to compare registers
|
||||
data_reg2 <= data_reg1; // reg2 and reg3 are compare registers
|
||||
data_reg3 <= data_reg2;
|
||||
end
|
||||
end
|
||||
|
||||
// Search and validate
|
||||
|
||||
always @(negedge clk) //
|
||||
begin
|
||||
if(!enable)
|
||||
begin
|
||||
lock <= 0;
|
||||
shift <= 0;
|
||||
data_out <= 8'h00;
|
||||
data_valid <= 0;
|
||||
frame_length <= 0;
|
||||
end
|
||||
|
||||
else
|
||||
begin
|
||||
if(data_reg3 === 8'h5f )
|
||||
begin
|
||||
CON_P <= 1'b1;
|
||||
end
|
||||
|
||||
else if({data_reg3[6:0],data_reg2[7]} === 8'h5f )
|
||||
begin
|
||||
CON_P <= 1'b1;
|
||||
end
|
||||
|
||||
else if({data_reg3[5:0],data_reg2[7:6]} === 8'h5f )
|
||||
begin
|
||||
CON_P <= 1'b1;
|
||||
end
|
||||
|
||||
else if({data_reg3[4:0],data_reg2[7:5]} === 8'h5f )
|
||||
begin
|
||||
CON_P <= 1'b1;
|
||||
end
|
||||
|
||||
else if({data_reg3[3:0],data_reg2[7:4]} === 8'h5f )
|
||||
begin
|
||||
CON_P <= 1'b1;
|
||||
end
|
||||
|
||||
else if({data_reg3[2:0],data_reg2[7:3]} === 8'h5f )
|
||||
begin
|
||||
CON_P <= 1'b1;
|
||||
end
|
||||
|
||||
else if({data_reg3[1:0],data_reg2[7:2]} === 8'h5f)
|
||||
begin
|
||||
CON_P <= 1'b1;
|
||||
end
|
||||
|
||||
else if({data_reg3[0],data_reg2[7:1]} === 8'h5f) //lock_pattern
|
||||
begin
|
||||
CON_P <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
CON_P <= 1'b0;
|
||||
end
|
||||
if(data_reg3 === 8'haf )
|
||||
begin
|
||||
CON_N <= 1'b1;
|
||||
end
|
||||
|
||||
else if({data_reg3[6:0],data_reg2[7]} === 8'haf )
|
||||
begin
|
||||
CON_N <= 1'b1;
|
||||
end
|
||||
|
||||
else if({data_reg3[5:0],data_reg2[7:6]} === 8'haf )
|
||||
begin
|
||||
CON_N <= 1'b1;
|
||||
end
|
||||
|
||||
else if({data_reg3[4:0],data_reg2[7:5]} === 8'haf )
|
||||
begin
|
||||
CON_N <= 1'b1;
|
||||
end
|
||||
|
||||
else if({data_reg3[3:0],data_reg2[7:4]} === 8'haf )
|
||||
begin
|
||||
CON_N <= 1'b1;
|
||||
end
|
||||
|
||||
else if({data_reg3[2:0],data_reg2[7:3]} === 8'haf )
|
||||
begin
|
||||
CON_N <= 1'b1;
|
||||
end
|
||||
|
||||
else if({data_reg3[1:0],data_reg2[7:2]} === 8'haf )
|
||||
begin
|
||||
CON_N <= 1'b1;
|
||||
end
|
||||
|
||||
else if({data_reg3[0],data_reg2[7:1]} === 8'haf )//lock_pattern
|
||||
begin
|
||||
CON_N <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
CON_N <= 1'b0;
|
||||
end
|
||||
|
||||
end //if (!lock) // end search
|
||||
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,264 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 19:21:39 08/15/2011
|
||||
// Design Name:
|
||||
// Module Name: RCB_FRL_RXMSG_Byte_Alignment
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module RCB_FRL_RXMSG_Byte_Alignment(
|
||||
input clk,
|
||||
input enable, //Active low reset
|
||||
input [7:0] data_in,
|
||||
|
||||
output reg data_valid,
|
||||
output reg [7:0] data_out,
|
||||
output reg data_correct,
|
||||
output reg data_wrong,
|
||||
output reg [39:0] data_all
|
||||
);
|
||||
|
||||
// parameter lock_pattern = 8'hff ; //Specifies the lock pattern
|
||||
// parameter pack_size = 100; // Current packet size
|
||||
// parameter word_size = 8; // Not currently used in code
|
||||
|
||||
reg [7:0] data_reg1; //First register used to re-align the data
|
||||
reg [7:0] data_reg2; //Second register used to re-align the data
|
||||
reg [7:0] data_reg3; //Third register used to re-align the data
|
||||
reg [2:0] shift; //designate the bit shift value of the package
|
||||
reg lock; //if high, then the correct shift value has been found.
|
||||
reg [7:0] byte_count; //word count in packet
|
||||
reg [2:0] front_count;
|
||||
reg [7:0] data_out_tmp; //pipeline register
|
||||
|
||||
reg [7:0] frame_length;
|
||||
|
||||
// wire end_pack = pack_size; // signifies end of packet
|
||||
|
||||
wire [7:0] CRC_ans;
|
||||
RCB_FRL_CRC_gen RCB_FRL_CRC_gen_inst ( .D({{8'h06},data_all}), .NewCRC(CRC_ans));
|
||||
|
||||
always @(negedge clk) // timing broken to set data_valid flag
|
||||
begin
|
||||
if (!enable)
|
||||
begin
|
||||
data_out_tmp <= 8'h00; //test
|
||||
end
|
||||
else
|
||||
begin
|
||||
case(shift) //Re-aligns the data depending on shift value
|
||||
3'h0 : data_out_tmp <= data_reg3;
|
||||
3'h1 : data_out_tmp <= ({data_reg3[6:0],data_reg2[7]});
|
||||
3'h2 : data_out_tmp <= ({data_reg3[5:0],data_reg2[7:6]});
|
||||
3'h3 : data_out_tmp <= ({data_reg3[4:0],data_reg2[7:5]});
|
||||
3'h4 : data_out_tmp <= ({data_reg3[3:0],data_reg2[7:4]});
|
||||
3'h5 : data_out_tmp <= ({data_reg3[2:0],data_reg2[7:3]});
|
||||
3'h6 : data_out_tmp <= ({data_reg3[1:0],data_reg2[7:2]});
|
||||
3'h7 : data_out_tmp <= ({data_reg3[0],data_reg2[7:1]});
|
||||
default : data_out_tmp <= data_reg3;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// Word counter, counts words in packet
|
||||
always@(negedge clk)
|
||||
begin
|
||||
if(!enable || !lock) // Active low reset
|
||||
begin
|
||||
byte_count <= 0; //Initializes byte count
|
||||
front_count <= 0;
|
||||
end
|
||||
|
||||
if(lock)//lock data_valid
|
||||
begin
|
||||
byte_count <= byte_count + 1; //Increments the byte count to keep track of packet boundry
|
||||
front_count <= front_count+1;
|
||||
end
|
||||
end
|
||||
|
||||
// Data shift registers
|
||||
always @(negedge clk) //
|
||||
begin
|
||||
if(!enable)
|
||||
begin
|
||||
data_reg1 <= 8'h00; //Initializes the registers
|
||||
data_reg2 <= 8'h00;
|
||||
data_reg3 <= 8'h00;
|
||||
end
|
||||
else
|
||||
begin
|
||||
data_reg1 <= data_in; // Registers incoming data, shifts to compare registers
|
||||
data_reg2 <= data_reg1; // reg2 and reg3 are compare registers
|
||||
data_reg3 <= data_reg2;
|
||||
end
|
||||
end
|
||||
|
||||
// Search and validate
|
||||
|
||||
always @(negedge clk) //
|
||||
begin
|
||||
if(!enable)
|
||||
begin
|
||||
lock <= 0;
|
||||
shift <= 0;
|
||||
data_out <= 8'h00;
|
||||
data_valid <= 0;
|
||||
frame_length <= 0;
|
||||
end
|
||||
|
||||
else
|
||||
begin
|
||||
if(!lock) //If not locked, search for lock pattern
|
||||
begin //begin search
|
||||
|
||||
data_correct <= 1'b0;
|
||||
data_wrong <= 1'b0;
|
||||
|
||||
if(data_reg3 === 8'hf5 )
|
||||
begin
|
||||
lock <= 1;
|
||||
shift <= 3'h0;
|
||||
end
|
||||
|
||||
else if({data_reg3[6:0],data_reg2[7]} === 8'hf5 )
|
||||
begin
|
||||
lock <= 1;
|
||||
shift <= 3'h1;
|
||||
end
|
||||
|
||||
else if({data_reg3[5:0],data_reg2[7:6]} === 8'hf5 )
|
||||
begin
|
||||
lock <= 1;
|
||||
shift <= 3'h2;
|
||||
end
|
||||
|
||||
else if({data_reg3[4:0],data_reg2[7:5]} === 8'hf5 )
|
||||
begin
|
||||
lock <= 1;
|
||||
shift <= 3'h3;
|
||||
end
|
||||
|
||||
else if({data_reg3[3:0],data_reg2[7:4]} === 8'hf5 )
|
||||
begin
|
||||
lock <= 1;
|
||||
shift <= 3'h4;
|
||||
end
|
||||
|
||||
else if({data_reg3[2:0],data_reg2[7:3]} === 8'hf5 )
|
||||
begin
|
||||
lock <= 1;
|
||||
shift <= 3'h5;
|
||||
end
|
||||
|
||||
else if({data_reg3[1:0],data_reg2[7:2]} === 8'hf5)
|
||||
begin
|
||||
lock <= 1;
|
||||
shift <= 3'h6;
|
||||
end
|
||||
|
||||
else if({data_reg3[0],data_reg2[7:1]} === 8'hf5) //lock_pattern
|
||||
begin
|
||||
lock <= 1;
|
||||
shift <= 3'h7;
|
||||
end
|
||||
|
||||
end //if (!lock) // end search
|
||||
|
||||
else if (lock)
|
||||
begin //Confirms that data is valid
|
||||
if( byte_count == 8'h00) //the frame head
|
||||
begin
|
||||
data_valid <= 0;
|
||||
data_out <= 8'hff; //output the frame head
|
||||
end
|
||||
else if(byte_count == 8'h01) //the frame length
|
||||
begin
|
||||
data_valid <= 0;
|
||||
data_out <= data_out_tmp;
|
||||
frame_length <= data_out_tmp;
|
||||
end
|
||||
else if(byte_count < /*8'd7*/frame_length + 8'h1)
|
||||
begin
|
||||
data_valid <= 1;
|
||||
data_out <= data_out_tmp;
|
||||
if (byte_count == 8'h02)
|
||||
begin
|
||||
data_all[39:32] <= data_out_tmp;
|
||||
end
|
||||
else if (byte_count == 8'h03)
|
||||
begin
|
||||
data_all[31:24] <= data_out_tmp;
|
||||
end
|
||||
else if (byte_count == 8'h04)
|
||||
begin
|
||||
data_all[23:16] <= data_out_tmp;
|
||||
end
|
||||
else if (byte_count == 8'h05)
|
||||
begin
|
||||
data_all[15:8] <= data_out_tmp;
|
||||
end
|
||||
else if (byte_count == 8'h06)
|
||||
begin
|
||||
data_all[7:0] <= data_out_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
else if (byte_count >= frame_length + 8'h1)
|
||||
begin
|
||||
data_valid <= 0;
|
||||
lock <= 0;
|
||||
shift <= 0;
|
||||
frame_length <= 0;
|
||||
if ( CRC_ans == data_out_tmp)
|
||||
begin
|
||||
data_correct <=1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
data_wrong <=1'b1;
|
||||
end
|
||||
end
|
||||
end //end if(lock)
|
||||
|
||||
end //end else if(enable)
|
||||
end //end always
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 18:23:12 08/15/2011
|
||||
// Design Name:
|
||||
// Module Name: RCB_FRL_RX_Data_FIFO_8bit
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module RCB_FRL_RX_Data_FIFO_8bit(
|
||||
input RDCLK,
|
||||
input RDEN,
|
||||
input WRCLK,
|
||||
input WREN,
|
||||
input RST,
|
||||
input [7:0] DI,
|
||||
output ALMOSTEMPTY,
|
||||
output ALMOSTFULL,
|
||||
output EMPTY,
|
||||
output FULL,
|
||||
output [7:0] DO
|
||||
);
|
||||
|
||||
wire [7:0] temp1;
|
||||
|
||||
FIFO18 FIFO18_inst (
|
||||
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
|
||||
.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
|
||||
.DO({temp1, DO[7:0]}), // 16-bit data output
|
||||
.DOP(), // 2-bit parity data output
|
||||
.EMPTY(EMPTY), // 1-bit empty output flag
|
||||
.FULL(FULL), // 1-bit full output flag
|
||||
.RDCOUNT(), // 12-bit read count output
|
||||
.RDERR(), // 1-bit read error output
|
||||
.WRCOUNT(), // 12-bit write count output
|
||||
.WRERR(), // 1-bit write error
|
||||
.DI({8'h0,DI[7:0]}), // 16-bit data input
|
||||
.DIP(), // 2-bit parity input
|
||||
.RDCLK(RDCLK), // 1-bit read clock input
|
||||
.RDEN(RDEN), // 1-bit read enable input
|
||||
.RST(RST), // 1-bit reset input
|
||||
.WRCLK(WRCLK), // 1-bit write clock input
|
||||
.WREN(WREN) // 1-bit write enable input
|
||||
);
|
||||
defparam FIFO18_inst.DATA_WIDTH = 9;
|
||||
defparam FIFO18_inst.ALMOST_EMPTY_OFFSET = 6;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 16:45:29 02/23/2009
|
||||
// Design Name:
|
||||
// Module Name: RCB_FRL_RX_MSG
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module RCB_FRL_RX_MSG(
|
||||
input CLKDIV,
|
||||
input RST,
|
||||
input [7:0] DATA_IN,
|
||||
output reg [39:0] DATA_OUT,
|
||||
output reg ack_r_one,
|
||||
output reg nack_r_one,
|
||||
output reg msg_r_p_one,
|
||||
output reg msg_r_n_one
|
||||
);
|
||||
|
||||
// RCB_FRL_RXMSG_Byte_Alignment RCB_FRL_RXMSG_Byte_Alignment_and_MSG_Decoder_inst(
|
||||
// .data_in(DATA_IN),
|
||||
// .clk(CLKDIV),
|
||||
// .enable(~RST),
|
||||
// .DATA_rem(),
|
||||
// .data_valid(),
|
||||
// .data_correct(msg_r_p),
|
||||
// .data_wrong(msg_r_n),
|
||||
// .data_all(DATA_rem)
|
||||
// );
|
||||
//
|
||||
// RCB_FRL_RXMSG_ACK_Decoder RCB_FRL_RXMSG_ACK_Decoder_inst(
|
||||
// .data_in(DATA_IN),
|
||||
// .clk(CLKDIV),
|
||||
// .enable(~RST),
|
||||
// .ack_r_one(ack_r_one),
|
||||
// .nack_r_one(nack_r_one)
|
||||
// );
|
||||
|
||||
reg [7:0] data_reg;
|
||||
always@(posedge CLKDIV) data_reg[7:0] <= DATA_IN[7:0];
|
||||
|
||||
parameter MSG_HEADER = 8'hF5;
|
||||
parameter MSG_SIZE = 8'h06;
|
||||
parameter ACK_SYM = 8'h5F;
|
||||
parameter NACK_SYM = 8'hAF;
|
||||
parameter DUMMY_WAIT = 8'h44;
|
||||
|
||||
reg [39:0] DATA_rem;
|
||||
reg [7:0] CRC_rem;
|
||||
|
||||
reg [8:0] msg_parser_state;
|
||||
localparam IDLE = 9'b0_0000_0001;
|
||||
localparam SIZE = 9'b0_0000_0010;
|
||||
localparam ADDR = 9'b0_0000_0100;
|
||||
localparam DATA_1 = 9'b0_0000_1000;
|
||||
localparam DATA_2 = 9'b0_0001_0000;
|
||||
localparam DATA_3 = 9'b0_0010_0000;
|
||||
localparam DATA_4 = 9'b0_0100_0000;
|
||||
localparam CRC = 9'b0_1000_0000;
|
||||
localparam OUTPUT = 9'b1_0000_0000;
|
||||
|
||||
wire [7:0] crc_calc;
|
||||
// RCB_FRL_CRC_gen RCB_FRL_CRC_gen_inst(
|
||||
CRC8_gen RCB_FRL_CRC_gen_inst(
|
||||
.D({MSG_SIZE,DATA_rem[39:0]}),
|
||||
.NewCRC(crc_calc)
|
||||
);
|
||||
|
||||
always@(posedge CLKDIV) DATA_OUT[39:0] <= DATA_rem[39:0];
|
||||
|
||||
// ack_r_one; nack_r_one
|
||||
always@(posedge CLKDIV) begin
|
||||
if(RST) begin
|
||||
ack_r_one <= 1'b0;
|
||||
nack_r_one <= 1'b0;
|
||||
end else if (msg_parser_state==IDLE) begin
|
||||
if(data_reg[7:0] == ACK_SYM) begin
|
||||
ack_r_one <= 1'b1;
|
||||
nack_r_one <= 1'b0;
|
||||
end else if (data_reg[7:0] == NACK_SYM) begin
|
||||
ack_r_one <= 1'b0;
|
||||
nack_r_one <= 1'b1;
|
||||
end else begin
|
||||
ack_r_one <= 1'b0;
|
||||
nack_r_one <= 1'b0;
|
||||
end
|
||||
end else begin
|
||||
ack_r_one <= 1'b0;
|
||||
nack_r_one <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// msg_r_p_one; msg_r_n_one;
|
||||
always@(posedge CLKDIV) begin
|
||||
if(RST) begin
|
||||
msg_r_p_one <= 1'b0;
|
||||
msg_r_n_one <= 1'b0;
|
||||
end else if (msg_parser_state==OUTPUT) begin
|
||||
if(CRC_rem[7:0]==crc_calc[7:0]) begin
|
||||
msg_r_p_one <= 1'b1;
|
||||
msg_r_n_one <= 1'b0;
|
||||
end else begin
|
||||
msg_r_p_one <= 1'b0;
|
||||
msg_r_n_one <= 1'b1;
|
||||
end
|
||||
end else begin
|
||||
msg_r_p_one <= 1'b0;
|
||||
msg_r_n_one <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// main state machine for parsing incoming messages
|
||||
always@(posedge CLKDIV) begin
|
||||
if (RST) begin
|
||||
DATA_rem[39:0] <= 40'h0_0000;
|
||||
CRC_rem[7:0] <= 8'h00;
|
||||
msg_parser_state <= IDLE;
|
||||
end else begin
|
||||
case (msg_parser_state)
|
||||
IDLE: begin
|
||||
DATA_rem[39:0] <= DATA_rem[39:0];
|
||||
CRC_rem[7:0] <= CRC_rem[7:0];
|
||||
|
||||
if (data_reg[7:0] == MSG_HEADER)
|
||||
msg_parser_state <= SIZE; // packet detected
|
||||
else
|
||||
msg_parser_state <= IDLE;
|
||||
|
||||
end
|
||||
|
||||
SIZE: begin // data_reg[7:0] == 8'h06
|
||||
DATA_rem[39:0] <= DATA_rem[39:0];
|
||||
CRC_rem[7:0] <= CRC_rem[7:0];
|
||||
|
||||
if (data_reg[7:0] == MSG_SIZE)
|
||||
msg_parser_state <= ADDR;
|
||||
else if (data_reg[7:0] == MSG_HEADER)
|
||||
msg_parser_state <= SIZE;
|
||||
else
|
||||
msg_parser_state <= IDLE;
|
||||
|
||||
end
|
||||
|
||||
ADDR: begin
|
||||
DATA_rem[39:32] <= data_reg[7:0]; // [39:32], first byte is address
|
||||
DATA_rem[31:0] <= DATA_rem[31:0];
|
||||
CRC_rem[7:0] <= CRC_rem[7:0];
|
||||
msg_parser_state <= DATA_1;
|
||||
end
|
||||
|
||||
DATA_1: begin
|
||||
DATA_rem[39:32] <= DATA_rem[39:32];
|
||||
DATA_rem[31:24] <= data_reg[7:0]; // [31:24], most significant bit first
|
||||
DATA_rem[23:0] <= DATA_rem[23:0];
|
||||
CRC_rem[7:0] <= CRC_rem[7:0];
|
||||
msg_parser_state <= DATA_2;
|
||||
end
|
||||
|
||||
DATA_2: begin
|
||||
DATA_rem[39:24] <= DATA_rem[39:24];
|
||||
DATA_rem[23:16] <= data_reg[7:0]; // [23:16]
|
||||
DATA_rem[15:0] <= DATA_rem[15:0];
|
||||
CRC_rem[7:0] <= CRC_rem[7:0];
|
||||
msg_parser_state <= DATA_3;
|
||||
end
|
||||
|
||||
DATA_3: begin
|
||||
DATA_rem[39:16] <= DATA_rem[39:16];
|
||||
DATA_rem[15:8] <= data_reg[7:0]; // [15:8]
|
||||
DATA_rem[7:0] <= DATA_rem[7:0];
|
||||
CRC_rem[7:0] <= CRC_rem[7:0];
|
||||
msg_parser_state <= DATA_4;
|
||||
end
|
||||
|
||||
DATA_4: begin
|
||||
DATA_rem[39:8] <= DATA_rem[39:8];
|
||||
DATA_rem[7:0] <= data_reg[7:0]; // [7:0]
|
||||
CRC_rem[7:0] <= CRC_rem[7:0];
|
||||
msg_parser_state <= CRC;
|
||||
end
|
||||
|
||||
CRC: begin
|
||||
DATA_rem[39:0] <= DATA_rem[39:0];
|
||||
CRC_rem[7:0] <= data_reg[7:0];
|
||||
msg_parser_state <= OUTPUT;
|
||||
end
|
||||
|
||||
OUTPUT: begin // a redundant cycle for output, release timing requirement
|
||||
// transmitter should be aware of this additional cycle and no information
|
||||
// should be transmitted in this cycle
|
||||
DATA_rem[39:0] <= DATA_rem[39:0];
|
||||
CRC_rem[7:0] <= CRC_rem[7:0];
|
||||
msg_parser_state <= IDLE;
|
||||
end
|
||||
|
||||
default: begin
|
||||
DATA_rem[39:0] <= DATA_rem[39:0];
|
||||
CRC_rem[7:0] <= CRC_rem[7:0];
|
||||
msg_parser_state <= IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,137 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 15:57:22 08/15/2011
|
||||
// Design Name:
|
||||
// Module Name: RCB_FRL_RX_OneDataChannel
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
// packet header is 0xF508, packet size is 29 bytes on each channel, no error check
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module RCB_FRL_RX_OneDataChannel(
|
||||
input CLKDIV,
|
||||
input RST,
|
||||
input [7:0] DATA_IN,
|
||||
// output data_valid,
|
||||
// output [7:0] data_out
|
||||
output reg data_valid,
|
||||
output reg [7:0] data_out
|
||||
);
|
||||
|
||||
// reg [15:0] input_reg1;
|
||||
// wire [7:0] input_reg1_wire, input_reg1_wire_inv;
|
||||
//
|
||||
// assign input_reg1_wire = DATA_IN;
|
||||
|
||||
// RCB_FRL_BYTE_Alignment RCB_FRL_BYTE_Alignment_inst (
|
||||
//// .data_in(input_reg1_wire),
|
||||
// .data_in(DATA_IN),
|
||||
// .clk(CLKDIV),
|
||||
// .enable(~RST),
|
||||
// .data_out(data_out),
|
||||
// .data_valid(data_valid)
|
||||
// );
|
||||
|
||||
reg [1:0] frame_decap_state;
|
||||
localparam IDLE = 2'b00;
|
||||
localparam HEADER = 2'b01;
|
||||
localparam DATA_OUT = 2'b10;
|
||||
|
||||
reg [7:0] data_reg;
|
||||
reg [4:0] counter;
|
||||
always@(posedge CLKDIV) data_reg[7:0] <= DATA_IN[7:0];
|
||||
|
||||
always@(posedge CLKDIV) begin
|
||||
if (RST) begin
|
||||
counter[4:0] <= 5'h00;
|
||||
data_valid <= 1'b0;
|
||||
data_out[7:0] <= 8'h00;
|
||||
frame_decap_state <= IDLE;
|
||||
end else begin
|
||||
case (frame_decap_state)
|
||||
IDLE: begin
|
||||
counter[4:0] <= 5'h00;
|
||||
data_valid <= 1'b0;
|
||||
data_out[7:0] <= 8'h00;
|
||||
|
||||
if ( data_reg[7:0] == 8'hF5 ) // frame detected
|
||||
frame_decap_state <= HEADER;
|
||||
else
|
||||
frame_decap_state <= IDLE;
|
||||
end
|
||||
|
||||
HEADER: begin
|
||||
counter[4:0] <= 5'h00;
|
||||
data_valid <= 1'b0;
|
||||
data_out[7:0] <= 8'h00;
|
||||
|
||||
if ( data_reg[7:0] == 8'h1D ) // frame detected
|
||||
// if ( data_reg[7:0] == 8'h08 ) // frame detected
|
||||
|
||||
frame_decap_state <= DATA_OUT;
|
||||
else if ( data_reg[7:0] == 8'hF5 )
|
||||
frame_decap_state <= HEADER;
|
||||
else
|
||||
frame_decap_state <= IDLE;
|
||||
end
|
||||
|
||||
DATA_OUT: begin
|
||||
counter[4:0] <= counter[4:0] + 5'h01;
|
||||
data_valid <= 1'b1;
|
||||
data_out[7:0] <= data_reg[7:0];
|
||||
|
||||
if (counter >= 5'h1C)
|
||||
frame_decap_state <= IDLE;
|
||||
else
|
||||
frame_decap_state <= DATA_OUT;
|
||||
end
|
||||
|
||||
default: begin
|
||||
counter[4:0] <= 5'h00;
|
||||
data_valid <= 1'b0;
|
||||
data_out[7:0] <= 8'h00;
|
||||
frame_decap_state <= IDLE;
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,172 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 11:07:49 02/11/2009
|
||||
// Design Name:
|
||||
// Module Name: utils
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module RCB_FRL_TX (
|
||||
input CLK,
|
||||
input CLKDIV,
|
||||
input RST,
|
||||
input [31:0] DATA_IN,
|
||||
input SEND_EN,
|
||||
input TRAINING_DONE,
|
||||
output [3:0] OSER_OQ,
|
||||
output RDEN
|
||||
);
|
||||
|
||||
reg [31:0] frame_data;
|
||||
|
||||
reg [8:0] count;
|
||||
parameter NUM = 10'h008; // packet payload size on a single LVDS channel is 8-byte
|
||||
|
||||
reg RDEN_REG;
|
||||
assign RDEN = RDEN_REG;
|
||||
|
||||
wire [7:0] PATTERN;
|
||||
wire [31:0] data_to_oserdes;
|
||||
// assign data_to_oserdes = TRAINING_DONE ? frame_data : {PATTERN,PATTERN,PATTERN,PATTERN};
|
||||
assign data_to_oserdes = TRAINING_DONE ? frame_data : {8'h5c,8'h5c,8'h5c,8'h5c}; // training pattern for Spartan6
|
||||
|
||||
|
||||
// using counter to implement the state machine, state transition
|
||||
always @ (posedge CLKDIV) begin
|
||||
if (RST == 1'b1) begin
|
||||
count <= 9'h000;
|
||||
end else begin
|
||||
|
||||
if (count == 9'h000) begin
|
||||
if (SEND_EN == 1'b1)
|
||||
count <= 9'h001;
|
||||
else
|
||||
count <= 9'h000;
|
||||
|
||||
//end else if (count == (NUM+9'h004) ) begin // determine how many 00 will be inserted in two successive packets
|
||||
end else if (count == (NUM+9'h002) ) begin // no 00 will be inserted in two successive packets
|
||||
if (SEND_EN == 1'b1) begin
|
||||
count <= 9'h001;
|
||||
end else begin
|
||||
count <= 9'h000;
|
||||
end
|
||||
|
||||
end else begin
|
||||
count <= count + 9'h001;
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
// RDEN_REG
|
||||
always @ (posedge CLKDIV) begin
|
||||
if (RST == 1'b1) begin
|
||||
RDEN_REG <= 1'b0;
|
||||
end
|
||||
else if (count == 9'h001) begin
|
||||
RDEN_REG <= 1'b1;
|
||||
end
|
||||
else if (count == NUM+9'h001) begin
|
||||
RDEN_REG <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// training pattern generator
|
||||
RCB_FRL_TrainingPattern RCB_FRL_TrainingPattern_inst(
|
||||
.clk (CLKDIV),
|
||||
.rst (RST),
|
||||
.trainingpattern (PATTERN)
|
||||
);
|
||||
|
||||
// frame encapsulation
|
||||
always @ (posedge CLKDIV) begin
|
||||
if ( RST == 1'b1 ) begin
|
||||
frame_data[31:0] <= 32'h00000000;
|
||||
end else if (count == 9'h001) begin // frame header
|
||||
frame_data[31:0] <= 32'hF5F5F5F5;
|
||||
end else if (count == 9'h002) begin
|
||||
frame_data[31:0] <= {NUM[7:0],NUM[7:0],NUM[7:0],NUM[7:0]}; // frame size
|
||||
end else if (count == 9'h000) begin
|
||||
frame_data[31:0] <= 32'h44444444; // dummy
|
||||
end else if (count > NUM+9'h002) begin
|
||||
frame_data[31:0] <= 32'h00000000; // error, should never in this state
|
||||
end else begin
|
||||
frame_data[31:0] <= DATA_IN[31:0]; // frame payload
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// output serdes
|
||||
RCB_FRL_OSERDES RCB_FRL_OSERDES_inst1 (
|
||||
.OQ(OSER_OQ[0]),
|
||||
.CLK(CLK),
|
||||
.CLKDIV(CLKDIV),
|
||||
.DI(data_to_oserdes[7:0]),
|
||||
.OCE(1'b1),
|
||||
.SR(RST)
|
||||
);
|
||||
RCB_FRL_OSERDES RCB_FRL_OSERDES_inst2 (
|
||||
.OQ(OSER_OQ[1]),
|
||||
.CLK(CLK),
|
||||
.CLKDIV(CLKDIV),
|
||||
.DI(data_to_oserdes[15:8]),
|
||||
.OCE(1'b1),
|
||||
.SR(RST)
|
||||
);
|
||||
RCB_FRL_OSERDES RCB_FRL_OSERDES_inst3 (
|
||||
.OQ(OSER_OQ[2]),
|
||||
.CLK(CLK),
|
||||
.CLKDIV(CLKDIV),
|
||||
.DI(data_to_oserdes[23:16]),
|
||||
.OCE(1'b1),
|
||||
.SR(RST)
|
||||
);
|
||||
RCB_FRL_OSERDES RCB_FRL_OSERDES_inst4 (
|
||||
.OQ(OSER_OQ[3]),
|
||||
.CLK(CLK),
|
||||
.CLKDIV(CLKDIV),
|
||||
.DI(data_to_oserdes[31:24]),
|
||||
.OCE(1'b1),
|
||||
.SR(RST)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,432 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 13:46:27 02/23/2009
|
||||
// Design Name:
|
||||
// Module Name: MSG_utils
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module RCB_FRL_TX_MSG (
|
||||
input clk,
|
||||
input clkdiv,
|
||||
input rst,
|
||||
input [39:0] data_in,
|
||||
input empty,
|
||||
output reg rden,
|
||||
output OSER_OQ,
|
||||
input ack_r_one,
|
||||
input nack_r_one,
|
||||
output reg txmsg_miss_one, // one cycle signal to indicate a TXMSG wasn't correctly received by another Sora-FRL end
|
||||
output reg txmsg_pass_one, // one cycle signal to indicate a TXMSG was correctly received by another Sora-FRL end
|
||||
input msg_r_p_one,
|
||||
input msg_r_n_one,
|
||||
input training_done
|
||||
);
|
||||
|
||||
reg [7:0] frame_data;
|
||||
wire NotReady;
|
||||
|
||||
reg msg_r_p_signal;
|
||||
reg msg_r_n_signal;
|
||||
|
||||
// reg [8:0] count;
|
||||
|
||||
parameter MSG_HEADER = 8'hF5;
|
||||
parameter MSG_SIZE = 8'h06;
|
||||
parameter ACK_SYM = 8'h5F;
|
||||
parameter NACK_SYM = 8'hAF;
|
||||
parameter DUMMY_WAIT = 8'h44;
|
||||
|
||||
parameter TIME_OUT = 9'h150;
|
||||
|
||||
parameter RETRY_MAX = 3'b011; // retransmit 3 times
|
||||
|
||||
// reg RDEN_REG;
|
||||
// assign RDEN = RDEN_REG;
|
||||
|
||||
parameter IDLE = 10'b00_0000_0001;
|
||||
parameter HEADER = 10'b00_0000_0010;
|
||||
parameter SIZE = 10'b00_0000_0100;
|
||||
parameter ADDR = 10'b00_0000_1000;
|
||||
parameter DATA_1 = 10'b00_0001_0000;
|
||||
parameter DATA_2 = 10'b00_0010_0000;
|
||||
parameter DATA_3 = 10'b00_0100_0000;
|
||||
parameter DATA_4 = 10'b00_1000_0000;
|
||||
parameter CRC = 10'b01_0000_0000;
|
||||
parameter WAIT_FOR_ACK = 10'b10_0000_0000;
|
||||
reg [9:0] msg_framer_state;
|
||||
|
||||
reg [8:0] cnt;
|
||||
|
||||
// calculate CRC8
|
||||
wire [7:0] CRC8;
|
||||
// RCB_FRL_CRC_gen RCB_FRL_CRC_gen_inst (
|
||||
CRC8_gen RCB_FRL_CRC_gen_inst (
|
||||
.D({MSG_SIZE,data_in[39:0]}),
|
||||
.NewCRC(CRC8)
|
||||
);
|
||||
|
||||
// Do not send out control message in training stage
|
||||
assign NotReady = empty | (~training_done);
|
||||
|
||||
// reg [3:0] times; // for each control message, we will retransmit up to 3 times
|
||||
reg [3:0] retry_cnt;
|
||||
|
||||
always@(posedge clkdiv) begin
|
||||
if (rst) begin
|
||||
rden <= 1'b0;
|
||||
retry_cnt <= 3'b000;
|
||||
cnt <= 9'h000;
|
||||
frame_data[7:0] <= 8'h00;
|
||||
msg_framer_state <= IDLE;
|
||||
end else begin
|
||||
case(msg_framer_state)
|
||||
IDLE: begin
|
||||
cnt <= 9'h000;
|
||||
retry_cnt <= 3'b000;
|
||||
|
||||
if(msg_r_p_signal) begin
|
||||
rden <= 1'b0;
|
||||
frame_data[7:0] <= ACK_SYM;
|
||||
msg_framer_state <= IDLE;
|
||||
end else if (msg_r_n_signal) begin
|
||||
rden <= 1'b0;
|
||||
frame_data[7:0] <= NACK_SYM;
|
||||
msg_framer_state <= IDLE;
|
||||
end else if (!NotReady) begin
|
||||
rden <= 1'b1;
|
||||
frame_data[7:0] <= 8'h00;
|
||||
msg_framer_state <= HEADER;
|
||||
end else begin
|
||||
rden <= 1'b0;
|
||||
frame_data[7:0] <= 8'h00;
|
||||
msg_framer_state <= IDLE;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
HEADER: begin
|
||||
rden <= 1'b0;
|
||||
retry_cnt <= retry_cnt;
|
||||
cnt <= 9'h000;
|
||||
frame_data[7:0] <= MSG_HEADER;
|
||||
msg_framer_state <= SIZE;
|
||||
end
|
||||
|
||||
SIZE: begin
|
||||
rden <= 1'b0;
|
||||
retry_cnt <= retry_cnt;
|
||||
cnt <= 9'h000;
|
||||
frame_data[7:0] <= MSG_SIZE;
|
||||
msg_framer_state <= ADDR;
|
||||
end
|
||||
|
||||
ADDR: begin
|
||||
rden <= 1'b0;
|
||||
retry_cnt <= retry_cnt;
|
||||
cnt <= 9'h000;
|
||||
frame_data[7:0] <= data_in[39:32];
|
||||
msg_framer_state <= DATA_1;
|
||||
end
|
||||
|
||||
DATA_1: begin
|
||||
rden <= 1'b0;
|
||||
retry_cnt <= retry_cnt;
|
||||
cnt <= 9'h000;
|
||||
frame_data[7:0] <= data_in[31:24];
|
||||
msg_framer_state <= DATA_2;
|
||||
end
|
||||
|
||||
DATA_2: begin
|
||||
rden <= 1'b0;
|
||||
retry_cnt <= retry_cnt;
|
||||
cnt <= 9'h000;
|
||||
frame_data[7:0] <= data_in[23:16];
|
||||
msg_framer_state <= DATA_3;
|
||||
end
|
||||
|
||||
DATA_3: begin
|
||||
rden <= 1'b0;
|
||||
retry_cnt <= retry_cnt;
|
||||
cnt <= 9'h000;
|
||||
frame_data[7:0] <= data_in[15:8];
|
||||
msg_framer_state <= DATA_4;
|
||||
end
|
||||
|
||||
DATA_4: begin
|
||||
rden <= 1'b0;
|
||||
retry_cnt <= retry_cnt;
|
||||
cnt <= 9'h000;
|
||||
frame_data[7:0] <= data_in[7:0];
|
||||
msg_framer_state <= CRC;
|
||||
end
|
||||
|
||||
CRC: begin
|
||||
rden <= 1'b0;
|
||||
retry_cnt <= retry_cnt;
|
||||
cnt <= 9'h000;
|
||||
frame_data[7:0] <= CRC8;
|
||||
msg_framer_state <= WAIT_FOR_ACK;
|
||||
end
|
||||
|
||||
WAIT_FOR_ACK: begin
|
||||
rden <= 1'b0;
|
||||
cnt <= cnt + 9'h001;
|
||||
|
||||
if (cnt > 9'h001) begin // leave two cycle space between a message and an ACK/NACK,
|
||||
// it will be easier for decoder to handle
|
||||
if (msg_r_p_signal)
|
||||
frame_data[7:0] <= ACK_SYM;
|
||||
else if (msg_r_n_signal)
|
||||
frame_data[7:0] <= NACK_SYM;
|
||||
else
|
||||
frame_data[7:0] <= DUMMY_WAIT;
|
||||
end else
|
||||
frame_data[7:0] <= DUMMY_WAIT;
|
||||
|
||||
if (ack_r_one) begin
|
||||
retry_cnt <= 3'b000;
|
||||
msg_framer_state <= IDLE;
|
||||
end else if ( nack_r_one | (cnt > TIME_OUT) ) begin
|
||||
if (retry_cnt >= RETRY_MAX) begin
|
||||
retry_cnt <= 3'b000;
|
||||
msg_framer_state <= IDLE;
|
||||
end else begin
|
||||
retry_cnt <= retry_cnt + 3'b001;
|
||||
msg_framer_state <= HEADER;
|
||||
end
|
||||
end else begin
|
||||
retry_cnt <= retry_cnt;
|
||||
msg_framer_state <= WAIT_FOR_ACK;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
default: begin
|
||||
rden <= 1'b0;
|
||||
retry_cnt <= 3'b000;
|
||||
cnt <= 9'h000;
|
||||
frame_data[7:0] <= 8'h00;
|
||||
msg_framer_state <= IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
// msg_r_p_signal
|
||||
always@(posedge clkdiv) begin
|
||||
if (rst)
|
||||
msg_r_p_signal <= 1'b0;
|
||||
else if (msg_r_p_one)
|
||||
msg_r_p_signal <= 1'b1;
|
||||
else if ( (msg_framer_state == IDLE) | ((msg_framer_state == WAIT_FOR_ACK)&(cnt > 9'h001)) )
|
||||
msg_r_p_signal <= 1'b0;
|
||||
else
|
||||
msg_r_p_signal <= msg_r_p_signal;
|
||||
end
|
||||
|
||||
// msg_r_n_signal
|
||||
always@(posedge clkdiv) begin
|
||||
if (rst)
|
||||
msg_r_n_signal <= 1'b0;
|
||||
else if (msg_r_n_one)
|
||||
msg_r_n_signal <= 1'b1;
|
||||
else if ( (msg_framer_state == IDLE) | ((msg_framer_state == WAIT_FOR_ACK)&(cnt > 9'h001)) )
|
||||
msg_r_n_signal <= 1'b0;
|
||||
else
|
||||
msg_r_n_signal <= msg_r_n_signal;
|
||||
end
|
||||
|
||||
// txmsg_miss_one
|
||||
always@(posedge clkdiv) begin
|
||||
if(rst)
|
||||
txmsg_miss_one <= 1'b0;
|
||||
else if ( (retry_cnt >= RETRY_MAX) & (cnt > TIME_OUT | nack_r_one) )
|
||||
txmsg_miss_one <= 1'b1;
|
||||
else
|
||||
txmsg_miss_one <= 1'b0;
|
||||
end
|
||||
|
||||
// txmsg_pass_one
|
||||
always@(posedge clkdiv) begin
|
||||
if(rst)
|
||||
txmsg_pass_one <= 1'b0;
|
||||
else if ( (msg_framer_state == WAIT_FOR_ACK) & (ack_r_one) )
|
||||
txmsg_pass_one <= 1'b1;
|
||||
else
|
||||
txmsg_pass_one <= 1'b0;
|
||||
end
|
||||
|
||||
// // main msg_framer_state machine
|
||||
// always@(posedge clkdiv) begin
|
||||
// if (rst) begin
|
||||
// count <= 9'h000;
|
||||
// RDEN_REG <= 1'b0;
|
||||
// TXMSG_MISS <= 1'b0;
|
||||
// TXMSG_PASS <= 1'b0;
|
||||
// times <= 4'h0;
|
||||
// end
|
||||
// else begin
|
||||
// if (count == 9'h1FF | count == 9'h1FE) begin
|
||||
// count <= 9'h000;
|
||||
// end else if (count == 9'h000) begin
|
||||
// if (msg_r_p) begin // Jiansong: ACK or NACK first
|
||||
// count <= 9'h1FF;
|
||||
// end else if (msg_r_n) begin
|
||||
// count <= 9'h1FE;
|
||||
// end else begin
|
||||
// if ( NotReady && (times == 4'h0) ) begin
|
||||
// count <= 9'h000;
|
||||
// end else begin // (!NotReady | times == 4'h1 | times ==4'h2)
|
||||
// count <= 9'h001;
|
||||
// end
|
||||
// end
|
||||
// RDEN_REG <= 1'b0;
|
||||
// TXMSG_MISS <= 1'b0;
|
||||
// TXMSG_PASS <= 1'b0;
|
||||
// times <= times;
|
||||
// end else if (count == 9'h001) begin
|
||||
// count <= 9'h002;
|
||||
//
|
||||
// if (times == 4'h0)
|
||||
// RDEN_REG <= 1'b1;
|
||||
// else
|
||||
// RDEN_REG <= 1'b0;
|
||||
//
|
||||
// times <= times + 4'h1;
|
||||
//
|
||||
// TXMSG_MISS <= 1'b0;
|
||||
// TXMSG_PASS <= 1'b0;
|
||||
// end else if (count == 9'h002) begin
|
||||
// count <= 9'h003;
|
||||
// RDEN_REG <= 1'b0;
|
||||
// TXMSG_MISS <= 1'b0;
|
||||
// TXMSG_PASS <= 1'b0;
|
||||
// times <= times;
|
||||
// end else if (count < 9'h009) begin // ignore ACK/NACK in message transmission period
|
||||
// count <= count + 9'h001;
|
||||
// RDEN_REG <= 1'b0;
|
||||
// TXMSG_MISS <= 1'b0;
|
||||
// TXMSG_PASS <= 1'b0;
|
||||
// times <= times;
|
||||
// end else begin
|
||||
// if(ACK | NACK | count == 9'h150)
|
||||
// count <= 9'h000;
|
||||
// else
|
||||
// count <= count + 9'h001;
|
||||
//
|
||||
// RDEN_REG <= 1'b0;
|
||||
//
|
||||
// if(ACK) begin
|
||||
// times <= 4'h0;
|
||||
// TXMSG_PASS <= 1'b1;
|
||||
// TXMSG_MISS <= 1'b0;
|
||||
// end else if (NACK | count == 9'h150) begin
|
||||
// if (times == 4'h3) begin
|
||||
// times <= 4'h0;
|
||||
// TXMSG_MISS <= 1'b1;
|
||||
// end else begin
|
||||
// times <= times;
|
||||
// TXMSG_MISS <= 1'b0;
|
||||
// end
|
||||
// TXMSG_PASS <= 1'b0;
|
||||
// end else begin
|
||||
// times <= times;
|
||||
// TXMSG_PASS <= 1'b0;
|
||||
// TXMSG_MISS <= 1'b0;
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
//
|
||||
// // frame encapsulation
|
||||
// always@(posedge clkdiv) begin
|
||||
// if (rst)
|
||||
// frame_data[7:0] <= 8'h00;
|
||||
// else if (count == 9'h001)
|
||||
// frame_data[7:0] <= 8'hF5;
|
||||
// else if (count == 9'h002)
|
||||
// frame_data[7:0] <= MSG_SIZE;
|
||||
// else if (count == 9'h000)
|
||||
// frame_data[7:0] <= 8'h44; // send 8'h44 on idle msg_framer_state
|
||||
// else if (count == 9'h003)
|
||||
// frame_data[7:0] <= data_in[39:32];
|
||||
// else if (count == 9'h004)
|
||||
// frame_data[7:0] <= data_in[31:24];
|
||||
// else if (count == 9'h005)
|
||||
// frame_data[7:0] <= data_in[23:16];
|
||||
// else if (count == 9'h006)
|
||||
// frame_data[7:0] <= data_in[15:8];
|
||||
// else if (count == 9'h007)
|
||||
// frame_data[7:0] <= data_in[7:0];
|
||||
// else if (count == 9'h008)
|
||||
// frame_data[7:0] <= CRC[7:0];
|
||||
// else if (count == 9'h1FF)
|
||||
// frame_data[7:0] <= 8'h5f;
|
||||
// else if (count == 9'h1FE)
|
||||
// frame_data[7:0] <= 8'haf;
|
||||
// else
|
||||
// frame_data[7:0] <= 8'h00;
|
||||
// end
|
||||
|
||||
// wire [7:0] PATTERN;
|
||||
// RCB_FRL_TrainingPattern RCB_FRL_TrainingPattern_inst(
|
||||
// .clk(clkdiv),
|
||||
// .rst(rst),
|
||||
// .trainingpattern(PATTERN)
|
||||
// );
|
||||
|
||||
wire [7:0] data_to_oserdes;
|
||||
// assign data_to_oserdes = training_done ? frame_data : PATTERN;
|
||||
assign data_to_oserdes = training_done ? frame_data : 8'h5c; // training pattern for spartan6
|
||||
|
||||
RCB_FRL_OSERDES_MSG RCB_FRL_OSERDES_MSG_inst (
|
||||
.OQ(OSER_OQ),
|
||||
.clk(clk),
|
||||
.clkdiv(clkdiv),
|
||||
.DI(data_to_oserdes),
|
||||
.OCE(1'b1),
|
||||
.SR(rst)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
// generate training pattern
|
||||
// pattern is f4c2, it occupies two clock cycles
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module RCB_FRL_TrainingPattern(
|
||||
input clk,
|
||||
input rst,
|
||||
output reg [7:0] trainingpattern
|
||||
);
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if(rst) begin
|
||||
trainingpattern <= 8'h00;
|
||||
end else begin
|
||||
if(trainingpattern == 8'hf4)
|
||||
trainingpattern <= 8'hc2;
|
||||
else
|
||||
trainingpattern <= 8'hf4;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module RCB_FRL_count_to_128(
|
||||
input clk,
|
||||
input rst,
|
||||
input count,
|
||||
input ud,
|
||||
output reg [6:0] counter_value
|
||||
);
|
||||
|
||||
//This module counts up/down between 0 to 128
|
||||
|
||||
//input clk, rst, count, ud;
|
||||
//output [6:0] counter_value;
|
||||
|
||||
wire [6:0] counter_value_preserver;
|
||||
//reg [6:0] counter_value/*synthesis syn_noprune = 1*/;
|
||||
|
||||
always@(posedge clk or posedge rst) begin
|
||||
if(rst == 1'b1)
|
||||
counter_value = 7'h00;
|
||||
else begin
|
||||
case({count,ud})
|
||||
2'b00: counter_value = 7'h00;
|
||||
2'b01: counter_value = counter_value_preserver;
|
||||
2'b10: counter_value = counter_value_preserver - 1;
|
||||
2'b11: counter_value = counter_value_preserver + 1;
|
||||
default: counter_value = 7'h00;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
assign counter_value_preserver = counter_value;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module RCB_FRL_count_to_16x(
|
||||
input clk,
|
||||
input rst,
|
||||
input count,
|
||||
output [3:0] counter_value
|
||||
);
|
||||
|
||||
//This module counts from 0 to 16
|
||||
|
||||
//input clk, rst, count;
|
||||
//output [3:0] counter_value;
|
||||
|
||||
reg [3:0] counter_value_preserver;
|
||||
|
||||
//assign counter_value = (count) ? counter_value_preserver + 1 : counter_value_preserver;
|
||||
assign counter_value = counter_value_preserver;
|
||||
|
||||
always@(posedge clk or posedge rst) begin
|
||||
if(rst == 1'b1) begin
|
||||
counter_value_preserver = 4'h0;
|
||||
end else if ( count == 1'b1 ) begin
|
||||
counter_value_preserver = counter_value_preserver + 1;
|
||||
end else begin
|
||||
counter_value_preserver = counter_value;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,396 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:54:12 04/26/2010
|
||||
// Design Name: Sora_FRL_RCB
|
||||
// Module Name: Sora_FRL_RCB
|
||||
// Project Name:
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description: top of Sora FRL module, this is an implementation of Sora fast radio link. Sora FRL is bi-directional that there're
|
||||
// both transmitter and reciver in this module.
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//More explanantion of IOs is available below
|
||||
|
||||
module Sora_FRL_RCB(
|
||||
//////// Sora FRL interface to FPGA pins ////////
|
||||
// inputs
|
||||
input CLK_I_p, //CLK2_p,
|
||||
input CLK_I_n, //CLK2_n,
|
||||
input [3:0] DATA_IN_p,
|
||||
input [3:0] DATA_IN_n,
|
||||
input MSG_IN_p,
|
||||
input MSG_IN_n,
|
||||
input STATUS_IN_p,
|
||||
input STATUS_IN_n,
|
||||
// outputs
|
||||
output CLK_O_p, //CLK1_p,
|
||||
output CLK_O_n, //CLK1_n,
|
||||
output [3:0] DATA_OUT_p,
|
||||
output [3:0] DATA_OUT_n,
|
||||
output MSG_OUT_p,
|
||||
output MSG_OUT_n,
|
||||
output STATUS_OUT_p,
|
||||
output STATUS_OUT_n,
|
||||
|
||||
//////// signals to FPGA internal logic ////////
|
||||
// reset from FPGA fabric
|
||||
input rst_in_internal,
|
||||
output rst_out_internal,
|
||||
output CLKDIV_R,
|
||||
// data input from internal logic
|
||||
input SEND_EN,
|
||||
input [31:0] DATA_INT_IN,
|
||||
output RDEN_DATA_INT_IN,
|
||||
// control message input from internal logic
|
||||
input [39:0] MSG_INT_IN,
|
||||
input EMPTY_MSG_INT_IN,
|
||||
output RDEN_MSG_INT_IN,
|
||||
// data output to internal logic
|
||||
output [31:0] DATA_INT_OUT,
|
||||
output reg WREN_DATA_INT_OUT,
|
||||
// state message output to internal logic
|
||||
// modified by Jiansong, 2010-5-27, we do not use FIFO to buf MSG_INT_OUT
|
||||
output [31:0] MSG_INT_OUT_Data,
|
||||
output [7:0] MSG_INT_OUT_Addr,
|
||||
output MSG_Valid,
|
||||
// debug info
|
||||
output reg [31:0] TXMSG_MISS_cnt,
|
||||
output reg [31:0] TXMSG_PASS_cnt,
|
||||
output Radio_status_error, // indicates error in received status signal from radio moudle
|
||||
output Sora_FRL_linkup,
|
||||
output [1:0] LED
|
||||
);
|
||||
|
||||
wire CLK_R;
|
||||
|
||||
wire ALMOSTEMPTY, ALMOSTFULL;
|
||||
|
||||
wire [31:0] DATA;
|
||||
wire WREN;
|
||||
wire [3:0] OSER_OQ;
|
||||
wire [31:0] DATA_IN;
|
||||
wire [7:0] MSG_IN;
|
||||
wire Lock_Status_TX;
|
||||
wire Lock_Status_RX;
|
||||
|
||||
wire LED_CLOCK_0;
|
||||
wire LED_CLOCK_1;
|
||||
wire LED_CLOCK_2;
|
||||
wire LED_CLOCK_3;
|
||||
|
||||
wire CLK180;
|
||||
|
||||
wire [39:0] MSG;
|
||||
wire OSER_OQ_MSG,ack_r_one,nack_r_one,BACK_WRONG, BACK_RIGHT;
|
||||
|
||||
wire STATUS_IN;
|
||||
wire STATUS_OUT;
|
||||
wire SEND_EN_TX;
|
||||
|
||||
wire DATA_SEND_EN, MSG_WREN;
|
||||
|
||||
// Status signal from adapter
|
||||
wire rst_in_status;
|
||||
wire FIFO_FULL_RX;
|
||||
wire TRAINING_DONE_RCB2Adapter;
|
||||
wire IDLE_RX;
|
||||
wire Status_RX_error;
|
||||
|
||||
wire STATUS_OUT_MSG_buf;
|
||||
wire msg_r_p_one;
|
||||
wire DATA_ALMOSTEMPTY;
|
||||
|
||||
// Status signal to adapter
|
||||
wire TRAINING_DONE_Adapter2RCB;
|
||||
|
||||
/////////////////// reset logic /////////////////
|
||||
|
||||
wire RST;
|
||||
// FRL local logic reset
|
||||
reg [31:0] rst_counter;
|
||||
reg reset_frl_local;
|
||||
initial
|
||||
rst_counter = 32'h0000_0000;
|
||||
always @ (posedge CLKDIV_R) begin
|
||||
// a local reset signal is triggered
|
||||
if (rst_in_internal | rst_in_status) begin
|
||||
rst_counter <= 32'h0000_0000;
|
||||
reset_frl_local <= 1'b1;
|
||||
end else if(rst_counter < 32'h0000_1130) begin // 100us
|
||||
rst_counter <= rst_counter + 32'h0000_0001;
|
||||
reset_frl_local <= 1'b1;
|
||||
end else
|
||||
reset_frl_local <= 1'b0;
|
||||
end
|
||||
|
||||
// propagate reset signal from status line to RCB internal logic
|
||||
assign rst_out_internal = rst_in_status;
|
||||
|
||||
assign RST = rst_in_internal | rst_in_status | reset_frl_local;
|
||||
|
||||
//////////////////////////////////////////////////
|
||||
|
||||
assign Sora_FRL_linkup = TRAINING_DONE_Adapter2RCB & TRAINING_DONE_RCB2Adapter;
|
||||
|
||||
assign DATA_SEND_EN = ~FIFO_FULL_RX & SEND_EN & TRAINING_DONE_RCB2Adapter; // modified by Jiansong, 2010-5-25, add training done as condition
|
||||
always@(posedge CLKDIV_R) WREN_DATA_INT_OUT <= ~DATA_ALMOSTEMPTY;
|
||||
|
||||
|
||||
// Determine whether TX will send DATA or MSG.
|
||||
assign LED[0] = LED_CLOCK_0;
|
||||
assign LED[1] = LED_CLOCK_1;
|
||||
|
||||
|
||||
Sora_FRL_STATUS_decoder Sora_FRL_STATUS_decoder_RCB_inst(
|
||||
.clk (CLKDIV_R),
|
||||
// .rst (rst_in_internal), // no need for a reset signal since there's no internal state
|
||||
|
||||
// input from STATUS line
|
||||
.status_in (STATUS_IN),
|
||||
|
||||
// four output states
|
||||
.RST_state (rst_in_status),
|
||||
.TRAININGDONE_state (TRAINING_DONE_RCB2Adapter),
|
||||
.IDLE_state (IDLE_RX), // this signal is used for monitoring
|
||||
.FIFOFULL_state (FIFO_FULL_RX),
|
||||
// error state
|
||||
.error_state (Status_RX_error)
|
||||
);
|
||||
|
||||
Sora_FRL_STATUS_encoder Sora_FRL_STATUS_encoder_RCB_inst(
|
||||
.clk (CLKDIV_R),
|
||||
// .rst (rst_in_internal), // reset the Status encoder's state machine
|
||||
|
||||
// input from STATUS line
|
||||
.status_out (STATUS_OUT),
|
||||
|
||||
// four output states
|
||||
// .RST_signal (rst_in_internal | reset_frl_local), // this signal is generated from internal fabric
|
||||
.RST_signal (rst_in_internal), // this signal is generated from internal fabric
|
||||
.TRAININGDONE_signal (TRAINING_DONE_Adapter2RCB),
|
||||
.IDLE_signal (rst_in_status), // this signal informs Status encoder to change its state to IDLE,
|
||||
// it happens when an RST state is received from Status line
|
||||
.FIFOFULL_signal (1'b0) // FIFO should not be full on RX path
|
||||
);
|
||||
|
||||
|
||||
RCB_FRL_TX Sora_FRL_RCB_TX_data_inst (
|
||||
.RST (RST),
|
||||
.CLK (CLK_R),
|
||||
.CLKDIV (CLKDIV_R),
|
||||
|
||||
.DATA_IN (DATA_INT_IN),
|
||||
.OSER_OQ (OSER_OQ),
|
||||
.SEND_EN (DATA_SEND_EN),
|
||||
.TRAINING_DONE (TRAINING_DONE_RCB2Adapter),
|
||||
.RDEN (RDEN_DATA_INT_IN)
|
||||
);
|
||||
|
||||
// debug info
|
||||
wire TXMSG_MISS;
|
||||
wire TXMSG_PASS;
|
||||
always@(posedge CLKDIV_R)begin
|
||||
if(RST)begin
|
||||
TXMSG_MISS_cnt <= 32'h0000_0000;
|
||||
TXMSG_PASS_cnt <= 32'h0000_0000;
|
||||
end else if(TXMSG_MISS) begin
|
||||
TXMSG_MISS_cnt <= TXMSG_MISS_cnt + 32'h0000_0001;
|
||||
TXMSG_PASS_cnt <= TXMSG_PASS_cnt;
|
||||
end else if(TXMSG_PASS) begin
|
||||
TXMSG_MISS_cnt <= TXMSG_MISS_cnt;
|
||||
TXMSG_PASS_cnt <= TXMSG_PASS_cnt + 32'h0000_0001;
|
||||
end else begin
|
||||
TXMSG_MISS_cnt <= TXMSG_MISS_cnt;
|
||||
TXMSG_PASS_cnt <= TXMSG_PASS_cnt;
|
||||
end
|
||||
end
|
||||
|
||||
RCB_FRL_TX_MSG Sora_FRL_RCB_TX_MSG_inst (
|
||||
.rst (RST),
|
||||
.clk (CLK_R),
|
||||
.clkdiv (CLKDIV_R),
|
||||
|
||||
.data_in (MSG_INT_IN[39:0]),
|
||||
.empty (EMPTY_MSG_INT_IN),
|
||||
.rden (RDEN_MSG_INT_IN),
|
||||
.OSER_OQ (OSER_OQ_MSG),
|
||||
.ack_r_one (ack_r_one), //input feedback from decode module
|
||||
.nack_r_one (nack_r_one),
|
||||
.txmsg_miss_one(TXMSG_MISS), // one cycle signal to indicate a TXMSG wasn't correctly received by another Sora-FRL end
|
||||
.txmsg_pass_one(TXMSG_PASS), // one cycle signal to indicate a TXMSG was correctly received by another Sora-FRL end
|
||||
.msg_r_p_one (msg_r_p_one),
|
||||
.msg_r_n_one (msg_r_n_one),
|
||||
.training_done (TRAINING_DONE_RCB2Adapter)
|
||||
);
|
||||
|
||||
|
||||
// serial clock output to the 'clock' LVDS channel
|
||||
// wire TX_CLOCK_PREBUF;
|
||||
// ODDR #( .DDR_CLK_EDGE("OPPOSITE_EDGE"), .INIT(1'b0), .SRTYPE("ASYNC") )
|
||||
// ODDR_TX_CLOCK ( .Q(TX_CLOCK_PREBUF), .C(CLK_R), .CE(1'b1), .D1(1'b1), .D2(1'b0), .R(1'b0), .S(1'b0) );
|
||||
OBUFDS OBUFDS_clock ( .I(CLK_R), .O(CLK_O_p), .OB(CLK_O_n) );
|
||||
|
||||
// differential outputs to LVDS channels
|
||||
OBUFDS OBUFDS_data0 ( .I(OSER_OQ[0]), .O(DATA_OUT_p[0]), .OB(DATA_OUT_n[0]) );
|
||||
OBUFDS OBUFDS_data1 ( .I(OSER_OQ[1]), .O(DATA_OUT_p[1]), .OB(DATA_OUT_n[1]) );
|
||||
OBUFDS OBUFDS_data2 ( .I(OSER_OQ[2]), .O(DATA_OUT_p[2]), .OB(DATA_OUT_n[2]) );
|
||||
OBUFDS OBUFDS_data3 ( .I(OSER_OQ[3]), .O(DATA_OUT_p[3]), .OB(DATA_OUT_n[3]) );
|
||||
OBUFDS OBUFDS_msg ( .I(OSER_OQ_MSG), .O(MSG_OUT_p), .OB(MSG_OUT_n) );
|
||||
OBUFDS OBUFDS_status ( .I(STATUS_OUT), .O(STATUS_OUT_p), .OB(STATUS_OUT_n) );
|
||||
|
||||
// differential input from the 'status' LVDS channel
|
||||
IBUFDS #( .DIFF_TERM("FALSE") ) IBUFDS_inst7 ( .I(STATUS_IN_p), .IB(STATUS_IN_n), .O(STATUS_IN) );
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////// clock ///////////////////////////////////////////
|
||||
// this is a candidate solution, but not used finally because DCM is not stable in this solution:
|
||||
// the clock source of Sora FRL comes from RAB, that is,
|
||||
// (1) RAB generates LVDS clock from its local oscillator,
|
||||
// (2) a serial-rate clock is transmitted together with data channels
|
||||
// (3) RCB receives the serial-rate clock, using a DCM to generate both serial-rate clock and parallel-rate clock
|
||||
// the two clocks should be phase synchronized in this way
|
||||
// (4) both serial-clock and parallel clock are propagated to Iserdes and Oserdes using BUFG
|
||||
// note: it is not the optimal clock solution since global clock net introduce larger skew than reginal clock net,
|
||||
// but with current PCB layout, reginal clock solution is not able to be applied since some LVDS channels
|
||||
// on a same LVDS port are routed to different IO banks (different clcok regions), which should be routed to
|
||||
// the same IO bank if we use regional clock net (BUFIO can only reach to a single clock region, BUFR can reach
|
||||
// to its own and two neighbor clock regions)
|
||||
|
||||
// differential input from the 'clock' LVDS channel
|
||||
// wire CLOCK_RX_BUF;
|
||||
// wire CLOCK_RX_ISERDES_OUT;
|
||||
// IBUFDS #( .DIFF_TERM("FALSE") ) IBUFDS_inst8 ( .I(CLK_I_p), .IB(CLK_I_n), .O(CLOCK_RX_BUF) );
|
||||
|
||||
// //IDELAY IN CLOCK PATH
|
||||
// IODELAY #( .IDELAY_TYPE("FIXED"), .IDELAY_VALUE(0), .ODELAY_VALUE(0), .REFCLK_FREQUENCY(200.00), .HIGH_PERFORMANCE_MODE("TRUE") )
|
||||
// IODELAY_CLOCK_RX ( .DATAOUT(CLOCK_RX_ISERDES_OUT), .IDATAIN(CLOCK_RX_BUF), .ODATAIN(1'b0), .DATAIN(1'b0), .T(),
|
||||
// .CE(1'b0), .INC(1'b0), .C(1'b0), .RST(RST) );
|
||||
|
||||
// BUFG BUFG_input ( .I(CLOCK_RX_ISERDES_OUT), .O(clock_input_global) );
|
||||
// BUFG BUFG_input ( .I(CLOCK_RX_BUF), .O(clock_input_global) );
|
||||
//
|
||||
// DCM_FRL DCM_FRL_inst (
|
||||
// .CLKIN_IN (clock_input_global),
|
||||
// .RST_IN (rst_in_internal),
|
||||
// .CLKDV_OUT (CLKDIV_R),
|
||||
// .CLK0_OUT (CLK_R),
|
||||
// .LOCKED_OUT ()
|
||||
// );
|
||||
|
||||
|
||||
// clock solution, it seems serial-clock and parallel clock are not synchronized in phase, the highest frequency will be limited therefore
|
||||
wire CLK_R1, CLK_R_pre;
|
||||
// IBUFDS #( .DIFF_TERM("FALSE") ) IBUFDS_inst8 ( .I(CLK_I_p), .IB(CLK_I_n), .O(CLK_R) );
|
||||
IBUFDS #( .DIFF_TERM("FALSE") ) IBUFDS_inst8 ( .I(CLK_I_p), .IB(CLK_I_n), .O(CLK_R_pre) );
|
||||
|
||||
// BUFR #( .BUFR_DIVIDE("1"), .SIM_DEVICE("VIRTEX5") )
|
||||
// BUFIO_CLK_R ( .O(CLK_R1), .CE(1'b1), .CLR(1'b0), .I(CLK_R_pre) );
|
||||
// BUFG BUFG_CLK_R (.I(CLK_R1), .O(CLK_R));
|
||||
BUFG BUFG_CLK_R (.I(CLK_R_pre), .O(CLK_R));
|
||||
|
||||
wire CLKDIV_R1;
|
||||
BUFR #( .BUFR_DIVIDE("4"), .SIM_DEVICE("VIRTEX5") )
|
||||
// BUFR_inst1( .O(CLKDIV_R1), .CE(1'b1), .CLR(1'b0), .I(CLK_R) );
|
||||
BUFR_inst1( .O(CLKDIV_R1), .CE(1'b1), .CLR(1'b0), .I(CLK_R_pre) );
|
||||
BUFG BUFG_CLKDIV_R (.I(CLKDIV_R1), .O(CLKDIV_R));
|
||||
|
||||
//////////////////////////////// clock ///////////////////////////////////////////
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
RCB_FRL_DDR_8TO1_16CHAN_RX Sora_FRL_RCB_RX_ISerDes_and_Training_inst (
|
||||
.RXCLK (CLK_R),
|
||||
.RXCLKDIV (CLKDIV_R),
|
||||
.RESET (RST),
|
||||
.IDLY_RESET (RST),
|
||||
|
||||
.DATA_RX_P ({DATA_IN_p,MSG_IN_p}),
|
||||
.DATA_RX_N ({DATA_IN_n,MSG_IN_n}),
|
||||
.INC_PAD (1'b0),
|
||||
.DEC_PAD (1'b0),
|
||||
.DATA_FROM_ISERDES ({DATA_IN[31:0],MSG_IN[7:0]}),
|
||||
.BITSLIP_PAD (1'b0),
|
||||
.TAP_00 (),
|
||||
.TAP_01 (),
|
||||
.TAP_02 (),
|
||||
.TAP_03 (),
|
||||
.TAP_04 (),
|
||||
.TAP_CLK (),
|
||||
.TRAINING_DONE (TRAINING_DONE_Adapter2RCB)
|
||||
);
|
||||
|
||||
|
||||
RCB_FRL_RX Sora_FRL_RCB_RX_data_inst (
|
||||
.CLKDIV (CLKDIV_R),
|
||||
// .RDCLK (CLKDIV_R),
|
||||
.RST (RST),
|
||||
|
||||
.DATA_IN (DATA_IN),
|
||||
.DATA_OUT (DATA_INT_OUT),
|
||||
.RDEN (~DATA_ALMOSTEMPTY),
|
||||
.ALMOSTEMPTY (DATA_ALMOSTEMPTY)
|
||||
// .fifo_WREN (fifo_WREN)
|
||||
);
|
||||
|
||||
assign MSG_Valid = msg_r_p_one; // added by jiansong, 2010-5-27
|
||||
RCB_FRL_RX_MSG Sora_FRL_RCB_RX_MSG_inst (
|
||||
.CLKDIV (CLKDIV_R),
|
||||
.RST (RST),
|
||||
|
||||
.DATA_IN (MSG_IN[7:0]),
|
||||
.DATA_OUT ({MSG_INT_OUT_Addr[7:0],MSG_INT_OUT_Data[31:0]}),
|
||||
.msg_r_n_one (msg_r_n_one),
|
||||
.msg_r_p_one (msg_r_p_one),
|
||||
.nack_r_one (nack_r_one),
|
||||
.ack_r_one (ack_r_one)
|
||||
);//these are for the radio board
|
||||
|
||||
RCB_FRL_LED_Clock RCB_FRL_LED_Clock_inst (
|
||||
.Test_Clock_in(CLK_R),
|
||||
.LED_Clock_out(LED_CLOCK_0),
|
||||
.RST(RST)
|
||||
);
|
||||
|
||||
RCB_FRL_LED_Clock_DIV RCB_FRL_LED_Clock_DIV_inst (
|
||||
.Test_Clock_in(CLKDIV_R),
|
||||
.LED_Clock_out(LED_CLOCK_1),
|
||||
.RST(RST)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,177 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 16:00:17 07/29/2011
|
||||
// Design Name:
|
||||
// Module Name: Sora_FRL_STATUS_IN
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
/////
|
||||
///// Decode four patterns for specific states
|
||||
///// Idle 00000000
|
||||
///// Reset 01010101
|
||||
///// FIFO full 00001111
|
||||
///// Training_done 00110011
|
||||
/////
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module Sora_FRL_STATUS_decoder(
|
||||
input clk,
|
||||
// input rst, // no need for a reset signal since these's no internal state
|
||||
|
||||
// input from STATUS line
|
||||
input status_in,
|
||||
|
||||
// four output states
|
||||
output reg RST_state,
|
||||
output reg TRAININGDONE_state,
|
||||
output reg IDLE_state,
|
||||
output reg FIFOFULL_state,
|
||||
// error state
|
||||
output reg error_state
|
||||
);
|
||||
|
||||
reg ambiguity; // indicates ambiguous status
|
||||
reg [3:0] error_cnt;
|
||||
|
||||
reg [7:0] shift_reg;
|
||||
parameter IDLE = 4'b0001;
|
||||
parameter RST = 4'b0010;
|
||||
parameter FIFOFULL = 4'b0100;
|
||||
parameter TRAININGDONE = 4'b1000;
|
||||
reg [3:0] INT_SAT;
|
||||
|
||||
// always@(posedge clk)begin
|
||||
// if(rst)
|
||||
// shift_reg <= 8'h00;
|
||||
// else
|
||||
// shift_reg <= {shift_reg[6:0], status_in};
|
||||
// end
|
||||
initial shift_reg <= 8'h00;
|
||||
always@(posedge clk) shift_reg <= {shift_reg[6:0], status_in};
|
||||
|
||||
// decoder
|
||||
initial begin
|
||||
ambiguity <= 1'b0;
|
||||
INT_SAT <= IDLE;
|
||||
end
|
||||
always@(posedge clk) begin
|
||||
ambiguity <= 1'b0;
|
||||
|
||||
if ( shift_reg == 8'h55 | shift_reg == 8'hAA) begin
|
||||
INT_SAT <= RST;
|
||||
end else if ( shift_reg == 8'hF0 | shift_reg == 8'h87 | shift_reg == 8'hC3 | shift_reg == 8'hE1 | shift_reg == 8'h78 | shift_reg == 8'h3C | shift_reg == 8'h1E | shift_reg == 8'h0F ) begin
|
||||
INT_SAT <= FIFOFULL;
|
||||
end else if ( shift_reg == 8'h33 | shift_reg == 8'h66 | shift_reg == 8'hCC | shift_reg == 8'h99 ) begin
|
||||
INT_SAT <= TRAININGDONE;
|
||||
end else if ( shift_reg == 8'h00) begin
|
||||
INT_SAT <= IDLE;
|
||||
end else begin// by default, the previous INT_SAT remains, this normally happen when the status is changing
|
||||
INT_SAT <= INT_SAT;
|
||||
ambiguity <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// detect error state
|
||||
initial
|
||||
error_cnt <= 4'b0000;
|
||||
always@(posedge clk) begin
|
||||
// if (rst) begin
|
||||
// error_cnt <= 4'b0000;
|
||||
// end else if(ambiguity) begin
|
||||
if (ambiguity) begin
|
||||
if (error_cnt != 4'b1000)
|
||||
error_cnt <= error_cnt + 4'b0001;
|
||||
else
|
||||
error_cnt <= error_cnt;
|
||||
end else begin
|
||||
error_cnt <= 4'b0000;
|
||||
end
|
||||
end
|
||||
always@(posedge clk) begin
|
||||
error_state <= (error_cnt == 4'b1000) ? 1'b1 : 1'b0;
|
||||
end
|
||||
|
||||
// determine the output signals
|
||||
initial begin
|
||||
RST_state <= 1'b0;
|
||||
TRAININGDONE_state <= 1'b0;
|
||||
FIFOFULL_state <= 1'b0;
|
||||
IDLE_state <= 1'b1;
|
||||
end
|
||||
always@(posedge clk) begin
|
||||
// if (rst) begin
|
||||
// RST_state <= 1'b0;
|
||||
// TRAININGDONE_state <= 1'b0;
|
||||
// FIFOFULL_state <= 1'b0;
|
||||
// IDLE_state <= 1'b1;
|
||||
// end else if (INT_SAT == RST) begin
|
||||
if (INT_SAT == RST) begin
|
||||
RST_state <= 1'b1;
|
||||
TRAININGDONE_state <= 1'b0;
|
||||
FIFOFULL_state <= 1'b0;
|
||||
IDLE_state <= 1'b0;
|
||||
end else if ( INT_SAT == FIFOFULL ) begin
|
||||
RST_state <= 1'b0;
|
||||
TRAININGDONE_state <= 1'b1;
|
||||
FIFOFULL_state <= 1'b1;
|
||||
IDLE_state <= 1'b0;
|
||||
end else if ( INT_SAT == TRAININGDONE ) begin
|
||||
RST_state <= 1'b0;
|
||||
TRAININGDONE_state <= 1'b1;
|
||||
FIFOFULL_state <= 1'b0;
|
||||
IDLE_state <= 1'b0;
|
||||
end else if ( INT_SAT == IDLE ) begin
|
||||
RST_state <= 1'b0;
|
||||
TRAININGDONE_state <= 1'b0;
|
||||
FIFOFULL_state <= 1'b0;
|
||||
IDLE_state <= 1'b1;
|
||||
end else begin // should not go into this branch
|
||||
RST_state <= 1'b0;
|
||||
TRAININGDONE_state <= 1'b0;
|
||||
FIFOFULL_state <= 1'b0;
|
||||
IDLE_state <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 16:08:11 07/29/2011
|
||||
// Design Name:
|
||||
// Module Name: Sora_FRL_STATUS_OUT
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
/////
|
||||
///// Generate four patterns for specific states
|
||||
///// Idle 00000000
|
||||
///// Reset 01010101
|
||||
///// FIFO full 00001111
|
||||
///// Training_done 00110011
|
||||
/////
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module Sora_FRL_STATUS_encoder(
|
||||
input clk,
|
||||
// input rst,
|
||||
|
||||
// input from STATUS line
|
||||
output status_out,
|
||||
|
||||
// four output states
|
||||
input RST_signal,
|
||||
input TRAININGDONE_signal,
|
||||
input IDLE_signal,
|
||||
input FIFOFULL_signal
|
||||
);
|
||||
|
||||
// wire rst_one;
|
||||
reg [2:0] counter;
|
||||
reg status_r;
|
||||
|
||||
reg [1:0] Status_state;
|
||||
parameter STATE_IDLE = 2'b00;
|
||||
parameter STATE_TRAININGDONE = 2'b01;
|
||||
parameter STATE_FIFOFULL = 2'b10;
|
||||
parameter STATE_RST = 2'b11;
|
||||
|
||||
parameter STR_IDLE = 8'b0000_0000;
|
||||
parameter STR_TRAININGDONE = 8'b0011_0011;
|
||||
parameter STR_FIFOFULL = 8'b0000_1111;
|
||||
parameter STR_RST = 8'b0101_0101;
|
||||
|
||||
// determine Status_state according to input signals
|
||||
initial
|
||||
Status_state <= STATE_IDLE;
|
||||
always@(posedge clk)begin
|
||||
// if (rst | RST_signal)
|
||||
if (RST_signal)
|
||||
Status_state <= STATE_RST;
|
||||
else if (IDLE_signal) // this signal is subtle, it's asserted when a RST state is received from Status line,
|
||||
// and in this case, FIFOFULL_signal & TRAININGDONE_signal should be deasserted outside of this module
|
||||
Status_state <= STATE_IDLE;
|
||||
else if (FIFOFULL_signal)
|
||||
Status_state <= STATE_FIFOFULL;
|
||||
else if (TRAININGDONE_signal)
|
||||
Status_state <= STATE_TRAININGDONE;
|
||||
else
|
||||
Status_state <= STATE_IDLE;
|
||||
end
|
||||
|
||||
initial
|
||||
counter <= 3'b000;
|
||||
always@(posedge clk)
|
||||
counter <= counter + 3'b001;
|
||||
// always@(posedge clk)begin
|
||||
// if (rst)
|
||||
// counter <= 3'b000;
|
||||
// else
|
||||
// counter <= counter + 3'b001;
|
||||
// end
|
||||
|
||||
assign status_out = status_r;
|
||||
// Status encoder
|
||||
always@(posedge clk)begin
|
||||
case(Status_state)
|
||||
STATE_RST:
|
||||
status_r <= STR_RST[counter];
|
||||
STATE_TRAININGDONE:
|
||||
status_r <= STR_TRAININGDONE[counter];
|
||||
STATE_FIFOFULL:
|
||||
status_r <= STR_FIFOFULL[counter];
|
||||
STATE_IDLE:
|
||||
status_r <= STR_IDLE[counter];
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,191 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 15:18:35 08/11/2009
|
||||
// Design Name:
|
||||
// Module Name: STATUS_IN
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
/////
|
||||
///// Decode four patterns for specific states
|
||||
///// Idle 00000000
|
||||
///// Reset 01010101
|
||||
///// FIFO full 00001111
|
||||
///// Training_done 00110011
|
||||
/////
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module RCB_FRL_STATUS_IN(
|
||||
input CLK,
|
||||
input MODULE_RST,
|
||||
output reg RESET, //output indicating reset state
|
||||
output reg FIFO_FULL, //output indicating full state
|
||||
output reg TRAINING_DONE, //output indicating done state
|
||||
input STATUS,
|
||||
output reg status_error // indicates error if ambiguous status lasts longer than 8 cycles
|
||||
// output reg IDLE_RESET // Jiansong: why we need IDLE_RESET?
|
||||
);
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// input CLK;
|
||||
// input MODULE_RST;
|
||||
// input STATUS;
|
||||
// output RESET,
|
||||
// FIFO_FULL,
|
||||
// TRAINING_DONE,
|
||||
// IDLE_RESET;
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
// reg RESET,
|
||||
// FIFO_FULL,
|
||||
// TRAINING_DONE,
|
||||
reg IDLE_RESET;
|
||||
reg IDLE_FLAG; // why we need this flag?
|
||||
|
||||
reg ambiguity; // indicates ambiguous status
|
||||
reg [2:0] error_cnt;
|
||||
|
||||
reg [7:0] shift_reg;
|
||||
parameter RST = 2'b00;
|
||||
parameter FULL = 2'b01;
|
||||
parameter DONE = 2'b10;
|
||||
parameter IDLE = 2'b11;
|
||||
reg [1:0] INT_SAT;
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
always @ ( negedge CLK ) begin
|
||||
if ( MODULE_RST == 1'b1 ) begin
|
||||
shift_reg <= 8'h00;
|
||||
end
|
||||
else begin
|
||||
shift_reg <= {shift_reg[6:0], STATUS};
|
||||
end
|
||||
end
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
/// Pattern Recognition
|
||||
// Modified by Jiansong, 2010-5-25, remove ambiguity
|
||||
always @ ( negedge CLK ) begin
|
||||
ambiguity <= 1'b0;
|
||||
|
||||
if ( shift_reg == 8'h55 | shift_reg == 8'hAA) begin
|
||||
INT_SAT <= RST;
|
||||
end
|
||||
else if ( shift_reg == 8'hF0 | shift_reg == 8'h87 | shift_reg == 8'hC3 | shift_reg == 8'hE1 | shift_reg == 8'h78 | shift_reg == 8'h3C | shift_reg == 8'h1E | shift_reg == 8'h0F ) begin
|
||||
INT_SAT <= FULL;
|
||||
end
|
||||
else if ( shift_reg == 8'h33 | shift_reg == 8'h66 | shift_reg == 8'hCC | shift_reg == 8'h99 ) begin
|
||||
INT_SAT <= DONE;
|
||||
end
|
||||
else if ( shift_reg == 8'h00) begin
|
||||
INT_SAT <= IDLE;
|
||||
end
|
||||
else begin// by default, the previous INT_SAT remains, this normally happen when the status is changing
|
||||
INT_SAT <= INT_SAT;
|
||||
ambiguity <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always@ (negedge CLK) begin
|
||||
if (MODULE_RST) begin
|
||||
error_cnt <= 3'b000;
|
||||
end else if(ambiguity) begin
|
||||
if (error_cnt != 3'b111)
|
||||
error_cnt <= error_cnt + 3'b001;
|
||||
else
|
||||
error_cnt <= error_cnt;
|
||||
end else begin
|
||||
error_cnt <= 3'b000;
|
||||
end
|
||||
end
|
||||
|
||||
always@ (negedge CLK) begin
|
||||
status_error <= (error_cnt == 3'b111) ? 1'b1 : 1'b0;
|
||||
end
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
/// States are exclusive of each other
|
||||
always @ (posedge CLK) begin
|
||||
if ( MODULE_RST == 1'b1 ) begin
|
||||
RESET <= 1'b0;
|
||||
TRAINING_DONE <= 1'b0;
|
||||
FIFO_FULL <= 1'b0;
|
||||
IDLE_RESET <= 0;
|
||||
IDLE_FLAG <= 0;
|
||||
end
|
||||
else if ( INT_SAT == RST) begin
|
||||
RESET <= 1'b1;
|
||||
TRAINING_DONE <= 1'b0;
|
||||
FIFO_FULL <= 1'b0;
|
||||
IDLE_RESET <= 0;
|
||||
IDLE_FLAG <= 0;
|
||||
end
|
||||
else if ( INT_SAT == DONE ) begin
|
||||
TRAINING_DONE <= 1'b1;
|
||||
FIFO_FULL <= 1'b0;
|
||||
RESET <= 1'b0;
|
||||
IDLE_RESET <= 0;
|
||||
IDLE_FLAG <= 0;
|
||||
end
|
||||
else if ( INT_SAT == FULL ) begin
|
||||
RESET <= 1'b0;
|
||||
FIFO_FULL <= 1'b1;
|
||||
TRAINING_DONE <= 1'b1;
|
||||
IDLE_RESET <= 0;
|
||||
IDLE_FLAG <= 0;
|
||||
end
|
||||
else if ( INT_SAT == IDLE ) begin
|
||||
if(IDLE_FLAG == 0) // Jiansong: edge detection
|
||||
begin
|
||||
IDLE_FLAG <= 1;
|
||||
IDLE_RESET <= 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
IDLE_RESET <= 0;
|
||||
end
|
||||
RESET <= 1'b0;
|
||||
FIFO_FULL <= 1'b0;
|
||||
TRAINING_DONE <= 1'b0;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 14:54:18 08/11/2009
|
||||
// Design Name:
|
||||
// Module Name: STATUS_OUT
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
/////
|
||||
///// Generate four patterns for specific states
|
||||
///// Idle 00000000
|
||||
///// Reset 01010101
|
||||
///// FIFO full 00001111
|
||||
///// Training_done 00110011
|
||||
/////
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module RCB_FRL_STATUS_OUT( CLK,
|
||||
RESET, // input indicating whether channel is reset, reset pulse of the whole lvds channel
|
||||
MODULE_RST, // reset pulse for this module only, should be shorter than RESET
|
||||
FIFO_FULL, // input indicating whether FIFO is FULL
|
||||
TRAINING_DONE, // input indicating whether TRAINING is done
|
||||
STATUS,
|
||||
INT_SAT // coded status output
|
||||
);
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
input CLK;
|
||||
input MODULE_RST;
|
||||
input RESET,
|
||||
FIFO_FULL,
|
||||
TRAINING_DONE;
|
||||
output STATUS;
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
reg STATUS;
|
||||
|
||||
output reg [1:0] INT_SAT;
|
||||
parameter RST = 2'b00;
|
||||
parameter FULL = 2'b01;
|
||||
parameter DONE = 2'b10;
|
||||
parameter IDLE = 2'b11;
|
||||
|
||||
reg [2:0] counter;
|
||||
|
||||
wire MODULE_RST_one;
|
||||
|
||||
rising_edge_detect MODULE_RESET_one_inst(
|
||||
.clk(CLK),
|
||||
.rst(1'b0),
|
||||
.in(MODULE_RST),
|
||||
.one_shot_out(MODULE_RST_one)
|
||||
);
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
/// Determine which state it is
|
||||
|
||||
always @ ( posedge CLK ) begin
|
||||
if ( counter == 3'b000 ) begin
|
||||
if ( RESET == 1'b1 ) begin
|
||||
INT_SAT <= RST;
|
||||
end
|
||||
else if ( FIFO_FULL == 1'b1 & TRAINING_DONE == 1'b1 ) begin
|
||||
INT_SAT <= FULL;
|
||||
end
|
||||
else if ( TRAINING_DONE == 1'b1 ) begin
|
||||
INT_SAT <= DONE;
|
||||
end
|
||||
else begin
|
||||
INT_SAT <= IDLE;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
/// Counter runs
|
||||
|
||||
always @ ( posedge CLK ) begin
|
||||
// if ( MODULE_RST == 1'b1 ) begin // Jiansong: how can it send out reset status
|
||||
if ( MODULE_RST_one == 1'b1 ) begin
|
||||
counter <= 3'b000;
|
||||
end
|
||||
else begin
|
||||
counter <= counter + 3'b001;
|
||||
end
|
||||
end
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
/// pattern encode
|
||||
/// Idle 00000000
|
||||
/// Reset 01010101
|
||||
/// FIFO_full 00001111
|
||||
/// Train Done 00110011
|
||||
|
||||
always @ ( posedge CLK) begin
|
||||
if ( INT_SAT == RST ) begin
|
||||
if ( counter == 3'b000 | counter == 3'b010 | counter == 3'b100 | counter == 3'b110 ) begin
|
||||
STATUS <= 1'b0;
|
||||
end
|
||||
else if (counter == 3'b001 | counter == 3'b011 | counter == 3'b101 | counter == 3'b111 ) begin
|
||||
STATUS <= 1'b1;
|
||||
end
|
||||
end
|
||||
else if ( INT_SAT == FULL) begin
|
||||
if (counter == 3'b000 | counter == 3'b001 | counter == 3'b010 | counter == 3'b011 ) begin
|
||||
STATUS <= 1'b0;
|
||||
end
|
||||
else if ( counter == 3'b100 | counter == 3'b101 | counter == 3'b110 | counter == 3'b111 ) begin
|
||||
STATUS <= 1'b1;
|
||||
end
|
||||
end
|
||||
else if ( INT_SAT == DONE) begin
|
||||
if ( counter == 3'b000 | counter == 3'b001 | counter == 3'b100 | counter == 3'b101 ) begin
|
||||
STATUS <= 1'b0;
|
||||
end
|
||||
else if ( counter == 3'b010 | counter == 3'b011 | counter == 3'b110 | counter == 3'b111 )begin
|
||||
STATUS <= 1'b1;
|
||||
end
|
||||
end
|
||||
else if ( INT_SAT == IDLE) begin
|
||||
STATUS <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
module RCB_FRL_data_check(CLK,RST,RDEN_DATA,RDEN_MSG,DATA,MSG,ERR0,ERR1,ERR2,ERR3,ERR_MSG);
|
||||
|
||||
input CLK,RST,RDEN_DATA,RDEN_MSG;
|
||||
input [31:0] DATA;
|
||||
input [39:0] MSG;
|
||||
|
||||
output reg [3:0] ERR0,ERR1,ERR2,ERR3,ERR_MSG;
|
||||
|
||||
reg [31:0] DATA_TEMP;
|
||||
reg [7:0] MSG_TEMP;
|
||||
|
||||
always @ (posedge CLK)
|
||||
begin
|
||||
if(RST)
|
||||
begin
|
||||
ERR0 <= 0;
|
||||
ERR1 <= 0;
|
||||
ERR2 <= 0;
|
||||
ERR3 <= 0;
|
||||
ERR_MSG <= 0;
|
||||
DATA_TEMP <= 0;
|
||||
MSG_TEMP <= 0;
|
||||
end
|
||||
else if(RDEN_DATA)
|
||||
begin
|
||||
DATA_TEMP <= DATA;
|
||||
MSG_TEMP <= MSG;
|
||||
if(DATA_TEMP[7:0] + 1 != DATA[7:0] && DATA[7:0] != 0)
|
||||
ERR0 <= ERR0 + 1;
|
||||
if(DATA_TEMP[15:8] + 1 != DATA[15:8] && DATA[15:8] != 0)
|
||||
ERR1 <= ERR1 + 1;
|
||||
if(DATA_TEMP[23:16] + 1 != DATA[23:16] && DATA[23:16] != 0)
|
||||
ERR2 <= ERR2 + 1;
|
||||
if(DATA_TEMP[31:24] + 1 != DATA[31:24] && DATA[31:24] != 0)
|
||||
ERR3 <= ERR3 + 1;
|
||||
if(MSG[39:32] + 1 != MSG[31:24] || MSG[31:24] + 1 != MSG[23:16] || MSG[23:16] + 1 != MSG[15:8] || MSG[15:8] + 1 != MSG[7:0])
|
||||
ERR_MSG <= ERR_MSG + 1;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module RCB_FRL_fifo_MSG(ALMOSTEMPTY, ALMOSTFULL, DO, EMPTY, FULL, DI, RDCLK, RDEN, WRCLK, WREN, RST);
|
||||
|
||||
output ALMOSTEMPTY, ALMOSTFULL, EMPTY, FULL;
|
||||
output [39:0] DO;
|
||||
input [39:0] DI;
|
||||
input RDCLK, RDEN, WRCLK, WREN, RST;
|
||||
|
||||
wire [63:40] zero;
|
||||
|
||||
FIFO36_72 #(
|
||||
.ALMOST_FULL_OFFSET(9'h080), // Sets almost full threshold
|
||||
.ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
|
||||
.DO_REG(1), // Enable output register (0 or 1)
|
||||
// Must be 1 if EN_SYN = "FALSE"
|
||||
.EN_ECC_READ("FALSE"), // Enable ECC decoder, "TRUE" or "FALSE"
|
||||
.EN_ECC_WRITE("FALSE"), // Enable ECC encoder, "TRUE" or "FALSE"
|
||||
.EN_SYN("FALSE"), // Specifies FIFO as Asynchronous ("FALSE")
|
||||
// or Synchronous ("TRUE")
|
||||
.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE"
|
||||
) FIFO36_72_inst (
|
||||
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
|
||||
.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
|
||||
.DBITERR(), // 1-bit double bit error status output
|
||||
.DO({zero[63:40],DO[39:0]}), // 32-bit data output
|
||||
.DOP(), // 4-bit parity data output
|
||||
.ECCPARITY(), // 8-bit generated error correction parity
|
||||
.EMPTY(EMPTY), // 1-bit empty output flag
|
||||
.FULL(FULL), // 1-bit full output flag
|
||||
.RDCOUNT(), // 9-bit read count output
|
||||
.RDERR(), // 1-bit read error output
|
||||
.SBITERR(), // 1-bit single bit error status output
|
||||
.WRCOUNT(), // 9-bit write count output
|
||||
.WRERR(), // 1-bit write error
|
||||
.DI({24'h000,DI}), // 32-bit data input
|
||||
.DIP(), // 4-bit parity input
|
||||
.RDCLK(RDCLK), // 1-bit read clock input
|
||||
.RDEN(RDEN), // 1-bit read enable input
|
||||
.RST(RST), // 1-bit reset input
|
||||
.WRCLK(WRCLK), // 1-bit write clock input
|
||||
.WREN(WREN) // 1-bit write enable input
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 16:08:11 07/29/2011
|
||||
// Design Name:
|
||||
// Module Name: Sora_FRL_STATUS_OUT
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module Sora_FRL_STATUS_encoder(
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
// input from STATUS line
|
||||
output status_out,
|
||||
|
||||
// four output states
|
||||
input RST_state,
|
||||
input TRAININGDONE_state,
|
||||
input IDLE_state,
|
||||
input FIFOFULL_state
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 12:18:33 05/14/2010
|
||||
// Design Name:
|
||||
// Module Name: Clock_module_FRL
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description: generate clocks from 200MHz clock input.
|
||||
// If Sora_FRL is used, only 133MHz for DDR2 module is needed
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module Clock_module_FRL(
|
||||
input clk200,
|
||||
input rst,
|
||||
output clk133,
|
||||
// output [4:0] locked_debug,
|
||||
output unlocked_err
|
||||
);
|
||||
|
||||
wire locked1, locked_pll;
|
||||
wire clk176, clk200_pll;
|
||||
assign unlocked_err = (~locked1) & (~locked_pll);
|
||||
|
||||
//assign locked_debug = {1'b0, 1'b0, 1'b0, locked1, locked_pll};
|
||||
|
||||
PLL_200MI_200MO PLL_200MI_200MO_inst(
|
||||
.CLKIN1_IN(clk200),
|
||||
.RST_IN(rst),
|
||||
.CLKOUT0_OUT(clk200_pll),
|
||||
.LOCKED_OUT(locked_pll)
|
||||
);
|
||||
|
||||
DCM_200MI_133MO_176MO DCM_200MI_133MO_176MO_inst(
|
||||
.CLKIN_IN(clk200_pll),
|
||||
.CLKDV_OUT(clk133),
|
||||
.CLKFX_OUT(clk176),
|
||||
.RST_IN(rst),
|
||||
.LOCKED_OUT(locked1),
|
||||
.CLK0_OUT()
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 01/05/2010
|
||||
// Design Name:
|
||||
// Module Name: parameters for Sora's configuration
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//`define sora_simulation // PCIe endpoint v1.8 is used in simulation, v1.9 is used in implementation
|
||||
|
||||
`define RADIO_CHANNEL_REGISTERS
|
||||
|
||||
`define MIMO_4X4
|
||||
|
||||
//`define sora_chipscope
|
||||
|
||||
//`define TF_RECOVERY // transfer recovery
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 17:44:53 09/03/2012
|
||||
// Design Name:
|
||||
// Module Name: TX_controller
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module TX_controller_noloss(
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
input [4:0] DDR2MaxBurstSize,
|
||||
// triggers
|
||||
input TX_Start_one,
|
||||
input [31:0] TX_Addr,
|
||||
input [31:0] TX_Size,
|
||||
/// connection to dma_ddr2_if
|
||||
output reg TX_data_req,
|
||||
input TX_data_ack,
|
||||
output reg [27:6] TX_Start_addr,
|
||||
output reg [2:0] TX_xfer_size
|
||||
);
|
||||
|
||||
//state machine state definitions for TX_state_sm0
|
||||
localparam IDLE_TSM0 = 3'b000;
|
||||
localparam TX_1 = 3'b001;
|
||||
localparam TX_2 = 3'b010;
|
||||
localparam TX_3 = 3'b011;
|
||||
localparam TX_4 = 3'b100;
|
||||
|
||||
//state machine state definitions for TX_state_sm1
|
||||
localparam IDLE_TSM1 = 4'h0;
|
||||
localparam CALC_NEXT_TX = 4'h1;
|
||||
localparam TX_CALC_4KB = 4'h2;
|
||||
localparam TX_CALC_2KB = 4'h3;
|
||||
localparam TX_CALC_1KB = 4'h4;
|
||||
localparam TX_CALC_512B = 4'h5;
|
||||
localparam TX_CALC_256B = 4'h6;
|
||||
localparam TX_CALC_128B = 4'h7;
|
||||
localparam TX_CALC_64B = 4'h8;
|
||||
localparam WAIT_TX_CALC = 4'h9;
|
||||
|
||||
/// Jiansong: TX registers
|
||||
reg TX_calc_next; // calculate next tx addr and tx size, signal for TX SM 1
|
||||
reg next_TX_ready; // ready to send out next tx request, signal for TX SM 0
|
||||
reg [31:0] TX_addr_now;
|
||||
reg [31:0] TX_size_now;
|
||||
reg [2:0] TX_state_0;
|
||||
reg [3:0] TX_state_1;
|
||||
|
||||
|
||||
//////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////////////////////////
|
||||
//// Jiansong: //////
|
||||
//// Logic for generating read DDR2 requests, according to //////
|
||||
//// TX request from host. A TX request is to transmit a block //////
|
||||
//// of data to radio module. The size of a block could be as //////
|
||||
//// large as several mega-bytes. In the following logic, a //////
|
||||
//// block will be divided to a series of small blocks with //////
|
||||
//// size up to 4KB. //////
|
||||
//////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////////////////////////////////////////////
|
||||
|
||||
reg TX_Start_signal;
|
||||
reg TX_Start_ack;
|
||||
|
||||
always@(posedge clk) begin
|
||||
if (rst)
|
||||
TX_Start_signal <= 1'b0;
|
||||
else if (TX_Start_one)
|
||||
TX_Start_signal <= 1'b1;
|
||||
else if (TX_Start_ack)
|
||||
TX_Start_signal <= 1'b0;
|
||||
else
|
||||
TX_Start_signal <= TX_Start_signal;
|
||||
end
|
||||
|
||||
/// TX state machine 0
|
||||
/// generate output TX_data_req, and TX_calc_next for TX_state_1
|
||||
always@(posedge clk)begin
|
||||
if(rst)begin
|
||||
TX_calc_next <= 1'b0;
|
||||
TX_data_req <= 1'b0;
|
||||
TX_Start_ack <= 1'b0;
|
||||
TX_state_0 <= IDLE_TSM0;
|
||||
end else begin
|
||||
case(TX_state_0)
|
||||
IDLE_TSM0: begin
|
||||
TX_calc_next <= 1'b0;
|
||||
TX_data_req <= 1'b0;
|
||||
|
||||
// next_TX_ready will remain high after the last TX request, but it doesn't matter
|
||||
if (next_TX_ready) begin
|
||||
TX_Start_ack <= 1'b0;
|
||||
TX_state_0 <= TX_1;
|
||||
end else if (TX_Start_signal) begin
|
||||
TX_Start_ack <= 1'b1;
|
||||
TX_state_0 <= TX_1;
|
||||
end else begin
|
||||
TX_Start_ack <= 1'b0;
|
||||
TX_state_0 <= IDLE_TSM0;
|
||||
end
|
||||
|
||||
end
|
||||
TX_1: begin // this state is used to set TX_xfer_size and TX_Start_addr output
|
||||
TX_calc_next <= 1'b1;
|
||||
TX_data_req <= 1'b0;
|
||||
TX_state_0 <= TX_2;
|
||||
end
|
||||
TX_2: begin // calc TX_size_next and TX_addr_next, send out TX request to DMA_DDR_IF
|
||||
TX_calc_next <= 1'b0;
|
||||
TX_data_req <= 1'b1;
|
||||
TX_state_0 <= TX_3;
|
||||
end
|
||||
TX_3: begin
|
||||
TX_calc_next <= 1'b0;
|
||||
if(TX_data_ack)begin
|
||||
TX_data_req <= 1'b0;
|
||||
TX_state_0 <= TX_4;
|
||||
end else begin
|
||||
TX_data_req <= 1'b1;
|
||||
TX_state_0 <= TX_3;
|
||||
end
|
||||
end
|
||||
TX_4: begin // wait for next_TX_ready
|
||||
TX_calc_next <= 1'b0;
|
||||
TX_data_req <= 1'b0;
|
||||
TX_state_0 <= IDLE_TSM0;
|
||||
end
|
||||
default:begin
|
||||
TX_calc_next <= 1'b0;
|
||||
TX_data_req <= 1'b0;
|
||||
TX_state_0 <= IDLE_TSM0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// set output: TX_xfer_size and TX_Start_addr[27:6]
|
||||
always@(posedge clk) TX_Start_addr[6] <= 1'b0;
|
||||
always@(posedge clk)begin
|
||||
if(rst)begin
|
||||
TX_xfer_size <= 3'b000;
|
||||
TX_Start_addr[27:7] <= 21'h00_0000;
|
||||
|
||||
end else if (TX_state_0 == TX_1)begin
|
||||
TX_Start_addr[27:7] <= TX_addr_now[27:7];
|
||||
|
||||
if(TX_size_now[27:10] != 0) // 1KB
|
||||
TX_xfer_size <= 3'b100;
|
||||
else if(TX_size_now[9] != 0) // 512B
|
||||
TX_xfer_size <= 3'b011;
|
||||
else if(TX_size_now[8] != 0) // 256B
|
||||
TX_xfer_size <= 3'b010;
|
||||
else if(TX_size_now[7] != 0) // 128B
|
||||
TX_xfer_size <= 3'b001;
|
||||
else // default to 128B
|
||||
TX_xfer_size <= 3'b001;
|
||||
|
||||
end else begin
|
||||
TX_xfer_size <= TX_xfer_size;
|
||||
TX_Start_addr[27:7] <= TX_Start_addr[27:7];
|
||||
end
|
||||
end
|
||||
|
||||
/// TX state machine 1
|
||||
/// calculate next size and address
|
||||
always@(posedge clk)begin
|
||||
if(rst)begin
|
||||
TX_addr_now[31:0] <= 32'h0000_0000;
|
||||
TX_size_now[31:0] <= 32'h0000_0000;
|
||||
next_TX_ready <= 1'b0;
|
||||
TX_state_1 <= IDLE_TSM1;
|
||||
end else begin
|
||||
case(TX_state_1)
|
||||
IDLE_TSM1:begin
|
||||
next_TX_ready <= next_TX_ready;
|
||||
if(TX_Start_signal & (~next_TX_ready))begin
|
||||
TX_addr_now[31:0] <= TX_Addr[31:0];
|
||||
TX_size_now[31:0] <= TX_Size[31:0];
|
||||
end else begin
|
||||
TX_addr_now[31:0] <= TX_addr_now[31:0];
|
||||
TX_size_now[31:0] <= TX_size_now[31:0];
|
||||
end
|
||||
if(TX_calc_next)
|
||||
TX_state_1 <= CALC_NEXT_TX;
|
||||
else
|
||||
TX_state_1 <= IDLE_TSM1;
|
||||
end
|
||||
CALC_NEXT_TX:begin
|
||||
TX_addr_now[31:0] <= TX_addr_now[31:0];
|
||||
TX_size_now[31:0] <= TX_size_now[31:0];
|
||||
next_TX_ready <= 1'b0;
|
||||
|
||||
if (TX_size_now[27:10] != 0)
|
||||
TX_state_1 <= TX_CALC_1KB;
|
||||
else if (TX_size_now[9] != 0)
|
||||
TX_state_1 <= TX_CALC_512B;
|
||||
else if (TX_size_now[8] != 0)
|
||||
TX_state_1 <= TX_CALC_256B;
|
||||
else if (TX_size_now[7] != 0)
|
||||
TX_state_1 <= TX_CALC_128B;
|
||||
else
|
||||
TX_state_1 <= TX_CALC_128B;
|
||||
|
||||
end
|
||||
TX_CALC_1KB:begin
|
||||
TX_addr_now[31:0] <= TX_addr_now[31:0] + 32'h0000_0400;
|
||||
TX_size_now[31:10] <= TX_size_now[31:10] - 1'b1;
|
||||
next_TX_ready <= 1'b0;
|
||||
TX_state_1 <= WAIT_TX_CALC;
|
||||
end
|
||||
TX_CALC_512B:begin
|
||||
TX_addr_now[31:0] <= TX_addr_now[31:0] + 32'h0000_0200;
|
||||
TX_size_now[31:9] <= TX_size_now[31:9] - 1'b1;
|
||||
next_TX_ready <= 1'b0;
|
||||
TX_state_1 <= WAIT_TX_CALC;
|
||||
end
|
||||
TX_CALC_256B:begin
|
||||
TX_addr_now[31:0] <= TX_addr_now[31:0] + 32'h0000_0100;
|
||||
TX_size_now[31:8] <= TX_size_now[31:8] - 1'b1;
|
||||
next_TX_ready <= 1'b0;
|
||||
TX_state_1 <= WAIT_TX_CALC;
|
||||
end
|
||||
TX_CALC_128B:begin
|
||||
TX_addr_now[31:0] <= TX_addr_now[31:0] + 32'h0000_0080;
|
||||
TX_size_now[31:7] <= TX_size_now[31:7] - 1'b1;
|
||||
next_TX_ready <= 1'b0;
|
||||
TX_state_1 <= WAIT_TX_CALC;
|
||||
end
|
||||
|
||||
WAIT_TX_CALC:begin
|
||||
TX_addr_now[31:0] <= TX_addr_now[31:0];
|
||||
TX_size_now[31:0] <= TX_size_now[31:0];
|
||||
if (TX_size_now[31:7] != 0)
|
||||
next_TX_ready <= 1'b1;
|
||||
else
|
||||
next_TX_ready <= 1'b0;
|
||||
TX_state_1 <= IDLE_TSM1;
|
||||
end
|
||||
|
||||
default:begin
|
||||
TX_addr_now[31:0] <= 32'h0000_0000;
|
||||
TX_size_now[31:0] <= 32'h0000_0000;
|
||||
TX_state_1 <= IDLE_TSM1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// /// update TX_addr_now and TX_size_now
|
||||
// always@(posedge clk)begin
|
||||
// if(rst)begin
|
||||
// TX_addr_now[31:0] <= 32'h0000_0000;
|
||||
// TX_size_now[31:0] <= 32'h0000_0000;
|
||||
// end else if (TX_Start_one)begin
|
||||
// TX_addr_now[31:0] <= TX_Addr[31:0];
|
||||
// TX_size_now[31:0] <= TX_Size[31:0];
|
||||
// end else if (update_TX_now)begin
|
||||
// TX_addr_now[31:0] <= TX_addr_next[31:0];
|
||||
// TX_size_now[31:0] <= TX_size_next[31:0];
|
||||
// end else begin
|
||||
// TX_addr_now[31:0] <= TX_addr_now[31:0];
|
||||
// TX_size_now[31:0] <= TX_size_now[31:0];
|
||||
// end
|
||||
// end
|
||||
//
|
||||
// /// generate next_TX_ready
|
||||
// always@(posedge clk)begin
|
||||
// if(rst)
|
||||
// next_TX_ready <= 1'b0;
|
||||
// else if (update_TX_now)
|
||||
// next_TX_ready <= 1'b1;
|
||||
// else if (TX_calc_next)
|
||||
// next_TX_ready <= 1'b0;
|
||||
// else
|
||||
// next_TX_ready <= next_TX_ready;
|
||||
// end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,154 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 06/01/2009
|
||||
// Design Name:
|
||||
// Module Name: completer_pkt_gen
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose: Completer Packet Generator module. This block creates the header
|
||||
// info for completer packets- it also passes along the data source and
|
||||
// address info for the TRN state machine block to request the data from
|
||||
// the egress data presenter.
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module completer_pkt_gen(
|
||||
input clk,
|
||||
input rst,
|
||||
//interface from RX Engine
|
||||
input [6:0] bar_hit, //denotes which base address was hit
|
||||
input comp_req, //gets asserted when the rx engine recevies a MemRd request
|
||||
input [31:0] MEM_addr, //needed to fetch data from egress_data_presenter
|
||||
input [15:0] MEM_req_id,//needed for completion header
|
||||
input [15:0] comp_id, //needed for completion header
|
||||
input [7:0] MEM_tag, //neede for completion header
|
||||
//interface to completion header fifo
|
||||
output reg comp_fifo_wren,
|
||||
output reg [63:0] comp_fifo_data
|
||||
);
|
||||
|
||||
|
||||
//State machine states
|
||||
localparam IDLE = 4'h0;
|
||||
localparam HEAD1 = 4'h1;
|
||||
localparam HEAD2 = 4'h2;
|
||||
|
||||
//parameters used to define fixed header fields
|
||||
localparam rsvd = 1'b0;
|
||||
localparam fmt = 2'b10; //always with data
|
||||
localparam CplD = 5'b01010; //completer
|
||||
localparam TC = 3'b000;
|
||||
localparam TD = 1'b0;
|
||||
localparam EP = 1'b0;
|
||||
localparam ATTR = 2'b00;
|
||||
localparam Length = 10'b0000000001; //length is always one DWORD
|
||||
localparam ByteCount = 12'b000000000100; //BC is always one DWORD
|
||||
localparam BCM = 1'b0;
|
||||
|
||||
reg [3:0] state;
|
||||
reg [6:0] bar_hit_reg;
|
||||
reg [26:0] MEM_addr_reg;
|
||||
reg [15:0] MEM_req_id_reg;
|
||||
reg [15:0] comp_id_reg;
|
||||
reg [7:0] MEM_tag_reg;
|
||||
|
||||
reg rst_reg;
|
||||
always@(posedge clk) rst_reg <= rst;
|
||||
|
||||
//if there is a memory read request then latch the header information
|
||||
//needed to create the completion TLP header
|
||||
always@(posedge clk)begin
|
||||
if(comp_req)begin
|
||||
bar_hit_reg <= bar_hit;
|
||||
MEM_addr_reg[26:0] <= MEM_addr[26:0];
|
||||
MEM_req_id_reg <= MEM_req_id;
|
||||
comp_id_reg <= comp_id;
|
||||
MEM_tag_reg <= MEM_tag;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// State machine
|
||||
// Builds headers for completion TLP headers
|
||||
// Writes them into a FIFO
|
||||
always @ (posedge clk) begin
|
||||
if (rst_reg) begin
|
||||
comp_fifo_data <= 0;
|
||||
comp_fifo_wren <= 1'b0;
|
||||
state <= IDLE;
|
||||
end else begin
|
||||
case (state)
|
||||
IDLE : begin
|
||||
comp_fifo_data <= 0;
|
||||
comp_fifo_wren <= 1'b0;
|
||||
if(comp_req)
|
||||
state<= HEAD1;
|
||||
else
|
||||
state<= IDLE;
|
||||
end
|
||||
HEAD1 : begin //create first 64-bit completion TLP header
|
||||
//NOTE: bar_hit_reg[6:0],MEM_addr_reg[26:2] are not part of completion TLP
|
||||
//header but are used by tx_trn_sm module to fetch data from the
|
||||
//egress_data_presenter
|
||||
comp_fifo_data <= {bar_hit_reg[6:0],MEM_addr_reg[26:2],
|
||||
rsvd,fmt,CplD,rsvd,TC,rsvd,rsvd,rsvd,rsvd,
|
||||
TD,EP,ATTR,rsvd,rsvd,Length};
|
||||
|
||||
comp_fifo_wren <= 1'b1; //write to comp header fifo
|
||||
state <= HEAD2;
|
||||
end
|
||||
HEAD2 : begin //create second 64-bit completion TLP header
|
||||
comp_fifo_data <= {comp_id_reg[15:0],3'b000, BCM,ByteCount,
|
||||
MEM_req_id_reg[15:0],MEM_tag_reg[7:0],rsvd,
|
||||
MEM_addr_reg[6:0]};
|
||||
comp_fifo_wren <= 1'b1; //write to comp header fifo
|
||||
state <= IDLE;
|
||||
end
|
||||
default : begin
|
||||
comp_fifo_data <= 0;
|
||||
comp_fifo_wren <= 1'b0;
|
||||
state <= IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,154 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 06/01/2009
|
||||
// Design Name:
|
||||
// Module Name: tx_engine
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose: Contains 25 ms timers for each outstanding read request. If any
|
||||
// timer reaches 0 than completion timeout is signalled.
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module completion_timeout(
|
||||
input clk,
|
||||
input rst,
|
||||
input [31:0] pending_req,
|
||||
output reg comp_timeout
|
||||
);
|
||||
|
||||
`ifdef ML505
|
||||
reg [15:0] count;
|
||||
`else
|
||||
reg [17:0] count; //free running counter creates 1.048576 ms timer
|
||||
`endif
|
||||
|
||||
wire [31:0] pending_req_rise;
|
||||
wire [31:0] pending_req_fall;
|
||||
reg [31:0] shift_in = 0;
|
||||
reg [4:0] reset_count[31:0];
|
||||
wire [31:0] srl_reset;
|
||||
wire [31:0] comp_timeout_vector;
|
||||
reg [31:0] comp_timeout_vector_d1;
|
||||
wire comp_timeout_or;
|
||||
wire comp_timeout_one;
|
||||
reg comp_timeout_d1;
|
||||
|
||||
always@(posedge clk)begin
|
||||
if(rst)
|
||||
count <= 0;
|
||||
else
|
||||
count <= count + 1;
|
||||
end
|
||||
|
||||
//timer is asserted every 1.045876 ms
|
||||
assign timer = (count == 0) ? 1'b1 : 1'b0;
|
||||
|
||||
//create 32 shift register instances and associated logic
|
||||
genvar i;
|
||||
generate
|
||||
for(i=0;i<32;i=i+1)begin: replicate
|
||||
edge_detect edge_detect_inst(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.in(pending_req[i]),
|
||||
.rise_out(pending_req_rise[i]),
|
||||
.fall_out(pending_req_fall[i])
|
||||
);
|
||||
|
||||
//pending req logic
|
||||
//create a signal that sets when pending req is high and resets
|
||||
//timer pulses. Pending req gets priority over timer if both
|
||||
//signals occur simultaneously
|
||||
always@(posedge clk)begin
|
||||
if(pending_req_rise[i]) //set latch
|
||||
shift_in[i] <= 1'b1;
|
||||
else if(timer || pending_req_fall[i]) //reset latch
|
||||
shift_in[i] <= 1'b0;
|
||||
end
|
||||
|
||||
always@(posedge clk)begin
|
||||
if(rst)
|
||||
reset_count[i][4:0] <= 5'b00000;
|
||||
else if (pending_req_fall[i] == 1'b1)
|
||||
reset_count[i][4:0] <= 5'b11001;
|
||||
else if (reset_count[i][4:0] == 5'b00000)
|
||||
reset_count[i][4:0] <= 5'b00000;
|
||||
else
|
||||
reset_count[i][4:0] <= reset_count[i][4:0] - 1;
|
||||
end
|
||||
assign srl_reset[i] = | reset_count[i][4:0];
|
||||
|
||||
|
||||
|
||||
SRLC32E #(
|
||||
.INIT(32'h00000000)
|
||||
) SRLC32E_inst (
|
||||
.Q(comp_timeout_vector[i]), // SRL data output
|
||||
.Q31(), // SRL cascade output pin
|
||||
.A(5'b11000), // 5-bit shift depth select input
|
||||
.CE((srl_reset[i]) ? srl_reset[i] : timer), // Clock enable input
|
||||
.CLK(clk), // Clock input
|
||||
.D((srl_reset[i]) ? ~srl_reset[i] : shift_in[i]) // SRL data input
|
||||
);
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always@(posedge clk)begin
|
||||
comp_timeout_vector_d1[31:0] <= comp_timeout_vector[31:0];
|
||||
end
|
||||
|
||||
assign comp_timeout_or = |comp_timeout_vector_d1[31:0];
|
||||
|
||||
|
||||
rising_edge_detect comp_timeout_one_inst(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.in(comp_timeout_or),
|
||||
.one_shot_out(comp_timeout_one)
|
||||
);
|
||||
|
||||
always@(posedge clk)begin
|
||||
comp_timeout_d1 <= comp_timeout_one;
|
||||
comp_timeout <= comp_timeout_d1;
|
||||
end
|
||||
|
||||
endmodule
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,74 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 06/01/2009
|
||||
// Design Name:
|
||||
// Module Name: tx_engine
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose: Detects rising and falling edge of input signal and outputs a
|
||||
// single-cycle signal upon detection
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module edge_detect(
|
||||
input clk,
|
||||
input rst,
|
||||
input in,
|
||||
output rise_out, //single-shot output
|
||||
output fall_out); //single-shot output
|
||||
|
||||
reg in_reg;
|
||||
|
||||
//one pipeline reg for the input signal
|
||||
always@(posedge clk)begin
|
||||
if(rst)begin
|
||||
in_reg <= 1'b0;
|
||||
end else begin
|
||||
in_reg <= in;
|
||||
end
|
||||
end
|
||||
|
||||
//detect the rising edge
|
||||
assign rise_out = ~in_reg & in;
|
||||
|
||||
//detect the falling edge
|
||||
assign fall_out = in_reg & ~in;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,442 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// ?2007-2008 Xilinx, Inc. All Rights Reserved.
|
||||
// Confidential and proprietary information of Xilinx, Inc.
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 06/01/2009
|
||||
// Design Name:
|
||||
// Module Name: firmware_ctrl_wrapper
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose: DMA Control and Status Register File wrapper.
|
||||
// Connects the internal_dma_ctrl (which allows transfers
|
||||
// sizes up to 4KB), to the dma_ctrl_status_reg_file module (which
|
||||
// increases the transfer size by queueing mulitple smaller
|
||||
// transfers).
|
||||
// If the user does not require transfer sizes larger than 4KB,
|
||||
// or wishes to control large transfer sizes through software,
|
||||
// the dma_ctrl_status_reg_file module may be removed.
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
// Jiansong:
|
||||
// TX flow control: implemented in dma control wrapper (register file)
|
||||
// (1) control signal: TX_fetch_next_4k, one cycle
|
||||
// it's the falling edge of egress_data_fifo almost full
|
||||
// egress_data_fifo almostfull is slightly less than half of the FIFO size
|
||||
// (2) TX has higher priority than transfer, or mrd > mwr
|
||||
//
|
||||
// modified by zjs:
|
||||
// (1) init TX desciptor request --------------------------- done
|
||||
// (2) dma read after TX descriptor ------------------------ done
|
||||
// (3) dma write TX descriptor after dma read -------------- done
|
||||
// (4) remove previous dma write logic --------------------- done
|
||||
// (5) control on RX path ---------------------------------- done
|
||||
// (5) register read
|
||||
// (6) register write
|
||||
// register write width, from 7 bits to 12 bits -------- done
|
||||
// (7) TX start (divide into small blocks) ----------------- done
|
||||
// (8) TX done --------------------------------------------- done
|
||||
// (9) radio registers
|
||||
// (10) relax 1MB dma read size limitation to 4GB ---------- done
|
||||
//
|
||||
// (11) transfer recovering:
|
||||
// If RCB is not mounted to PC stably, some PCIe packets may be lost on PCIe
|
||||
// physical layer. In this case, transfer (dma read) may dead-lock at a waiting
|
||||
// for packet state. Transfer recovering is to recover from this state. In this
|
||||
// design, mechanism of transfer recovering is aggressive, that if tranferstart
|
||||
// bit in transfercontrol register is deasserted, (1) all dma read related state
|
||||
// machine will return to IDLE state, (2) all calculation in dma_ctrl_wrapper,
|
||||
// rx trn monitor and nonposted_pkt_gen will be cleared to zero, (3) read_req_wrapper
|
||||
// will be cleared, all WRs will be bypassed, (4) pkt already in non_posted_header_fifo
|
||||
// will still be sent out, completer received in rx_engine will still be write
|
||||
// in to ddr. THIS MECHANISM REQUIRES DRIVER DELAY SEVERAL MICROSECONDS BETWEEN
|
||||
// TRANSFERSTART'S DEASSERTING AND ASSERTING, TO WAIT FOR ALL THE PENDING COMPLETERS
|
||||
// PROCESSED.
|
||||
//
|
||||
// (12) performance counter
|
||||
// measure two durations: (1) from TX_des request sent to tx_engine to new des
|
||||
// received (2) from transfer start to transfer done.
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
`include "Sora_config.v"
|
||||
|
||||
module firmware_ctrl_wrapper(
|
||||
input clk,
|
||||
// input hard_rst,
|
||||
input rst,
|
||||
// hot reset to whole system
|
||||
output hostreset,
|
||||
|
||||
output [4:0] DDR2MaxBurstSize,
|
||||
|
||||
/// Jiansong: interface to radio module
|
||||
// input Radio_TX_done,
|
||||
// output Radio_TX_start,
|
||||
output TX_Ongoing_o,
|
||||
|
||||
output TX_Start_one_o,
|
||||
output [31:0] TX_Addr,
|
||||
output [31:0] TX_Size,
|
||||
output TX_Start_2nd_one_o,
|
||||
output [31:0] TX_Addr_2nd,
|
||||
output [31:0] TX_Size_2nd,
|
||||
`ifdef MIMO_4X4
|
||||
output TX_Start_3rd_one_o,
|
||||
output [31:0] TX_Addr_3rd,
|
||||
output [31:0] TX_Size_3rd,
|
||||
output TX_Start_4th_one_o,
|
||||
output [31:0] TX_Addr_4th,
|
||||
output [31:0] TX_Size_4th,
|
||||
`endif //MIMO_4X4
|
||||
//interface from RX Engine
|
||||
input [31:0] reg_data_in,
|
||||
//// input [6:0] reg_wr_addr,
|
||||
input [11:0] reg_wr_addr,
|
||||
input reg_wren,
|
||||
///Jiansong: interface from RX engine, TX desc recived
|
||||
input new_des_one,
|
||||
input [31:0] SourceAddr_L,
|
||||
input [31:0] SourceAddr_H,
|
||||
input [31:0] DestAddr,
|
||||
input [23:0] FrameSize,
|
||||
input [7:0] FrameControl,
|
||||
///Jiansong: interface to RX engine, indicate the system is in dma read for TX desc
|
||||
/// when this signal is asserted, received cpld will not be count in
|
||||
/// length subtraction
|
||||
output Wait_for_TX_desc,
|
||||
output transferstart_o,
|
||||
output transferstart_one,
|
||||
input set_transfer_done_bit,
|
||||
output [63:0] TransferSrcAddr,
|
||||
/// Jiansong: interface to/from tx engine
|
||||
input [11:0] reg_rd_addr,
|
||||
output [31:0] reg_data_out,
|
||||
//interface to TX Engine
|
||||
output [63:0] dmaras,
|
||||
output [31:0] dmarad,
|
||||
output [31:0] dmarxs,
|
||||
output read_last,
|
||||
output rd_dma_start,
|
||||
input rd_dma_done, //from RX Engine
|
||||
|
||||
/// Jiansong: interface to/from posted_packet_generator
|
||||
/// TX desc write back
|
||||
output TX_desc_write_back_req,
|
||||
input TX_desc_write_back_ack,
|
||||
output [63:0] SourceAddr_r,
|
||||
output [31:0] DestAddr_r,
|
||||
output [23:0] FrameSize_r,
|
||||
output [7:0] FrameControl_r,
|
||||
output [63:0] DescAddr_r,
|
||||
/// Jiansong: RX path
|
||||
output RXEnable,
|
||||
output [63:0] RXBufAddr,
|
||||
output [31:0] RXBufSize,
|
||||
output RXEnable_2nd,
|
||||
output [63:0] RXBufAddr_2nd,
|
||||
output [31:0] RXBufSize_2nd,
|
||||
`ifdef MIMO_4X4
|
||||
output RXEnable_3rd,
|
||||
output [63:0] RXBufAddr_3rd,
|
||||
output [31:0] RXBufSize_3rd,
|
||||
output RXEnable_4th,
|
||||
output [63:0] RXBufAddr_4th,
|
||||
output [31:0] RXBufSize_4th,
|
||||
`endif //MIMO_4X4
|
||||
|
||||
/// Jiansong: error inputs
|
||||
input egress_overflow_one,
|
||||
input RX_FIFO_full,
|
||||
input [31:0] egress_rd_data_count,
|
||||
input [31:0] egress_wr_data_count,
|
||||
|
||||
//interface from performance counters
|
||||
// input [31:0] dma_wr_count,
|
||||
// input [31:0] dma_rd_count,
|
||||
//interface from memory controller
|
||||
input phy_init_done,
|
||||
// hardware status input
|
||||
input trn_lnk_up_n_c,
|
||||
//interface from dma_ddr2_if
|
||||
input pause_read_requests,
|
||||
|
||||
// radio related inputs/outputs
|
||||
`ifdef RADIO_CHANNEL_REGISTERS
|
||||
|
||||
output [31:0] Radio_Cmd_Data,
|
||||
output [6:0] Radio_Cmd_Addr,
|
||||
output Radio_Cmd_RdWr,
|
||||
output Radio_Cmd_wren,
|
||||
input [31:0] Channel_Reg_Read_Value,
|
||||
input [7:0] Channel_Reg_Read_Addr,
|
||||
input Channel_ReadDone_in,
|
||||
/// registers for 2nd to 4th paths/radios
|
||||
output [31:0] Radio_2nd_Cmd_Data,
|
||||
output [6:0] Radio_2nd_Cmd_Addr,
|
||||
output Radio_2nd_Cmd_RdWr,
|
||||
output Radio_2nd_Cmd_wren,
|
||||
input [31:0] Channel_2nd_Reg_Read_Value,
|
||||
input [7:0] Channel_2nd_Reg_Read_Addr,
|
||||
input Channel_2nd_ReadDone_in,
|
||||
`ifdef MIMO_4X4
|
||||
output [31:0] Radio_3rd_Cmd_Data,
|
||||
output [6:0] Radio_3rd_Cmd_Addr,
|
||||
output Radio_3rd_Cmd_RdWr,
|
||||
output Radio_3rd_Cmd_wren,
|
||||
input [31:0] Channel_3rd_Reg_Read_Value,
|
||||
input [7:0] Channel_3rd_Reg_Read_Addr,
|
||||
input Channel_3rd_ReadDone_in,
|
||||
output [31:0] Radio_4th_Cmd_Data,
|
||||
output [6:0] Radio_4th_Cmd_Addr,
|
||||
output Radio_4th_Cmd_RdWr,
|
||||
output Radio_4th_Cmd_wren,
|
||||
input [31:0] Channel_4th_Reg_Read_Value,
|
||||
input [7:0] Channel_4th_Reg_Read_Addr,
|
||||
input Channel_4th_ReadDone_in,
|
||||
`endif //MIMO_4X4
|
||||
|
||||
`endif //RADIO_CHANNEL_REGISTERS
|
||||
// debug signals
|
||||
input [31:0] DebugRX1Overflowcount_in,
|
||||
input [31:0] DebugRX2Overflowcount_in,
|
||||
|
||||
input [31:0] DebugDDREgressFIFOCnt,
|
||||
input [31:0] DebugDDRFIFOFullCnt,
|
||||
input [31:0] DebugDDRSignals,
|
||||
input [8:0] DebugDDRSMs,
|
||||
|
||||
input [15:0] PCIeLinkStatus_in,
|
||||
input [15:0] PCIeLinkControl_in
|
||||
// input [31:0] Debug18DDR1_in,
|
||||
// input [31:0] Debug19DDR2_in,
|
||||
// input [31:0] Debug20RX1_in,
|
||||
// input [31:0] Debug21RX2_in,
|
||||
//// input [4:0] Debug22RX3_in,
|
||||
// input [31:0] Debug23RX4_in,
|
||||
// input [31:0] Debug24RX5_in,
|
||||
// input [31:0] Debug25RX6_in,
|
||||
// input [31:0] Debug26RX7_in,
|
||||
// input [31:0] Debug27RX8_in,
|
||||
// input [31:0] Debug28RX9_in,
|
||||
// input [31:0] Debug29RX10_in,
|
||||
// input [9:0] Debug30RXEngine_in,
|
||||
// input [11:0] Debug31RXDataFIFOfullcnt_in,
|
||||
// input [11:0] Debug32RXXferFIFOfullcnt_in,
|
||||
// input [23:0] Debug33RXDataFIFOWRcnt_in,
|
||||
// input [23:0] Debug34RXDataFIFORDcnt_in,
|
||||
// input [23:0] Debug35RXXferFIFOWRcnt_in,
|
||||
// input [23:0] Debug36RXXferFIFORDcnt_in,
|
||||
// input [31:0] Debug37completion_pending_in,
|
||||
// input [4:0] Debug38tag_value_in,
|
||||
// input [7:0] FIFOErrors_in,
|
||||
// input [4:0] locked_debug
|
||||
);
|
||||
|
||||
|
||||
// internal signal for performance counter
|
||||
// wire transferstart_one; // one cycle signal valid when transferstart bit is set by driver
|
||||
wire [23:0] round_trip_latency; /// 24 bits performance value
|
||||
wire [23:0] transfer_duration; /// 24 bits performance value
|
||||
|
||||
// performance counter
|
||||
performance_counter performance_counter_inst (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.transferstart_one (transferstart_one),
|
||||
.rd_dma_done_one (rd_dma_done),
|
||||
.new_des_one (new_des_one),
|
||||
.round_trip_latency (round_trip_latency),
|
||||
.transfer_duration (transfer_duration)
|
||||
);
|
||||
|
||||
// Instantiate the DMA Control and Status Register File logic
|
||||
// This module interfaces with the
|
||||
// dma_ctrl_status_reg_file dma_ctrl_status_reg_file_inst (
|
||||
register_table register_table_inst (
|
||||
|
||||
.clk(clk),
|
||||
// .hard_rst(hard_rst),
|
||||
.rst(rst),
|
||||
// hot reset to whole system
|
||||
.hostreset(hostreset),
|
||||
|
||||
.DDR2MaxBurstSize(DDR2MaxBurstSize[4:0]),
|
||||
|
||||
/// Jiansong: performance value input
|
||||
.round_trip_latency_i(round_trip_latency), /// 24 bits performance value
|
||||
.transfer_duration_i(transfer_duration), /// 24 bits performance value
|
||||
|
||||
/// Jiansong: interface to radio module
|
||||
// .Radio_TX_done(Radio_TX_done),
|
||||
// .Radio_TX_start(Radio_TX_start),
|
||||
.TX_Ongoing_o(TX_Ongoing_o),
|
||||
|
||||
.TX_Start_one_o (TX_Start_one_o),
|
||||
.TX_Addr (TX_Addr[31:0]),
|
||||
.TX_Size (TX_Size[31:0]),
|
||||
.TX_Start_2nd_one_o (TX_Start_2nd_one_o),
|
||||
.TX_Addr_2nd (TX_Addr_2nd[31:0]),
|
||||
.TX_Size_2nd (TX_Size_2nd[31:0]),
|
||||
`ifdef MIMO_4X4
|
||||
.TX_Start_3rd_one_o (TX_Start_3rd_one_o),
|
||||
.TX_Addr_3rd (TX_Addr_3rd[31:0]),
|
||||
.TX_Size_3rd (TX_Size_3rd[31:0]),
|
||||
.TX_Start_4th_one_o (TX_Start_4th_one_o),
|
||||
.TX_Addr_4th (TX_Addr_4th[31:0]),
|
||||
.TX_Size_4th (TX_Size_4th[31:0]),
|
||||
`endif //MIMO_4X4
|
||||
|
||||
//interface from RX Engine
|
||||
.reg_data_in(reg_data_in[31:0]),
|
||||
//// .reg_wr_addr(reg_wr_addr[6:0]),
|
||||
.reg_wr_addr(reg_wr_addr[11:0]),
|
||||
.reg_wren(reg_wren),
|
||||
|
||||
.transferstart_o (transferstart_o),
|
||||
.transferstart_one (transferstart_one),
|
||||
.set_transfer_done_bit (set_transfer_done_bit),
|
||||
.TransferSrcAddr (TransferSrcAddr[63:0]),
|
||||
|
||||
/// Jiansong: RX path
|
||||
.RXEnable_o (RXEnable),
|
||||
.RXBufAddr_o (RXBufAddr),
|
||||
.RXBufSize_o (RXBufSize),
|
||||
.RXEnable_2nd_o (RXEnable_2nd),
|
||||
.RXBufAddr_2nd_o (RXBufAddr_2nd),
|
||||
.RXBufSize_2nd_o (RXBufSize_2nd),
|
||||
`ifdef MIMO_4X4
|
||||
.RXEnable_3rd_o (RXEnable_3rd),
|
||||
.RXBufAddr_3rd_o (RXBufAddr_3rd),
|
||||
.RXBufSize_3rd_o (RXBufSize_3rd),
|
||||
.RXEnable_4th_o (RXEnable_4th),
|
||||
.RXBufAddr_4th_o (RXBufAddr_4th),
|
||||
.RXBufSize_4th_o (RXBufSize_4th),
|
||||
`endif //MIMO_4X4
|
||||
|
||||
//register read interface
|
||||
.reg_rd_addr(reg_rd_addr[11:0]),
|
||||
.reg_data_out(reg_data_out[31:0]),
|
||||
|
||||
/// Jiansong: error inputs
|
||||
.egress_overflow_one(egress_overflow_one),
|
||||
.RX_FIFO_full(RX_FIFO_full),
|
||||
.egress_rd_data_count(egress_rd_data_count),
|
||||
.egress_wr_data_count(egress_wr_data_count),
|
||||
.pause_read_requests(pause_read_requests),
|
||||
|
||||
//interface to/from Perfomance Counter modules
|
||||
// .dma_wr_count(dma_wr_count),
|
||||
// .dma_rd_count(dma_rd_count),
|
||||
|
||||
//interface from memory controller
|
||||
.phy_init_done(phy_init_done),
|
||||
//hardware status input
|
||||
.trn_lnk_up_n_c(trn_lnk_up_n_c),
|
||||
|
||||
// radio related inputs/outputs
|
||||
`ifdef RADIO_CHANNEL_REGISTERS
|
||||
|
||||
.Radio_Cmd_Data (Radio_Cmd_Data[31:0]),
|
||||
.Radio_Cmd_Addr (Radio_Cmd_Addr[6:0]),
|
||||
.Radio_Cmd_RdWr (Radio_Cmd_RdWr),
|
||||
.Radio_Cmd_wren (Radio_Cmd_wren),
|
||||
.RadioRegRead_Value_in (Channel_Reg_Read_Value[31:0]),
|
||||
.RadioRegRead_Addr_in (Channel_Reg_Read_Addr[7:0]),
|
||||
.RadioReg_ReadDone_in (Channel_ReadDone_in),
|
||||
/// registers for 2nd to 4th paths/radios
|
||||
.Radio_2nd_Cmd_Data (Radio_2nd_Cmd_Data[31:0]),
|
||||
.Radio_2nd_Cmd_Addr (Radio_2nd_Cmd_Addr[6:0]),
|
||||
.Radio_2nd_Cmd_RdWr (Radio_2nd_Cmd_RdWr),
|
||||
.Radio_2nd_Cmd_wren (Radio_2nd_Cmd_wren),
|
||||
.RadioRegRead_2nd_Value_in (Channel_2nd_Reg_Read_Value[31:0]),
|
||||
.RadioRegRead_2nd_Addr_in (Channel_2nd_Reg_Read_Addr[7:0]),
|
||||
.RadioReg_2nd_ReadDone_in (Channel_2nd_ReadDone_in),
|
||||
`ifdef MIMO_4X4
|
||||
.Radio_3rd_Cmd_Data (Radio_3rd_Cmd_Data[31:0]),
|
||||
.Radio_3rd_Cmd_Addr (Radio_3rd_Cmd_Addr[6:0]),
|
||||
.Radio_3rd_Cmd_RdWr (Radio_3rd_Cmd_RdWr),
|
||||
.Radio_3rd_Cmd_wren (Radio_3rd_Cmd_wren),
|
||||
.RadioRegRead_3rd_Value_in (Channel_3rd_Reg_Read_Value[31:0]),
|
||||
.RadioRegRead_3rd_Addr_in (Channel_3rd_Reg_Read_Addr[7:0]),
|
||||
.RadioReg_3rd_ReadDone_in (Channel_3rd_ReadDone_in),
|
||||
.Radio_4th_Cmd_Data (Radio_4th_Cmd_Data[31:0]),
|
||||
.Radio_4th_Cmd_Addr (Radio_4th_Cmd_Addr[6:0]),
|
||||
.Radio_4th_Cmd_RdWr (Radio_4th_Cmd_RdWr),
|
||||
.Radio_4th_Cmd_wren (Radio_4th_Cmd_wren),
|
||||
.RadioRegRead_4th_Value_in (Channel_4th_Reg_Read_Value[31:0]),
|
||||
.RadioRegRead_4th_Addr_in (Channel_4th_Reg_Read_Addr[7:0]),
|
||||
.RadioReg_4th_ReadDone_in (Channel_4th_ReadDone_in),
|
||||
`endif //MIMO_4X4
|
||||
|
||||
`endif //RADIO_CHANNEL_REGISTERS
|
||||
.DebugRX1Overflowcount_in (DebugRX1Overflowcount_in),
|
||||
.DebugRX2Overflowcount_in (DebugRX2Overflowcount_in),
|
||||
.PCIeLinkStatus_in(PCIeLinkStatus_in),
|
||||
.PCIeLinkControl_in(PCIeLinkControl_in),
|
||||
|
||||
.DebugDDREgressFIFOCnt_in (DebugDDREgressFIFOCnt[31:0]),
|
||||
.DebugDDRFIFOFullCnt_in (DebugDDRFIFOFullCnt[31:0]),
|
||||
.DebugDDRSignals_in (DebugDDRSignals[31:0]),
|
||||
.DebugDDRSMs_in (DebugDDRSMs[8:0])
|
||||
// debug inputs
|
||||
// .Debug18DDR1_in(Debug18DDR1_in),
|
||||
// .Debug19DDR2_in(Debug19DDR2_in),
|
||||
// .Debug20RX1_in(Debug20RX1_in),
|
||||
// .Debug21RX2_in(Debug21RX2_in),
|
||||
//// .Debug22RX3_in(Debug22RX3_in),
|
||||
// .Debug23RX4_in(Debug23RX4_in),
|
||||
// .Debug24RX5_in(Debug24RX5_in),
|
||||
// .Debug25RX6_in(Debug25RX6_in),
|
||||
// .Debug26RX7_in(Debug26RX7_in),
|
||||
// .Debug27RX8_in(Debug27RX8_in),
|
||||
// .Debug28RX9_in(Debug28RX9_in),
|
||||
// .Debug29RX10_in(Debug29RX10_in),
|
||||
// .Debug30RXEngine_in(Debug30RXEngine_in),
|
||||
// .Debug31RXDataFIFOfullcnt_in(Debug31RXDataFIFOfullcnt_in),
|
||||
// .Debug32RXXferFIFOfullcnt_in(Debug32RXXferFIFOfullcnt_in),
|
||||
// .Debug33RXDataFIFOWRcnt_in(Debug33RXDataFIFOWRcnt_in),
|
||||
// .Debug34RXDataFIFORDcnt_in(Debug34RXDataFIFORDcnt_in),
|
||||
// .Debug35RXXferFIFOWRcnt_in(Debug35RXXferFIFOWRcnt_in),
|
||||
// .Debug36RXXferFIFORDcnt_in(Debug36RXXferFIFORDcnt_in),
|
||||
// .Debug37completion_pending_in(Debug37completion_pending_in),
|
||||
// .Debug38tag_value_in(Debug38tag_value_in),
|
||||
// .FIFOErrors_in(FIFOErrors_in),
|
||||
// .locked_debug(locked_debug)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,191 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 06/01/2009
|
||||
// Design Name:
|
||||
// Module Name: tx_engine
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose: Internal DMA Control and status register file for PCIE-DDR2 DMA
|
||||
// design. This register file should only be used for dma transfers
|
||||
// up to 4KB in size.
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module internal_dma_ctrl
|
||||
(
|
||||
input clk,
|
||||
input rst,
|
||||
//interface from dma_ctrl_status_reg file;
|
||||
//these inputs could also be directly driven from the host system if desired
|
||||
//in which case the dma_ctrl_status_reg_file block should be removed from the
|
||||
//design
|
||||
input [31:0] reg_data_in,
|
||||
input [6:0] reg_wr_addr,
|
||||
input [6:0] reg_rd_addr,
|
||||
input reg_wren,
|
||||
output reg [31:0] reg_data_out, //reg_data_out is never used
|
||||
|
||||
//DMA parameter control outputs to TX and RX engines
|
||||
output [63:0] dmaras, //Read address source (from host memory)
|
||||
output reg [31:0] dmarad, //Read address destination (to backend memory)
|
||||
output reg [31:0] dmarxs, //Read transfer size in bytes
|
||||
|
||||
output rd_dma_start, //read dma start control signal
|
||||
input rd_dma_done, //read dma done signal from RX engine
|
||||
|
||||
//Performance counts from performance counter module
|
||||
//Not used in this module because the copies in dma_ctrl_status_reg_file
|
||||
//are used instead
|
||||
input [31:0] dma_wr_count,
|
||||
input [31:0] dma_rd_count
|
||||
);
|
||||
|
||||
|
||||
reg [31:0] dmaras_l, dmaras_u;
|
||||
reg [31:0] dmacst;
|
||||
|
||||
//concatanate to form the 64 bit outputs
|
||||
assign dmaras[63:0] = {dmaras_u,dmaras_l};
|
||||
|
||||
////assign wr_dma_start = dmacst[0];
|
||||
assign rd_dma_start = dmacst[2];
|
||||
|
||||
|
||||
//block for writing into the regfile
|
||||
//--when reg_wren is asserted, reg_data_in will be written to one of the
|
||||
//registers as chosen by reg_wr_addr selection signal
|
||||
always@(posedge clk or posedge rst) begin
|
||||
if(rst) begin
|
||||
dmaras_l <= 0;
|
||||
dmaras_u <= 0;
|
||||
dmarad <= 0;
|
||||
dmarxs <= 0;
|
||||
end else begin
|
||||
if(reg_wren) begin
|
||||
case(reg_wr_addr)
|
||||
7'b000_1100: dmaras_l <= reg_data_in; //0x0C
|
||||
7'b001_0000: dmaras_u <= reg_data_in; //0x10
|
||||
7'b001_0100: dmarad <= reg_data_in; //0x14
|
||||
7'b001_1100: dmarxs <= reg_data_in; //0x1C
|
||||
default: begin
|
||||
dmaras_l <= dmaras_l;
|
||||
dmaras_u <= dmaras_u;
|
||||
dmarad <= dmarad;
|
||||
dmarxs <= dmarxs;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//use a separate always block for dmacst[3:2] for clarity
|
||||
//dmacst[2] == rd_dma_start; host sets this bit to start a dma transfer
|
||||
// it is automatically cleared when the
|
||||
// dma transfer completes
|
||||
//dmacst[3] == rd_dma_done; asserted when the dma transfer is finished
|
||||
// this bit can be polled by the host or it could
|
||||
// be used to drive hardware block to generate
|
||||
// an interrupt
|
||||
// this bit must be cleared by the host by
|
||||
// writing a "1" to it.
|
||||
always@(posedge clk) begin
|
||||
if(rst) begin
|
||||
dmacst[3:2] <= 2'b00;
|
||||
end else begin
|
||||
if(rd_dma_done) begin //rd_dma_done from RX Engine
|
||||
dmacst[2] <= 1'b0;
|
||||
dmacst[3] <= 1'b1;
|
||||
end else if(reg_wren) begin
|
||||
case(reg_wr_addr)
|
||||
7'b010_1000: begin //0x28
|
||||
/// Jiansong:
|
||||
//take care of the unused bits in this always
|
||||
//block
|
||||
dmacst[31:4] <= reg_data_in[31:4];
|
||||
dmacst[1:0] <= reg_data_in[1:0];
|
||||
//set the start bit if the host writes a 1
|
||||
//the host cannot clear this bit
|
||||
if(reg_data_in[2])
|
||||
dmacst[2] <= 1'b1;
|
||||
else
|
||||
dmacst[2] <= dmacst[2];
|
||||
|
||||
//clear the done bit if the host writes a 1
|
||||
//the host cannot set this bit
|
||||
if(reg_data_in[3])
|
||||
dmacst[3] <= 1'b0;
|
||||
else
|
||||
dmacst[3] <= dmacst[3];
|
||||
end
|
||||
default: begin
|
||||
dmacst[3:2] <= dmacst[3:2];
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// output register for cpu
|
||||
// this is a read of the reg_file
|
||||
// the case stmt is a mux which selects which reg location
|
||||
// makes it to the output data bus
|
||||
// Not used in this design
|
||||
|
||||
always@(posedge clk or posedge rst )
|
||||
begin
|
||||
if(rst)
|
||||
begin
|
||||
reg_data_out <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
case(reg_rd_addr[6:0])
|
||||
7'b000_1100: reg_data_out <= dmaras_l;
|
||||
7'b001_0000: reg_data_out <= dmaras_u;
|
||||
7'b001_0100: reg_data_out <= dmarad;
|
||||
7'b001_1100: reg_data_out <= dmarxs;
|
||||
7'b010_1000: reg_data_out <= dmacst;
|
||||
7'b011_0000: reg_data_out <= dma_wr_count;
|
||||
7'b011_0100: reg_data_out <= dma_rd_count;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,225 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 06/01/2009
|
||||
// Design Name:
|
||||
// Module Name: tx_engine
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose: Non-Posted Packet Builder module. This module takes the
|
||||
// length info from the Non-Posted Packet Slicer, and requests a tag from
|
||||
// the Tag Generator and uses that info to build a non-posted memory read
|
||||
// header which it writes into a FIFO
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
// modified by zjs:
|
||||
// tag content modified: from {length[9:0], addr[21:0]} to {isDes, 8'h000, addr[21:0]}
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module non_posted_pkt_builder(
|
||||
input clk,
|
||||
input rst,
|
||||
input [15:0] req_id, //from pcie block
|
||||
//to/from the non_posted_pkt_slicer
|
||||
input go,
|
||||
output reg ack,
|
||||
input [63:0] dmaras,
|
||||
input [31:0] dmarad,
|
||||
input [9:0] length,
|
||||
/// Jiansong: added for TX des request
|
||||
input isDes,
|
||||
//to/from the tag_generator
|
||||
input [7:0] tag_value,
|
||||
input tag_gnt,
|
||||
output reg tag_inc,
|
||||
//to the non_posted_pkt_header_fifo
|
||||
output reg [63:0] header_data_out,
|
||||
output reg header_data_wren,
|
||||
//to the read_request_wrapper
|
||||
output reg [4:0] tx_waddr,
|
||||
output reg [31:0] tx_wdata,
|
||||
output reg tx_we
|
||||
);
|
||||
|
||||
//State machine states
|
||||
localparam IDLE = 4'h0;
|
||||
localparam HEAD1 = 4'h1;
|
||||
localparam HEAD2 = 4'h2;
|
||||
localparam WAIT_FOR_GO_DEASSERT = 4'h3;
|
||||
|
||||
//parameters used to define fixed header fields
|
||||
localparam rsvd = 1'b0; //reserved and unused header fields to zero
|
||||
localparam MRd = 5'b00000; //format for memory read header
|
||||
localparam TC = 3'b000; //traffic class 0
|
||||
localparam TD = 1'b0; //digest bit always 0
|
||||
localparam EP = 1'b0; //poisoned bit always 0
|
||||
//localparam ATTR = 2'b10;//enable relaxed ordering to allow completions to pass
|
||||
//for completion streaming mode
|
||||
localparam ATTR = 2'b00; //Jiansong: Maybe it's the cause of CPU memory read lock problem
|
||||
localparam LastBE = 4'b1111; //LastBE is always asserted since all transfers
|
||||
//are on 128B boundaries and are always at least
|
||||
//128B long
|
||||
localparam FirstBE = 4'b1111;//FirstBE is always asserted since all transfers
|
||||
//are on 128B boundaries
|
||||
|
||||
|
||||
wire [1:0] fmt;
|
||||
reg [3:0] state;
|
||||
reg [63:0] dmaras_reg;
|
||||
reg [31:0] dmarad_reg;
|
||||
|
||||
|
||||
reg rst_reg;
|
||||
always@(posedge clk) rst_reg <= rst;
|
||||
|
||||
|
||||
//if the upper DWord of the destination address is zero
|
||||
//than make the format of the packet header 3DW; otherwise 4DW
|
||||
assign fmt[1:0] = (dmaras_reg[63:32] == 0) ? 2'b00 : 2'b01;
|
||||
|
||||
//if the non_posted_pkt_slicer asserts "go" then register the dma read params
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)begin
|
||||
dmaras_reg[63:0] <= 0;
|
||||
end else if(go)begin
|
||||
dmaras_reg <= dmaras;
|
||||
end
|
||||
end
|
||||
|
||||
//dmarad is sent to the read_request_wrapper so that the RX engine knows
|
||||
//where to put the incoming completion data in the DDR2
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)begin
|
||||
dmarad_reg[31:0] <= 0;
|
||||
end else if(go)begin
|
||||
dmarad_reg <= dmarad;
|
||||
end
|
||||
end
|
||||
|
||||
// State machine
|
||||
// Builds headers for non-posted memory reads
|
||||
// Writes them into a FIFO
|
||||
always @ (posedge clk) begin
|
||||
if (rst_reg) begin
|
||||
header_data_out <= 0;
|
||||
header_data_wren <= 1'b0;
|
||||
ack <= 1'b0;
|
||||
tag_inc <=1'b0;
|
||||
tx_waddr[4:0] <= 0;
|
||||
tx_wdata[31:0] <= 0;
|
||||
tx_we <= 1'b0;
|
||||
state <= IDLE;
|
||||
end else begin
|
||||
case (state)
|
||||
IDLE : begin
|
||||
header_data_out <= 0;
|
||||
header_data_wren <= 1'b0;
|
||||
ack <= 1'b0;
|
||||
tag_inc <=1'b0;
|
||||
tx_waddr[4:0] <= 0;
|
||||
tx_wdata[31:0] <= 0;
|
||||
tx_we <= 1'b0;
|
||||
if(go)
|
||||
state<= HEAD1;
|
||||
else
|
||||
state<= IDLE;
|
||||
end
|
||||
HEAD1 : begin
|
||||
//wait for the tag_generator to grant a tag via tag_gnt and then
|
||||
//write the first 64-bits of a non-posted header into the
|
||||
//non-posted fifo
|
||||
header_data_out <= {rsvd,fmt[1:0],MRd,rsvd,TC,rsvd,rsvd,rsvd,rsvd,
|
||||
TD,EP,ATTR,rsvd,rsvd,length[9:0],req_id[15:0],
|
||||
tag_value[7:0],LastBE,FirstBE};
|
||||
ack <= 0;
|
||||
tag_inc <=1'b0;
|
||||
tx_waddr[4:0] <= 0;
|
||||
tx_wdata[31:0] <= 0;
|
||||
tx_we <= 1'b0;
|
||||
if(tag_gnt == 1'b0)begin
|
||||
state <= HEAD1;
|
||||
header_data_wren <= 1'b0;
|
||||
end else begin
|
||||
header_data_wren <= 1'b1;
|
||||
state <= HEAD2;
|
||||
end
|
||||
end
|
||||
HEAD2 : begin
|
||||
//write the next 32 or 64 bits of a non-posted header to the
|
||||
//non-posted header fifo (32 if 3DW - 64 if 4DW header)
|
||||
header_data_out <= (fmt[0]==1'b1)
|
||||
? {dmaras_reg[63:2],2'b00}
|
||||
: {dmaras_reg[31:2], 2'b00, dmaras_reg[63:32]};
|
||||
header_data_wren <= 1'b1;
|
||||
//also write needed information by the RX engine into the
|
||||
//Read Request Wrapper
|
||||
tx_waddr[4:0] <= tag_value[4:0];
|
||||
//// tx_wdata[31:0] <= {length[9:0],dmarad_reg[27:6]};
|
||||
tx_wdata[31:0] <= {isDes,9'b0_0000_0000,dmarad_reg[27:6]};
|
||||
tx_we <= 1'b1;
|
||||
ack <= 1'b1; //acknowledge to the non-posted_packet_slicer that
|
||||
//the packet has been queued up for transmission
|
||||
tag_inc <=1'b1;//only assert tag_inc once - the tag gets
|
||||
//incremented for every clock cycle that it is
|
||||
//asserted
|
||||
state <= WAIT_FOR_GO_DEASSERT;
|
||||
end
|
||||
WAIT_FOR_GO_DEASSERT : begin
|
||||
//ack causes "go" to deassert but we need to give the
|
||||
//non-posted_pkt_slicer a chance to deassert "go" before returning
|
||||
//to IDLE
|
||||
header_data_wren <= 1'b0;
|
||||
tx_we <= 1'b0;
|
||||
tag_inc <=1'b0;
|
||||
ack <= 1'b0;
|
||||
state <= IDLE;
|
||||
end
|
||||
default : begin
|
||||
header_data_out <= 0;
|
||||
header_data_wren <= 1'b0;
|
||||
ack <= 1'b0;
|
||||
tag_inc <=1'b0;
|
||||
tx_waddr[4:0] <= 0;
|
||||
tx_wdata[31:0] <= 0;
|
||||
tx_we <= 1'b0;
|
||||
state <= IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 06/01/2009
|
||||
// Design Name:
|
||||
// Module Name: Sora_RCB_top
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose: Non-Posted Packet Generator wrapper file.
|
||||
// Connects the NonPosted Packet Slicer and Non-Posted Packet Builder modules
|
||||
// together
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
// modified by Jiansong Zhang:
|
||||
// add logic for TX descriptor request ----------- done
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
`include "Sora_config.v"
|
||||
|
||||
module non_posted_pkt_gen(
|
||||
input clk,
|
||||
input rst,
|
||||
/// Jiansong: control signal for transfer recovering
|
||||
`ifdef TF_RECOVERY
|
||||
input transferstart,
|
||||
`endif
|
||||
//inputs from dma_ctrl_wrapper
|
||||
input [63:0] dmaras,
|
||||
input [31:0] dmarad,
|
||||
input [31:0] dmarxs,
|
||||
input rd_dma_start,
|
||||
/// Jiansong: added for TX descriptor request
|
||||
input rd_TX_des_start,
|
||||
input [63:0] TX_des_addr,
|
||||
//inputs from pcie block plus
|
||||
input [2:0] read_req_size,
|
||||
input [15:0] req_id,
|
||||
//outputs to non posted header fifo
|
||||
output non_posted_fifo_wren,
|
||||
output [63:0] non_posted_fifo_data,
|
||||
//in and outs to tag_generator
|
||||
output tag_inc,
|
||||
input tag_gnt,
|
||||
input [7:0] tag_value,
|
||||
//outputs to read_request_wrapper
|
||||
output [4:0] tx_waddr,
|
||||
output [31:0] tx_wdata,
|
||||
output tx_we
|
||||
);
|
||||
|
||||
//internal wrapper connections
|
||||
wire [31:0] dmarad_reg;
|
||||
wire [63:0] dmaras_reg;
|
||||
wire [9:0] length;
|
||||
wire ack,go; //handshake signals
|
||||
|
||||
wire isDes;
|
||||
wire rd_dma_start_one;
|
||||
wire rd_TX_des_start_one;
|
||||
|
||||
/// Jiansong: moved here from tx engine
|
||||
rising_edge_detect rd_dma_start_one_inst(
|
||||
.clk(clk),
|
||||
.rst(rst_reg),
|
||||
.in(rd_dma_start),
|
||||
.one_shot_out(rd_dma_start_one)
|
||||
);
|
||||
|
||||
/// Jiansong: added for TX des request trigger
|
||||
rising_edge_detect rd_TX_des_start_one_inst(
|
||||
.clk(clk),
|
||||
.rst(rst_reg),
|
||||
.in(rd_TX_des_start),
|
||||
.one_shot_out(rd_TX_des_start_one)
|
||||
);
|
||||
|
||||
non_posted_pkt_slicer non_posted_pkt_slicer_inst(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
/// Jiansong: control signal for transfer recovering
|
||||
`ifdef TF_RECOVERY
|
||||
.transferstart(transferstart),
|
||||
`endif
|
||||
//interface to dma_ctrl_wrapper
|
||||
.rd_TX_des_start_one(rd_TX_des_start_one),/// Jiansong:
|
||||
.TX_des_addr(TX_des_addr), /// added for TX des request
|
||||
.isDes(isDes), ///
|
||||
.rd_dma_start(rd_dma_start_one),
|
||||
.dmarad(dmarad),
|
||||
.dmarxs(dmarxs),
|
||||
.dmaras(dmaras),
|
||||
.read_req_size(read_req_size), //from pcie block
|
||||
//interface to non_posted_pkt_builder
|
||||
.ack(ack),
|
||||
.go(go),
|
||||
.dmarad_reg(dmarad_reg[31:0]),
|
||||
.dmaras_reg(dmaras_reg[63:0]),
|
||||
.length(length[9:0])
|
||||
);
|
||||
|
||||
non_posted_pkt_builder non_posted_pkt_builder_inst(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.req_id(req_id[15:0]), //from pcie block
|
||||
//interface to/from non_posted_pkt_slicer
|
||||
.go(go),
|
||||
.ack(ack),
|
||||
.dmaras(dmaras_reg[63:0]),
|
||||
.dmarad(dmarad_reg[31:0]),
|
||||
.length(length[9:0]),
|
||||
.isDes(isDes), /// Jiansong:
|
||||
//interface to/from tag_generator
|
||||
.tag_value(tag_value[7:0]),
|
||||
.tag_gnt(tag_gnt),
|
||||
.tag_inc(tag_inc),
|
||||
//interface to/from a64_64_distram_np(non-posted header fifo)
|
||||
.header_data_out(non_posted_fifo_data[63:0]),
|
||||
.header_data_wren(non_posted_fifo_wren),
|
||||
//interface to read_request_wrapper
|
||||
.tx_waddr(tx_waddr[4:0]),
|
||||
.tx_wdata(tx_wdata[31:0]),
|
||||
.tx_we(tx_we)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,389 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 06/01/2009
|
||||
// Design Name:
|
||||
// Module Name: tx_engine
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose: Non-Posted Packet Slicer module.
|
||||
// The rules for calculating the number of packets are the following:
|
||||
// 1 - Max Read Request Size cannot be violated
|
||||
// 2 - address and length combos cannot cross a 4kb boundary
|
||||
// Assumptions: Xfers will start on 128B boundaries
|
||||
// Xfers will be power of 2 multiples of 128B to 4KB
|
||||
// i.e. 128, 256, 512, 1024, 2048, 4096
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
// comment by Jiansong Zhang:
|
||||
// looks this module can handle dma read request larger than 4KB and up to 4G
|
||||
//
|
||||
// modified by Jiansong Zhang:
|
||||
// add state for TX descriptor request
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
`include "Sora_config.v"
|
||||
|
||||
module non_posted_pkt_slicer(
|
||||
input clk,
|
||||
input rst,
|
||||
/// Jiansong: control signal for transfer recovering
|
||||
`ifdef TF_RECOVERY
|
||||
input transferstart,
|
||||
`endif
|
||||
//input from dma_ctrl_wrapper
|
||||
input rd_dma_start,
|
||||
input [31:0] dmarad,
|
||||
input [31:0] dmarxs,
|
||||
input [63:0] dmaras,
|
||||
input [2:0] read_req_size,//from pcie block
|
||||
/// Jiansong: added for TX descriptor request
|
||||
input rd_TX_des_start_one,
|
||||
input [63:0] TX_des_addr,
|
||||
output reg isDes,
|
||||
//in/outs to_From non_posted_pkt_builder
|
||||
input ack,
|
||||
output reg go,
|
||||
output reg [31:0] dmarad_reg,
|
||||
output reg [63:0] dmaras_reg,
|
||||
output [9:0] length
|
||||
);
|
||||
|
||||
//state machine state definitions for state[3:0]
|
||||
localparam IDLE = 4'h0;
|
||||
localparam IDLE_WAIT = 4'h1;
|
||||
localparam START = 4'h2;
|
||||
localparam NORMAL = 4'h3;
|
||||
localparam CROSS = 4'h4;
|
||||
localparam LAST = 4'h5;
|
||||
localparam WAIT_FOR_ACK = 4'h6;
|
||||
localparam REGISTER_DMA_REG = 4'h7;
|
||||
localparam START_TX_DES_REQ = 4'h8;
|
||||
|
||||
//duplicate registers for timing purposes
|
||||
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [31:0] dmarad_new,dmarad_reg2;
|
||||
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [31:0] dmarxs_new,dmarxs_reg,
|
||||
dmarxs_reg2;
|
||||
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] dmaras_new,dmaras_reg2;
|
||||
wire [31:0] dmarad_add, dmarad_term;
|
||||
wire [31:0] dmarxs_sub, dmarxs_term;
|
||||
wire [63:0] dmaras_add, dmaras_term;
|
||||
reg [3:0] state;
|
||||
reg update_dma_reg;
|
||||
reg stay_2x; //to keep state[3:0] from switching during multi-cycle
|
||||
reg [12:0] length_byte;
|
||||
wire [63:0] dmaras_temp;
|
||||
wire four_kb_cross; //marks a 4KB crossing combinations
|
||||
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [12:0] four_kb_xfer,
|
||||
four_kb_xfer2;
|
||||
wire less_than_rrs;//marks a transfer less than max read request size
|
||||
wire [12:0] read_req_size_bytes;
|
||||
reg last_flag;
|
||||
reg rst_reg;
|
||||
|
||||
always@(posedge clk) rst_reg <= rst;
|
||||
|
||||
|
||||
//calculate the max read request size in bytes,
|
||||
//instead of the encoding as specified
|
||||
//in the PCI Express Base Specification
|
||||
assign read_req_size_bytes =13'h0001<<(read_req_size+7);
|
||||
|
||||
//lookahead to see if the next xfer address crosses a 4KB boundary
|
||||
//and flag if so
|
||||
//if the 12th bit of the destination changes than a 4KB boundary will be
|
||||
//crossed;
|
||||
//synthesis tool should remove everything above bit[12]
|
||||
assign dmaras_temp = dmaras_reg + read_req_size_bytes;
|
||||
assign four_kb_cross = (dmaras_temp[12] == dmaras_reg2[12]) ? 1'b0 : 1'b1;
|
||||
|
||||
//flag if the xfer size is less than read request size
|
||||
assign less_than_rrs = (dmarxs_reg <= read_req_size_bytes) ? 1'b1 : 1'b0;
|
||||
|
||||
//Pre-calculate the four KB boundary address in case it's needed
|
||||
//Essentially four_kb_xfer is how many bytes in the current transfer
|
||||
//are we away from the 4KB boundary
|
||||
//need four_kb_xfer to be a register in order to meet 250 MHz timing
|
||||
always@(posedge clk)begin
|
||||
four_kb_xfer[12:0] = 13'h1000 - dmaras_reg[11:0];
|
||||
four_kb_xfer2[12:0] = 13'h1000 - dmaras_reg2[11:0];
|
||||
end
|
||||
|
||||
//This state machine determines how to break up the larger requests into
|
||||
//the smaller packets based on: RRS and 4KB crossing
|
||||
//
|
||||
//Uses some multi-cycle paths:
|
||||
// state, dma*_reg, four_kb_xfer -> dma*_new
|
||||
//are 2x multi-cycle paths
|
||||
//The signal "stay_2x" ensures that the state variable
|
||||
//state are static for at least two clock
|
||||
//cycles when in the NORMAL, CROSS, and LAST states - of course
|
||||
//dma*_reg and four_kb_xfer signals must also be static for 2 cycles
|
||||
//while in these states
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TF_RECOVERY
|
||||
if (rst_reg | (~transferstart)) begin
|
||||
`else
|
||||
if (rst_reg) begin
|
||||
`endif
|
||||
state <= IDLE;
|
||||
update_dma_reg <= 0;
|
||||
stay_2x <= 1'b0;
|
||||
go <= 0;
|
||||
last_flag <= 1'b0;
|
||||
end else begin
|
||||
case (state)
|
||||
IDLE : begin
|
||||
//wait for the start signal from the dma_ctrl_wrapper before doing
|
||||
//anything
|
||||
update_dma_reg <= 0;
|
||||
stay_2x <= 1'b0;
|
||||
go <= 0;
|
||||
last_flag <= 1'b0;
|
||||
if(rd_dma_start)
|
||||
state <= IDLE_WAIT;
|
||||
else if(rd_TX_des_start_one) /// Jiansong:
|
||||
state <= START_TX_DES_REQ; /// add states for tx descriptor request generation
|
||||
else
|
||||
state <= IDLE;
|
||||
end
|
||||
IDLE_WAIT: begin //idle_wait added because of four_kb_xfer
|
||||
//being registered
|
||||
state <= START;
|
||||
end
|
||||
|
||||
/// Jiansong: states added for tx descriptor request
|
||||
START_TX_DES_REQ: begin
|
||||
go <= 1; //send the current address/length values while
|
||||
//the new ones are being calculated
|
||||
if(stay_2x == 1'b0)begin
|
||||
state <= START_TX_DES_REQ;
|
||||
stay_2x <= 1'b1;
|
||||
end else begin
|
||||
last_flag <= 1;
|
||||
stay_2x <= 1'b0;
|
||||
state <= WAIT_FOR_ACK;
|
||||
end
|
||||
end
|
||||
|
||||
START : begin /// Jiansong: start dma read
|
||||
update_dma_reg <= 0;
|
||||
stay_2x <= 1'b0;
|
||||
go <= 0;
|
||||
//determine addresses/lengths of the next packet
|
||||
//may be normal i.e. read request size
|
||||
//cross a 4kb boundary
|
||||
//or the last packet of the xfer (which may also be normal if the
|
||||
//last packet happens to be the same as max payload size)
|
||||
//and go to the correct state to do the arithmetic
|
||||
case ({four_kb_cross, less_than_rrs})
|
||||
2'b00:
|
||||
state <= NORMAL;
|
||||
2'b01:
|
||||
state <= LAST;
|
||||
2'b10:
|
||||
state <= CROSS;
|
||||
2'b11://because four_kb_cross uses look-ahead math, need to
|
||||
//determine if we will really cross a four KB boundary
|
||||
//in the case where we have a transfer which is flagged
|
||||
//as less_than_mps and do the appropriate transfer
|
||||
if(dmarxs_reg > four_kb_xfer)
|
||||
state <= CROSS;
|
||||
else
|
||||
state <= LAST;
|
||||
endcase
|
||||
end
|
||||
|
||||
NORMAL : begin //add a RRS to the current parameters
|
||||
go <= 1; //send the current address/length values while
|
||||
//the new ones are being calculated
|
||||
if(stay_2x == 1'b0)begin
|
||||
state <= NORMAL;
|
||||
stay_2x <= 1'b1;
|
||||
end else begin
|
||||
stay_2x <= 1'b0;
|
||||
state <= WAIT_FOR_ACK;
|
||||
end
|
||||
end
|
||||
CROSS : begin //add just enough to the current parameters
|
||||
//to get us to the 4KB boundary
|
||||
go <= 1;
|
||||
if(stay_2x == 1'b0)begin
|
||||
state <= CROSS;
|
||||
stay_2x <= 1'b1;
|
||||
end else begin
|
||||
stay_2x <= 1'b0;
|
||||
state <= WAIT_FOR_ACK;
|
||||
end
|
||||
end
|
||||
LAST : begin //add the remaining to the current parameters
|
||||
go <= 1;
|
||||
last_flag <= 1'b1;
|
||||
if(stay_2x == 1'b0)begin
|
||||
state <= LAST;
|
||||
stay_2x <= 1'b1;
|
||||
end else begin
|
||||
stay_2x <= 1'b0;
|
||||
state <= WAIT_FOR_ACK;
|
||||
end
|
||||
end
|
||||
|
||||
WAIT_FOR_ACK : begin
|
||||
if(ack)begin
|
||||
update_dma_reg <= 1'b1;
|
||||
go <= 1'b0;
|
||||
if(last_flag)begin
|
||||
state <= IDLE;
|
||||
end else begin
|
||||
state <= REGISTER_DMA_REG;
|
||||
end
|
||||
end else begin
|
||||
update_dma_reg <= 1'b0;
|
||||
go <= 1'b1;
|
||||
state <= WAIT_FOR_ACK;
|
||||
end
|
||||
end
|
||||
|
||||
REGISTER_DMA_REG: begin
|
||||
//go ahead and update the current address/length values
|
||||
//for the next go-around through the state machine
|
||||
update_dma_reg <= 1'b0;
|
||||
state <= IDLE_WAIT;
|
||||
end
|
||||
|
||||
default : begin
|
||||
update_dma_reg <= 0;
|
||||
go <= 0;
|
||||
state <= IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
//determine what we will add to the dest. address
|
||||
assign dmarad_term = (state == NORMAL) ? read_req_size_bytes :
|
||||
(state == CROSS) ? four_kb_xfer :
|
||||
(state == LAST) ? dmarxs_reg :
|
||||
read_req_size_bytes;
|
||||
//do the addition for the dest. address
|
||||
assign dmarad_add = dmarad_reg2 + dmarad_term;
|
||||
|
||||
//determine what we will add to the source address
|
||||
assign dmaras_term = (state == NORMAL) ? read_req_size_bytes :
|
||||
(state == CROSS) ? four_kb_xfer2 :
|
||||
(state == LAST) ? dmarxs_reg :
|
||||
read_req_size_bytes;
|
||||
//do the addition for the source address
|
||||
assign dmaras_add = dmaras_reg2 + dmaras_term;
|
||||
|
||||
//determine how much to subtract from the transfer size
|
||||
assign dmarxs_term = (state == NORMAL) ? read_req_size_bytes :
|
||||
(state == CROSS) ? four_kb_xfer2 :
|
||||
(state == LAST) ? dmarxs_reg :
|
||||
read_req_size_bytes;
|
||||
//do the subtraction to the transfer size
|
||||
assign dmarxs_sub = dmarxs_reg2 - dmarxs_term;
|
||||
|
||||
always@(posedge clk)begin
|
||||
if(stay_2x)begin
|
||||
dmarad_new <= dmarad_add;
|
||||
dmaras_new <= dmaras_add;
|
||||
dmarxs_new <= dmarxs_sub;
|
||||
end
|
||||
end
|
||||
|
||||
//register dmarad,dmarxs, and dmaras when rd_dma_start is high
|
||||
//rd_dma_start is only asserted for one clock cycle
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)begin
|
||||
dmarad_reg <= 32'h0000_0000;
|
||||
dmarxs_reg <= 32'h0000_0000;
|
||||
dmaras_reg <= 64'h0000_0000_0000_0000;
|
||||
dmarad_reg2 <= 32'h0000_0000;
|
||||
dmarxs_reg2 <= 32'h0000_0000;
|
||||
dmaras_reg2 <= 64'h0000_0000_0000_0000;
|
||||
end else if(rd_dma_start)begin
|
||||
dmarad_reg <= dmarad;
|
||||
dmarxs_reg <= dmarxs;
|
||||
dmaras_reg <= dmaras;
|
||||
dmarad_reg2 <= dmarad;
|
||||
dmarxs_reg2 <= dmarxs;
|
||||
dmaras_reg2 <= dmaras;
|
||||
end else if(update_dma_reg)begin
|
||||
dmarad_reg <= dmarad_new;
|
||||
dmarxs_reg <= dmarxs_new;
|
||||
dmaras_reg <= dmaras_new;
|
||||
dmarad_reg2 <= dmarad_new;
|
||||
dmarxs_reg2 <= dmarxs_new;
|
||||
dmaras_reg2 <= dmaras_new;
|
||||
end else if(rd_TX_des_start_one)begin /// Jiansong:
|
||||
dmaras_reg <= TX_des_addr; /// added for TX descriptor request
|
||||
end
|
||||
end
|
||||
|
||||
//additional output from state machine
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)
|
||||
length_byte[12:0] <= 0;
|
||||
else if(state == NORMAL)
|
||||
length_byte[12:0] <= read_req_size_bytes[12:0];
|
||||
else if (state == LAST)
|
||||
length_byte[12:0] <= dmarxs_reg2[12:0];
|
||||
else if (state == CROSS)
|
||||
length_byte[12:0] <= four_kb_xfer2[12:0];
|
||||
else if (state == START_TX_DES_REQ) /// Jiansong:
|
||||
length_byte[12:0] <= 13'h0020; /// added for TX descriptor request, 32 bytes TX des
|
||||
else
|
||||
length_byte <= length_byte;
|
||||
end
|
||||
|
||||
assign length[9:0] = length_byte[11:2];
|
||||
|
||||
/// Jiansong: added for TX descriptor request
|
||||
always@ (posedge clk)begin
|
||||
if(rst_reg)
|
||||
isDes <= 0;
|
||||
else if ((state == NORMAL) | (state == LAST) | (state == CROSS))
|
||||
isDes <= 0;
|
||||
else if (state == START_TX_DES_REQ)
|
||||
isDes <= 1;
|
||||
else
|
||||
isDes <= isDes;
|
||||
end
|
||||
|
||||
endmodule
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,86 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 06/01/2009
|
||||
// Design Name:
|
||||
// Module Name: tx_engine
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose: A small shadow-RAM to qualify the data entries in the dual-port
|
||||
// compram
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
// Modification by zjs, 2009-6-18, pending
|
||||
// (1) move posted packet generator and non-posted packet generator out --- done
|
||||
// (2) add dma write data fifo --------------- done
|
||||
// (3) modify tx sm
|
||||
// scheduling -------------------------- done
|
||||
// disable write dma done -------------- done
|
||||
// register/memory read ---------------- done
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module pending_comp_ram_32x1(
|
||||
input clk,
|
||||
input d_in,
|
||||
input [4:0] addr,
|
||||
input we,
|
||||
output reg [31:0] d_out = 32'h00000000
|
||||
);
|
||||
|
||||
|
||||
wire [31:0] addr_decode;
|
||||
|
||||
//binary-to-onehot address decoder for ram
|
||||
assign addr_decode[31:0] = 32'h00000001 << addr[4:0];
|
||||
|
||||
//generate a 32-entry ram with
|
||||
//addressable inputs entries
|
||||
//and outputs which are always present;
|
||||
//essentially this is a 32x1 register file
|
||||
genvar i;
|
||||
generate
|
||||
for(i=0;i<32;i=i+1)begin: bitram
|
||||
always@(posedge clk)begin
|
||||
if(addr_decode[i] && we)begin
|
||||
d_out[i] <= d_in;
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 12:17:59 11/12/2009
|
||||
// Design Name:
|
||||
// Module Name: performance_counter
|
||||
// Project Name: Sora
|
||||
// Target Devices: LX50T1136-1
|
||||
// Tool versions: ISE 10.02
|
||||
// Description: We measure the durations in this module (1) from TX_des request sent to tx_engine to new des
|
||||
// received (2) from transfer start to transfer done.
|
||||
// A counter (125MHz or 250MHz depends on DMA clock) is implemeted.
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module performance_counter(
|
||||
input clk,
|
||||
input rst,
|
||||
input transferstart_one,
|
||||
input rd_dma_done_one,
|
||||
input new_des_one,
|
||||
output reg [23:0] round_trip_latency,
|
||||
output reg [23:0] transfer_duration
|
||||
);
|
||||
|
||||
reg [39:0] counter; /// free run 40bits counter, more than two hours per cycle on 125MHz clock
|
||||
reg [23:0] snapshot_transferstart; /// record the lower 24 bit of counter when transferstart, more than 100ms per cycle on 125MHz clock
|
||||
|
||||
/// counter
|
||||
always@(posedge clk) begin
|
||||
if(rst)
|
||||
counter <= 40'h00_0000_0000;
|
||||
else
|
||||
counter <= counter + 40'h00_0000_0001;
|
||||
end
|
||||
|
||||
/// snapshot_transferstart
|
||||
always@(posedge clk) begin
|
||||
if(rst)
|
||||
snapshot_transferstart <= 24'h00_0000;
|
||||
else if (transferstart_one)
|
||||
snapshot_transferstart <= counter[23:0];
|
||||
else
|
||||
snapshot_transferstart <= snapshot_transferstart;
|
||||
end
|
||||
|
||||
/// round_trip_latency
|
||||
always@(posedge clk) begin
|
||||
if (rst)
|
||||
round_trip_latency <= 24'h00_0000;
|
||||
else if (new_des_one)
|
||||
round_trip_latency <= counter[23:0] + (~snapshot_transferstart) + 24'h00_0001;
|
||||
else
|
||||
round_trip_latency <= round_trip_latency;
|
||||
end
|
||||
|
||||
/// transfer_duration
|
||||
always@(posedge clk) begin
|
||||
if (rst)
|
||||
transfer_duration <= 24'h00_0000;
|
||||
else if (rd_dma_done_one)
|
||||
transfer_duration <= counter[23:0] + (~snapshot_transferstart) + 24'h00_0001;
|
||||
else
|
||||
transfer_duration <= transfer_duration;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,170 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 06/01/2009
|
||||
// Design Name:
|
||||
// Module Name: tx_engine
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose: Posted Packet Builder module. This module takes the
|
||||
// length info from the Posted Packet Slicer, and requests a tag from
|
||||
// the Tag Generator and uses that info to build a posted memory write header
|
||||
// which it writes into a FIFO
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module posted_pkt_builder(
|
||||
input clk,
|
||||
input rst,
|
||||
input [15:0] req_id, //from pcie block
|
||||
//to/from posted_pkt_slicer
|
||||
input posted_fifo_full,
|
||||
input go,
|
||||
output reg ack,
|
||||
input [63:0] dmawad,
|
||||
input [9:0] length,
|
||||
//to posted_pkt_header_fifo
|
||||
output reg [63:0] header_data_out,
|
||||
output reg header_data_wren
|
||||
);
|
||||
|
||||
|
||||
//State machine states
|
||||
localparam IDLE = 4'h0;
|
||||
localparam HEAD1 = 4'h1;
|
||||
localparam HEAD2 = 4'h2;
|
||||
localparam WAIT_FOR_GO_DEASSERT = 4'h3;
|
||||
|
||||
//parameters used to define fixed header fields
|
||||
localparam rsvd = 1'b0; //reserved and unused header fields to zero
|
||||
localparam MWr = 5'b00000; //format for memory write header
|
||||
localparam TC = 3'b000; //traffic class 0
|
||||
localparam TD = 1'b0; //digest bit always 0
|
||||
localparam EP = 1'b0; //poisoned bit always 0
|
||||
localparam ATTR = 2'b00; //no snoop or relaxed-ordering
|
||||
localparam LastBE = 4'b1111; //LastBE is always asserted since all transfers
|
||||
//are on 128B boundaries and are always at least
|
||||
//128B long
|
||||
localparam FirstBE = 4'b1111;//FirstBE is always asserted since all transfers
|
||||
//are on 128B boundaries
|
||||
|
||||
|
||||
wire [1:0] fmt;
|
||||
reg [3:0] state;
|
||||
reg [63:0] dmawad_reg;
|
||||
|
||||
reg rst_reg;
|
||||
always@(posedge clk) rst_reg <= rst;
|
||||
|
||||
|
||||
//if the upper DWord of the destination address is zero
|
||||
//than make the format of the packet header 3DW; otherwise 4DW
|
||||
assign fmt[1:0] = (dmawad_reg[63:32] == 0) ? 2'b10 : 2'b11;
|
||||
|
||||
//if the posted_pkt_slicer asserts "go" then register the dma write params
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)begin
|
||||
dmawad_reg[63:0] <= 0;
|
||||
end else if(go)begin
|
||||
dmawad_reg <= dmawad;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// State machine
|
||||
// Builds headers for posted memory writes
|
||||
// Writes them into a FIFO
|
||||
always @ (posedge clk) begin
|
||||
if (rst_reg) begin
|
||||
header_data_out <= 0;
|
||||
header_data_wren <= 1'b0;
|
||||
ack <= 1'b0;
|
||||
state <= IDLE;
|
||||
end else begin
|
||||
case (state)
|
||||
IDLE : begin
|
||||
header_data_out <= 0;
|
||||
header_data_wren <= 1'b0;
|
||||
ack <= 1'b0;
|
||||
if(go & ~posted_fifo_full) // Jiansong: prevent p_hdr_fifo overflow
|
||||
state<= HEAD1;
|
||||
else
|
||||
state<= IDLE;
|
||||
end
|
||||
HEAD1 : begin
|
||||
//write the first 64-bits of a posted header into the
|
||||
//posted fifo
|
||||
header_data_out <= {rsvd,fmt[1:0],MWr,rsvd,TC,rsvd,rsvd,rsvd,rsvd,
|
||||
TD,EP,ATTR,rsvd,rsvd,length[9:0],req_id[15:0],
|
||||
8'b00000000 ,LastBE,FirstBE};
|
||||
ack <= 0;
|
||||
header_data_wren <= 1'b1;
|
||||
state <= HEAD2;
|
||||
end
|
||||
HEAD2 : begin
|
||||
//write the next 32 or 64 bits of a posted header to the
|
||||
//posted header fifo (32 if 3DW - 64 if 4DW header)
|
||||
header_data_out <= (fmt[0]==1'b1)
|
||||
? {dmawad_reg[63:2],2'b00}
|
||||
: {dmawad_reg[31:2], 2'b00, dmawad_reg[63:32]};
|
||||
header_data_wren <= 1'b1;
|
||||
ack <= 1'b1; //acknowledge to the posted_packet_slicer that
|
||||
//the packet has been queued up for transmission
|
||||
state <= WAIT_FOR_GO_DEASSERT;
|
||||
end
|
||||
WAIT_FOR_GO_DEASSERT: begin
|
||||
//ack causes "go" to deassert but we need to give the
|
||||
//posted_pkt_slicer a chance to deassert "go" before returning
|
||||
//to IDLE
|
||||
header_data_out <= 0;
|
||||
header_data_wren <= 1'b0;
|
||||
ack <= 1'b0;
|
||||
state <= IDLE;
|
||||
end
|
||||
default : begin
|
||||
header_data_out <= 0;
|
||||
header_data_wren <= 1'b0;
|
||||
ack <= 1'b0;
|
||||
state <= IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,340 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:19:22 06/22/2009
|
||||
// Design Name:
|
||||
// Module Name: posted_pkt_gen_sora
|
||||
// Project Name: Sora
|
||||
// Target Devices: virtex-5 LX50T
|
||||
// Tool versions: ISE 10.1.02
|
||||
// Description: This module is created by Jiansong Zhang. Main purpose of this module is
|
||||
// to generate posted packet header and data. We have two data sources: RX path
|
||||
// and TX descriptor write back.
|
||||
// On RX path, when every 28DW data is arrived, we
|
||||
// generates three PCIe packets: (1) 28DW data packet (2) RX descriptor for next
|
||||
// data block, valid bit is 0 (3) RX descriptor for this data block, valid bit is 1.
|
||||
// This design facilitates driver for recognizing the latest data in RX buffer.
|
||||
// For TX desc write back, we write back the TX descriptor and set own bit to 0.
|
||||
// TX desc write back has higher priority.
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
`include "Sora_config.v"
|
||||
|
||||
module posted_pkt_gen_sora(
|
||||
input clk,
|
||||
input rst,
|
||||
//interface from/to dma_ctrl_wrapper
|
||||
/// Jiansong: TX desc write back
|
||||
input TX_desc_write_back_req,
|
||||
output TX_desc_write_back_ack,
|
||||
input [63:0] SourceAddr,
|
||||
input [31:0] DestAddr,
|
||||
input [23:0] FrameSize,
|
||||
input [7:0] FrameControl,
|
||||
input [63:0] DescAddr, /// Jiansong: pending
|
||||
/// Jiansong: RX path
|
||||
input RXEnable,
|
||||
input [63:0] RXBufAddr,
|
||||
input [31:0] RXBufSize,
|
||||
input RXEnable_2nd,
|
||||
input [63:0] RXBufAddr_2nd,
|
||||
input [31:0] RXBufSize_2nd,
|
||||
`ifdef MIMO_4X4
|
||||
input RXEnable_3rd,
|
||||
input [63:0] RXBufAddr_3rd,
|
||||
input [31:0] RXBufSize_3rd,
|
||||
input RXEnable_4th,
|
||||
input [63:0] RXBufAddr_4th,
|
||||
input [31:0] RXBufSize_4th,
|
||||
`endif //MIMO_4X4
|
||||
//interface to PCIe Endpoint Block Plus
|
||||
input [2:0] max_pay_size,
|
||||
input [15:0] req_id,
|
||||
//interface to posted header fifo (a64_128_distram_fifo_p)
|
||||
output posted_fifo_wren,
|
||||
output [63:0] posted_fifo_data,
|
||||
input posted_fifo_full, /// pending
|
||||
//interface to dma write data fifo in TX engine
|
||||
output [63:0] dma_write_data_fifo_data,
|
||||
output dma_write_data_fifo_wren,
|
||||
input dma_write_data_fifo_full,
|
||||
//interface to RX data fifo
|
||||
input [63:0] RX_FIFO_data,
|
||||
output RX_FIFO_RDEN,
|
||||
input RX_FIFO_pempty,
|
||||
input [31:0] RX_TS_FIFO_data,
|
||||
output RX_TS_FIFO_RDEN,
|
||||
input RX_TS_FIFO_empty,
|
||||
input [63:0] RX_FIFO_2nd_data,
|
||||
output RX_FIFO_2nd_RDEN,
|
||||
input RX_FIFO_2nd_pempty,
|
||||
input [31:0] RX_TS_FIFO_2nd_data,
|
||||
output RX_TS_FIFO_2nd_RDEN,
|
||||
input RX_TS_FIFO_2nd_empty,
|
||||
`ifdef MIMO_4X4
|
||||
input [63:0] RX_FIFO_3rd_data,
|
||||
output RX_FIFO_3rd_RDEN,
|
||||
input RX_FIFO_3rd_pempty,
|
||||
input [31:0] RX_TS_FIFO_3rd_data,
|
||||
output RX_TS_FIFO_3rd_RDEN,
|
||||
input RX_TS_FIFO_3rd_empty,
|
||||
input [63:0] RX_FIFO_4th_data,
|
||||
output RX_FIFO_4th_RDEN,
|
||||
input RX_FIFO_4th_pempty,
|
||||
input [31:0] RX_TS_FIFO_4th_data,
|
||||
output RX_TS_FIFO_4th_RDEN,
|
||||
input RX_TS_FIFO_4th_empty
|
||||
`endif //MIMO_4X4
|
||||
// interface to 2nd RX data fifo
|
||||
//`ifdef SORA_FRL_2nd
|
||||
// input [63:0] RX_FIFO_2nd_data,
|
||||
// output RX_FIFO_2nd_RDEN,
|
||||
// input RX_FIFO_2nd_pempty,
|
||||
//`endif
|
||||
// debug interface
|
||||
// output [31:0] Debug20RX1,
|
||||
//// output [4:0] Debug22RX3,
|
||||
// output [31:0] Debug24RX5,
|
||||
// output [31:0] Debug26RX7,
|
||||
// output [31:0] Debug27RX8,
|
||||
// output [31:0] Debug28RX9,
|
||||
// output [31:0] Debug29RX10
|
||||
);
|
||||
|
||||
//internal wrapper connections
|
||||
wire [63:0] dmawad_reg;
|
||||
wire [9:0] length;
|
||||
wire ack,go; //handshake signals
|
||||
|
||||
//`ifdef SORA_FRL_2nd // two radios
|
||||
// posted_pkt_scheduler_2radios posted_pkt_scheduler_2radios_inst (
|
||||
// .clk(clk),
|
||||
// .rst(rst),
|
||||
// //interface to PCIe Endpoint Block Plus
|
||||
// .max_pay_size(max_pay_size),
|
||||
// //interface from/to RX data fifo
|
||||
// .RX_FIFO_data (RX_FIFO_data),
|
||||
// .RX_FIFO_RDEN (RX_FIFO_RDEN),
|
||||
// .RX_FIFO_pempty (RX_FIFO_pempty),
|
||||
// //interface from/to the 2nd RX data fifo
|
||||
// .RX_FIFO_2nd_data (RX_FIFO_2nd_data),
|
||||
// .RX_FIFO_2nd_RDEN (RX_FIFO_2nd_RDEN),
|
||||
// .RX_FIFO_2nd_pempty (RX_FIFO_2nd_pempty),
|
||||
// //interface from/to dma ctrl wrapper
|
||||
// /// TX descriptor write back
|
||||
// .TX_desc_write_back_req (TX_desc_write_back_req),
|
||||
// .TX_desc_write_back_ack (TX_desc_write_back_ack),
|
||||
// .SourceAddr (SourceAddr),
|
||||
// .DestAddr (DestAddr),
|
||||
// .FrameSize (FrameSize),
|
||||
// .FrameControl (FrameControl),
|
||||
// .DescAddr (DescAddr),
|
||||
// /// RX control signals
|
||||
// .RXEnable (RXEnable),
|
||||
// .RXBufAddr (RXBufAddr),
|
||||
// .RXBufSize (RXBufSize),
|
||||
// /// RX control signals for the 2nd RX buffer
|
||||
// .RXBufAddr_2nd (RXBufAddr_2nd),
|
||||
// .RXBufSize_2nd (RXBufSize_2nd),
|
||||
// //interface from/to dma write data fifo in TX engine
|
||||
// .dma_write_data_fifo_data (dma_write_data_fifo_data),
|
||||
// .dma_write_data_fifo_wren (dma_write_data_fifo_wren),
|
||||
// .dma_write_data_fifo_full (dma_write_data_fifo_full),
|
||||
// //interface to posted pkt builder
|
||||
// .go(go),
|
||||
// .ack(ack),
|
||||
// .dmawad(dmawad_reg[63:0]),
|
||||
// .length(length[9:0]),
|
||||
// //interface from a64_128_distram_p(posted header fifo)
|
||||
// .posted_fifo_full(posted_fifo_full),
|
||||
// // debug interface
|
||||
// .Debug20RX1(Debug20RX1),
|
||||
// .Debug22RX3(Debug22RX3),
|
||||
// .Debug24RX5(Debug24RX5),
|
||||
// .Debug26RX7(Debug26RX7),
|
||||
// .Debug27RX8(Debug27RX8),
|
||||
// .Debug28RX9(Debug28RX9),
|
||||
// .Debug29RX10(Debug29RX10)
|
||||
// );
|
||||
//`endif
|
||||
|
||||
`ifdef MIMO_4X4 // 4 radios
|
||||
posted_pkt_scheduler_4radios posted_pkt_scheduler_4radios_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
//interface to PCIe Endpoint Block Plus
|
||||
.max_pay_size(max_pay_size),
|
||||
//interface from/to RX data fifo
|
||||
.RX_FIFO_data (RX_FIFO_data),
|
||||
.RX_FIFO_RDEN (RX_FIFO_RDEN),
|
||||
.RX_FIFO_pempty (RX_FIFO_pempty),
|
||||
.RX_TS_FIFO_data (RX_TS_FIFO_data),
|
||||
.RX_TS_FIFO_RDEN (RX_TS_FIFO_RDEN),
|
||||
.RX_TS_FIFO_empty (RX_TS_FIFO_empty),
|
||||
//interface from/to the 2nd RX data fifo
|
||||
.RX_FIFO_2nd_data (RX_FIFO_2nd_data),
|
||||
.RX_FIFO_2nd_RDEN (RX_FIFO_2nd_RDEN),
|
||||
.RX_FIFO_2nd_pempty (RX_FIFO_2nd_pempty),
|
||||
.RX_TS_FIFO_2nd_data (RX_TS_FIFO_2nd_data),
|
||||
.RX_TS_FIFO_2nd_RDEN (RX_TS_FIFO_2nd_RDEN),
|
||||
.RX_TS_FIFO_2nd_empty (RX_TS_FIFO_2nd_empty),
|
||||
//interface from/to the 3rd RX data fifo
|
||||
.RX_FIFO_3rd_data (RX_FIFO_3rd_data),
|
||||
.RX_FIFO_3rd_RDEN (RX_FIFO_3rd_RDEN),
|
||||
.RX_FIFO_3rd_pempty (RX_FIFO_3rd_pempty),
|
||||
.RX_TS_FIFO_3rd_data (RX_TS_FIFO_3rd_data),
|
||||
.RX_TS_FIFO_3rd_RDEN (RX_TS_FIFO_3rd_RDEN),
|
||||
.RX_TS_FIFO_3rd_empty (RX_TS_FIFO_3rd_empty),
|
||||
//interface from/to the 4th RX data fifo
|
||||
.RX_FIFO_4th_data (RX_FIFO_4th_data),
|
||||
.RX_FIFO_4th_RDEN (RX_FIFO_4th_RDEN),
|
||||
.RX_FIFO_4th_pempty (RX_FIFO_4th_pempty),
|
||||
.RX_TS_FIFO_4th_data (RX_TS_FIFO_4th_data),
|
||||
.RX_TS_FIFO_4th_RDEN (RX_TS_FIFO_4th_RDEN),
|
||||
.RX_TS_FIFO_4th_empty (RX_TS_FIFO_4th_empty),
|
||||
//interface from/to dma ctrl wrapper
|
||||
/// TX descriptor write back
|
||||
.TX_desc_write_back_req (TX_desc_write_back_req),
|
||||
.TX_desc_write_back_ack (TX_desc_write_back_ack),
|
||||
.SourceAddr (SourceAddr),
|
||||
.DestAddr (DestAddr),
|
||||
.FrameSize (FrameSize),
|
||||
.FrameControl (FrameControl),
|
||||
.DescAddr (DescAddr),
|
||||
/// RX control signals
|
||||
.RXEnable (RXEnable),
|
||||
.RXBuf_1stAddr (RXBufAddr),
|
||||
.RXBuf_1stSize (RXBufSize),
|
||||
/// RX control signals for the 2nd RX buffer
|
||||
.RXEnable_2nd (RXEnable_2nd),
|
||||
.RXBuf_2ndAddr (RXBufAddr_2nd),
|
||||
.RXBuf_2ndSize (RXBufSize_2nd),
|
||||
/// RX control signals for the 3rd RX buffer
|
||||
.RXEnable_3rd (RXEnable_3rd),
|
||||
.RXBuf_3rdAddr (RXBufAddr_3rd),
|
||||
.RXBuf_3rdSize (RXBufSize_3rd),
|
||||
/// RX control signals for the 4th RX buffer
|
||||
.RXEnable_4th (RXEnable_4th),
|
||||
.RXBuf_4thAddr (RXBufAddr_4th),
|
||||
.RXBuf_4thSize (RXBufSize_4th),
|
||||
//interface from/to dma write data fifo in TX engine
|
||||
.dma_write_data_fifo_data (dma_write_data_fifo_data),
|
||||
.dma_write_data_fifo_wren (dma_write_data_fifo_wren),
|
||||
.dma_write_data_fifo_full (dma_write_data_fifo_full),
|
||||
//interface to posted pkt builder
|
||||
.go(go),
|
||||
.ack(ack),
|
||||
.dmawad(dmawad_reg[63:0]),
|
||||
.length(length[9:0]),
|
||||
//interface from a64_128_distram_p(posted header fifo)
|
||||
.posted_fifo_full(posted_fifo_full)
|
||||
// debug interface
|
||||
// .Debug20RX1(Debug20RX1),
|
||||
//// .Debug22RX3(Debug22RX3),
|
||||
// .Debug24RX5(Debug24RX5),
|
||||
// .Debug26RX7(Debug26RX7),
|
||||
// .Debug27RX8(Debug27RX8),
|
||||
// .Debug28RX9(Debug28RX9),
|
||||
// .Debug29RX10(Debug29RX10)
|
||||
);
|
||||
`endif //MIMO_4X4
|
||||
|
||||
`ifdef single_radio
|
||||
posted_pkt_scheduler posted_pkt_scheduler_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
//interface to PCIe Endpoint Block Plus
|
||||
.max_pay_size(max_pay_size),
|
||||
//interface from/to RX data fifo
|
||||
.RX_FIFO_data (RX_FIFO_data[63:0]),
|
||||
.RX_FIFO_RDEN (RX_FIFO_RDEN),
|
||||
.RX_FIFO_pempty (RX_FIFO_pempty),
|
||||
.RX_TS_FIFO_data (RX_TS_FIFO_data[31:0]),
|
||||
.RX_TS_FIFO_RDEN (RX_TS_FIFO_RDEN),
|
||||
.RX_TS_FIFO_empty (RX_TS_FIFO_empty),
|
||||
//interface from/to dma ctrl wrapper
|
||||
/// TX descriptor write back
|
||||
.TX_desc_write_back_req (TX_desc_write_back_req),
|
||||
.TX_desc_write_back_ack (TX_desc_write_back_ack),
|
||||
.SourceAddr (SourceAddr),
|
||||
.DestAddr (DestAddr),
|
||||
.FrameSize (FrameSize),
|
||||
.FrameControl (FrameControl),
|
||||
.DescAddr (DescAddr),
|
||||
/// RX control signals
|
||||
.RXEnable (RXEnable),
|
||||
.RXBufAddr (RXBufAddr),
|
||||
.RXBufSize (RXBufSize),
|
||||
//interface from/to dma write data fifo in TX engine
|
||||
.dma_write_data_fifo_data (dma_write_data_fifo_data),
|
||||
.dma_write_data_fifo_wren (dma_write_data_fifo_wren),
|
||||
.dma_write_data_fifo_full (dma_write_data_fifo_full),
|
||||
//interface to posted pkt builder
|
||||
.go(go),
|
||||
.ack(ack),
|
||||
.dmawad(dmawad_reg[63:0]),
|
||||
.length(length[9:0]),
|
||||
//interface from a64_128_distram_p(posted header fifo)
|
||||
.posted_fifo_full(posted_fifo_full),
|
||||
// debug interface
|
||||
.Debug20RX1(Debug20RX1),
|
||||
.Debug22RX3(Debug22RX3),
|
||||
.Debug24RX5(Debug24RX5),
|
||||
.Debug26RX7(Debug26RX7),
|
||||
.Debug27RX8(Debug27RX8),
|
||||
.Debug28RX9(Debug28RX9),
|
||||
.Debug29RX10(Debug29RX10)
|
||||
);
|
||||
`endif //single_radio
|
||||
|
||||
/// build posted packet header and put in fifo
|
||||
posted_pkt_builder posted_pkt_builder_inst(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.req_id(req_id[15:0]),//from pcie block
|
||||
//interface to posted_pkt_scheduler
|
||||
.posted_fifo_full(posted_fifo_full),
|
||||
.go(go),
|
||||
.ack(ack),
|
||||
.dmawad(dmawad_reg[63:0]),
|
||||
.length(length[9:0]),
|
||||
//interface to/from a64_128_distram_p(posted header fifo)
|
||||
.header_data_out(posted_fifo_data[63:0]),
|
||||
.header_data_wren(posted_fifo_wren)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,883 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 18:15:25 09/05/2012
|
||||
// Design Name:
|
||||
// Module Name: posted_pkt_scheduler_4radios
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module posted_pkt_scheduler_4radios(
|
||||
input clk,
|
||||
input rst,
|
||||
//interface to PCIe Endpoint Block Plus
|
||||
input [2:0] max_pay_size,
|
||||
//interface from/to RX data fifo
|
||||
input [63:0] RX_FIFO_data,
|
||||
output RX_FIFO_RDEN,
|
||||
input RX_FIFO_pempty,
|
||||
input [31:0] RX_TS_FIFO_data,
|
||||
output RX_TS_FIFO_RDEN,
|
||||
input RX_TS_FIFO_empty,
|
||||
//interface from/to the 2nd RX data fifo
|
||||
input [63:0] RX_FIFO_2nd_data,
|
||||
output RX_FIFO_2nd_RDEN,
|
||||
input RX_FIFO_2nd_pempty,
|
||||
input [31:0] RX_TS_FIFO_2nd_data,
|
||||
output RX_TS_FIFO_2nd_RDEN,
|
||||
input RX_TS_FIFO_2nd_empty,
|
||||
//interface from/to the 3rd RX data fifo
|
||||
input [63:0] RX_FIFO_3rd_data,
|
||||
output RX_FIFO_3rd_RDEN,
|
||||
input RX_FIFO_3rd_pempty,
|
||||
input [31:0] RX_TS_FIFO_3rd_data,
|
||||
output RX_TS_FIFO_3rd_RDEN,
|
||||
input RX_TS_FIFO_3rd_empty,
|
||||
//interface from/to the 4th RX data fifo
|
||||
input [63:0] RX_FIFO_4th_data,
|
||||
output RX_FIFO_4th_RDEN,
|
||||
input RX_FIFO_4th_pempty,
|
||||
input [31:0] RX_TS_FIFO_4th_data,
|
||||
output RX_TS_FIFO_4th_RDEN,
|
||||
input RX_TS_FIFO_4th_empty,
|
||||
//interface from/to dma ctrl wrapper
|
||||
/// TX descriptor write back
|
||||
input TX_desc_write_back_req,
|
||||
output reg TX_desc_write_back_ack,
|
||||
input [63:0] SourceAddr,
|
||||
input [31:0] DestAddr,
|
||||
input [23:0] FrameSize,
|
||||
input [7:0] FrameControl,
|
||||
input [63:0] DescAddr,
|
||||
/// RX control signals
|
||||
input RXEnable,
|
||||
input [63:0] RXBuf_1stAddr,
|
||||
input [31:0] RXBuf_1stSize,
|
||||
/// RX control signals for the 2nd RX buffer
|
||||
input RXEnable_2nd,
|
||||
input [63:0] RXBuf_2ndAddr,
|
||||
input [31:0] RXBuf_2ndSize,
|
||||
/// RX control signals for the 3rd RX buffer
|
||||
input RXEnable_3rd,
|
||||
input [63:0] RXBuf_3rdAddr,
|
||||
input [31:0] RXBuf_3rdSize,
|
||||
/// RX control signals for the 4th RX buffer
|
||||
input RXEnable_4th,
|
||||
input [63:0] RXBuf_4thAddr,
|
||||
input [31:0] RXBuf_4thSize,
|
||||
//interface from/to dma write data fifo in TX engine
|
||||
output reg [63:0] dma_write_data_fifo_data,
|
||||
output reg dma_write_data_fifo_wren,
|
||||
input dma_write_data_fifo_full,
|
||||
//interface to posted pkt builder
|
||||
output reg go,
|
||||
input ack,
|
||||
output reg [63:0] dmawad,
|
||||
output [9:0] length,
|
||||
//interface from a64_128_distram_p(posted header fifo)
|
||||
input posted_fifo_full
|
||||
// debug interface
|
||||
// output reg [31:0] Debug20RX1,
|
||||
//// output reg [4:0] Debug22RX3,
|
||||
// output reg [31:0] Debug24RX5,
|
||||
// output reg [31:0] Debug26RX7,
|
||||
// output reg [31:0] Debug27RX8,
|
||||
// output reg [31:0] Debug28RX9,
|
||||
// output reg [31:0] Debug29RX10
|
||||
);
|
||||
|
||||
//state machine state definitions for state
|
||||
localparam IDLE = 5'b00000;
|
||||
localparam TX_DESC_WRITE_BACK = 5'b00001;
|
||||
localparam TX_DESC_WRITE_BACK2 = 5'b00010;
|
||||
localparam TX_DESC_WRITE_BACK3 = 5'b00011;
|
||||
localparam TX_DESC_WRITE_BACK4 = 5'b00100;
|
||||
localparam WAIT_FOR_ACK = 5'b00101;
|
||||
localparam RX_PACKET = 5'b00110;
|
||||
localparam RX_PACKET2 = 5'b00111;
|
||||
localparam RX_PACKET3 = 5'b01000;
|
||||
localparam RX_PACKET4 = 5'b01001;
|
||||
localparam RX_PACKET5 = 5'b01010;
|
||||
localparam RX_PACKET6 = 5'b01011;
|
||||
localparam RX_PACKET_WAIT_FOR_ACK = 5'b01100;
|
||||
localparam RX_DESC_WAIT = 5'b10011;
|
||||
localparam RX_DESC = 5'b01101;
|
||||
localparam RX_DESC2 = 5'b01110;
|
||||
localparam RX_CLEAR = 5'b10000;
|
||||
localparam RX_CLEAR2 = 5'b11111;
|
||||
localparam RX_CLEAR_WAIT_FOR_ACK = 5'b10101;
|
||||
localparam RX_CLEAR_WAIT = 5'b11100;
|
||||
|
||||
reg [4:0] state;
|
||||
|
||||
localparam RX_FRAME_SIZE_BYTES = 13'h0070; // data frame size is 112 bytes
|
||||
localparam TX_DESC_SIZE_BYTES = 13'h0020; // TX descriptor size is 32 bytes
|
||||
localparam RX_DESC_SIZE_BYTES = 13'h0010; // RX descriptor size is 16 bytes
|
||||
|
||||
// Signals for RoundRobin scheduling, two RX paths, pending
|
||||
// reg Current_Path; // 0: Current path is RX FIFO 1; 1: Current path is RX FIFO 2
|
||||
|
||||
// Signals for RoundRobin scheduling, four RX paths
|
||||
reg [1:0] pathindex_inturn; // 00: path 1; 01: path 2; 10: path 3; 11: path 4
|
||||
|
||||
reg RX_FIFO_RDEN_cntl; // read RX FIFO signal, we use one state machine for all the FIFOs, pathindex_inturn
|
||||
// is used to select one of the RX FIFOs
|
||||
reg RX_TS_FIFO_RDEN_cntl; // read RX TS FIFO signal, we use one state machine for all the FIFOs, pathindex_inturn
|
||||
// is used to select one of the RX FIFOs
|
||||
wire [31:0] RX_TS_FIFO_data_cntl;
|
||||
|
||||
reg [13:0] cnt; // counter for RX data
|
||||
reg [63:0] fifo_data_pipe; // pipeline data register between RX fifo and
|
||||
// dma write data fifo, also swap the upper and lower
|
||||
// DW
|
||||
|
||||
reg [12:0] length_byte; // output posted packet length
|
||||
|
||||
////////////// RX Path 1 //////////////////////
|
||||
reg buf_inuse; // whether this RX Buf is in use
|
||||
reg [31:0] RoundNumber; // indicates how many rounds we have wroten in RX buffer
|
||||
reg [31:0] RoundNumber_next;
|
||||
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] dmawad_now1_1st, dmawad_now2_1st;
|
||||
reg [63:0] dmawad_next_1st; // next RX data destination address
|
||||
// reg [63:0] dmawad_desc; // current rx descriptor address
|
||||
// Pipeline registers
|
||||
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] RXBuf_1stAddr_r1, RXBuf_1stAddr_r2;
|
||||
reg [31:0] RXBuf_1stSize_r;
|
||||
|
||||
////////////// RX Path 2 //////////////////////
|
||||
reg buf_inuse_2nd; // whether this RX Buf is in use
|
||||
reg [31:0] RoundNumber_2nd; // indicates how many rounds we have wroten in RX buffer
|
||||
reg [31:0] RoundNumber_next_2nd;
|
||||
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] dmawad_now1_2nd, dmawad_now2_2nd;
|
||||
reg [63:0] dmawad_next_2nd; // next RX data destination address
|
||||
// reg [63:0] dmawad_desc_2nd; // current rx descriptor address
|
||||
// Pipeline registers
|
||||
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] RXBuf_2ndAddr_r1, RXBuf_2ndAddr_r2;
|
||||
reg [31:0] RXBuf_2ndSize_r;
|
||||
|
||||
////////////// RX Path 3 //////////////////////
|
||||
reg buf_inuse_3rd; // whether this RX Buf is in use
|
||||
reg [31:0] RoundNumber_3rd; // indicates how many rounds we have wroten in RX buffer
|
||||
reg [31:0] RoundNumber_next_3rd;
|
||||
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] dmawad_now1_3rd, dmawad_now2_3rd;
|
||||
reg [63:0] dmawad_next_3rd; // next RX data destination address
|
||||
// reg [63:0] dmawad_desc_3rd; // current rx descriptor address
|
||||
// Pipeline registers
|
||||
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] RXBuf_3rdAddr_r1, RXBuf_3rdAddr_r2;
|
||||
reg [31:0] RXBuf_3rdSize_r;
|
||||
|
||||
////////////// RX Path 4 //////////////////////
|
||||
reg buf_inuse_4th; // whether this RX Buf is in use
|
||||
reg [31:0] RoundNumber_4th; // indicates how many rounds we have wroten in RX buffer
|
||||
reg [31:0] RoundNumber_next_4th;
|
||||
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] dmawad_now1_4th, dmawad_now2_4th;
|
||||
reg [63:0] dmawad_next_4th; // next RX data destination address
|
||||
// reg [63:0] dmawad_desc_4th; // current rx descriptor address
|
||||
// Pipeline registers
|
||||
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg [63:0] RXBuf_4thAddr_r1, RXBuf_4thAddr_r2;
|
||||
reg [31:0] RXBuf_4thSize_r;
|
||||
|
||||
|
||||
reg rst_reg;
|
||||
always@(posedge clk) rst_reg <= rst;
|
||||
|
||||
// // Debug register
|
||||
// always@(posedge clk)begin
|
||||
// Debug20RX1[3:0] <= state[3:0];
|
||||
// Debug20RX1[7:4] <= {3'b000,buf_inuse};
|
||||
// Debug20RX1[23:8] <= {3'b000,length_byte[12:0]};
|
||||
// Debug20RX1[27:24] <= {1'b0,max_pay_size};
|
||||
// Debug20RX1[31:28] <= {3'b000,posted_fifo_full};
|
||||
// end
|
||||
//
|
||||
//// always@(posedge clk)begin
|
||||
//// Debug22RX3[3:0] <= {3'b000,dma_write_data_fifo_full};
|
||||
//// Debug22RX3[4] <= RX_FIFO_pempty;
|
||||
//// end
|
||||
//
|
||||
// always@(posedge clk)begin
|
||||
// if (rst)
|
||||
// Debug24RX5[31:0] <= 32'h0000_0000;
|
||||
// else begin
|
||||
// if (RX_FIFO_RDEN)
|
||||
// Debug24RX5 <= Debug24RX5 + 8'h0000_0001;
|
||||
// else
|
||||
// Debug24RX5 <= Debug24RX5;
|
||||
// end
|
||||
// end
|
||||
//
|
||||
// always@(posedge clk)begin
|
||||
// if(rst)
|
||||
// Debug26RX7 <= 32'h0000_0000;
|
||||
// else if (dma_write_data_fifo_wren)
|
||||
// Debug26RX7 <= Debug26RX7 + 32'h0000_0001;
|
||||
// else
|
||||
// Debug26RX7 <= Debug26RX7;
|
||||
// end
|
||||
//
|
||||
// always@(posedge clk)begin
|
||||
// if (rst)
|
||||
// Debug27RX8 <= 32'h0000_0000;
|
||||
// else if (state == RX_PACKET)
|
||||
// Debug27RX8 <= Debug27RX8 + 32'h0000_0001;
|
||||
// else
|
||||
// Debug27RX8 <= Debug27RX8;
|
||||
// end
|
||||
//
|
||||
// always@(posedge clk)begin
|
||||
// Debug28RX9 <= dmawad[31:0];
|
||||
// Debug29RX10 <= dmawad[63:32];
|
||||
// end
|
||||
|
||||
// pipeline registers for RX path 1
|
||||
always@(posedge clk)begin
|
||||
RXBuf_1stAddr_r1 <= RXBuf_1stAddr;
|
||||
RXBuf_1stAddr_r2 <= RXBuf_1stAddr;
|
||||
RXBuf_1stSize_r <= RXBuf_1stSize;
|
||||
end
|
||||
|
||||
// pipeline registers for RX path 2
|
||||
always@(posedge clk)begin
|
||||
RXBuf_2ndAddr_r1 <= RXBuf_2ndAddr;
|
||||
RXBuf_2ndAddr_r2 <= RXBuf_2ndAddr;
|
||||
RXBuf_2ndSize_r <= RXBuf_2ndSize;
|
||||
end
|
||||
|
||||
// pipeline registers for RX path 3
|
||||
always@(posedge clk)begin
|
||||
RXBuf_3rdAddr_r1 <= RXBuf_3rdAddr;
|
||||
RXBuf_3rdAddr_r2 <= RXBuf_3rdAddr;
|
||||
RXBuf_3rdSize_r <= RXBuf_3rdSize;
|
||||
end
|
||||
|
||||
// pipeline registers for RX path 4
|
||||
always@(posedge clk)begin
|
||||
RXBuf_4thAddr_r1 <= RXBuf_4thAddr;
|
||||
RXBuf_4thAddr_r2 <= RXBuf_4thAddr;
|
||||
RXBuf_4thSize_r <= RXBuf_4thSize;
|
||||
end
|
||||
|
||||
wire [12:0] frame_size_bytes; // RX data frame size, min(RX_FRAME_SIZE_BYTES, max_pay_size_bytes)
|
||||
wire [12:0] max_pay_size_bytes; // max payload size from pcie core
|
||||
|
||||
//calculate the max payload size in bytes for ease of calculations
|
||||
//instead of the encoding as specified
|
||||
//in the PCI Express Base Specification
|
||||
assign max_pay_size_bytes =13'h0001<<(max_pay_size+7);
|
||||
assign frame_size_bytes = (RX_FRAME_SIZE_BYTES <= max_pay_size_bytes) ? RX_FRAME_SIZE_BYTES :
|
||||
max_pay_size_bytes;
|
||||
//generate TX_desc_write_back_ack signal
|
||||
always@(posedge clk) begin
|
||||
if (rst_reg)
|
||||
TX_desc_write_back_ack <= 1'b0;
|
||||
else if (state == TX_DESC_WRITE_BACK)
|
||||
TX_desc_write_back_ack <= 1'b1;
|
||||
else
|
||||
TX_desc_write_back_ack <= 1'b0;
|
||||
end
|
||||
|
||||
/// Jiansong: pipeline data register between RX fifo and
|
||||
/// dma write data fifo, also swap the upper and lower DW
|
||||
//always@(posedge clk) fifo_data_pipe[63:0] <= {RX_FIFO_data[31:0],RX_FIFO_data[63:32]};
|
||||
// always@(posedge clk) fifo_data_pipe[63:0] <= (~Current_Path) ?
|
||||
// {RX_FIFO_data[15:0],RX_FIFO_data[31:16],
|
||||
// RX_FIFO_data[47:32],RX_FIFO_data[63:48]} :
|
||||
// {RX_FIFO_2nd_data[15:0],RX_FIFO_2nd_data[31:16],
|
||||
// RX_FIFO_2nd_data[47:32],RX_FIFO_2nd_data[63:48]};
|
||||
always@(posedge clk) fifo_data_pipe[63:0] <= (pathindex_inturn[1] == 1'b0) ?
|
||||
( (pathindex_inturn[0] == 1'b0) ?
|
||||
{RX_FIFO_data[15:0],RX_FIFO_data[31:16],
|
||||
RX_FIFO_data[47:32],RX_FIFO_data[63:48]} :
|
||||
{RX_FIFO_2nd_data[15:0],RX_FIFO_2nd_data[31:16],
|
||||
RX_FIFO_2nd_data[47:32],RX_FIFO_2nd_data[63:48]}
|
||||
)
|
||||
: ( (pathindex_inturn[0] == 1'b0) ?
|
||||
{RX_FIFO_3rd_data[15:0],RX_FIFO_3rd_data[31:16],
|
||||
RX_FIFO_3rd_data[47:32],RX_FIFO_3rd_data[63:48]} :
|
||||
{RX_FIFO_4th_data[15:0],RX_FIFO_4th_data[31:16],
|
||||
RX_FIFO_4th_data[47:32],RX_FIFO_4th_data[63:48]}
|
||||
);
|
||||
|
||||
// assign RX_FIFO_RDEN = Current_Path & RX_FIFO_RDEN_cntl;
|
||||
// assign RX_FIFO_2nd_RDEN = (~Current_Path) & RX_FIFO_RDEN_cntl;
|
||||
|
||||
assign RX_FIFO_RDEN = (pathindex_inturn == 2'b00) & RX_FIFO_RDEN_cntl;
|
||||
assign RX_FIFO_2nd_RDEN = (pathindex_inturn == 2'b01) & RX_FIFO_RDEN_cntl;
|
||||
assign RX_FIFO_3rd_RDEN = (pathindex_inturn == 2'b10) & RX_FIFO_RDEN_cntl;
|
||||
assign RX_FIFO_4th_RDEN = (pathindex_inturn == 2'b11) & RX_FIFO_RDEN_cntl;
|
||||
|
||||
assign RX_TS_FIFO_RDEN = (pathindex_inturn == 2'b00) & RX_TS_FIFO_RDEN_cntl;
|
||||
assign RX_TS_FIFO_2nd_RDEN = (pathindex_inturn == 2'b01) & RX_TS_FIFO_RDEN_cntl;
|
||||
assign RX_TS_FIFO_3rd_RDEN = (pathindex_inturn == 2'b10) & RX_TS_FIFO_RDEN_cntl;
|
||||
assign RX_TS_FIFO_4th_RDEN = (pathindex_inturn == 2'b11) & RX_TS_FIFO_RDEN_cntl;
|
||||
|
||||
assign RX_TS_FIFO_data_cntl[31:0] = (pathindex_inturn[1] == 1'b0) ?
|
||||
( (pathindex_inturn[0] == 1'b0) ? RX_TS_FIFO_data[31:0] : RX_TS_FIFO_2nd_data[31:0] )
|
||||
: ( (pathindex_inturn[0] == 1'b0) ? RX_TS_FIFO_3rd_data[31:0] : RX_TS_FIFO_4th_data[31:0] );
|
||||
|
||||
//main state machine
|
||||
always@ (posedge clk) begin
|
||||
if (rst_reg) begin
|
||||
state <= IDLE;
|
||||
RX_FIFO_RDEN_cntl <= 1'b0;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
dma_write_data_fifo_wren <= 1'b0;
|
||||
dma_write_data_fifo_data <= 64'h0000_0000_0000_0000;
|
||||
go <= 1'b0;
|
||||
buf_inuse <= 1'b0;
|
||||
buf_inuse_2nd <= 1'b0;
|
||||
buf_inuse_3rd <= 1'b0;
|
||||
buf_inuse_4th <= 1'b0;
|
||||
pathindex_inturn <= 2'b00;
|
||||
cnt <= 13'h0000;
|
||||
end else begin
|
||||
case (state)
|
||||
IDLE : begin
|
||||
cnt <= 13'h0000;
|
||||
go <= 1'b0;
|
||||
RX_FIFO_RDEN_cntl <= 1'b0;
|
||||
dma_write_data_fifo_wren <= 1'b0;
|
||||
dma_write_data_fifo_data <= 64'h0000_0000_0000_0000;
|
||||
// check if need to generate a posted packet
|
||||
if(~posted_fifo_full & ~dma_write_data_fifo_full) begin
|
||||
if(TX_desc_write_back_req)
|
||||
state <= TX_DESC_WRITE_BACK;
|
||||
else begin
|
||||
casex({ pathindex_inturn[1:0],
|
||||
((~RX_FIFO_pempty)&(~RX_TS_FIFO_empty)),
|
||||
((~RX_FIFO_2nd_pempty)&(~RX_TS_FIFO_2nd_empty)),
|
||||
((~RX_FIFO_3rd_pempty)&(~RX_TS_FIFO_3rd_empty)),
|
||||
((~RX_FIFO_4th_pempty)&(~RX_TS_FIFO_4th_empty)) })
|
||||
|
||||
6'b00_1xxx, 6'b01_1000, 6'b10_1x00, 6'b11_1xx0: begin // path1's turn
|
||||
pathindex_inturn <= 2'b00;
|
||||
buf_inuse <= 1'b1;
|
||||
cnt <= frame_size_bytes;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b1;
|
||||
state <= RX_CLEAR;
|
||||
end
|
||||
|
||||
6'b00_01xx, 6'b01_x1xx, 6'b10_0100, 6'b11_01x0: begin // path2's turn
|
||||
pathindex_inturn <= 2'b01;
|
||||
buf_inuse_2nd <= 1'b1;
|
||||
cnt <= frame_size_bytes;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b1;
|
||||
state <= RX_CLEAR;
|
||||
end
|
||||
|
||||
6'b00_001x, 6'b01_x01x, 6'b10_xx1x, 6'b11_0010: begin // path3's turn
|
||||
pathindex_inturn <= 2'b10;
|
||||
buf_inuse_3rd <= 1'b1;
|
||||
cnt <= frame_size_bytes;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b1;
|
||||
state <= RX_CLEAR;
|
||||
end
|
||||
|
||||
6'b00_0001, 6'b01_x001, 6'b10_xx01, 6'b11_xxx1: begin // path4's turn
|
||||
pathindex_inturn <= 2'b11;
|
||||
buf_inuse_4th <= 1'b1;
|
||||
cnt <= frame_size_bytes;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b1;
|
||||
state <= RX_CLEAR;
|
||||
end
|
||||
|
||||
default: begin // IDLE state
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b1;
|
||||
state <= IDLE;
|
||||
end
|
||||
|
||||
endcase
|
||||
|
||||
// case({Path_Priority, ~RX_FIFO_pempty, ~RX_FIFO_2nd_pempty})
|
||||
// 3'b010, 3'b011, 3'b110: begin
|
||||
// Current_Path <= 1'b0;
|
||||
// buf_inuse <= 1'b0;
|
||||
// cnt <= frame_size_bytes;
|
||||
// state <= RX_CLEAR;
|
||||
// end
|
||||
// 3'b101, 3'b111, 3'b001: begin
|
||||
// Current_Path <= 1'b1;
|
||||
// buf_inuse_2nd <= 1'b0;
|
||||
// cnt <= frame_size_bytes;
|
||||
// state <= RX_CLEAR;
|
||||
// end
|
||||
// 3'b000, 3'b100: begin
|
||||
// state <= IDLE;
|
||||
// end
|
||||
// endcase
|
||||
end
|
||||
end else
|
||||
state <= IDLE;
|
||||
end
|
||||
// start TX desc write back flow
|
||||
TX_DESC_WRITE_BACK : begin // write TX descriptor into dma write data fifo
|
||||
go <= 1'b0;
|
||||
RX_FIFO_RDEN_cntl <= 1'b0;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
dma_write_data_fifo_wren <= 1'b1;
|
||||
// TimeStamp(4B), TXStatus(2B), CRC(2B)
|
||||
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
|
||||
state <= TX_DESC_WRITE_BACK2;
|
||||
end
|
||||
TX_DESC_WRITE_BACK2 : begin
|
||||
go <= 1'b0;
|
||||
RX_FIFO_RDEN_cntl <= 1'b0;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
dma_write_data_fifo_wren <= 1'b1;
|
||||
// SourceAddr(8B)
|
||||
dma_write_data_fifo_data[63:0] <= SourceAddr;
|
||||
state <= TX_DESC_WRITE_BACK3;
|
||||
end
|
||||
TX_DESC_WRITE_BACK3 : begin
|
||||
go <= 1'b0;
|
||||
RX_FIFO_RDEN_cntl <= 1'b0;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
dma_write_data_fifo_wren <= 1'b1;
|
||||
// NextDesc(4B), DestAddr(4B)
|
||||
dma_write_data_fifo_data[63:0] <= {32'h0000_0000,DestAddr};
|
||||
state <= TX_DESC_WRITE_BACK4;
|
||||
end
|
||||
TX_DESC_WRITE_BACK4 : begin
|
||||
go <= 1'b1;
|
||||
RX_FIFO_RDEN_cntl <= 1'b0;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
dma_write_data_fifo_wren <= 1'b1;
|
||||
// Reserved(4B), FrameControl, FrameSize(3B)
|
||||
dma_write_data_fifo_data[63:0] <= {32'h0000_0000,FrameControl,FrameSize};
|
||||
state <= WAIT_FOR_ACK;
|
||||
end
|
||||
WAIT_FOR_ACK : begin
|
||||
RX_FIFO_RDEN_cntl <= 1'b0;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
dma_write_data_fifo_wren <= 1'b0;
|
||||
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
|
||||
if(ack) begin
|
||||
go <= 1'b0;
|
||||
state <= IDLE;
|
||||
end else begin
|
||||
go <= 1'b1;
|
||||
state <= WAIT_FOR_ACK;
|
||||
end
|
||||
end
|
||||
|
||||
// start of a clear next desc -> generate RX packet -> write des flow,
|
||||
// clear RX descriptor of next block
|
||||
RX_CLEAR : begin
|
||||
RX_FIFO_RDEN_cntl <= 1'b0;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
go <= 1'b0;
|
||||
dma_write_data_fifo_wren <= 1'b1;
|
||||
// clear RX desc
|
||||
dma_write_data_fifo_data[63:0] <= {64'h0000_0000_0000_0000};
|
||||
state <= RX_CLEAR2;
|
||||
end
|
||||
RX_CLEAR2 : begin
|
||||
RX_FIFO_RDEN_cntl <= 1'b0;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
go <= 1'b1;
|
||||
dma_write_data_fifo_wren <= 1'b1;
|
||||
// write round number in RX desc. In case it's the head of RX buffer,
|
||||
// RoundNumber could be old
|
||||
// dma_write_data_fifo_data[63:0] <= {32'h0000_0000,RoundNumber};
|
||||
dma_write_data_fifo_data[63:0] <= {RX_TS_FIFO_data_cntl[31:0]+32'h0000_001C,RoundNumber[31:0]};
|
||||
state <= RX_CLEAR_WAIT_FOR_ACK;
|
||||
end
|
||||
RX_CLEAR_WAIT_FOR_ACK : begin
|
||||
// RX_FIFO_RDEN <= 1'b0; // this is a modification here, previously (in SISO), we read out the first data in IDLE state
|
||||
dma_write_data_fifo_wren <= 1'b0;
|
||||
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
if(ack) begin
|
||||
go <= 1'b0;
|
||||
if (~posted_fifo_full & ~dma_write_data_fifo_full) begin
|
||||
RX_FIFO_RDEN_cntl <= 1'b1;
|
||||
state <= RX_PACKET;
|
||||
end else begin
|
||||
RX_FIFO_RDEN_cntl <= 1'b0;
|
||||
state <= RX_CLEAR_WAIT;
|
||||
end
|
||||
end else begin
|
||||
go <= 1'b1;
|
||||
RX_FIFO_RDEN_cntl <= 1'b0;
|
||||
state <= RX_CLEAR_WAIT_FOR_ACK;
|
||||
end
|
||||
end
|
||||
RX_CLEAR_WAIT : begin
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
if (~posted_fifo_full & ~dma_write_data_fifo_full) begin
|
||||
RX_FIFO_RDEN_cntl <= 1'b1;
|
||||
state <= RX_PACKET;
|
||||
end else begin
|
||||
RX_FIFO_RDEN_cntl <= 1'b0;
|
||||
state <= RX_CLEAR_WAIT;
|
||||
end
|
||||
end
|
||||
|
||||
// start of RX packet generation flow
|
||||
RX_PACKET : begin
|
||||
go <= 1'b0;
|
||||
cnt <= cnt - 13'h0008;
|
||||
RX_FIFO_RDEN_cntl <= 1'b1;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
dma_write_data_fifo_wren <= 1'b0;
|
||||
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
|
||||
state <= RX_PACKET2;
|
||||
end
|
||||
RX_PACKET2 : begin
|
||||
go <= 1'b0;
|
||||
cnt <= cnt - 13'h0008;
|
||||
RX_FIFO_RDEN_cntl <= 1'b1;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
dma_write_data_fifo_wren <= 1'b0;
|
||||
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
|
||||
//// fifo_data_pipe[63:0] <= {RX_FIFO_data[31:0],RX_FIFO_data[63:32]};
|
||||
state <= RX_PACKET3;
|
||||
end
|
||||
RX_PACKET3 : begin
|
||||
go <= 1'b0;
|
||||
RX_FIFO_RDEN_cntl <= 1'b1;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
dma_write_data_fifo_wren <= 1'b1;
|
||||
//// fifo_data_pipe[63:0] <= {RX_FIFO_data[31:0],RX_FIFO_data[63:32]};
|
||||
dma_write_data_fifo_data[63:0] <= fifo_data_pipe[63:0];
|
||||
if (cnt == 13'h0010) begin
|
||||
state <= RX_PACKET4;
|
||||
end else begin
|
||||
cnt <= cnt - 13'h0008;
|
||||
state <= RX_PACKET3;
|
||||
end
|
||||
end
|
||||
RX_PACKET4 : begin
|
||||
go <= 1'b0;
|
||||
RX_FIFO_RDEN_cntl <= 1'b0;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
dma_write_data_fifo_wren <= 1'b1;
|
||||
//// fifo_data_pipe[63:0] <= {RX_FIFO_data[31:0],RX_FIFO_data[63:32]};
|
||||
dma_write_data_fifo_data[63:0] <= fifo_data_pipe[63:0];
|
||||
state <= RX_PACKET5;
|
||||
end
|
||||
RX_PACKET5 : begin
|
||||
go <= 1'b0;
|
||||
RX_FIFO_RDEN_cntl <= 1'b0;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
dma_write_data_fifo_wren <= 1'b1;
|
||||
//// fifo_data_pipe[63:0] <= {RX_FIFO_data[31:0],RX_FIFO_data[63:32]};
|
||||
dma_write_data_fifo_data[63:0] <= fifo_data_pipe[63:0];
|
||||
state <= RX_PACKET6;
|
||||
end
|
||||
RX_PACKET6 : begin
|
||||
go <= 1'b1;
|
||||
RX_FIFO_RDEN_cntl <= 1'b0;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
dma_write_data_fifo_wren <= 1'b1;
|
||||
//// fifo_data_pipe[63:0] <= {RX_FIFO_data[31:0],RX_FIFO_data[63:32]};
|
||||
dma_write_data_fifo_data[63:0] <= fifo_data_pipe[63:0];
|
||||
state <= RX_PACKET_WAIT_FOR_ACK;
|
||||
end
|
||||
RX_PACKET_WAIT_FOR_ACK : begin
|
||||
RX_FIFO_RDEN_cntl <= 1'b0;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
dma_write_data_fifo_wren <= 1'b0;
|
||||
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
|
||||
if(ack) begin
|
||||
go <= 1'b0;
|
||||
if (~posted_fifo_full & ~dma_write_data_fifo_full)
|
||||
state <= RX_DESC;
|
||||
else
|
||||
state <= RX_DESC_WAIT;
|
||||
end else begin
|
||||
go <= 1'b1;
|
||||
state <= RX_PACKET_WAIT_FOR_ACK;
|
||||
end
|
||||
end
|
||||
RX_DESC_WAIT : begin
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
if (~posted_fifo_full & ~dma_write_data_fifo_full)
|
||||
state <= RX_DESC;
|
||||
else
|
||||
state <= RX_DESC_WAIT;
|
||||
end
|
||||
|
||||
// start of RX desc flow
|
||||
RX_DESC : begin
|
||||
RX_FIFO_RDEN_cntl <= 1'b0;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
go <= 1'b0;
|
||||
dma_write_data_fifo_wren <= 1'b1;
|
||||
// data will be swapped later
|
||||
// dma_write_data_fifo_data[63:0] <= {56'h00_0000_0000_0000,8'h01};
|
||||
dma_write_data_fifo_data[63:0] <= 64'hFFFF_FFFF_FFFF_FFFF;
|
||||
state <= RX_DESC2;
|
||||
end
|
||||
RX_DESC2 : begin
|
||||
RX_FIFO_RDEN_cntl <= 1'b0;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
go <= 1'b1;
|
||||
dma_write_data_fifo_wren <= 1'b1;
|
||||
// dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
|
||||
// Write Round number in RX desc. It's used as debug info
|
||||
// dma_write_data_fifo_data[63:0] <= {32'h0000_0000,RoundNumber};
|
||||
dma_write_data_fifo_data[63:0] <= {RX_TS_FIFO_data_cntl[31:0],RoundNumber[31:0]};
|
||||
state <= WAIT_FOR_ACK;
|
||||
end
|
||||
default: begin
|
||||
go <= 1'b0;
|
||||
RX_FIFO_RDEN_cntl <= 1'b0;
|
||||
RX_TS_FIFO_RDEN_cntl <= 1'b0;
|
||||
dma_write_data_fifo_wren <= 1'b0;
|
||||
dma_write_data_fifo_data[63:0] <= 64'h0000_0000_0000_0000;
|
||||
state <= IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// update dmawad_next_1st and RoundNumber_next for RX path 1
|
||||
always@(posedge clk) begin
|
||||
if(~buf_inuse | rst_reg) begin
|
||||
dmawad_next_1st <= RXBuf_1stAddr_r1;
|
||||
RoundNumber_next <= 32'h0000_0000;
|
||||
end else if ((state == RX_PACKET3) && (pathindex_inturn[1:0] == 2'b00)) begin
|
||||
// if end of RX buf is arrived, dmawad_next_1st will return to start address at next cycle
|
||||
// if((dmawad_now2_1st + 64'h0000_0000_0000_0080) == (RXBuf_1stAddr_r2+RXBuf_1stSize_r))
|
||||
if((dmawad_now2_1st + 64'h0000_0000_0000_0080) >= (RXBuf_1stAddr_r2+RXBuf_1stSize_r)) begin
|
||||
dmawad_next_1st <= RXBuf_1stAddr_r1;
|
||||
RoundNumber_next <= RoundNumber + 32'h0000_0001;
|
||||
end else begin
|
||||
dmawad_next_1st <= dmawad_now1_1st + 64'h0000_0000_0000_0080;
|
||||
RoundNumber_next <= RoundNumber_next;
|
||||
end
|
||||
end else begin
|
||||
dmawad_next_1st <= dmawad_next_1st;
|
||||
RoundNumber_next <= RoundNumber_next;
|
||||
end
|
||||
end
|
||||
|
||||
// update dmawad_next_2nd and RoundNumber_next_2nd for RX path 2
|
||||
always@(posedge clk) begin
|
||||
if(~buf_inuse_2nd | rst_reg) begin
|
||||
dmawad_next_2nd <= RXBuf_2ndAddr_r1;
|
||||
RoundNumber_next_2nd <= 32'h0000_0000;
|
||||
end else if ((state == RX_PACKET3) && (pathindex_inturn[1:0] == 2'b01)) begin
|
||||
// if end of RX buf is arrived, dmawad_next will return to start address at next cycle
|
||||
// if((dmawad_now2_1st + 64'h0000_0000_0000_0080) == (RXBuf_1stAddr_r2+RXBuf_1stSize_r))
|
||||
if((dmawad_now2_2nd + 64'h0000_0000_0000_0080) >= (RXBuf_2ndAddr_r2+RXBuf_2ndSize_r)) begin
|
||||
dmawad_next_2nd <= RXBuf_2ndAddr_r1;
|
||||
RoundNumber_next_2nd <= RoundNumber_2nd + 32'h0000_0001;
|
||||
end else begin
|
||||
dmawad_next_2nd <= dmawad_now1_2nd + 64'h0000_0000_0000_0080;
|
||||
RoundNumber_next_2nd <= RoundNumber_next_2nd;
|
||||
end
|
||||
end else begin
|
||||
dmawad_next_2nd <= dmawad_next_2nd;
|
||||
RoundNumber_next_2nd <= RoundNumber_next_2nd;
|
||||
end
|
||||
end
|
||||
|
||||
// update dmawad_next_3rd and RoundNumber_next_3rd for RX path 3
|
||||
always@(posedge clk) begin
|
||||
if(~buf_inuse_3rd | rst_reg) begin
|
||||
dmawad_next_3rd <= RXBuf_3rdAddr_r1;
|
||||
RoundNumber_next_3rd <= 32'h0000_0000;
|
||||
end else if ((state == RX_PACKET3) && (pathindex_inturn[1:0] == 2'b10)) begin
|
||||
// if end of RX buf is arrived, dmawad_next will return to start address at next cycle
|
||||
// if((dmawad_now2 + 64'h0000_0000_0000_0080) == (RXBufAddr_r2+RXBufSize_r))
|
||||
if((dmawad_now2_3rd + 64'h0000_0000_0000_0080) >= (RXBuf_3rdAddr_r2+RXBuf_3rdSize_r)) begin
|
||||
dmawad_next_3rd <= RXBuf_3rdAddr_r1;
|
||||
RoundNumber_next_3rd <= RoundNumber_3rd + 32'h0000_0001;
|
||||
end else begin
|
||||
dmawad_next_3rd <= dmawad_now1_3rd + 64'h0000_0000_0000_0080;
|
||||
RoundNumber_next_3rd <= RoundNumber_next_3rd;
|
||||
end
|
||||
end else begin
|
||||
dmawad_next_3rd <= dmawad_next_3rd;
|
||||
RoundNumber_next_3rd <= RoundNumber_next_3rd;
|
||||
end
|
||||
end
|
||||
|
||||
// update dmawad_next_2nd and RoundNumber_next_2nd for RX path 4
|
||||
always@(posedge clk) begin
|
||||
if(~buf_inuse_4th | rst_reg) begin
|
||||
dmawad_next_4th <= RXBuf_4thAddr_r1;
|
||||
RoundNumber_next_4th <= 32'h0000_0000;
|
||||
end else if ((state == RX_PACKET3) && (pathindex_inturn[1:0] == 2'b11)) begin
|
||||
// if end of RX buf is arrived, dmawad_next will return to start address at next cycle
|
||||
// if((dmawad_now2 + 64'h0000_0000_0000_0080) == (RXBufAddr_r2+RXBufSize_r))
|
||||
if((dmawad_now2_4th + 64'h0000_0000_0000_0080) >= (RXBuf_4thAddr_r2+RXBuf_4thSize_r)) begin
|
||||
dmawad_next_4th <= RXBuf_4thAddr_r1;
|
||||
RoundNumber_next_4th <= RoundNumber_4th + 32'h0000_0001;
|
||||
end else begin
|
||||
dmawad_next_4th <= dmawad_now1_4th + 64'h0000_0000_0000_0080;
|
||||
RoundNumber_next_4th <= RoundNumber_next_4th;
|
||||
end
|
||||
end else begin
|
||||
dmawad_next_4th <= dmawad_next_4th;
|
||||
RoundNumber_next_4th <= RoundNumber_next_4th;
|
||||
end
|
||||
end
|
||||
|
||||
// update dmawad_now for RX path 1
|
||||
always@(posedge clk)begin
|
||||
if(state == IDLE)begin
|
||||
dmawad_now1_1st <= dmawad_next_1st;
|
||||
dmawad_now2_1st <= dmawad_next_1st;
|
||||
RoundNumber <= RoundNumber_next;
|
||||
end else begin
|
||||
dmawad_now1_1st <= dmawad_now1_1st;
|
||||
dmawad_now2_1st <= dmawad_now2_1st;
|
||||
RoundNumber <= RoundNumber;
|
||||
end
|
||||
end
|
||||
|
||||
// update dmawad_now_2nd for RX path 2
|
||||
always@(posedge clk)begin
|
||||
if(state == IDLE)begin
|
||||
dmawad_now1_2nd <= dmawad_next_2nd;
|
||||
dmawad_now2_2nd <= dmawad_next_2nd;
|
||||
RoundNumber_2nd <= RoundNumber_next_2nd;
|
||||
end else begin
|
||||
dmawad_now1_2nd <= dmawad_now1_2nd;
|
||||
dmawad_now2_2nd <= dmawad_now2_2nd;
|
||||
RoundNumber_2nd <= RoundNumber_2nd;
|
||||
end
|
||||
end
|
||||
|
||||
// update dmawad_now_3rd for RX path 3
|
||||
always@(posedge clk)begin
|
||||
if(state == IDLE)begin
|
||||
dmawad_now1_3rd <= dmawad_next_3rd;
|
||||
dmawad_now2_3rd <= dmawad_next_3rd;
|
||||
RoundNumber_3rd <= RoundNumber_next_3rd;
|
||||
end else begin
|
||||
dmawad_now1_3rd <= dmawad_now1_3rd;
|
||||
dmawad_now2_3rd <= dmawad_now2_3rd;
|
||||
RoundNumber_3rd <= RoundNumber_3rd;
|
||||
end
|
||||
end
|
||||
|
||||
// update dmawad_now_4th for RX path 4
|
||||
always@(posedge clk)begin
|
||||
if(state == IDLE)begin
|
||||
dmawad_now1_4th <= dmawad_next_4th;
|
||||
dmawad_now2_4th <= dmawad_next_4th;
|
||||
RoundNumber_4th <= RoundNumber_next_4th;
|
||||
end else begin
|
||||
dmawad_now1_4th <= dmawad_now1_4th;
|
||||
dmawad_now2_4th <= dmawad_now2_4th;
|
||||
RoundNumber_4th <= RoundNumber_4th;
|
||||
end
|
||||
end
|
||||
|
||||
// dmawad output
|
||||
always@(posedge clk) begin
|
||||
if(rst_reg) begin
|
||||
dmawad <= 64'h0000_0000_0000_0000;
|
||||
end else if (state == TX_DESC_WRITE_BACK) begin
|
||||
dmawad <= DescAddr;
|
||||
end else if (state == RX_CLEAR) begin
|
||||
if (pathindex_inturn[1] == 1'b0) begin
|
||||
if (pathindex_inturn[0] == 1'b0) begin // pathindex_inturn == 2'b00
|
||||
if((dmawad_now2_1st + 64'h0000_0000_0000_0080) >= (RXBuf_1stAddr_r2+RXBuf_1stSize_r)) begin
|
||||
dmawad <= RXBuf_1stAddr_r1;
|
||||
end else begin
|
||||
dmawad <= dmawad_now1_1st + 64'h0000_0000_0000_0080;
|
||||
end
|
||||
end else begin // pathindex_inturn == 2'b01
|
||||
if((dmawad_now2_2nd + 64'h0000_0000_0000_0080) >= (RXBuf_2ndAddr_r2+RXBuf_2ndSize_r)) begin
|
||||
dmawad <= RXBuf_2ndAddr_r1;
|
||||
end else begin
|
||||
dmawad <= dmawad_now1_2nd + 64'h0000_0000_0000_0080;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
if (pathindex_inturn[0] == 1'b0) begin // pathindex_inturn == 2'b10
|
||||
if((dmawad_now2_3rd + 64'h0000_0000_0000_0080) >= (RXBuf_3rdAddr_r2+RXBuf_3rdSize_r)) begin
|
||||
dmawad <= RXBuf_3rdAddr_r1;
|
||||
end else begin
|
||||
dmawad <= dmawad_now1_3rd + 64'h0000_0000_0000_0080;
|
||||
end
|
||||
end else begin // pathindex_inturn == 2'b11
|
||||
if((dmawad_now2_4th + 64'h0000_0000_0000_0080) >= (RXBuf_4thAddr_r2+RXBuf_4thSize_r)) begin
|
||||
dmawad <= RXBuf_4thAddr_r1;
|
||||
end else begin
|
||||
dmawad <= dmawad_now1_4th + 64'h0000_0000_0000_0080;
|
||||
end
|
||||
end
|
||||
end
|
||||
end else if (state == RX_PACKET) begin // calculation
|
||||
dmawad <= (pathindex_inturn[1] == 1'b0) ?
|
||||
( (pathindex_inturn[0] == 1'b0) ?
|
||||
dmawad_now1_1st + 64'h0000_0000_0000_0010 : dmawad_now1_2nd + 64'h0000_0000_0000_0010
|
||||
)
|
||||
: ( (pathindex_inturn[0] == 1'b0) ?
|
||||
dmawad_now1_3rd + 64'h0000_0000_0000_0010 : dmawad_now1_4th + 64'h0000_0000_0000_0010
|
||||
);
|
||||
end else if (state == RX_DESC) begin
|
||||
dmawad <= (pathindex_inturn[1] == 1'b0) ?
|
||||
( (pathindex_inturn[0] == 1'b0) ?
|
||||
dmawad_now1_1st : dmawad_now1_2nd
|
||||
)
|
||||
: ( (pathindex_inturn[0] == 1'b0) ?
|
||||
dmawad_now1_3rd : dmawad_now1_4th
|
||||
);
|
||||
end else begin
|
||||
dmawad <= dmawad;
|
||||
end
|
||||
end
|
||||
|
||||
// length output value from state machine
|
||||
always@(posedge clk) begin
|
||||
if(rst_reg)
|
||||
length_byte[12:0] <= 13'h0000;
|
||||
else if (state == TX_DESC_WRITE_BACK)
|
||||
length_byte[12:0] <= TX_DESC_SIZE_BYTES[12:0];
|
||||
else if (state == RX_CLEAR)
|
||||
length_byte[12:0] <= RX_DESC_SIZE_BYTES[12:0];
|
||||
else if (state == RX_PACKET)
|
||||
length_byte[12:0] <= frame_size_bytes[12:0];
|
||||
else if (state == RX_DESC)
|
||||
length_byte[12:0] <= RX_DESC_SIZE_BYTES[12:0];
|
||||
else
|
||||
length_byte <= length_byte;
|
||||
end
|
||||
|
||||
assign length[9:0] = length_byte[11:2];
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,175 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 06/01/2009
|
||||
// Design Name:
|
||||
// Module Name: read_req_wrapper
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose: A wrapper which contains a RAM with read request information
|
||||
// (dualport_32x32_compram) and a small shadow RAM which qualifies the
|
||||
// entries in the dualport_32x32_compram
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
`include "Sora_config.v"
|
||||
|
||||
module read_req_wrapper(
|
||||
input clk,
|
||||
input rst,
|
||||
`ifdef TF_RECOVERY
|
||||
input transferstart, // Jiansong: control signal for transfer recovering
|
||||
`endif
|
||||
input [4:0] tx_waddr,
|
||||
input [31:0] tx_wdata,
|
||||
input tx_we,
|
||||
input [4:0] rx_waddr,
|
||||
input [31:0] rx_wdata,
|
||||
input rx_we,
|
||||
input [4:0] rx_raddr,
|
||||
output [31:0] rx_rdata,
|
||||
input pending_comp_done, /// Jiansong: for what purpose?
|
||||
output [31:0] completion_pending,
|
||||
output comp_timeout
|
||||
);
|
||||
|
||||
|
||||
reg we;
|
||||
reg [4:0] wr_addr;
|
||||
reg [31:0] wr_data;
|
||||
|
||||
reg [4:0] wr_addr_r;
|
||||
wire [4:0] wr_addr_rst;
|
||||
reg pending_data;
|
||||
|
||||
//32x32 dual-port distributed ram built with CoreGen
|
||||
//this ram holds completion information for the RX engine
|
||||
//provided from the TX engine
|
||||
//The tag from outgoing non-posted memory read requests is
|
||||
//used as the address to the ram. The data stored in the
|
||||
//32-bit data window is as follows
|
||||
// bits 21 - 0 = ddr2 destination address (6 LSBs not stored)
|
||||
// 31 - 22 = length in DWORDs of the request
|
||||
//
|
||||
//Both the RX and TX engines have write access to this ram
|
||||
//The TX engine writes the initial information and the RX engine
|
||||
//updates the DDR2 address as the completion packets are serviced
|
||||
//In order to share the write port a simple protocol is followed
|
||||
// 1. TX engine has priority over RX engine
|
||||
// 2. TX engine writes are always a single-cycle and cannot occur in
|
||||
// consecutive cycles
|
||||
// 3. RX engine writes are always double-cycle
|
||||
|
||||
always@(posedge clk) begin
|
||||
`ifdef TF_RECOVERY
|
||||
if (rst | (~transferstart))
|
||||
`else
|
||||
if (rst)
|
||||
`endif
|
||||
wr_addr_r[4:0] <= wr_addr_r[4:0] + 5'b00001;
|
||||
else
|
||||
wr_addr_r[4:0] <= 5'b00000;
|
||||
end
|
||||
|
||||
assign wr_addr_rst = wr_addr_r;
|
||||
|
||||
/// Jiansong: reset logic added. clear the rams
|
||||
// always@(*)begin
|
||||
always@(posedge clk)begin
|
||||
`ifdef TF_RECOVERY
|
||||
if(rst | (~transferstart))begin
|
||||
`else
|
||||
if(rst)begin
|
||||
`endif
|
||||
wr_addr[4:0] <= wr_addr_rst[4:0];
|
||||
we <= 1'b1;
|
||||
wr_data[31:0] <= 32'h0000_0000;
|
||||
pending_data <= 1'b0;
|
||||
end else if(tx_we)begin
|
||||
wr_addr[4:0] <= tx_waddr[4:0];
|
||||
we <= tx_we;
|
||||
wr_data[31:0] <= tx_wdata[31:0];
|
||||
pending_data <= 1'b1;
|
||||
end else begin
|
||||
wr_addr[4:0] <= rx_waddr[4:0];
|
||||
we <= rx_we;
|
||||
wr_data[31:0] <= rx_wdata[31:0];
|
||||
pending_data <= ~pending_comp_done;
|
||||
end
|
||||
end
|
||||
|
||||
dualport_32x32_compram dualport_32x32_compram_inst(
|
||||
.a(wr_addr[4:0]),
|
||||
.d(wr_data[31:0]),
|
||||
.dpra(rx_raddr[4:0]),
|
||||
.clk(clk),
|
||||
.we(we),
|
||||
.spo(),
|
||||
.dpo(rx_rdata[31:0])
|
||||
);
|
||||
|
||||
//A small 32x1 shadow ram to qualify the entries in the dualport
|
||||
//This ram has an addressable write port, the read data port is not
|
||||
//addressable, i.e. all 32 bits are present. The data stored represents
|
||||
//whether the dual-port ram contains a valid entry or not. The tx engine
|
||||
//sets the bit when writing to the dualport ram - the rx engine clears it
|
||||
//when the final completion packet has been received.
|
||||
//Same protocol rules as dual-port ram for writes
|
||||
|
||||
pending_comp_ram_32x1 pending_comp_ram_32x1_inst(
|
||||
.clk(clk),
|
||||
// .d_in((tx_we)?1'b1:~pending_comp_done),
|
||||
.d_in(pending_data),
|
||||
.addr(wr_addr[4:0]),
|
||||
.we(we),
|
||||
.d_out(completion_pending[31:0])
|
||||
);
|
||||
|
||||
completion_timeout completion_timeout_inst(
|
||||
.clk(clk),
|
||||
`ifdef TF_RECOVERY
|
||||
.rst(rst | (~transferstart)),
|
||||
`else
|
||||
.rst(rst),
|
||||
`endif
|
||||
.pending_req(completion_pending[31:0]),
|
||||
.comp_timeout(comp_timeout)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,70 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 06/01/2009
|
||||
// Design Name:
|
||||
// Module Name: tx_engine
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose: Detects rising edge of input signal and outputs a single-shot
|
||||
// signal upon detection
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
module rising_edge_detect(
|
||||
input clk,
|
||||
input rst,
|
||||
input in,
|
||||
output one_shot_out);
|
||||
|
||||
reg in_reg;
|
||||
|
||||
//register the input
|
||||
always@(posedge clk)begin
|
||||
if(rst)begin
|
||||
in_reg <= 1'b0;
|
||||
end else begin
|
||||
in_reg <= in;
|
||||
end
|
||||
end
|
||||
|
||||
//detect the rising edge
|
||||
assign one_shot_out = ~in_reg & in;
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,490 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 06/01/2009
|
||||
// Design Name:
|
||||
// Module Name: rx_engine
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose: RX Engine Wrapper file. Connects all of the individual modules
|
||||
// and FIFOs that interface between the Block Plus LogiCore and the DMA-DDR
|
||||
// Interface Block (dma_ddr2_if)
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
// modified by Jiansong Zhang:
|
||||
// (1)add 1 bit to differentiate TX descriptor from normal data ---- done
|
||||
// (2)TX des parser ------------------------------------------------ done
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
`include "Sora_config.v"
|
||||
|
||||
module rx_engine(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
//interface to dma_ddr2_if
|
||||
output wire [127:0] ingress_data,
|
||||
// output wire [1:0] ingress_fifo_ctrl, //bit 1 = unused bit 0 = write_en
|
||||
output ingress_fifo_wren,
|
||||
// input wire [1:0] ingress_fifo_status, //bit 1 = full bit 0 = almostfull
|
||||
output wire [2:0] ingress_xfer_size,
|
||||
output wire [27:6] ingress_start_addr,
|
||||
output wire ingress_data_req,
|
||||
input wire ingress_data_ack,
|
||||
//interface to dma_ctrl_wrapper
|
||||
input wire rd_dma_start, //indicates the start of a read dma xfer
|
||||
input wire [31:0] dmarad, //destination addres(ddr2) only 13 bits used /// why put destination here?
|
||||
input wire [31:0] dmarxs,
|
||||
output wire rd_dma_done, //dma transfer complete /// Jiansong: it's fake? not fake
|
||||
///Jiansong: interface to dma control wrapper
|
||||
output new_des_one,
|
||||
output wire [31:0] SourceAddr_L,
|
||||
output wire [31:0] SourceAddr_H,
|
||||
output wire [31:0] DestAddr,
|
||||
output wire [23:0] FrameSize,
|
||||
output wire [7:0] FrameControl,
|
||||
/// Jiansong: interface from dma control wrapper
|
||||
input wire Wait_for_TX_desc,
|
||||
`ifdef TF_RECOVERY
|
||||
input wire transferstart, // control signal for transfer recovering
|
||||
`endif
|
||||
//interface to read_request_wrapper
|
||||
output [4:0] rx_waddr,
|
||||
output [31:0] rx_wdata,
|
||||
output rx_we,
|
||||
output [4:0] rx_raddr,
|
||||
input [31:0] rx_rdata,
|
||||
output pending_comp_done,
|
||||
input [31:0] completion_pending,
|
||||
//interface from PCIe Endpoint Block Plus - RX TRN
|
||||
input wire [63:0] trn_rd,
|
||||
input wire [7:0] trn_rrem_n,
|
||||
input wire trn_rsof_n,
|
||||
input wire trn_reof_n,
|
||||
input wire trn_rsrc_rdy_n,
|
||||
input wire trn_rsrc_dsc_n,
|
||||
output wire trn_rdst_rdy_n,
|
||||
input wire trn_rerrfwd_n,
|
||||
output wire trn_rnp_ok_n,
|
||||
input wire [6:0] trn_rbar_hit_n,
|
||||
input wire [11:0] trn_rfc_npd_av,
|
||||
input wire [7:0] trn_rfc_nph_av,
|
||||
input wire [11:0] trn_rfc_pd_av,
|
||||
input wire [7:0] trn_rfc_ph_av,
|
||||
input wire [11:0] trn_rfc_cpld_av,
|
||||
input wire [7:0] trn_rfc_cplh_av,
|
||||
output wire trn_rcpl_streaming_n,
|
||||
//interface to TX Engine (completer_pkt_gen)
|
||||
output wire [6:0] bar_hit_o,
|
||||
output wire MRd_o,
|
||||
output wire MWr_o,
|
||||
output wire [31:0] MEM_addr_o,
|
||||
output wire [15:0] MEM_req_id_o,
|
||||
output wire [7:0] MEM_tag_o,
|
||||
output wire header_fields_valid_o,
|
||||
output wire [31:0] write_data,
|
||||
output wire write_data_wren,
|
||||
input wire read_last
|
||||
/// Jiansong: output to tx_sm
|
||||
// output wire [9:0] np_rx_cnt_qw
|
||||
// /// Jiansong: debug register
|
||||
// output [9:0] Debug30RXEngine,
|
||||
// output reg [11:0] Debug31RXDataFIFOfullcnt,
|
||||
// output reg [11:0] Debug32RXXferFIFOfullcnt,
|
||||
// output reg [23:0] Debug33RXDataFIFOWRcnt,
|
||||
// output reg [23:0] Debug34RXDataFIFORDcnt,
|
||||
// output reg [23:0] Debug35RXXferFIFOWRcnt,
|
||||
// output reg [23:0] Debug36RXXferFIFORDcnt
|
||||
);
|
||||
|
||||
|
||||
wire [27:6] mem_dest_addr;
|
||||
wire [10:0] mem_dma_size;
|
||||
wire mem_dma_start;
|
||||
|
||||
wire [63:0] write_data_fifo_data;
|
||||
wire write_data_fifo_cntrl;
|
||||
wire write_data_fifo_status;
|
||||
wire [127:0] read_data_fifo_data;
|
||||
wire read_data_fifo_cntrl;
|
||||
wire read_data_fifo_status;
|
||||
|
||||
wire fourdw_n_threedw; //fourdw = 1'b1; 3dw = 1'b0;
|
||||
wire payload;
|
||||
wire [2:0] tc;
|
||||
wire td;
|
||||
wire ep;
|
||||
wire [1:0] attr;
|
||||
wire [9:0] dw_length;
|
||||
wire [15:0] MEM_req_id;
|
||||
wire [7:0] MEM_tag;
|
||||
wire [15:0] CMP_comp_id;
|
||||
wire [2:0] CMP_compl_stat;
|
||||
wire CMP_bcm;
|
||||
wire [11:0] CMP_byte_count;
|
||||
wire [63:0] MEM_addr;
|
||||
wire [15:0] CMP_req_id;
|
||||
wire [7:0] CMP_tag;
|
||||
wire [6:0] CMP_lower_addr;
|
||||
wire MRd;
|
||||
wire MWr;
|
||||
wire CplD;
|
||||
reg CplD_r; // Jiansong: pipeline register to solve Mrd write to fifo bug
|
||||
wire Msg;
|
||||
wire UR;
|
||||
wire [6:0] bar_hit;
|
||||
wire header_fields_valid;
|
||||
|
||||
reg [63:0] trn_rd_reg;
|
||||
reg [7:0] trn_rrem_reg_n;
|
||||
reg trn_rsof_reg_n;
|
||||
reg trn_reof_reg_n;
|
||||
reg trn_rsrc_rdy_reg_n;
|
||||
reg trn_rsrc_dsc_reg_n;
|
||||
reg trn_rerrfwd_reg_n;
|
||||
reg [6:0] trn_rbar_hit_reg_n;
|
||||
reg [11:0] trn_rfc_npd_av_reg;
|
||||
reg [7:0] trn_rfc_nph_av_reg;
|
||||
reg [11:0] trn_rfc_pd_av_reg;
|
||||
reg [7:0] trn_rfc_ph_av_reg;
|
||||
reg [11:0] trn_rfc_cpld_av_reg;
|
||||
reg [7:0] trn_rfc_cplh_av_reg;
|
||||
|
||||
wire read_xfer_fifo_status;
|
||||
wire write_xfer_fifo_status;
|
||||
wire xfer_trn_mem_fifo_rden;
|
||||
wire [27:6] mem_dest_addr_fifo;
|
||||
wire [10:0] mem_dma_size_fifo;
|
||||
|
||||
/// Jiansong: added for TX des
|
||||
wire isDes;
|
||||
wire isDes_fifo;
|
||||
|
||||
//assign some outputs
|
||||
assign bar_hit_o[6:0] = bar_hit[6:0];
|
||||
assign MRd_o = MRd;
|
||||
assign MWr_o = MWr;
|
||||
assign MEM_addr_o[31:0] = MEM_addr[31:0];
|
||||
assign MEM_req_id_o[15:0] = MEM_req_id[15:0];
|
||||
assign MEM_tag_o[7:0] = MEM_tag[7:0];
|
||||
assign header_fields_valid_o = header_fields_valid;
|
||||
//send the write data info and wren enable signal out to write Posted MemWr
|
||||
//data to the dma_ctrl_wrapper (or any other target block for that matter)
|
||||
assign write_data[31:0] = write_data_fifo_data[31:0];
|
||||
assign write_data_wren = write_data_fifo_cntrl;
|
||||
|
||||
//all the outputs of the endpoint need to be pipelined
|
||||
//to meet 250 MHz timing of an 8 lane design
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
trn_rd_reg[63:0] <= trn_rd[63:0] ;
|
||||
trn_rrem_reg_n[7:0] <= trn_rrem_n[7:0] ;
|
||||
trn_rsof_reg_n <= trn_rsof_n ;
|
||||
trn_reof_reg_n <= trn_reof_n ;
|
||||
trn_rsrc_rdy_reg_n <= trn_rsrc_rdy_n ;
|
||||
trn_rsrc_dsc_reg_n <= trn_rsrc_dsc_n ;
|
||||
trn_rerrfwd_reg_n <= trn_rerrfwd_n ;
|
||||
trn_rbar_hit_reg_n[6:0] <= trn_rbar_hit_n[6:0] ;
|
||||
trn_rfc_npd_av_reg[11:0] <= trn_rfc_npd_av[11:0] ;
|
||||
trn_rfc_nph_av_reg[7:0] <= trn_rfc_nph_av[7:0] ;
|
||||
trn_rfc_pd_av_reg[11:0] <= trn_rfc_pd_av[11:0] ;
|
||||
trn_rfc_ph_av_reg[7:0] <= trn_rfc_ph_av[7:0] ;
|
||||
trn_rfc_cpld_av_reg[11:0] <= trn_rfc_cpld_av[11:0];
|
||||
trn_rfc_cplh_av_reg[7:0] <= trn_rfc_cplh_av[7:0] ;
|
||||
end
|
||||
|
||||
|
||||
|
||||
//Instantiate the Receive TRN Monitor block
|
||||
//This module interfaces to the DMA
|
||||
//Control/Status Register File and the Read Request Fifo to determine when a
|
||||
//DMA transfer has completed fully.
|
||||
rx_trn_monitor rx_trn_monitor_inst(
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
// interface to dma_ctrl_wrapper
|
||||
.rd_dma_start (rd_dma_start),
|
||||
.dmarad (dmarad[31:0]),
|
||||
.dmarxs (dmarxs[31:0]),
|
||||
.rd_dma_done (rd_dma_done),
|
||||
.read_last (read_last),
|
||||
///Jiansong: signal from dma control wrapper
|
||||
.Wait_for_TX_desc (Wait_for_TX_desc),
|
||||
`ifdef TF_RECOVERY
|
||||
.transferstart (transferstart),
|
||||
`endif
|
||||
//interface to read_request_wrapper
|
||||
.rx_waddr (rx_waddr[4:0]),
|
||||
.rx_wdata (rx_wdata[31:0]),
|
||||
.rx_we (rx_we),
|
||||
.rx_raddr (rx_raddr[4:0]),
|
||||
.rx_rdata(rx_rdata[31:0]),
|
||||
.pending_comp_done(pending_comp_done),
|
||||
.completion_pending(completion_pending[31:0]),
|
||||
//PCIe Endpoint Block Plus interface
|
||||
// RX TRN
|
||||
.trn_rd (trn_rd_reg), // I [63/31:0]
|
||||
.trn_rrem_n (trn_rrem_reg_n), // I [7:0]
|
||||
.trn_rsof_n (trn_rsof_reg_n), // I
|
||||
.trn_reof_n (trn_reof_reg_n), // I
|
||||
.trn_rsrc_rdy_n (trn_rsrc_rdy_reg_n), // I
|
||||
.trn_rsrc_dsc_n (trn_rsrc_dsc_reg_n), // I
|
||||
.trn_rerrfwd_n (trn_rerrfwd_reg_n), // I
|
||||
.trn_rbar_hit_n (trn_rbar_hit_reg_n), // I [6:0]
|
||||
.trn_rfc_npd_av (trn_rfc_npd_av_reg), // I [11:0]
|
||||
.trn_rfc_nph_av (trn_rfc_nph_av_reg), // I [7:0]
|
||||
.trn_rfc_pd_av (trn_rfc_pd_av_reg), // I [11:0]
|
||||
.trn_rfc_ph_av (trn_rfc_ph_av_reg), // I [7:0]
|
||||
.trn_rfc_cpld_av (trn_rfc_cpld_av_reg),// I [11:0]
|
||||
.trn_rfc_cplh_av (trn_rfc_cplh_av_reg),// I [7:0]
|
||||
//interface from rx_trn_data_fsm
|
||||
.fourdw_n_threedw (fourdw_n_threedw),
|
||||
.payload (payload),
|
||||
.tc (tc[2:0]),
|
||||
.td (td),
|
||||
.ep (ep),
|
||||
.attr (attr[1:0]),
|
||||
.dw_length (dw_length[9:0]),
|
||||
.MEM_req_id (MEM_req_id[15:0]),
|
||||
.MEM_tag (MEM_tag[7:0]),
|
||||
.CMP_comp_id (CMP_comp_id[15:0]),
|
||||
.CMP_compl_stat (CMP_compl_stat[2:0]),
|
||||
.CMP_bcm (CMP_bcm),
|
||||
.CMP_byte_count (CMP_byte_count[11:0]),
|
||||
.MEM_addr (MEM_addr[63:0]),
|
||||
.CMP_req_id (CMP_req_id[15:0]),
|
||||
.CMP_tag (CMP_tag[7:0]),
|
||||
.CMP_lower_addr (CMP_lower_addr[6:0]),
|
||||
.MRd (MRd),
|
||||
.MWr (MWr),
|
||||
.CplD (CplD),
|
||||
.Msg (Msg),
|
||||
.UR (UR),
|
||||
.header_fields_valid(header_fields_valid),
|
||||
.data_valid (write_data_fifo_cntrl),
|
||||
//Outputs to xfer_trn_mem_fifo
|
||||
.isDes (isDes), ///Jiansong: added for TX des
|
||||
.mem_dest_addr (mem_dest_addr),
|
||||
.mem_dma_size (mem_dma_size),
|
||||
.mem_dma_start (mem_dma_start)
|
||||
// Jiansong: output to tx_sm
|
||||
// .np_rx_cnt_qw (np_rx_cnt_qw)
|
||||
// Debug output
|
||||
// .Debug30RXEngine (Debug30RXEngine)
|
||||
);
|
||||
|
||||
//Instantiate the Recieve TRN State Machine
|
||||
//This module interfaces to the Block Plus RX
|
||||
//TRN. It presents the 64-bit data from completer and and forwards that
|
||||
//data with a data_valid signal. This block also decodes packet header info
|
||||
//and forwards it to the rx_trn_monitor block.
|
||||
rx_trn_data_fsm rx_trn_data_fsm_inst(
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
// Rx Local-Link from PCIe Endpoint Block Plus
|
||||
.trn_rd (trn_rd_reg), // I [63/31:0]
|
||||
.trn_rrem_n (trn_rrem_reg_n), // I [7:0]
|
||||
.trn_rsof_n (trn_rsof_reg_n), // I
|
||||
.trn_reof_n (trn_reof_reg_n), // I
|
||||
.trn_rsrc_rdy_n (trn_rsrc_rdy_reg_n), // I
|
||||
.trn_rsrc_dsc_n (trn_rsrc_dsc_reg_n), // I
|
||||
.trn_rdst_rdy_n (trn_rdst_rdy_n), // O
|
||||
.trn_rerrfwd_n (trn_rerrfwd_reg_n), // I
|
||||
.trn_rnp_ok_n (trn_rnp_ok_n), // O
|
||||
.trn_rbar_hit_n (trn_rbar_hit_reg_n), // I [6:0]
|
||||
.trn_rfc_npd_av (trn_rfc_npd_av_reg), // I [11:0]
|
||||
.trn_rfc_nph_av (trn_rfc_nph_av_reg), // I [7:0]
|
||||
.trn_rfc_pd_av (trn_rfc_pd_av_reg), // I [11:0]
|
||||
.trn_rfc_ph_av (trn_rfc_ph_av_reg), // I [7:0]
|
||||
.trn_rfc_cpld_av (trn_rfc_cpld_av_reg), // I [11:0]
|
||||
.trn_rfc_cplh_av (trn_rfc_cplh_av_reg), // I [7:0]
|
||||
.trn_rcpl_streaming_n(trn_rcpl_streaming_n), // O
|
||||
//Data write signals for writing completion data to the data_trn_mem_fifo
|
||||
//or for writing data to targets memories. Could easily demux using bar_hit
|
||||
//signals to steer the data to different locations
|
||||
.data_out (write_data_fifo_data[63:0]),
|
||||
.data_out_be (),
|
||||
.data_valid (write_data_fifo_cntrl),
|
||||
.data_fifo_status (write_data_fifo_status),
|
||||
//Header field signals
|
||||
//interfaced to rx_trn_monitor
|
||||
.fourdw_n_threedw (fourdw_n_threedw),
|
||||
.payload (payload),
|
||||
.tc (tc[2:0]),
|
||||
.td (td),
|
||||
.ep (ep),
|
||||
.attr (attr[1:0]),
|
||||
.dw_length (dw_length[9:0]),
|
||||
.MEM_req_id (MEM_req_id[15:0]),
|
||||
.MEM_tag (MEM_tag[7:0]),
|
||||
.CMP_comp_id (CMP_comp_id[15:0]),
|
||||
.CMP_compl_stat (CMP_compl_stat[2:0]),
|
||||
.CMP_bcm (CMP_bcm),
|
||||
.CMP_byte_count (CMP_byte_count[11:0]),
|
||||
.MEM_addr (MEM_addr[63:0]),
|
||||
.CMP_req_id (CMP_req_id[15:0]),
|
||||
.CMP_tag (CMP_tag[7:0]),
|
||||
.CMP_lower_addr (CMP_lower_addr[6:0]),
|
||||
.MRd (MRd),
|
||||
.MWr (MWr),
|
||||
.CplD (CplD),
|
||||
.Msg (Msg),
|
||||
.UR (UR),
|
||||
.bar_hit (bar_hit[6:0]),
|
||||
.header_fields_valid(header_fields_valid)
|
||||
);
|
||||
|
||||
always@(posedge clk) CplD_r <= CplD;
|
||||
|
||||
//Instantiate the Data TRN Mem FIFO
|
||||
//This is an 8KB FIFO constructed of BRAM
|
||||
//Provides additional buffering in case the dma_ddr2_if is busy with
|
||||
//egress. Also, converts the datapath from 64-bit to 128 bit
|
||||
data_trn_mem_fifo data_trn_mem_fifo_inst(
|
||||
.din (write_data_fifo_data[63:0]),
|
||||
.rd_clk (clk),
|
||||
.rd_en (read_data_fifo_cntrl),
|
||||
.rst (rst),
|
||||
.wr_clk (clk),
|
||||
// .wr_en (write_data_fifo_cntrl & CplD),
|
||||
.wr_en (write_data_fifo_cntrl & CplD_r), // Jiansong: slove Mrd write to data fifo bug
|
||||
//by swapping the DWORD order on dout we get /// Jiansong: swapping is necessary?
|
||||
// read_data_fifo_data[127:0] =
|
||||
// B15,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1,B0
|
||||
.dout ({read_data_fifo_data[63:0],read_data_fifo_data[127:64]}),
|
||||
.empty (read_data_fifo_status),
|
||||
.full (write_data_fifo_status) /// Jiansong: no control here
|
||||
);
|
||||
|
||||
|
||||
//Instantiate the Xfer TRN Mem FIFO
|
||||
//This is an 34X128 FIFO constructed of Distributed RAM
|
||||
xfer_trn_mem_fifo xfer_trn_mem_fifo_inst(
|
||||
.din ({isDes,mem_dest_addr[27:6],mem_dma_size[10:0]}),
|
||||
.clk (clk),
|
||||
.rd_en (xfer_trn_mem_fifo_rden),
|
||||
.rst (rst),
|
||||
.wr_en (mem_dma_start),
|
||||
.dout ({isDes_fifo,mem_dest_addr_fifo[27:6],mem_dma_size_fifo[10:0]}),
|
||||
.empty (read_xfer_fifo_status),
|
||||
.full (write_xfer_fifo_status) /// Jiansong: no control here
|
||||
);
|
||||
|
||||
//// Jiansong: Debug register out
|
||||
//always@(posedge clk)begin
|
||||
// if (rst)
|
||||
// Debug31RXDataFIFOfullcnt <= 32'h0000_0000;
|
||||
// else if (write_data_fifo_status)
|
||||
// Debug31RXDataFIFOfullcnt <= Debug31RXDataFIFOfullcnt + 1'b1;
|
||||
// else
|
||||
// Debug31RXDataFIFOfullcnt <= Debug31RXDataFIFOfullcnt;
|
||||
//end
|
||||
//always@(posedge clk)begin
|
||||
// if (rst)
|
||||
// Debug32RXXferFIFOfullcnt <= 32'h0000_0000;
|
||||
// else if (write_xfer_fifo_status)
|
||||
// Debug32RXXferFIFOfullcnt <= Debug32RXXferFIFOfullcnt + 1'b1;
|
||||
// else
|
||||
// Debug32RXXferFIFOfullcnt <= Debug32RXXferFIFOfullcnt;
|
||||
//end
|
||||
//always@(posedge clk)begin
|
||||
// if (rst)
|
||||
// Debug33RXDataFIFOWRcnt <= 32'h0000_0000;
|
||||
// else if (write_data_fifo_cntrl & CplD)
|
||||
// Debug33RXDataFIFOWRcnt <= Debug33RXDataFIFOWRcnt + 1'b1;
|
||||
// else
|
||||
// Debug33RXDataFIFOWRcnt <= Debug33RXDataFIFOWRcnt;
|
||||
//end
|
||||
//always@(posedge clk)begin
|
||||
// if (rst)
|
||||
// Debug34RXDataFIFORDcnt <= 32'h0000_0000;
|
||||
// else if (read_data_fifo_cntrl)
|
||||
// Debug34RXDataFIFORDcnt <= Debug34RXDataFIFORDcnt + 1'b1;
|
||||
// else
|
||||
// Debug34RXDataFIFORDcnt <= Debug34RXDataFIFORDcnt;
|
||||
//end
|
||||
//always@(posedge clk)begin
|
||||
// if (rst)
|
||||
// Debug35RXXferFIFOWRcnt <= 32'h0000_0000;
|
||||
// else if (mem_dma_start)
|
||||
// Debug35RXXferFIFOWRcnt <= Debug35RXXferFIFOWRcnt + 1'b1;
|
||||
// else
|
||||
// Debug35RXXferFIFOWRcnt <= Debug35RXXferFIFOWRcnt;
|
||||
//end
|
||||
//always@(posedge clk)begin
|
||||
// if (rst)
|
||||
// Debug36RXXferFIFORDcnt <= 32'h0000_0000;
|
||||
// else if (xfer_trn_mem_fifo_rden)
|
||||
// Debug36RXXferFIFORDcnt <= Debug36RXXferFIFORDcnt + 1'b1;
|
||||
// else
|
||||
// Debug36RXXferFIFORDcnt <= Debug36RXXferFIFORDcnt;
|
||||
//end
|
||||
|
||||
//Instantiate the Receive Memory Data State Machine
|
||||
rx_mem_data_fsm rx_mem_data_fsm_inst(
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
//interface to dma_ddr2_if block
|
||||
.ingress_data (ingress_data),
|
||||
// .ingress_fifo_ctrl (ingress_fifo_ctrl),
|
||||
.ingress_fifo_wren (ingress_fifo_wren),
|
||||
// .ingress_fifo_status (ingress_fifo_status),
|
||||
.ingress_xfer_size (ingress_xfer_size),
|
||||
.ingress_start_addr (ingress_start_addr),
|
||||
.ingress_data_req (ingress_data_req),
|
||||
.ingress_data_ack (ingress_data_ack),
|
||||
//interface to xfer_trn_mem_fifo
|
||||
.isDes_fifo(isDes_fifo), /// Jiansong: added for TX des
|
||||
.mem_dest_addr_fifo (mem_dest_addr_fifo),
|
||||
.mem_dma_size_fifo (mem_dma_size_fifo),
|
||||
.mem_dma_start (1'b0),
|
||||
.mem_trn_fifo_empty (read_xfer_fifo_status),
|
||||
.mem_trn_fifo_rden (xfer_trn_mem_fifo_rden),
|
||||
//interface to data_trn_mem_fifo
|
||||
.data_fifo_data (read_data_fifo_data[127:0]),
|
||||
.data_fifo_cntrl (read_data_fifo_cntrl),
|
||||
.data_fifo_status (read_data_fifo_status),
|
||||
///Jiansong: interface to dma control wrapper
|
||||
.new_des_one(new_des_one),
|
||||
.SourceAddr_L(SourceAddr_L),
|
||||
.SourceAddr_H(SourceAddr_H),
|
||||
.DestAddr(DestAddr),
|
||||
.FrameSize(FrameSize),
|
||||
.FrameControl(FrameControl)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,352 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 06/01/2009
|
||||
// Design Name:
|
||||
// Module Name: rx_mem_data_fsm
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose: Receive Memory Data State Machine module. This module takes the
|
||||
// data from the width conversion fifo (data_trn_mem_fifo) and send it into the
|
||||
// dma_ddr2_if block
|
||||
// that passes the data off to the MIG memory controller to write to the DDR2
|
||||
// memory.
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
// modified by Jiansong Zhang
|
||||
// add TX descriptor handling here ---------------- done
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
|
||||
module rx_mem_data_fsm(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
//interface to dma_ddr2_if block
|
||||
output reg [127:0] ingress_data,
|
||||
// output reg [1:0] ingress_fifo_ctrl, //bit 1 = unused bit 0 = write_en
|
||||
output reg ingress_fifo_wren,
|
||||
// input wire [1:0] ingress_fifo_status, //bit 1 = full bit 0 = almostfull
|
||||
output reg [2:0] ingress_xfer_size,
|
||||
output reg [27:6] ingress_start_addr,
|
||||
output reg ingress_data_req,
|
||||
input wire ingress_data_ack,
|
||||
//interface to xfer_trn_mem_fifo
|
||||
input wire isDes_fifo, /// Jiansong: added for TX des
|
||||
input wire [27:6] mem_dest_addr_fifo,
|
||||
input wire [10:0] mem_dma_size_fifo,
|
||||
input wire mem_dma_start,//start signal not used-monitor empty instead
|
||||
input wire mem_trn_fifo_empty,
|
||||
output reg mem_trn_fifo_rden,
|
||||
//interface to data_trn_mem_fifo
|
||||
input wire [127:0] data_fifo_data,
|
||||
output reg data_fifo_cntrl,
|
||||
input wire data_fifo_status,
|
||||
///Jiansong: interface to dma control wrapper
|
||||
output reg new_des_one, /// Jiansong: is one cycle ok?
|
||||
output wire [31:0] SourceAddr_L,
|
||||
output wire [31:0] SourceAddr_H,
|
||||
output wire [31:0] DestAddr,
|
||||
output wire [23:0] FrameSize,
|
||||
output wire [7:0] FrameControl
|
||||
// output reg [4:0] state /// liuchang: for debug
|
||||
);
|
||||
|
||||
reg [4:0] state;
|
||||
reg [9:0] cnt;
|
||||
//reg [1:0] ingress_fifo_ctrl_pipe = 2'b00;
|
||||
reg ingress_fifo_wren_pipe;
|
||||
|
||||
/// liuchang
|
||||
reg [10:0] mem_dma_size_fifo_r;
|
||||
reg [27:6] mem_dest_addr_fifo_r;
|
||||
|
||||
/// Jiansong
|
||||
reg [127:0] TX_des_1;
|
||||
reg [127:0] TX_des_2;
|
||||
|
||||
/// Jiansong: parse TX descriptor
|
||||
assign SourceAddr_L[31:0] = TX_des_1[95:64];
|
||||
assign SourceAddr_H[31:0] = TX_des_1[127:96];
|
||||
assign DestAddr[31:0] = TX_des_2[31:0];
|
||||
assign FrameSize[23:0] = TX_des_2[87:64];
|
||||
assign FrameControl[7:0] = TX_des_2[95:88];
|
||||
/// Jiansong: check own bit?
|
||||
|
||||
|
||||
reg rst_reg;
|
||||
always@(posedge clk) rst_reg <= rst;
|
||||
|
||||
// Jiansong: data fifo empty pipeline
|
||||
reg data_fifo_status_r;
|
||||
always@(posedge clk) data_fifo_status_r <= data_fifo_status;
|
||||
|
||||
localparam IDLE = 5'b00000;
|
||||
localparam WREQ = 5'b00001;
|
||||
localparam WDATA2 = 5'b00010;
|
||||
localparam WDONE = 5'b00011;
|
||||
localparam MREQ = 5'b00100;
|
||||
localparam MREQ2 = 5'b00101;
|
||||
localparam MREQ_WAIT = 5'b00110; /// liuchang
|
||||
|
||||
/// Jiansong:
|
||||
localparam PARSE_TX_DES = 5'b01000;
|
||||
localparam READ_TX_DES_1 = 5'b10000;
|
||||
localparam READ_TX_DES_2 = 5'b11000;
|
||||
|
||||
//This state machine block waits for the xfer_trn_mem_fifo to go non-empty.
|
||||
//It then performs the following steps:
|
||||
// 1. read the transfer size and destination
|
||||
// information out of the xfer_trn_mem_fifo
|
||||
// 2. encode the transfer size info from DWORDS to the encoding used by
|
||||
// dma_ddr2_if block
|
||||
// 3. transfer the correct amount of data from the data_trn_mem_fifo to
|
||||
// the dma_ddr2_if (ingress data fifo)
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if(rst_reg)
|
||||
begin
|
||||
state <= IDLE;
|
||||
ingress_xfer_size <= 3'b000;
|
||||
ingress_start_addr <= 22'h000000;
|
||||
ingress_data_req <= 1'b0;
|
||||
data_fifo_cntrl <= 1'b0;
|
||||
mem_trn_fifo_rden <= 1'b0;
|
||||
cnt <= 10'h000;
|
||||
new_des_one <= 1'b0;
|
||||
TX_des_1 <= 128'h00000000_00000000_00000000_00000000;
|
||||
TX_des_2 <= 128'h00000000_00000000_00000000_00000000;
|
||||
mem_dma_size_fifo_r <= 11'h000; /// liuchang
|
||||
mem_dest_addr_fifo_r[27:6] <= 22'h00_0000; /// liuchang
|
||||
end
|
||||
else
|
||||
begin
|
||||
case(state)
|
||||
IDLE: begin
|
||||
new_des_one <= 1'b0;
|
||||
//wait for non-empty case and assert the read enable if so
|
||||
if(~mem_trn_fifo_empty)begin
|
||||
mem_trn_fifo_rden <= 1'b1;
|
||||
ingress_data_req <= 1'b0;
|
||||
state <= MREQ;
|
||||
end else begin
|
||||
state <= IDLE;
|
||||
end
|
||||
end
|
||||
MREQ: begin //deassert the read enable
|
||||
mem_trn_fifo_rden <= 1'b0;
|
||||
// state <= MREQ2; /// liuchang
|
||||
state <= MREQ_WAIT; /// liuchang
|
||||
end
|
||||
MREQ_WAIT: begin /// liuchang
|
||||
mem_dma_size_fifo_r <= mem_dma_size_fifo;
|
||||
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo[27:6];
|
||||
state <= MREQ2;
|
||||
end
|
||||
MREQ2:begin
|
||||
if(isDes_fifo) begin /// Jiansong: parse TX des
|
||||
// check whether TX descriptor data arrived in
|
||||
// if (~data_fifo_status)begin
|
||||
if (~data_fifo_status_r)begin
|
||||
state <= PARSE_TX_DES;
|
||||
data_fifo_cntrl <= 1'b1; /// read enable the 1st cycle
|
||||
end else begin
|
||||
state <= MREQ2;
|
||||
data_fifo_cntrl <= 1'b0;
|
||||
end
|
||||
end else begin
|
||||
state <= WREQ;
|
||||
//encode the transfer size information for the dma_ddr2_if
|
||||
//also load a counter with the number of 128-bit (16 byte)
|
||||
//transfers it will require to fullfill the total data
|
||||
|
||||
/// liuchang
|
||||
if(mem_dma_size_fifo_r[10]) begin
|
||||
ingress_xfer_size <= 3'b110; // 4k byte
|
||||
cnt <= 10'h100;
|
||||
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b10000000000;
|
||||
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b1000000;
|
||||
end else if(mem_dma_size_fifo_r[9]) begin // 2k
|
||||
ingress_xfer_size <= 3'b101;
|
||||
cnt <= 10'h080;
|
||||
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b01000000000;
|
||||
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0100000;
|
||||
end else if(mem_dma_size_fifo_r[8]) begin // 1k
|
||||
ingress_xfer_size <= 3'b100;
|
||||
cnt <= 10'h040;
|
||||
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00100000000;
|
||||
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0010000;
|
||||
end else if(mem_dma_size_fifo_r[7]) begin // 512
|
||||
ingress_xfer_size <= 3'b011;
|
||||
cnt <= 10'h020;
|
||||
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00010000000;
|
||||
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0001000;
|
||||
end else if(mem_dma_size_fifo_r[6]) begin // 256
|
||||
ingress_xfer_size <= 3'b010;
|
||||
cnt <= 10'h010;
|
||||
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00001000000;
|
||||
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0000100;
|
||||
end else if(mem_dma_size_fifo_r[5]) begin // 128
|
||||
ingress_xfer_size <= 3'b001;
|
||||
cnt <= 10'h008;
|
||||
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00000100000;
|
||||
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0000010;
|
||||
end else if(mem_dma_size_fifo_r[4]) begin // 64 byte
|
||||
ingress_xfer_size <= 3'b000;
|
||||
cnt <= 10'h004;
|
||||
mem_dma_size_fifo_r <= mem_dma_size_fifo_r - 11'b00000010000;
|
||||
mem_dest_addr_fifo_r[27:6] <= mem_dest_addr_fifo_r[27:6] + 7'b0000001;
|
||||
end
|
||||
|
||||
/// liuchang
|
||||
/*
|
||||
case(mem_dma_size_fifo)
|
||||
11'b00000010000: begin //64 byte
|
||||
ingress_xfer_size <= 3'b000;
|
||||
//64 bytes / 16 byte/xfer = 4 xfers
|
||||
cnt <= 10'h004;
|
||||
end
|
||||
11'b00000100000: begin //128
|
||||
ingress_xfer_size <= 3'b001;
|
||||
cnt <= 10'h008;
|
||||
end
|
||||
11'b00001000000: begin //256
|
||||
ingress_xfer_size <= 3'b010;
|
||||
cnt <= 10'h010;
|
||||
end
|
||||
11'b00010000000: begin //512
|
||||
ingress_xfer_size <= 3'b011;
|
||||
cnt <= 10'h020;
|
||||
end
|
||||
11'b00100000000: begin //1k
|
||||
ingress_xfer_size <= 3'b100;
|
||||
cnt <= 10'h040;
|
||||
end
|
||||
11'b01000000000: begin //2k
|
||||
ingress_xfer_size <= 3'b101;
|
||||
cnt <= 10'h080;
|
||||
end
|
||||
11'b10000000000: begin //4k
|
||||
ingress_xfer_size <= 3'b110;
|
||||
cnt <= 10'h100;
|
||||
end
|
||||
endcase
|
||||
*/
|
||||
ingress_start_addr[27:6] <= mem_dest_addr_fifo_r[27:6];
|
||||
ingress_data_req <= 1'b1;//request access to ingress fifo
|
||||
end
|
||||
end
|
||||
|
||||
/// Jiansong: parse TX des
|
||||
PARSE_TX_DES: begin
|
||||
state <= READ_TX_DES_1;
|
||||
data_fifo_cntrl <= 1'b1; /// read enable the 2nd cycle
|
||||
end
|
||||
READ_TX_DES_1: begin
|
||||
state <= READ_TX_DES_2;
|
||||
data_fifo_cntrl <= 1'b0;
|
||||
/// read data, 1st cycle
|
||||
TX_des_2[127:0] <= data_fifo_data[127:0];
|
||||
new_des_one <= 1'b0;
|
||||
end
|
||||
READ_TX_DES_2: begin
|
||||
state <= IDLE; /// Jiansong: possible timing problem here
|
||||
/// read data, 2nd cycle
|
||||
TX_des_2[127:0] <= data_fifo_data[127:0];
|
||||
TX_des_1[127:0] <= TX_des_2[127:0];
|
||||
new_des_one <= 1'b1;
|
||||
end
|
||||
|
||||
WREQ: begin /// Jiansong: data should be already in data_trn_mem_fifo
|
||||
if(ingress_data_ack) begin//wait for a grant from the dma_ddr2_if
|
||||
state <= WDATA2;
|
||||
ingress_data_req <= 1'b0;
|
||||
data_fifo_cntrl <= 1'b1;
|
||||
end else begin
|
||||
state <= WREQ;
|
||||
end
|
||||
end
|
||||
WDATA2: begin
|
||||
//keep data_fifo_cntrl asserted until cnt is 1 - then deassert
|
||||
//and finish
|
||||
if(cnt == 10'h001)begin
|
||||
state <= WDONE;
|
||||
data_fifo_cntrl <= 1'b0;
|
||||
end else begin
|
||||
cnt <= cnt - 1'b1;
|
||||
data_fifo_cntrl <= 1'b1;
|
||||
state <= WDATA2;
|
||||
end
|
||||
end
|
||||
|
||||
WDONE: begin
|
||||
// state <= IDLE; /// liuchang
|
||||
if(mem_dma_size_fifo_r[10:4] == 7'h00) /// liuchang
|
||||
state <= IDLE;
|
||||
else
|
||||
state <= MREQ2;
|
||||
end
|
||||
default:begin
|
||||
state <= IDLE;
|
||||
ingress_xfer_size <= 3'b000;
|
||||
ingress_start_addr <= 22'h000000;
|
||||
ingress_data_req <= 1'b0;
|
||||
data_fifo_cntrl <= 1'b0;
|
||||
mem_trn_fifo_rden <= 1'b0;
|
||||
cnt <= 10'h000;
|
||||
mem_dma_size_fifo_r <= 11'h000; /// liuchang
|
||||
mem_dest_addr_fifo_r[27:6] <= 22'h00_0000; /// liuchang
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
/// Jiansong: timing ok? all driven by the same clk
|
||||
//data_fifo_cntrl is used as both a read enable to the data_trn_mem_fifo and
|
||||
//a write enable to the ingress fifo (in dma_ddr2_if). The write enable
|
||||
//needs to be pipelined by two clocks so that it is synched with the
|
||||
//ingress_data (normally it would only need one pipeline register but since
|
||||
//ingress_data is pipelined, it requires two.
|
||||
always@(posedge clk) begin // Jiansong: add logic to prevent TX des write into DDR
|
||||
// ingress_fifo_ctrl_pipe[1:0] <= {1'b0,(data_fifo_cntrl&(~isDes_fifo))};//1st pipeline
|
||||
// ingress_fifo_ctrl[1:0] <= ingress_fifo_ctrl_pipe[1:0]; //2nd pipeline
|
||||
ingress_fifo_wren_pipe <= data_fifo_cntrl&(~isDes_fifo); //1st pipeline
|
||||
ingress_fifo_wren <= ingress_fifo_wren_pipe; //2nd pipeline
|
||||
ingress_data[127:0] <= data_fifo_data[127:0]; //pipelined data
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,452 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 06/01/2009
|
||||
// Design Name:
|
||||
// Module Name: rx_trn_data_fsm
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose: Receive TRN Data FSM. This module interfaces to the Block Plus RX
|
||||
// TRN. It presents the 64-bit data from completer and and forwards that
|
||||
// data with a data_valid signal. This block also decodes packet header info
|
||||
// and forwards it to the rx_trn_monitor block.
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module rx_trn_data_fsm(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
// Rx Local-Link
|
||||
input wire [63:0] trn_rd,
|
||||
input wire [7:0] trn_rrem_n,
|
||||
input wire trn_rsof_n,
|
||||
input wire trn_reof_n,
|
||||
input wire trn_rsrc_rdy_n,
|
||||
input wire trn_rsrc_dsc_n,
|
||||
output reg trn_rdst_rdy_n,
|
||||
input wire trn_rerrfwd_n,
|
||||
output wire trn_rnp_ok_n,
|
||||
input wire [6:0] trn_rbar_hit_n,
|
||||
input wire [11:0] trn_rfc_npd_av,
|
||||
input wire [7:0] trn_rfc_nph_av,
|
||||
input wire [11:0] trn_rfc_pd_av,
|
||||
input wire [7:0] trn_rfc_ph_av,
|
||||
input wire [11:0] trn_rfc_cpld_av,
|
||||
input wire [7:0] trn_rfc_cplh_av,
|
||||
output wire trn_rcpl_streaming_n,
|
||||
//DATA FIFO SIGNALS
|
||||
output reg [63:0] data_out,
|
||||
output wire [7:0] data_out_be,
|
||||
output reg data_valid,
|
||||
input wire data_fifo_status,
|
||||
//END DATA FIFO SIGNALS
|
||||
|
||||
//HEADER FIELD SIGNALS
|
||||
//The following are registered from the header fields of the current packet
|
||||
//See the PCIe Base Specification for definitions of these headers
|
||||
output reg fourdw_n_threedw, //fourdw = 1'b1; 3dw = 1'b0;
|
||||
output reg payload,
|
||||
output reg [2:0] tc, //traffic class
|
||||
output reg td, //digest
|
||||
output reg ep, //poisoned bit
|
||||
output reg [1:0] attr, //attribute field
|
||||
output reg [9:0] dw_length, //DWORD Length
|
||||
//the following fields are dependent on the type of TLP being received
|
||||
//regs with MEM prefix are valid for memory TLPS and regs with CMP prefix
|
||||
//are valid for completion TLPS
|
||||
output reg [15:0] MEM_req_id, //requester ID for memory TLPs
|
||||
output reg [7:0] MEM_tag, //tag for non-posted memory read request
|
||||
output reg [15:0] CMP_comp_id, //completer id for completion TLPs
|
||||
output reg [2:0]CMP_compl_stat, //status for completion TLPs
|
||||
output reg CMP_bcm, //byte count modified field for completions TLPs
|
||||
output reg [11:0] CMP_byte_count, //remaining byte count for completion TLPs
|
||||
output reg [63:0] MEM_addr, //address field for memory TLPs
|
||||
output reg [15:0] CMP_req_id, //requester if for completions TLPs
|
||||
output reg [7:0] CMP_tag, //tag field for completion TLPs
|
||||
output reg [6:0] CMP_lower_addr, //lower address field for completion TLPs
|
||||
//decode of the format field
|
||||
output wire MRd, //Mem read
|
||||
output wire MWr, //Mem write
|
||||
output wire CplD, //Completion w/ data
|
||||
output wire Msg, //Message TLP
|
||||
output wire UR, //Unsupported request TLP i.e. IO, CPL,etc..
|
||||
|
||||
output reg [6:0] bar_hit, //valid when a BAR is hit
|
||||
output reg header_fields_valid//valid signal to qualify the above header fields
|
||||
//END HEADER FIELD SIGNALS
|
||||
|
||||
);
|
||||
|
||||
//state machine states
|
||||
localparam IDLE = 3'b000;
|
||||
localparam NOT_READY = 3'b001;
|
||||
localparam SOF = 3'b010;
|
||||
localparam HEAD2 = 3'b011;
|
||||
localparam BODY = 3'b100;
|
||||
localparam EOF = 3'b101;
|
||||
|
||||
//additional pipelines regs for RX TRN interface
|
||||
reg [63:0] trn_rd_d1;
|
||||
reg [7:0] trn_rrem_d1_n;
|
||||
reg trn_rsof_d1_n;
|
||||
reg trn_reof_d1_n;
|
||||
reg trn_rsrc_rdy_d1_n;
|
||||
reg trn_rsrc_dsc_d1_n;
|
||||
reg trn_rerrfwd_d1_n;
|
||||
reg [6:0] trn_rbar_hit_d1_n;
|
||||
reg [11:0] trn_rfc_npd_av_d1;
|
||||
reg [7:0] trn_rfc_nph_av_d1;
|
||||
reg [11:0] trn_rfc_pd_av_d1;
|
||||
reg [7:0] trn_rfc_ph_av_d1;
|
||||
reg [11:0] trn_rfc_cpld_av_d1;
|
||||
reg [7:0] trn_rfc_cplh_av_d1;
|
||||
//second pipeline
|
||||
reg [63:0] trn_rd_d2;
|
||||
reg [7:0] trn_rrem_d2_n;
|
||||
reg trn_rsof_d2_n;
|
||||
reg trn_reof_d2_n;
|
||||
reg trn_rsrc_rdy_d2_n;
|
||||
reg trn_rsrc_dsc_d2_n;
|
||||
reg trn_rerrfwd_d2_n;
|
||||
reg [6:0] trn_rbar_hit_d2_n;
|
||||
reg [11:0] trn_rfc_npd_av_d2;
|
||||
reg [7:0] trn_rfc_nph_av_d2;
|
||||
reg [11:0] trn_rfc_pd_av_d2;
|
||||
reg [7:0] trn_rfc_ph_av_d2;
|
||||
reg [11:0] trn_rfc_cpld_av_d2;
|
||||
reg [7:0] trn_rfc_cplh_av_d2;
|
||||
|
||||
|
||||
|
||||
reg [4:0] rx_packet_type;
|
||||
reg [2:0] trn_state;
|
||||
wire [63:0] data_out_mux;
|
||||
wire [7:0] data_out_be_mux;
|
||||
reg data_valid_early;
|
||||
|
||||
reg rst_reg;
|
||||
always@(posedge clk) rst_reg <= rst;
|
||||
|
||||
|
||||
// TIE constant signals here
|
||||
assign trn_rnp_ok_n = 1'b0;
|
||||
assign trn_rcpl_streaming_n = 1'b0; //use completion streaming mode
|
||||
|
||||
|
||||
//all the outputs of the endpoint should be pipelined
|
||||
//to help meet required timing of an 8 lane design
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
trn_rd_d1[63:0] <= trn_rd[63:0] ;
|
||||
trn_rrem_d1_n[7:0] <= trn_rrem_n[7:0] ;
|
||||
trn_rsof_d1_n <= trn_rsof_n ;
|
||||
trn_reof_d1_n <= trn_reof_n ;
|
||||
trn_rsrc_rdy_d1_n <= trn_rsrc_rdy_n ;
|
||||
trn_rsrc_dsc_d1_n <= trn_rsrc_dsc_n ;
|
||||
trn_rerrfwd_d1_n <= trn_rerrfwd_n ;
|
||||
trn_rbar_hit_d1_n[6:0] <= trn_rbar_hit_n[6:0] ;
|
||||
trn_rfc_npd_av_d1[11:0] <= trn_rfc_npd_av[11:0] ;
|
||||
trn_rfc_nph_av_d1[7:0] <= trn_rfc_nph_av[7:0] ;
|
||||
trn_rfc_pd_av_d1[11:0] <= trn_rfc_pd_av[11:0] ;
|
||||
trn_rfc_ph_av_d1[7:0] <= trn_rfc_ph_av[7:0] ;
|
||||
trn_rfc_cpld_av_d1[11:0] <= trn_rfc_cpld_av[11:0];
|
||||
trn_rfc_cplh_av_d1[7:0] <= trn_rfc_cplh_av[7:0] ;
|
||||
trn_rd_d2[63:0] <= trn_rd_d1[63:0] ;
|
||||
trn_rrem_d2_n[7:0] <= trn_rrem_d1_n[7:0] ;
|
||||
trn_rsof_d2_n <= trn_rsof_d1_n ;
|
||||
trn_reof_d2_n <= trn_reof_d1_n ;
|
||||
trn_rsrc_rdy_d2_n <= trn_rsrc_rdy_d1_n ;
|
||||
trn_rsrc_dsc_d2_n <= trn_rsrc_dsc_d1_n ;
|
||||
trn_rerrfwd_d2_n <= trn_rerrfwd_d1_n ;
|
||||
trn_rbar_hit_d2_n[6:0] <= trn_rbar_hit_d1_n[6:0] ;
|
||||
trn_rfc_npd_av_d2[11:0] <= trn_rfc_npd_av_d1[11:0] ;
|
||||
trn_rfc_nph_av_d2[7:0] <= trn_rfc_nph_av_d1[7:0] ;
|
||||
trn_rfc_pd_av_d2[11:0] <= trn_rfc_pd_av_d1[11:0] ;
|
||||
trn_rfc_ph_av_d2[7:0] <= trn_rfc_ph_av_d1[7:0] ;
|
||||
trn_rfc_cpld_av_d2[11:0] <= trn_rfc_cpld_av_d1[11:0];
|
||||
trn_rfc_cplh_av_d2[7:0] <= trn_rfc_cplh_av_d1[7:0] ;
|
||||
end
|
||||
|
||||
|
||||
assign rx_sof_d1 = ~trn_rsof_d1_n & ~trn_rsrc_rdy_d1_n;
|
||||
|
||||
// Assign packet type information about the current RX Packet
|
||||
// rx_packet_type is decoded in always block directly below these assigns
|
||||
assign MRd = rx_packet_type[4];
|
||||
assign MWr = rx_packet_type[3];
|
||||
assign CplD = rx_packet_type[2];
|
||||
assign Msg = rx_packet_type[1];
|
||||
assign UR = rx_packet_type[0];
|
||||
|
||||
//register the packet header fields and decode the packet type
|
||||
//both memory and completion TLP header fields are registered for each
|
||||
//received packet, however, only the fields for the incoming type will be
|
||||
//valid
|
||||
always@(posedge clk )
|
||||
begin
|
||||
if(rst_reg)begin
|
||||
rx_packet_type[4:0] <= 5'b00000;
|
||||
fourdw_n_threedw <= 0;
|
||||
payload <= 0;
|
||||
tc[2:0] <= 0; //traffic class
|
||||
td <= 0; //digest
|
||||
ep <= 0; //poisoned bit
|
||||
attr[1:0] <= 0;
|
||||
dw_length[9:0] <= 0;
|
||||
MEM_req_id[15:0] <= 0;
|
||||
MEM_tag[7:0] <= 0;
|
||||
CMP_comp_id[15:0] <= 0;
|
||||
CMP_compl_stat[2:0] <= 0;
|
||||
CMP_bcm <= 0;
|
||||
CMP_byte_count[11:0] <= 0;
|
||||
end else begin
|
||||
if(rx_sof_d1)begin
|
||||
//these fields same for all TLPs
|
||||
fourdw_n_threedw <= trn_rd_d1[61];
|
||||
payload <= trn_rd_d1[62];
|
||||
tc[2:0] <= trn_rd_d1[54:52]; //traffic class
|
||||
td <= trn_rd_d1[47]; //digest
|
||||
ep <= trn_rd_d1[46]; //poisoned bit
|
||||
attr[1:0] <= trn_rd_d1[45:44];
|
||||
dw_length[9:0] <= trn_rd_d1[41:32];
|
||||
//also latch bar_hit
|
||||
bar_hit[6:0] <= ~trn_rbar_hit_d1_n[6:0];
|
||||
//these following fields dependent on packet type
|
||||
//i.e. memory packet fields are only valid for mem packet types
|
||||
//and completer packet fields are only valid for completer packet type;
|
||||
//memory packet fields
|
||||
MEM_req_id[15:0] <= trn_rd_d1[31:16];
|
||||
MEM_tag[7:0] <= trn_rd_d1[15:8];
|
||||
//first and last byte enables not needed because plus core delivers
|
||||
|
||||
//completer packet fields
|
||||
CMP_comp_id[15:0] <= trn_rd_d1[31:16];
|
||||
CMP_compl_stat[2:0] <= trn_rd_d1[15:13];
|
||||
CMP_bcm <= trn_rd_d1[12];
|
||||
CMP_byte_count[11:0] <= trn_rd_d1[11:0];
|
||||
|
||||
//add message fields here if needed
|
||||
|
||||
//decode the packet type and register in rx_packet_type
|
||||
casex({trn_rd_d1[62],trn_rd_d1[60:56]})
|
||||
6'b000000: begin //mem read
|
||||
rx_packet_type[4:0] <= 5'b10000;
|
||||
end
|
||||
6'b100000: begin //mem write
|
||||
rx_packet_type[4:0] <= 5'b01000;
|
||||
end
|
||||
6'b101010: begin //completer with data
|
||||
rx_packet_type[4:0] <= 5'b00100;
|
||||
end
|
||||
6'bx10xxx: begin //message
|
||||
rx_packet_type[4:0] <= 5'b00010;
|
||||
end
|
||||
default: begin //all other packet types are unsupported for this design
|
||||
rx_packet_type[4:0] <= 5'b00001;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Now do the same for the second header of the current packet
|
||||
always@(posedge clk )begin
|
||||
if(rst_reg)begin
|
||||
MEM_addr[63:0] <= 0;
|
||||
CMP_req_id[15:0] <= 0;
|
||||
CMP_tag[7:0] <= 0;
|
||||
CMP_lower_addr[6:0] <= 0;
|
||||
end else begin
|
||||
if(trn_state == SOF & ~trn_rsrc_rdy_d1_n)begin //packet is in process of
|
||||
//reading out second header
|
||||
if(fourdw_n_threedw)
|
||||
MEM_addr[63:0] <= trn_rd_d1[63:0];
|
||||
else
|
||||
MEM_addr[63:0] <= {32'h00000000,trn_rd_d1[63:32]};
|
||||
|
||||
CMP_req_id[15:0] <= trn_rd_d1[63:48];
|
||||
CMP_tag[7:0] <= trn_rd_d1[47:40];
|
||||
CMP_lower_addr[6:0] <= trn_rd_d1[48:32];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// generate a valid signal for the headers field
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)
|
||||
header_fields_valid <= 0;
|
||||
else
|
||||
header_fields_valid <= ~trn_rsrc_rdy_d2_n & trn_rsof_d1_n;
|
||||
end
|
||||
|
||||
|
||||
//This state machine keeps track of what state the RX TRN interface
|
||||
//is currently in
|
||||
always @ (posedge clk )
|
||||
begin
|
||||
if(rst_reg)
|
||||
begin
|
||||
trn_state <= IDLE;
|
||||
trn_rdst_rdy_n <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
case(trn_state)
|
||||
IDLE: begin
|
||||
trn_rdst_rdy_n <= 1'b0;
|
||||
if(rx_sof_d1)
|
||||
trn_state <= SOF;
|
||||
else
|
||||
trn_state <= IDLE;
|
||||
end
|
||||
/// Jiansong: notice, completion streaming here
|
||||
NOT_READY: begin // This state is a placeholder only - it is currently not
|
||||
// entered from any other state
|
||||
// This state could be used for throttling the PCIe
|
||||
// Endpoint Block Plus RX TRN interface, however, this
|
||||
// should not be done when using completion streaming
|
||||
// mode as this reference design does
|
||||
trn_rdst_rdy_n <= 1'b1;
|
||||
trn_state <= IDLE;
|
||||
end
|
||||
SOF: begin
|
||||
if(~trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
|
||||
trn_state <= EOF;
|
||||
else if(trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
|
||||
trn_state <= HEAD2;
|
||||
else
|
||||
trn_state <= SOF;
|
||||
end
|
||||
HEAD2: begin
|
||||
if(~trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
|
||||
trn_state <= EOF;
|
||||
else if(trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
|
||||
trn_state <= BODY;
|
||||
else
|
||||
trn_state <= HEAD2;
|
||||
end
|
||||
BODY: begin
|
||||
if(~trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
|
||||
trn_state <= EOF;
|
||||
else
|
||||
trn_state <= BODY;
|
||||
end
|
||||
EOF: begin
|
||||
if(~trn_rsof_d1_n & ~trn_rsrc_rdy_d1_n)
|
||||
trn_state <= SOF;
|
||||
else if(trn_rsof_d1_n & trn_rsrc_rdy_d1_n)
|
||||
trn_state <= IDLE;
|
||||
else if(~trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
|
||||
trn_state <= EOF;
|
||||
else
|
||||
trn_state <= IDLE;
|
||||
end
|
||||
default: begin
|
||||
trn_state <= IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//data shifter logic
|
||||
//need to shift the data depending if we receive a four DWORD or three DWORD
|
||||
//TLP type - Note that completion packets will always be 3DW TLPs
|
||||
assign data_out_mux[63:0] = (fourdw_n_threedw)
|
||||
? trn_rd_d2[63:0]
|
||||
: {trn_rd_d2[31:0],trn_rd_d1[63:32]};
|
||||
|
||||
/// Jiansong: notice, why? 64bit data? likely should be modified
|
||||
//swap the byte ordering to little endian
|
||||
//e.g. data_out = B7,B6,B5,B4,B3,B2,B1,B0
|
||||
always@(posedge clk)
|
||||
data_out[63:0] <= {data_out_mux[7:0],data_out_mux[15:8],
|
||||
data_out_mux[23:16],data_out_mux[31:24],
|
||||
data_out_mux[39:32],data_out_mux[47:40],
|
||||
data_out_mux[55:48],data_out_mux[63:56]};
|
||||
|
||||
//Data byte enable logic:
|
||||
//Need to add byte enable logic for incoming memory transactions if desired
|
||||
//to allow memory transaction granularity smaller than DWORD.
|
||||
//
|
||||
//This design always requests data on 128 byte boundaries so for
|
||||
//completion TLPs the byte enables would always be asserted
|
||||
//
|
||||
//Note that the endpoint block plus uses negative logic, however,
|
||||
//I decided to use positive logic for the user application.
|
||||
assign data_out_be = 8'hff;
|
||||
|
||||
//data_valid generation logic
|
||||
//Generally, data_valid should be asserted the same amount of cycles
|
||||
//that trn_rsrc_rdy_n is asserted (minus the cycles that sof and
|
||||
//eof are asserted).
|
||||
//There are two exceptions to this:
|
||||
// - 3DW TLPs with odd number of DW without Digest
|
||||
// In this case an extra cycle is required
|
||||
// - eof is used to generate this extra cycle
|
||||
// - 4DW TLPs with even number of DW with Digest
|
||||
// In this case an extra cycle needs to be removed
|
||||
// - the last cycle is removed
|
||||
|
||||
// Jiansong: fix Mrd data to fifo bug
|
||||
always@(*)begin
|
||||
case({fourdw_n_threedw, dw_length[0], td})
|
||||
3'b010: data_valid_early = ~trn_rsrc_rdy_d2_n
|
||||
& trn_rsof_d2_n
|
||||
& ~trn_reof_d2_n
|
||||
& payload;
|
||||
3'b101: data_valid_early = ~trn_rsrc_rdy_d2_n
|
||||
& trn_reof_d1_n
|
||||
& payload;
|
||||
default: data_valid_early = ~trn_rsrc_rdy_d2_n
|
||||
& trn_rsof_d2_n
|
||||
& trn_reof_d2_n
|
||||
& payload;
|
||||
endcase
|
||||
end
|
||||
|
||||
//delay by one clock to match data_out (and presumably data_out_be)
|
||||
always@(posedge clk)
|
||||
if(rst_reg)
|
||||
data_valid <= 1'b0;
|
||||
else
|
||||
data_valid <= data_valid_early;
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,635 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 06/01/2009
|
||||
// Design Name:
|
||||
// Module Name: rx_trn_monitor
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose: Receive TRN Monitor module. This module interfaces to the DMA
|
||||
// Control/Status Register File and the Read Request Fifo to determine when a
|
||||
// DMA transfer has completed fully. This module could also monitor the TRN
|
||||
// Interface to determine any errors.
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
`include "Sora_config.v"
|
||||
|
||||
module rx_trn_monitor(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
//DMA_CTRL_WRAPPER FILE SIGNALS
|
||||
input wire rd_dma_start, //indicates the start of a read dma xfer
|
||||
input wire [31:0] dmarad, //destination addres(ddr2) only 13 bits used
|
||||
input wire [31:0] dmarxs, //size of the complete transfer
|
||||
output reg rd_dma_done, //dma transfer complete
|
||||
input wire read_last,
|
||||
///Jiansong: interface to RX engine, indicate the system is in dma read for TX desc
|
||||
/// when this signal is asserted, received cpld will not be count in
|
||||
/// length subtraction
|
||||
input wire Wait_for_TX_desc,
|
||||
`ifdef TF_RECOVERY
|
||||
input wire transferstart, // control signal for transfer recovering
|
||||
`endif
|
||||
//Read Request Wrapper interface signals
|
||||
//this is requests of the dma transfer and how the TX ENGINE broke them down
|
||||
//into smaller xfers
|
||||
output reg [4:0] rx_waddr,
|
||||
output reg [31:0] rx_wdata,
|
||||
output reg rx_we,
|
||||
output wire [4:0] rx_raddr,
|
||||
input [31:0] rx_rdata,
|
||||
output reg pending_comp_done,
|
||||
input [31:0] completion_pending,
|
||||
//PCIe Endpoint Block Plus interface
|
||||
// Rx TRN
|
||||
input wire [63:0] trn_rd,
|
||||
input wire [7:0] trn_rrem_n,
|
||||
input wire trn_rsof_n,
|
||||
input wire trn_reof_n,
|
||||
input wire trn_rsrc_rdy_n,
|
||||
input wire trn_rsrc_dsc_n,
|
||||
input wire trn_rerrfwd_n,
|
||||
input wire [6:0] trn_rbar_hit_n,
|
||||
input wire [11:0] trn_rfc_npd_av,
|
||||
input wire [7:0] trn_rfc_nph_av,
|
||||
input wire [11:0] trn_rfc_pd_av,
|
||||
input wire [7:0] trn_rfc_ph_av,
|
||||
input wire [11:0] trn_rfc_cpld_av,
|
||||
input wire [7:0] trn_rfc_cplh_av,
|
||||
//interface from rx_trn_data_fsm
|
||||
input wire fourdw_n_threedw, //fourdw = 1'b1; 3dw = 1'b0;
|
||||
input wire payload,
|
||||
input wire [2:0] tc, //traffic class
|
||||
input wire td, //digest
|
||||
input wire ep, //poisoned bit
|
||||
input wire [1:0] attr,
|
||||
input wire [9:0] dw_length,
|
||||
input wire [15:0] MEM_req_id,
|
||||
input wire [7:0] MEM_tag,
|
||||
input wire [15:0] CMP_comp_id,
|
||||
input wire [2:0]CMP_compl_stat,
|
||||
input wire CMP_bcm,
|
||||
input wire [11:0] CMP_byte_count,
|
||||
input wire [63:0] MEM_addr,
|
||||
input wire [15:0] CMP_req_id,
|
||||
input wire [7:0] CMP_tag,
|
||||
input wire [6:0] CMP_lower_addr,
|
||||
input wire MRd,
|
||||
input wire MWr,
|
||||
input wire CplD,
|
||||
input wire Msg,
|
||||
input wire UR,
|
||||
input wire header_fields_valid,
|
||||
input wire data_valid,
|
||||
//Outputs to xfer_trn_mem_fifo
|
||||
output reg isDes, /// Jiansong: added for TX des
|
||||
output wire [27:6] mem_dest_addr,
|
||||
output reg [10:0] mem_dma_size,
|
||||
output wire mem_dma_start
|
||||
/// Jiansong: output to tx_sm
|
||||
// output wire [9:0] np_rx_cnt_qw
|
||||
/// Jiansong: debug register
|
||||
// output reg [9:0] Debug30RXEngine
|
||||
);
|
||||
|
||||
//states for memctrl_state
|
||||
localparam IDLE = 5'b00000;
|
||||
localparam CALC_NEXT_ADDR = 5'b00001;
|
||||
localparam WRITEBACK_ADDR = 5'b00010;
|
||||
localparam WRITEBACK_ADDR2 = 5'b00011;
|
||||
|
||||
//states for addsub_state
|
||||
localparam AS_IDLE = 2'b00;
|
||||
localparam REGISTER_CALC = 2'b01;
|
||||
localparam WAIT_FOR_REG = 2'b10;
|
||||
|
||||
//additional pipelines regs for RXTRN interface to match rx_trn_data_fsm module
|
||||
reg [63:0] trn_rd_d1;
|
||||
reg [7:0] trn_rrem_d1_n;
|
||||
reg trn_rsof_d1_n;
|
||||
reg trn_reof_d1_n;
|
||||
reg trn_rsrc_rdy_d1_n;
|
||||
reg trn_rsrc_dsc_d1_n;
|
||||
reg trn_rerrfwd_d1_n;
|
||||
reg [6:0] trn_rbar_hit_d1_n;
|
||||
reg [11:0] trn_rfc_npd_av_d1;
|
||||
reg [7:0] trn_rfc_nph_av_d1;
|
||||
reg [11:0] trn_rfc_pd_av_d1;
|
||||
reg [7:0] trn_rfc_ph_av_d1;
|
||||
reg [11:0] trn_rfc_cpld_av_d1;
|
||||
reg [7:0] trn_rfc_cplh_av_d1;
|
||||
|
||||
|
||||
//registers to store output of comp ram
|
||||
reg [27:6] cur_dest_addr; //bottom 5 lsb all zero
|
||||
|
||||
//state machine registers
|
||||
reg [4:0] memctrl_state;
|
||||
reg [1:0] addsub_state;
|
||||
|
||||
//single-shot signal which qualifies the header fields
|
||||
wire header_fields_valid_one;
|
||||
|
||||
//ddr2 memory address which gets written back into the compram
|
||||
wire [27:6] next_mem_dest_addr;
|
||||
|
||||
reg data_valid_reg;
|
||||
|
||||
//pipelined registers
|
||||
reg CplD_r1, CplD_r2;
|
||||
|
||||
//signals to calculate and assert rd_dma_done
|
||||
reg add_calc = 0;
|
||||
reg sub_calc = 0;
|
||||
reg add_complete;
|
||||
reg sub_complete;
|
||||
reg stay_2x;
|
||||
reg update_dmarxs_div8_reg;
|
||||
reg [9:0] dmarxs_div8_reg_new;
|
||||
reg [9:0] dw_length_d1;
|
||||
reg [9:0] dmarxs_div8_reg;
|
||||
reg [9:0] dmarxs_div8_now;
|
||||
wire rd_dma_done_early, rd_dma_done_early_one;
|
||||
reg rd_dma_done_i;
|
||||
wire rd_dma_done_one;
|
||||
|
||||
|
||||
reg rst_reg;
|
||||
always@(posedge clk) rst_reg <= rst;
|
||||
|
||||
///// Jiansong: debug output
|
||||
//always@(posedge clk) begin
|
||||
// Debug30RXEngine[9:0] <= dmarxs_div8_now[9:0];
|
||||
//end
|
||||
|
||||
|
||||
/// Jiansong:
|
||||
wire rd_dma_start_one;
|
||||
reg rd_dma_start_reg;
|
||||
rising_edge_detect rd_dma_start_one_inst(
|
||||
.clk(clk),
|
||||
.rst(rst_reg),
|
||||
.in(rd_dma_start_reg),
|
||||
.one_shot_out(rd_dma_start_one)
|
||||
);
|
||||
//register for timing purposes
|
||||
always@(posedge clk)
|
||||
rd_dma_start_reg <= rd_dma_start;
|
||||
|
||||
|
||||
|
||||
|
||||
/// Jiansong: notice, pipeline registers
|
||||
//all the outputs of the endpoint should be pipelined
|
||||
//to help meet required timing of an 8 lane design
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
trn_rd_d1[63:0] <= trn_rd[63:0] ;
|
||||
trn_rrem_d1_n[7:0] <= trn_rrem_n[7:0] ;
|
||||
trn_rsof_d1_n <= trn_rsof_n ;
|
||||
trn_reof_d1_n <= trn_reof_n ;
|
||||
trn_rsrc_rdy_d1_n <= trn_rsrc_rdy_n ;
|
||||
trn_rsrc_dsc_d1_n <= trn_rsrc_dsc_n ;
|
||||
trn_rerrfwd_d1_n <= trn_rerrfwd_n ;
|
||||
trn_rbar_hit_d1_n[6:0] <= trn_rbar_hit_n[6:0] ;
|
||||
trn_rfc_npd_av_d1[11:0] <= trn_rfc_npd_av[11:0] ;
|
||||
trn_rfc_nph_av_d1[7:0] <= trn_rfc_nph_av[7:0] ;
|
||||
trn_rfc_pd_av_d1[11:0] <= trn_rfc_pd_av[11:0] ;
|
||||
trn_rfc_ph_av_d1[7:0] <= trn_rfc_ph_av[7:0] ;
|
||||
trn_rfc_cpld_av_d1[11:0] <= trn_rfc_cpld_av[11:0];
|
||||
trn_rfc_cplh_av_d1[7:0] <= trn_rfc_cplh_av[7:0] ;
|
||||
end
|
||||
|
||||
|
||||
|
||||
/*****************************************************************************
|
||||
Placeholder for the following TBD logic blocks:
|
||||
|
||||
- Check ECRC Logic - not implemented and not supported by Endpoint Block Plus
|
||||
Rev 1.6.1
|
||||
|
||||
- Check unsupported request
|
||||
- Mem transaction but no BAR hit is unsupported
|
||||
|
||||
- Completion timeout logic error
|
||||
|
||||
- Check for unexpected completer
|
||||
|
||||
- Completion Status bits check
|
||||
|
||||
******************************************************************************/
|
||||
|
||||
//Jiansong: we don't need to modify CMP-write-to-fifo logics, but the address may be wrong
|
||||
// (RCB address 0).
|
||||
|
||||
//use the completion packet tag field to address the comp ram for reading
|
||||
assign rx_raddr[4:0] = CMP_tag[4:0];
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//State machine for calculating the next DDR2 address in a series of
|
||||
//completions i.e. a single read request split up into multiple completions
|
||||
//Update the address in the compram for each completion packet received
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)begin
|
||||
memctrl_state <= IDLE;
|
||||
cur_dest_addr[27:6] <= 0;
|
||||
isDes <= 0; /// Jiansong: added for TX des
|
||||
rx_waddr <= 0;
|
||||
rx_wdata <= 0;
|
||||
rx_we <= 1'b0;
|
||||
pending_comp_done <= 1'b0;
|
||||
end else begin
|
||||
case(memctrl_state)
|
||||
IDLE:begin
|
||||
rx_waddr[4:0] <= 5'b00000;
|
||||
rx_wdata[31:0] <= 32'h00000000;
|
||||
rx_we <= 1'b0;
|
||||
pending_comp_done <= 1'b0;
|
||||
//when header_fields_valid_one and CplD, rx_rdata already has
|
||||
//the correct information on it so go ahead and latch the
|
||||
//current destination address, then jump to CALC_NEXT_ADDR
|
||||
//in order to calculate the destination address for the next
|
||||
//future completion packet
|
||||
if(header_fields_valid_one && CplD)begin
|
||||
memctrl_state <= CALC_NEXT_ADDR;
|
||||
cur_dest_addr[27:6] <= rx_rdata[21:0];
|
||||
isDes <= rx_rdata[31]; /// Jiansong: added for TX des
|
||||
end else begin
|
||||
memctrl_state <= IDLE;
|
||||
end
|
||||
end
|
||||
CALC_NEXT_ADDR:begin //wait state
|
||||
memctrl_state <= WRITEBACK_ADDR;
|
||||
end
|
||||
WRITEBACK_ADDR:begin //write back the ddr2 destination address
|
||||
//don't really care about the length field in the compram as
|
||||
//I use the packet header information to determine when the
|
||||
//series of completion packets are done - see below
|
||||
// i.e. if(dw_length[9:0] == CMP_byte_count[11:2])
|
||||
memctrl_state <= WRITEBACK_ADDR2;
|
||||
rx_waddr[4:0] <= rx_raddr[4:0];
|
||||
rx_wdata[31:0] <= {10'b0000000000, next_mem_dest_addr[27:6]};
|
||||
rx_we <= 1'b1;
|
||||
//if byte_count and length field are the same then it is the
|
||||
//last packet and assert pending_comp_done
|
||||
if(dw_length[9:0] == CMP_byte_count[11:2])
|
||||
pending_comp_done <= 1'b1;
|
||||
else
|
||||
pending_comp_done <= 1'b0;
|
||||
end
|
||||
WRITEBACK_ADDR2:begin //rx write needs to be at least 2 clock cycles
|
||||
memctrl_state <= IDLE;
|
||||
end
|
||||
default:begin
|
||||
cur_dest_addr[27:6] <= 0;
|
||||
rx_waddr <= 0;
|
||||
rx_wdata <= 0;
|
||||
rx_we <= 1'b0;
|
||||
pending_comp_done <= 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
//Additional statemachine inputs/outputs
|
||||
|
||||
//the falling edge of data_valid creates a one shot signal to start the
|
||||
//memory xfer and start calculations for the next xfer address
|
||||
rising_edge_detect header_fields_valid_one_inst(
|
||||
.clk(clk),
|
||||
.rst(rst_reg),
|
||||
.in(header_fields_valid),
|
||||
.one_shot_out(header_fields_valid_one)
|
||||
);
|
||||
|
||||
|
||||
assign next_mem_dest_addr[27:6] = (dw_length[9:0] != 10'b0000000000)
|
||||
//assumes 64B boundary
|
||||
? cur_dest_addr[27:6] + dw_length[9:4]
|
||||
//special case for 4KB
|
||||
: cur_dest_addr[27:6] + 7'b1000000;
|
||||
//end of state machine
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//logic for interfacing to xfer_trn_mem_fifo
|
||||
// -mem_dest_addr
|
||||
// -mem_dma_size
|
||||
// -mem_dma_start
|
||||
|
||||
assign mem_dest_addr[27:6] = cur_dest_addr[27:6];
|
||||
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)begin
|
||||
mem_dma_size[10:0] <= 11'b00000000000;
|
||||
end else begin
|
||||
if(CplD & header_fields_valid_one)begin
|
||||
mem_dma_size[10:0] <= (dw_length[9:0] != 10'b0000000000)
|
||||
? {1'b0,dw_length[9:0]}
|
||||
: 11'b10000000000;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//Make a falling edge detector of data_valid
|
||||
//This will signal mem_dma_start which means that for
|
||||
//every completer packet received, it will get written into
|
||||
//the DDR2 as soon as the last chunk of data has been written
|
||||
//to the buffering fifo. Make sure to qualify with the CplD signal
|
||||
//as the data_valid signal could also be asserted during a Posted MemWr target
|
||||
//transaction.
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)begin
|
||||
data_valid_reg <= 1'b0;
|
||||
end else begin
|
||||
data_valid_reg <= data_valid;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge clk)begin
|
||||
CplD_r1 <= CplD;
|
||||
CplD_r2 <= CplD_r1;
|
||||
end
|
||||
|
||||
/// Jiansong: falling edge detector
|
||||
assign mem_dma_start = data_valid_reg & ~data_valid & CplD_r2;
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/// Jiansong: modification in following logics for transfer recovering
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
//Logic for detecting when an DMA Read has completed
|
||||
//and for starting a continuation transfer early.
|
||||
//Due to the way the dma_ctrl_wrapper works, i.e. breaks up large
|
||||
//transfers into 4KB or smaller
|
||||
//sub-transfers, to keep the bandwidth high the dma_ctrl_wrapper must
|
||||
//issue these sub-transfers in a staggered fashion. That is, the next
|
||||
//sub-transfer should be executed slightly before the current one is finished.
|
||||
//The rd_dma_done_early signal accomplishes this by detecting when the current
|
||||
//transfer is ALMOST complete and signalling to the dma_ctrl_wrapper to
|
||||
//issue the next sub-transfer. In addition to detecting early completion,
|
||||
//we need logic to detect when the full (large) dma transfer is completed
|
||||
//A register, dmarxs_div8_now[9:0], keeps track of how many outstanding
|
||||
//DWORDS of data are remaining to be received. As a completion packet is
|
||||
//received, the dwlength field in the packet is subtracted off of this
|
||||
//register. Conversely, as transfers are executed by the dma_ctrl_wrapper,
|
||||
//the amount of the transfer is added to the register. When the register
|
||||
//reaches 0 the DMA is basically complete (although there may be some
|
||||
//transfers which are smaller than 1KB that need to execute to completely
|
||||
//finish the full dma transfer - see the comments below about the
|
||||
//rd_dma_done_early signal).
|
||||
|
||||
//divide dmarxs by 8 (left-shift 3 bits) also pipeline for timing
|
||||
//this is the term that will get added to dmarxs_div8_now register
|
||||
always@(posedge clk) dmarxs_div8_reg[9:0] <= dmarxs[12:3];
|
||||
|
||||
//need to make sure we use dw_length_d1 in calculations
|
||||
//below since sub_calc is set using trn_reof_d1_n i.e.
|
||||
//there is potential for dw_length to change very soon
|
||||
//after trn_reof_d1_n, like if another type of packet
|
||||
//gets received or a different size completion;
|
||||
//dw_length_d1 is the term that will get subtracted from dmarxs_div8_now reg
|
||||
//always@(posedge clk) dw_length_d1[9:0] <= dw_length[9:0];
|
||||
// Jiansong: make sure dw_length will not change before subcalculation
|
||||
always@(posedge clk) begin
|
||||
if (header_fields_valid_one & CplD)
|
||||
dw_length_d1[9:0] <= dw_length[9:0];
|
||||
end
|
||||
|
||||
//add_calc and sub_calc signals are inputs to the addsub statemachine
|
||||
//and tell the state machine which arithmetic operation to execute
|
||||
|
||||
//if dma_ctrl_wrapper executes a dma transfer by asserting rd_dma_start
|
||||
//then we need to do the addition
|
||||
/// Jiansong: add reset and transferstart control
|
||||
always@(posedge clk)begin
|
||||
`ifdef TF_RECOVERY
|
||||
if (rst_reg | (~transferstart))
|
||||
`else
|
||||
if (rst_reg)
|
||||
`endif
|
||||
add_calc <= 1'b0;
|
||||
else if(rd_dma_start_one) //set the bit
|
||||
add_calc <= 1'b1;
|
||||
else if (add_complete) //reset the bit
|
||||
add_calc <= 1'b0;
|
||||
end
|
||||
|
||||
//if a completion packet has been received then we need to subtract
|
||||
/// Jiansong: add reset and transferstart control
|
||||
always@(posedge clk)begin
|
||||
//// if(~trn_reof_d1_n & ~trn_rsrc_rdy_d1_n & CplD) //set the bit
|
||||
`ifdef TF_RECOVERY
|
||||
if (rst_reg | (~transferstart))
|
||||
`else
|
||||
if (rst_reg)
|
||||
`endif
|
||||
sub_calc <= 1'b0;
|
||||
else if(~trn_reof_d1_n & ~trn_rsrc_rdy_d1_n & CplD & ~Wait_for_TX_desc) //set the bit, fliter out TX des
|
||||
sub_calc <= 1'b1;
|
||||
else if (sub_complete) //reset the bit
|
||||
sub_calc <= 1'b0;
|
||||
end
|
||||
|
||||
//This state machine does the addtion and subtraction of the dmarxs_div8_now
|
||||
//register
|
||||
//
|
||||
//Uses some multi-cycle paths:
|
||||
// addsub_state, dmarxs_div8_reg, dmarxs_div8_now -> dmarxs_div8_reg_new
|
||||
//are 2x multi-cycle paths
|
||||
//The signal "stay_2x" ensures that the state variable
|
||||
//addsub_state are static for at least two clock
|
||||
//cycles when in the AS_IDLE state - of course
|
||||
// dmarxs_div8_reg, dmarxs_div8_now signals must also be static for 2 cycles
|
||||
// while in this state
|
||||
always@(posedge clk)begin
|
||||
`ifdef TF_RECOVERY
|
||||
if(rst_reg | (~transferstart))begin
|
||||
`else
|
||||
if(rst_reg)begin
|
||||
`endif
|
||||
dmarxs_div8_reg_new[9:0] <= 0;
|
||||
update_dmarxs_div8_reg <= 1'b0;
|
||||
add_complete <= 1'b0;
|
||||
sub_complete <= 1'b0;
|
||||
stay_2x <= 1'b0;
|
||||
addsub_state <= AS_IDLE;
|
||||
end else begin
|
||||
case(addsub_state)
|
||||
AS_IDLE: begin
|
||||
update_dmarxs_div8_reg <= 1'b0;
|
||||
if(add_calc)begin
|
||||
//if add_calc is asserted then add the current value (*_now) to
|
||||
//the incoming dma xfer size (*_reg)
|
||||
dmarxs_div8_reg_new[9:0] <= dmarxs_div8_now[9:0]
|
||||
+ dmarxs_div8_reg[9:0];
|
||||
//make sure to stay in this state for two clock cycles
|
||||
if(~stay_2x)begin
|
||||
addsub_state <= AS_IDLE;
|
||||
add_complete <= 1'b0;
|
||||
update_dmarxs_div8_reg <= 1'b0;
|
||||
stay_2x <= 1'b1;
|
||||
//then update the current value (dmawxs_div8_now)
|
||||
end else begin
|
||||
addsub_state <= REGISTER_CALC;
|
||||
add_complete <= 1'b1;//clear add_calc
|
||||
update_dmarxs_div8_reg <= 1'b1;
|
||||
stay_2x <= 1'b0;
|
||||
end
|
||||
end else if (sub_calc)begin
|
||||
//if sub_calc is asserted then subtract the dw_length field
|
||||
//from the incoming completion packet from the current value
|
||||
dmarxs_div8_reg_new[9:0] <= dmarxs_div8_now[9:0]
|
||||
- {1'b0, dw_length_d1[9:1]};
|
||||
//likewise make sure to stat in this state for two clocks
|
||||
if(~stay_2x)begin
|
||||
addsub_state <= AS_IDLE;
|
||||
sub_complete <= 1'b0;
|
||||
update_dmarxs_div8_reg <= 1'b0;
|
||||
stay_2x <= 1'b1;
|
||||
//then update the current value (dmawxs_div8_now)
|
||||
end else begin
|
||||
addsub_state <= REGISTER_CALC;
|
||||
sub_complete <= 1'b1;//clear sub_calc
|
||||
update_dmarxs_div8_reg <= 1'b1;
|
||||
stay_2x <= 1'b0;
|
||||
end
|
||||
end else begin
|
||||
dmarxs_div8_reg_new[9:0] <= dmarxs_div8_now[9:0];
|
||||
addsub_state <= AS_IDLE;
|
||||
sub_complete <= 1'b0;
|
||||
add_complete <= 1'b0;
|
||||
stay_2x <= 1'b0;
|
||||
end
|
||||
end
|
||||
REGISTER_CALC:begin
|
||||
sub_complete <= 1'b0;
|
||||
add_complete <= 1'b0;
|
||||
addsub_state <= WAIT_FOR_REG;
|
||||
update_dmarxs_div8_reg <= 1'b1;
|
||||
stay_2x <= 1'b0;
|
||||
end
|
||||
WAIT_FOR_REG:begin
|
||||
update_dmarxs_div8_reg <= 1'b0;
|
||||
stay_2x <= 1'b0;
|
||||
addsub_state <= AS_IDLE;
|
||||
end
|
||||
default:begin
|
||||
dmarxs_div8_reg_new[9:0] <= 0;
|
||||
update_dmarxs_div8_reg <= 1'b0;
|
||||
add_complete <= 1'b0;
|
||||
sub_complete <= 1'b0;
|
||||
stay_2x <= 1'b0;
|
||||
addsub_state <= AS_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
//dmarxs_div8_now keeps the running total of the outstanding dma request
|
||||
always@(posedge clk)begin
|
||||
`ifdef TF_RECOVERY
|
||||
if(rst_reg | (~transferstart))begin
|
||||
`else
|
||||
if(rst_reg)begin
|
||||
`endif
|
||||
dmarxs_div8_now[9:0] <= 0;
|
||||
end else if(update_dmarxs_div8_reg)begin
|
||||
dmarxs_div8_now[9:0] <= dmarxs_div8_reg_new[9:0];
|
||||
end
|
||||
end
|
||||
|
||||
/// Jiansong: why pipeline?
|
||||
//when dmarxs_div8_now is zero then assert rd_dma_done_i
|
||||
//need to pipeline rd_dma_done_i for 250 MHz timing
|
||||
//reason: because it is fed-back into dmarxs_div8_now counter
|
||||
//(via update_dmarxs_div8_reg)and creates too many levels of logic if not
|
||||
//pipelined
|
||||
always@(posedge clk)begin
|
||||
rd_dma_done_i <= (dmarxs_div8_now[9:0] == 0) ? 1'b1 : 1'b0;
|
||||
end
|
||||
|
||||
//the rd_dma_done_early signal is asserted when the current count
|
||||
//dmarxs_div8_now has decremented down to 176 DWORDS (or 704 bytes)
|
||||
//the rd_dma_done_early signal is fedback to the dma_ctrl_wrapper so that
|
||||
//it can execute another sub-transfer
|
||||
//assign rd_dma_done_early = (dmarxs_div8_now[9:0] == 10'h0B0) ? 1'b1 : 1'b0;
|
||||
// Jiansong: the size of compeleter could be 64bytes or 128bytes, "==" could be not satisfied
|
||||
//assign rd_dma_done_early = (dmarxs_div8_now[9:0] <= 10'h0B0) ? 1'b1 : 1'b0;
|
||||
assign rd_dma_done_early = (dmarxs_div8_now[9:0] == 10'h000) ? 1'b1 : 1'b0;
|
||||
|
||||
//rising edge detectors for rd_dma_done_i and rd_dma_done_early
|
||||
rising_edge_detect rd_dma_done_one_inst(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.in(rd_dma_done_i),
|
||||
.one_shot_out(rd_dma_done_one)
|
||||
);
|
||||
rising_edge_detect rd_dma_done_early_one_inst(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.in(rd_dma_done_early),
|
||||
.one_shot_out(rd_dma_done_early_one)
|
||||
);
|
||||
|
||||
/// Jiansong: parameter to tune
|
||||
//If rd_dma_done_early comparison number is adjusted than this logic should be
|
||||
//adjusted accordingly. For example, if the comparison is 10'h070 (or 448
|
||||
//bytes) than the _early signal should only be used when the transfer size,
|
||||
//dmarxs, is larger than this. In this particular case 1KB is the next larger
|
||||
//transfer size. Note that these choices could be fine
|
||||
//tuned for higher-performance on a system-by-system basis
|
||||
always@(posedge clk)begin
|
||||
//Any transfer 1KB or larger and the *early signal is used -
|
||||
//Also, always use the regular done signal if it is the very last transfer.
|
||||
//// if(read_last || dmarxs[12:10] == 0) ///Jiansong: bug in 1KB size
|
||||
if(read_last || dmarxs[12:11] == 0)
|
||||
rd_dma_done <= rd_dma_done_one;
|
||||
else
|
||||
rd_dma_done <= rd_dma_done_early_one;
|
||||
end
|
||||
|
||||
///// Jiansong: output to tx_sm
|
||||
//always@(posedge clk)begin
|
||||
// np_rx_cnt_qw[9:0] <= dmarxs_div8_now[9:0];
|
||||
//end
|
||||
//assign np_rx_cnt_qw[9:0] = dmarxs_div8_now[9:0];
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 06/01/2009
|
||||
// Design Name:
|
||||
// Module Name: tx_engine
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose: Create tags for the non-posted packet generators.
|
||||
// Uses a simple 5-bit counter which rolls over
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module tag_generator(
|
||||
input clk,
|
||||
input rst,
|
||||
output reg np_tag_gnt,
|
||||
input np_tag_inc,
|
||||
output [7:0] tag_value,
|
||||
input [31:0] completion_pending);
|
||||
|
||||
|
||||
reg rst_reg;
|
||||
reg [4:0] tag_value_i;
|
||||
always@(posedge clk) rst_reg <= rst;
|
||||
|
||||
//check to see if the tag is already in use
|
||||
//assert the grant signal if it is not
|
||||
always@(posedge clk)begin
|
||||
if(completion_pending[tag_value_i[4:0]])
|
||||
np_tag_gnt <= 1'b0;
|
||||
else
|
||||
np_tag_gnt <= 1'b1;
|
||||
end
|
||||
|
||||
|
||||
assign tag_value[7:0] = {3'b000,tag_value_i[4:0]};
|
||||
|
||||
//tag generator is simply a counter with enable
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)begin
|
||||
tag_value_i[4:0] <= 5'b00000;
|
||||
end else if(np_tag_inc)begin
|
||||
tag_value_i <= tag_value_i + 1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,663 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
`include "Sora_config.v"
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 19:46:08 09/03/2012
|
||||
// Design Name:
|
||||
// Module Name: transfer_controller
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module transfer_controller(
|
||||
input clk,
|
||||
input rst,
|
||||
// triggers
|
||||
`ifdef TF_RECOVERY
|
||||
input transferstart,
|
||||
`endif
|
||||
input transferstart_one,
|
||||
output set_transfer_done_bit,
|
||||
input [63:0] TransferSrcAddr,
|
||||
///Jiansong: interface from RX engine, TX desc received
|
||||
input new_des_one,
|
||||
input [31:0] SourceAddr_L,
|
||||
input [31:0] SourceAddr_H,
|
||||
input [31:0] DestAddr,
|
||||
input [23:0] FrameSize,
|
||||
input [7:0] FrameControl,
|
||||
///Jiansong: interface to RX engine, indicate the system is in dma read for TX desc
|
||||
/// when this signal is asserted, received cpld will not be count in
|
||||
/// length subtraction
|
||||
output reg Wait_for_TX_desc,
|
||||
/// Jiansong: interface to/from posted_packet_generator
|
||||
/// TX desc write back
|
||||
output reg TX_desc_write_back_req,
|
||||
input TX_desc_write_back_ack,
|
||||
output reg [63:0] SourceAddr_r,
|
||||
output reg [31:0] DestAddr_r,
|
||||
output reg [23:0] FrameSize_r,
|
||||
output reg [7:0] FrameControl_r,
|
||||
output reg [63:0] DescAddr_r,
|
||||
/// Jiansong: interface to non_posted packet generator
|
||||
output reg rd_TX_des_start,
|
||||
output [63:0] TX_des_addr,
|
||||
//outputs to Internal DMA CTRL block
|
||||
output reg [31:0] reg_data_in_o,
|
||||
output reg [6:0] reg_wr_addr_o,
|
||||
output reg reg_wren_o,
|
||||
|
||||
//Input DMA done signals from TX and RX Engines
|
||||
input rd_dma_done_i,
|
||||
|
||||
//Output DMA done signals to Internal DMA CTRL block
|
||||
//these are copies of the *_dma_done_i inputs
|
||||
output reg rd_dma_done_o,
|
||||
//the *_last signals are used by the tx_trn_sm block and rx_trn_data_fsm
|
||||
//block so they can generate the most accurate *_done signals possible;
|
||||
//this is needed for accurate performance measurements
|
||||
output read_last, //active high during the very last DMA read of a series
|
||||
|
||||
//input from dma_ddr2_if
|
||||
input pause_read_requests
|
||||
|
||||
);
|
||||
|
||||
//state machine state definitions for state_sm0
|
||||
localparam IDLE_SM0 = 4'h0;
|
||||
localparam READ_1 = 4'h7;
|
||||
localparam READ_2 = 4'h8;
|
||||
localparam READ_3 = 4'h9;
|
||||
localparam READ_4 = 4'ha;
|
||||
localparam READ_5 = 4'hb;
|
||||
localparam READ_6 = 4'hc;
|
||||
|
||||
//state machine state definitions for state_sm3
|
||||
localparam IDLE_SM3 = 4'h0;
|
||||
localparam CALC_NEXT_READ = 4'h1;
|
||||
localparam READ_CALC_4KB = 4'h2;
|
||||
localparam READ_CALC_2KB = 4'h3;
|
||||
localparam READ_CALC_1KB = 4'h4;
|
||||
localparam READ_CALC_512B = 4'h5;
|
||||
localparam READ_CALC_256B = 4'h6;
|
||||
localparam READ_CALC_128B = 4'h7;
|
||||
localparam WAIT_READ_CALC = 4'h8;
|
||||
|
||||
//state machine state definitions for state_sm4
|
||||
localparam IDLE_SM4 = 3'b000;
|
||||
localparam START_RD = 3'b001;
|
||||
localparam WAIT_FOR_RDDONE = 3'b010;
|
||||
/// Jiansong: pipeline registers
|
||||
reg new_des_one_r;
|
||||
//reg [63:0] SourceAddr_r;
|
||||
//reg [31:0] DestAddr_r;
|
||||
//reg [23:0] FrameSize_r;
|
||||
//reg [7:0] FrameControl_r;
|
||||
|
||||
//the dma*_now are used for providing DMA parameters to the
|
||||
//DMA Internal CTRL block
|
||||
reg [31:0] dmarad_now;
|
||||
reg [63:0] dmaras_now;
|
||||
reg [31:0] dmarxs_now;
|
||||
//the dma*_next registers make up the "next" set of DMA parameters in a series
|
||||
//of DMA transactions
|
||||
reg [31:0] dmarad_next;
|
||||
reg [63:0] dmaras_next;
|
||||
reg [31:0] dmarxs_next;
|
||||
|
||||
//State machine state variables
|
||||
reg [3:0] state_0;
|
||||
reg [3:0] state_3;
|
||||
reg [2:0] state_4;
|
||||
|
||||
reg [31:0] reg_data_in_o_r;
|
||||
reg [6:0] reg_wr_addr_o_r;
|
||||
reg reg_wren_o_r;
|
||||
|
||||
reg update_dma_rnow;
|
||||
reg set_rd_done_bit;
|
||||
reg start_sm0_rdma_flow;
|
||||
reg read_calc_next;
|
||||
reg stay_2x_3;
|
||||
|
||||
assign set_transfer_done_bit = set_rd_done_bit;
|
||||
|
||||
/// Jiansong: generate Wait_for_TX_desc signal
|
||||
always@(posedge clk)begin
|
||||
`ifdef TF_RECOVERY
|
||||
if(rst | (~transferstart))
|
||||
`else
|
||||
if(rst)
|
||||
`endif
|
||||
Wait_for_TX_desc <= 0;
|
||||
else if (transferstart_one)
|
||||
Wait_for_TX_desc <= 1;
|
||||
else if (new_des_one_r)
|
||||
Wait_for_TX_desc <= 0;
|
||||
else
|
||||
Wait_for_TX_desc <= Wait_for_TX_desc;
|
||||
end
|
||||
|
||||
/// Jiansong: output signal for tx desc
|
||||
always@(posedge clk)begin
|
||||
`ifdef TF_RECOVERY
|
||||
if(rst | (~transferstart))
|
||||
`else
|
||||
if(rst)
|
||||
`endif
|
||||
rd_TX_des_start <= 1'b0;
|
||||
else if (transferstart_one)
|
||||
rd_TX_des_start <= 1'b1;
|
||||
else if (new_des_one_r)
|
||||
rd_TX_des_start <= 1'b0;
|
||||
else
|
||||
rd_TX_des_start <= rd_TX_des_start;
|
||||
end
|
||||
|
||||
assign TX_des_addr = TransferSrcAddr[63:0];
|
||||
|
||||
//drive the *_done outputs to the Internal Control Block
|
||||
//with the *_done inputs from the RX and TX engines
|
||||
always@(*) rd_dma_done_o = rd_dma_done_i;
|
||||
|
||||
|
||||
/// Jiansong: dma read related logic should be kept, and dma write related
|
||||
/// logic is no longer used
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
//NOTE:All of the code beneath this comment block are statemachines for
|
||||
//driving 4KB, 2KB, 1KB, 512B, 256B, and 128B sub-transfers to the
|
||||
//Internal Control Block
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/// Jiansong: remove dma write related states and keep dma read related states
|
||||
//State machine 0 block; Drives the Internal CTRL Block outputs:
|
||||
//reg_data_in_o[31:0], reg_wr_addr_o[6:0], and reg_wren_o.
|
||||
|
||||
//This machine (state 0) waits for a signal from state machines 2 or 4
|
||||
//(either start_sm0_wdma_flow or start_sm0_rdma_flow signals)
|
||||
//When one of these signals is asserted, a series of register writes to
|
||||
//the Internal Control Block occurs which effectively causes a small
|
||||
//sub-transfer to execute (4KB, 2KB, 1KB, 512B, 256B, 128B.
|
||||
//The dma*_now signals are passed to the Internal Control Block (via
|
||||
//reg_data_in_o, reg_wr_addr_o and reg_wren_o) as the sub-transfer parameters.
|
||||
//This state machine also asserts the
|
||||
//write_calc_next and read_calc_next signals which are inputs to state
|
||||
//machines 1 and 3 and which cause those state machines to calculate the
|
||||
//DMA parameters for the next sub-transfer.
|
||||
|
||||
always@(posedge clk) begin
|
||||
`ifdef TF_RECOVERY
|
||||
if(rst | (~transferstart))begin
|
||||
`else
|
||||
if(rst)begin
|
||||
`endif
|
||||
state_0 <= IDLE_SM0;
|
||||
reg_data_in_o_r[31:0] <= 32'h00000000;
|
||||
reg_wr_addr_o_r[6:0] <= 7'b0000000;
|
||||
reg_wren_o_r <= 1'b0;
|
||||
read_calc_next <= 1'b0;
|
||||
end else begin
|
||||
case(state_0)
|
||||
IDLE_SM0: begin
|
||||
reg_data_in_o_r[31:0] <= 32'h00000000;
|
||||
reg_wr_addr_o_r[6:0] <= 7'b0000000;
|
||||
reg_wren_o_r <= 1'b0;
|
||||
read_calc_next <= 1'b0;
|
||||
if(start_sm0_rdma_flow & ~pause_read_requests)begin /// Jiansong: enter READ_1 state
|
||||
state_0 <= READ_1;
|
||||
end
|
||||
end
|
||||
|
||||
//start of the series of writes to the dma read sub-transfer registers
|
||||
//in the Internal Control Block
|
||||
READ_1: begin //write the dmarad register
|
||||
reg_data_in_o_r[31:0] <= dmarad_now[31:0];
|
||||
reg_wr_addr_o_r[6:0] <= 7'b0010100;
|
||||
reg_wren_o_r <= 1'b1;
|
||||
read_calc_next <= 1'b1;
|
||||
state_0 <= READ_2;
|
||||
end
|
||||
READ_2: begin //write the dmaras_l register
|
||||
reg_data_in_o_r[31:0] <= dmaras_now[31:0];
|
||||
reg_wr_addr_o_r[6:0] <= 7'b0001100;
|
||||
reg_wren_o_r <= 1'b1;
|
||||
read_calc_next <= 1'b0;
|
||||
state_0 <= READ_3;
|
||||
end
|
||||
READ_3: begin //write the dmarad_u register
|
||||
reg_data_in_o_r[31:0] <= dmaras_now[63:32];
|
||||
reg_wr_addr_o_r[6:0] <= 7'b0010000;
|
||||
reg_wren_o_r <= 1'b1;
|
||||
state_0 <= READ_4;
|
||||
end
|
||||
READ_4: begin //write the dmarxs register with the next
|
||||
//largest possible sub-transfer size
|
||||
//// if(dmarxs_now[20:12] != 0)
|
||||
if(dmarxs_now[31:12] != 0)
|
||||
reg_data_in_o_r[31:0] <= 32'h00001000; //4KB
|
||||
else if (dmarxs_now[11])
|
||||
reg_data_in_o_r[31:0] <= 32'h00000800; //2KB
|
||||
else if (dmarxs_now[10])
|
||||
reg_data_in_o_r[31:0] <= 32'h00000400; //1KB
|
||||
else if (dmarxs_now[9])
|
||||
reg_data_in_o_r[31:0] <= 32'h00000200; //512B
|
||||
else if (dmarxs_now[8])
|
||||
reg_data_in_o_r[31:0] <= 32'h00000100; //256B
|
||||
else if (dmarxs_now[7])
|
||||
reg_data_in_o_r[31:0] <= 32'h00000080; //128B
|
||||
else
|
||||
reg_data_in_o_r[31:0] <= 32'h00000080;
|
||||
reg_wr_addr_o_r[6:0] <= 7'b0011100;
|
||||
reg_wren_o_r <= 1'b1;
|
||||
state_0 <= READ_5;
|
||||
end
|
||||
READ_5: begin //write a 1 to the done bit (dmacst[3] in Internal
|
||||
//Control Block) in order to clear the start
|
||||
//bit
|
||||
reg_data_in_o_r[31:0] <= 32'h00000008;
|
||||
reg_wr_addr_o_r[6:0] <= 7'b0101000;
|
||||
reg_wren_o_r <= 1'b1;
|
||||
state_0 <= READ_6;
|
||||
end
|
||||
READ_6: begin //write a 1 to the start bit (dmacst[2] in Internal
|
||||
//Control Block) in order to execute the sub-transfer
|
||||
reg_data_in_o_r[31:0] <= 32'h00000004;
|
||||
reg_wr_addr_o_r[6:0] <= 7'b0101000;
|
||||
reg_wren_o_r <= 1'b1;
|
||||
state_0 <= IDLE_SM0;
|
||||
end
|
||||
default:begin
|
||||
state_0 <= IDLE_SM0;
|
||||
reg_data_in_o_r[31:0] <= 32'h00000000;
|
||||
reg_wr_addr_o_r[6:0] <= 7'b0000000;
|
||||
reg_wren_o_r <= 1'b0;
|
||||
read_calc_next <= 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
//pipeline register outputs for 250 MHz timing
|
||||
always@(posedge clk)begin
|
||||
reg_data_in_o[31:0] <= reg_data_in_o_r[31:0];
|
||||
reg_wr_addr_o[6:0] <= reg_wr_addr_o_r[6:0];
|
||||
reg_wren_o <= reg_wren_o_r;
|
||||
end
|
||||
|
||||
//read_last is used by rx_engine so that it can signal
|
||||
//the correct *_done signal for the performance counters
|
||||
//Normally, rx_engine will use the *_early signal to
|
||||
//fire off a continuation transfer; on the last one
|
||||
//however, we would like the done signal to be accurate
|
||||
//for the performance counters
|
||||
|
||||
////assign read_last = (dmarxs_now == 0) ? 1'b1: 1'b0;
|
||||
/// Jiansong: protection. otherwise, if transfer size has size smaller than 128B, it will never stop
|
||||
assign read_last = (dmarxs_now[31:7] == 0) ? 1'b1: 1'b0;
|
||||
|
||||
//Calculate the next address, xfer size for writes /// Jiansong: for reads
|
||||
//and transfer to dma*_now registers
|
||||
//Uses some multi-cycle paths:
|
||||
// state_3 -> dma*_next
|
||||
//and dma*_now -> dma*_next
|
||||
//are both 2x multi-cycle paths
|
||||
//The signal "stay_2x_3" ensures that the state variable
|
||||
//state_3 is static for at least two clock
|
||||
//cycles when in the READ_CALC_*B states - the
|
||||
//dma*_now -> dma*_next paths must also be static during
|
||||
//these states
|
||||
always@(posedge clk)begin
|
||||
`ifdef TF_RECOVERY
|
||||
if(rst | (~transferstart))begin
|
||||
`else
|
||||
if(rst)begin
|
||||
`endif
|
||||
state_3 <= IDLE_SM3;
|
||||
stay_2x_3 <= 1'b0;
|
||||
update_dma_rnow <= 1'b0;
|
||||
dmarxs_next[31:0] <= 13'b0000000000000;
|
||||
dmaras_next[63:0] <= 64'h0000000000000000;
|
||||
dmarad_next[31:0] <= 32'h00000000;
|
||||
end else begin
|
||||
case(state_3)
|
||||
IDLE_SM3:begin
|
||||
update_dma_rnow <= 1'b0;
|
||||
stay_2x_3 <= 1'b0;
|
||||
if(new_des_one_r)begin
|
||||
dmarad_next <= DestAddr_r;
|
||||
dmarxs_next <= FrameSize_r;
|
||||
dmaras_next <= SourceAddr_r;
|
||||
end
|
||||
//if state machine 0 asserts read_calc_next and there
|
||||
//is still sub-transfers to be completed then go
|
||||
//ahead and precalculate the dma*_next parameters for the
|
||||
//next sub-transfer
|
||||
//// if(read_calc_next && (dmarxs_now[20:7] != 0))
|
||||
if(read_calc_next && (dmarxs_now[31:7] != 0)) /// Jiansong: 1M size limitation is relaxed
|
||||
state_3 <= CALC_NEXT_READ;
|
||||
else
|
||||
state_3 <= IDLE_SM3;
|
||||
end
|
||||
//This state is to figure out which will be the next
|
||||
//sub-transfer size based on sampling the dmarxs_now
|
||||
//signals - priority encoded for the largest possible transfer
|
||||
//to occur first.
|
||||
CALC_NEXT_READ:begin
|
||||
stay_2x_3 <= 1'b0;
|
||||
update_dma_rnow <= 1'b0;
|
||||
//// if(dmarxs_now[20:12] != 0)
|
||||
if(dmarxs_now[31:12] != 0) /// Jianosng: 1M size limitation is relaxed to 4G
|
||||
state_3 <= READ_CALC_4KB;
|
||||
else if (dmarxs_now[11])
|
||||
state_3 <= READ_CALC_2KB;
|
||||
else if (dmarxs_now[10])
|
||||
state_3 <= READ_CALC_1KB;
|
||||
else if (dmarxs_now[9])
|
||||
state_3 <= READ_CALC_512B;
|
||||
else if (dmarxs_now[8])
|
||||
state_3 <= READ_CALC_256B;
|
||||
else if (dmarxs_now[7])
|
||||
state_3 <= READ_CALC_128B;
|
||||
else
|
||||
state_3 <= READ_CALC_128B;
|
||||
end
|
||||
//The READ_CALC_*B states are for updating the dma*_next registers
|
||||
//with the correct terms
|
||||
READ_CALC_4KB:begin
|
||||
//subtract 4KB from dmarxs and add 4KB to dmarad_next and dmaras_next
|
||||
//// dmarxs_next[20:12] <= dmarxs_now[20:12] - 1'b1;
|
||||
dmarxs_next[31:12] <= dmarxs_now[31:12] - 1'b1;
|
||||
dmaras_next[63:0] <= dmaras_now[63:0] + 64'h0000000000001000;
|
||||
dmarad_next[31:0] <= dmarad_now[31:0] + 31'h00001000;
|
||||
//stay in this state for at least two clock cycles
|
||||
if(stay_2x_3 == 1'b0)begin
|
||||
state_3 <= READ_CALC_4KB;
|
||||
stay_2x_3 <= 1'b1;
|
||||
update_dma_rnow <= 1'b0;
|
||||
end else begin
|
||||
state_3 <= WAIT_READ_CALC;
|
||||
stay_2x_3 <= 1'b0;
|
||||
update_dma_rnow <= 1'b1;
|
||||
end
|
||||
end
|
||||
READ_CALC_2KB:begin
|
||||
//subtract 2KB from dmarxs and add 2KB to dmarad_next and dmaras_next
|
||||
dmarxs_next[11] <= 1'b0;
|
||||
dmaras_next[63:0] <= dmaras_now[63:0] + 64'h0000000000000800;
|
||||
dmarad_next[31:0] <= dmarad_now[31:0] + 31'h00000800;
|
||||
//stay in this state for at least two clock cycles
|
||||
if(stay_2x_3 == 1'b0)begin
|
||||
state_3 <= READ_CALC_2KB;
|
||||
stay_2x_3 <= 1'b1;
|
||||
update_dma_rnow <= 1'b0;
|
||||
end else begin
|
||||
state_3 <= WAIT_READ_CALC;
|
||||
stay_2x_3 <= 1'b0;
|
||||
update_dma_rnow <= 1'b1;
|
||||
end
|
||||
end
|
||||
READ_CALC_1KB:begin
|
||||
//subtract 1KB from dmarxs and add 1KB to dmarad_next and dmaras_next
|
||||
dmarxs_next[10] <= 1'b0;
|
||||
dmaras_next[63:0] <= dmaras_now[63:0] + 64'h0000000000000400;
|
||||
dmarad_next[31:0] <= dmarad_now[31:0] + 31'h00000400;
|
||||
//stay in this state for at least two clock cycles
|
||||
if(stay_2x_3 == 1'b0)begin
|
||||
state_3 <= READ_CALC_1KB;
|
||||
stay_2x_3 <= 1'b1;
|
||||
update_dma_rnow <= 1'b0;
|
||||
end else begin
|
||||
state_3 <= WAIT_READ_CALC;
|
||||
stay_2x_3 <= 1'b0;
|
||||
update_dma_rnow <= 1'b1;
|
||||
end
|
||||
end
|
||||
READ_CALC_512B:begin
|
||||
//subtract 512B from dmarxs and add 512B to dmarad_next and dmaras_next
|
||||
dmarxs_next[9] <= 1'b0;
|
||||
dmaras_next[63:0] <= dmaras_now[63:0] + 64'h0000000000000200;
|
||||
dmarad_next[31:0] <= dmarad_now[31:0] + 31'h00000200;
|
||||
//stay in this state for at least two clock cycles
|
||||
if(stay_2x_3 == 1'b0)begin
|
||||
state_3 <= READ_CALC_512B;
|
||||
stay_2x_3 <= 1'b1;
|
||||
update_dma_rnow <= 1'b0;
|
||||
end else begin
|
||||
state_3 <= WAIT_READ_CALC;
|
||||
stay_2x_3 <= 1'b0;
|
||||
update_dma_rnow <= 1'b1;
|
||||
end
|
||||
end
|
||||
READ_CALC_256B:begin
|
||||
//subtract 256B from dmarxs and add 256B to dmarad_next and dmaras_next
|
||||
dmarxs_next[8] <= 1'b0;
|
||||
dmaras_next[63:0] <= dmaras_now[63:0] + 64'h0000000000000100;
|
||||
dmarad_next[31:0] <= dmarad_now[31:0] + 31'h00000100;
|
||||
//stay in this state for at least two clock cycles
|
||||
if(stay_2x_3 == 1'b0)begin
|
||||
state_3 <= READ_CALC_256B;
|
||||
stay_2x_3 <= 1'b1;
|
||||
update_dma_rnow <= 1'b0;
|
||||
end else begin
|
||||
state_3 <= WAIT_READ_CALC;
|
||||
stay_2x_3 <= 1'b0;
|
||||
update_dma_rnow <= 1'b1;
|
||||
end
|
||||
end
|
||||
READ_CALC_128B:begin
|
||||
//subtract 128B from dmarxs and add 128B to dmarad_next and dmaras_next
|
||||
dmarxs_next[7] <= 1'b0;
|
||||
dmaras_next[63:0] <= dmaras_now[63:0] + 64'h0000000000000080;
|
||||
dmarad_next[31:0] <= dmarad_now[31:0] + 31'h00000080;
|
||||
//stay in this state for at least two clock cycles
|
||||
if(stay_2x_3 == 1'b0)begin
|
||||
state_3 <= READ_CALC_128B;
|
||||
stay_2x_3 <= 1'b1;
|
||||
update_dma_rnow <= 1'b0;
|
||||
end else begin
|
||||
state_3 <= WAIT_READ_CALC;
|
||||
stay_2x_3 <= 1'b0;
|
||||
update_dma_rnow <= 1'b1;
|
||||
end
|
||||
end
|
||||
WAIT_READ_CALC:begin
|
||||
stay_2x_3 <= 1'b0;
|
||||
update_dma_rnow <= 1'b0;
|
||||
state_3 <= IDLE_SM3;
|
||||
end
|
||||
default:begin
|
||||
state_3 <= IDLE_SM3;
|
||||
stay_2x_3 <= 1'b0;
|
||||
update_dma_rnow <= 1'b0;
|
||||
dmarxs_next[31:0] <= 13'b0000000000000;
|
||||
dmaras_next[63:0] <= 64'h0000000000000000;
|
||||
dmarad_next[31:0] <= 32'h00000000;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/// Jiansong:generate request for tx desc write back
|
||||
always@(posedge clk)begin
|
||||
`ifdef TF_RECOVERY
|
||||
if(rst | (~transferstart)) begin
|
||||
`else
|
||||
if(rst) begin
|
||||
`endif
|
||||
TX_desc_write_back_req <= 1'b0;
|
||||
end else if (set_rd_done_bit) begin
|
||||
TX_desc_write_back_req <= 1'b1;
|
||||
end else if (TX_desc_write_back_ack) begin
|
||||
TX_desc_write_back_req <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
/// Jiansong: pipeline registers for timing
|
||||
always@(posedge clk)begin
|
||||
`ifdef TF_RECOVERY
|
||||
if(rst | (~transferstart))begin
|
||||
`else
|
||||
if(rst)begin
|
||||
`endif
|
||||
new_des_one_r <= 1'b0;
|
||||
end else begin
|
||||
new_des_one_r <= new_des_one;
|
||||
end
|
||||
end
|
||||
always@(posedge clk)begin
|
||||
`ifdef TF_RECOVERY
|
||||
if(rst | ((~transferstart)))begin
|
||||
`else
|
||||
if(rst)begin
|
||||
`endif
|
||||
SourceAddr_r <= 64'h0000_0000_0000_0000;
|
||||
DestAddr_r <= 32'h0000_0000;
|
||||
FrameSize_r <= 24'h00_00_00;
|
||||
FrameControl_r <= 8'h00;
|
||||
DescAddr_r <= 64'h0000_0000_0000_0000;
|
||||
end else if(new_des_one)begin
|
||||
SourceAddr_r <= {SourceAddr_H,SourceAddr_L};
|
||||
DestAddr_r <= DestAddr;
|
||||
FrameSize_r <= FrameSize;
|
||||
FrameControl_r <= FrameControl;
|
||||
DescAddr_r <= TransferSrcAddr[63:0];
|
||||
end else if (set_rd_done_bit) begin
|
||||
SourceAddr_r <= SourceAddr_r;
|
||||
DestAddr_r <= DestAddr_r;
|
||||
FrameSize_r <= FrameSize_r;
|
||||
FrameControl_r <= {FrameControl_r[7:1],1'b0}; // clear own bit
|
||||
DescAddr_r <= DescAddr_r;
|
||||
end else begin
|
||||
SourceAddr_r <= SourceAddr_r;
|
||||
DestAddr_r <= DestAddr_r;
|
||||
FrameSize_r <= FrameSize_r;
|
||||
FrameControl_r <= FrameControl_r;
|
||||
DescAddr_r <= DescAddr_r;
|
||||
end
|
||||
end
|
||||
|
||||
//register dmarad,dmarxs, and dmaras when rd_dma_start_one is high
|
||||
//rd_dma_start_one is only asserted for one clock cycle
|
||||
always@(posedge clk)begin
|
||||
`ifdef TF_RECOVERY
|
||||
if(rst | (~transferstart))begin
|
||||
`else
|
||||
if(rst)begin
|
||||
`endif
|
||||
dmaras_now <= 64'h0000_0000_0000_0000;
|
||||
dmarxs_now <= 32'h0000_0000;
|
||||
dmarad_now <= 32'h0000_0000;
|
||||
end else if(new_des_one_r)begin /// Jiansong: dma read (or data transfer) is started
|
||||
/// after a new descriptor is received
|
||||
dmarad_now <= DestAddr_r;
|
||||
dmarxs_now <= FrameSize_r;
|
||||
dmaras_now <= SourceAddr_r;
|
||||
end else if(update_dma_rnow)begin
|
||||
dmarad_now <= dmarad_next;
|
||||
dmarxs_now <= dmarxs_next;
|
||||
dmaras_now <= dmaras_next;
|
||||
end
|
||||
end
|
||||
|
||||
//state machine for start_sm0_rdma_flow signal
|
||||
//This state machine controls state machine 0 by
|
||||
//driving the start_sm0_rdma_flow signal. It monitors
|
||||
//the rd_dma_done signal from the rx_engine
|
||||
//and starts a new dma subtransfer whenever rd_dma_done is signalled
|
||||
always@(posedge clk)begin
|
||||
`ifdef TF_RECOVERY
|
||||
if(rst | (~transferstart))begin
|
||||
`else
|
||||
if(rst)begin
|
||||
`endif
|
||||
start_sm0_rdma_flow <= 1'b0;
|
||||
state_4 <= IDLE_SM4;
|
||||
set_rd_done_bit <= 1'b0;
|
||||
end else begin
|
||||
case(state_4)
|
||||
IDLE_SM4:begin
|
||||
start_sm0_rdma_flow <= 1'b0;
|
||||
set_rd_done_bit <= 1'b0;
|
||||
//wait for the start signal from the host
|
||||
if(new_des_one_r) /// Jiansong: dma read (or data transfer) is started
|
||||
/// after a new descriptor is received
|
||||
state_4 <= START_RD;
|
||||
end
|
||||
START_RD:begin
|
||||
//start the state_0 state machine by
|
||||
//asserting start_sm0_rdma_flow signal
|
||||
start_sm0_rdma_flow <= 1'b1;
|
||||
//when state_0 finally starts go to the
|
||||
//WAIT_FOR_RDDONE state
|
||||
if(state_0 == READ_1)
|
||||
state_4 <= WAIT_FOR_RDDONE;
|
||||
else
|
||||
state_4 <= START_RD;
|
||||
end
|
||||
WAIT_FOR_RDDONE:begin
|
||||
start_sm0_rdma_flow <= 1'b0;
|
||||
//If the rx_engine signals rd_dma_done_i and we
|
||||
//have completed the last subtransfer (i.e. dmarxs_now == 0) then
|
||||
//set the dmacst[3] bit via set_rd_done_bit and go to the IDLE state;
|
||||
//Otherwise start the next subtransfer by going to the
|
||||
//START_RD state
|
||||
//// if(rd_dma_done_i && (dmarxs_now == 0))begin ///Jiansong: will not stop if has piece smaller than 128B
|
||||
if(rd_dma_done_i && (dmarxs_now[31:7] == 0))begin
|
||||
state_4 <= IDLE_SM4;
|
||||
set_rd_done_bit <= 1'b1;
|
||||
end else if(rd_dma_done_i)begin
|
||||
state_4 <= START_RD;
|
||||
set_rd_done_bit <= 1'b0;
|
||||
end else begin
|
||||
state_4 <= WAIT_FOR_RDDONE;
|
||||
set_rd_done_bit <= 1'b0;
|
||||
end
|
||||
end
|
||||
default:begin
|
||||
start_sm0_rdma_flow <= 1'b0;
|
||||
state_4 <= IDLE_SM4;
|
||||
set_rd_done_bit <= 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,358 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 06/01/2009
|
||||
// Design Name:
|
||||
// Module Name: tx_engine
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose: Tx engine wrapper file. Connects
|
||||
// accompanying fifos to the TX TRN State Machine module.
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
// Modification by zjs, 2009-6-18, pending
|
||||
// (1) move posted packet generator and non-posted packet generator out --- done
|
||||
// (2) add dma write data fifo --------------- done
|
||||
// (3) modify tx sm
|
||||
// scheduling -------------------------- done
|
||||
// disable write dma done -------------- done
|
||||
// register/memory read ---------------- done
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module tx_engine(
|
||||
input clk,
|
||||
// input rst,
|
||||
// input hostreset,
|
||||
input full_rst,
|
||||
input soft_rst,
|
||||
|
||||
/// Jiansong: new interface added for register read / memory read operation
|
||||
//interface to DMA control wrapper, for register data
|
||||
input [31:0] Mrd_data_in, // 32 bits register read assumed
|
||||
output [11:0] Mrd_data_addr,
|
||||
|
||||
//interface to PCIE Endpoint Block Plus
|
||||
input [15:0] pcie_id,
|
||||
output [63:0] trn_td,
|
||||
output [7:0] trn_trem_n,
|
||||
output trn_tsof_n,
|
||||
output trn_teof_n,
|
||||
output trn_tsrc_rdy_n,
|
||||
output trn_tsrc_dsc_n,
|
||||
input trn_tdst_rdy_n,
|
||||
input trn_tdst_dsc_n,
|
||||
output trn_terrfwd_n,
|
||||
input [2:0] trn_tbuf_av,
|
||||
|
||||
/// Jiansong: interface to non_posted_pkt_gen
|
||||
input non_posted_fifo_wren,
|
||||
input [63:0] non_posted_fifo_data,
|
||||
|
||||
/// Jiansong: interface to posted_pkt_gen
|
||||
input posted_fifo_wren,
|
||||
input [63:0] posted_fifo_data,
|
||||
output posted_fifo_full,
|
||||
|
||||
/// Jiansong: interface from posted_pkt_gen to dma write data fifo
|
||||
input [63:0] dma_write_data_fifo_data,
|
||||
input dma_write_data_fifo_wren,
|
||||
output dma_write_data_fifo_full,
|
||||
|
||||
/// Jiansong: keep completion logic in TX engine
|
||||
//interface to RX Engine
|
||||
input [6:0] bar_hit,
|
||||
input MRd,
|
||||
input MWr,
|
||||
input [31:0] MEM_addr,
|
||||
input [15:0] MEM_req_id,
|
||||
input [7:0] MEM_tag,
|
||||
input header_fields_valid,
|
||||
// Jiansong: input from rx_monitor
|
||||
input rd_dma_start, //indicates the start of a read dma xfer
|
||||
input [12:3] dmarxs //size of the complete transfer
|
||||
// input [9:0] np_rx_cnt_qw,
|
||||
// input transferstart,
|
||||
// input Wait_for_TX_desc
|
||||
// debug interface
|
||||
// output [31:0] Debug21RX2,
|
||||
// output [31:0] Debug25RX6,
|
||||
// output [7:0] FIFOErrors
|
||||
);
|
||||
|
||||
wire posted_hdr_fifo_rden;
|
||||
wire [63:0] posted_hdr_fifo;
|
||||
wire posted_hdr_fifo_empty;
|
||||
|
||||
wire non_posted_hdr_fifo_rden;
|
||||
wire [63:0] non_posted_hdr_fifo;
|
||||
wire non_posted_hdr_fifo_empty;
|
||||
wire non_posted_hdr_fifo_full;
|
||||
|
||||
wire comp_fifo_wren;
|
||||
wire [63:0] comp_fifo_data;
|
||||
wire comp_hdr_fifo_rden;
|
||||
wire [63:0] comp_hdr_fifo;
|
||||
wire comp_hdr_fifo_empty;
|
||||
wire comp_hdr_fifo_full;
|
||||
|
||||
/// Jiansong: posted data fifo interface
|
||||
wire [63:0] posted_data_fifo_data;
|
||||
wire posted_data_fifo_rden;
|
||||
wire posted_data_fifo_empty;
|
||||
wire posted_data_fifo_real_full;
|
||||
|
||||
/// Jiansong
|
||||
wire rst_tx;
|
||||
|
||||
// /// FIFO errors
|
||||
// reg p_hdr_fifo_overflow;
|
||||
// reg p_hdr_fifo_underflow;
|
||||
// reg p_data_fifo_overflow;
|
||||
// reg p_data_fifo_underflow;
|
||||
// reg cmp_hdr_fifo_overflow;
|
||||
// reg cmp_hdr_fifo_underflow;
|
||||
// reg np_hdr_fifo_overflow;
|
||||
// reg np_hdr_fifo_underflow;
|
||||
|
||||
// assign FIFOErrors[0] = p_hdr_fifo_overflow;
|
||||
// assign FIFOErrors[1] = p_hdr_fifo_underflow;
|
||||
// assign FIFOErrors[2] = p_data_fifo_overflow;
|
||||
// assign FIFOErrors[3] = p_data_fifo_underflow;
|
||||
// assign FIFOErrors[4] = cmp_hdr_fifo_overflow;
|
||||
// assign FIFOErrors[5] = cmp_hdr_fifo_underflow;
|
||||
// assign FIFOErrors[6] = np_hdr_fifo_overflow;
|
||||
// assign FIFOErrors[7] = np_hdr_fifo_underflow;
|
||||
//
|
||||
// always@(posedge clk) begin
|
||||
// if (rst_tx)
|
||||
// p_hdr_fifo_overflow <= 1'b0;
|
||||
// else if (posted_fifo_full & posted_fifo_wren)
|
||||
// p_hdr_fifo_overflow <= 1'b1;
|
||||
// else
|
||||
// p_hdr_fifo_overflow <= p_hdr_fifo_overflow;
|
||||
// end
|
||||
// always@(posedge clk) begin
|
||||
// if (rst_tx)
|
||||
// p_hdr_fifo_underflow <= 1'b0;
|
||||
// else if (posted_hdr_fifo_empty & posted_hdr_fifo_rden)
|
||||
// p_hdr_fifo_underflow <= 1'b1;
|
||||
// else
|
||||
// p_hdr_fifo_underflow <= p_hdr_fifo_underflow;
|
||||
// end
|
||||
// always@(posedge clk) begin
|
||||
// if (rst_tx)
|
||||
// p_data_fifo_overflow <= 1'b0;
|
||||
// else if (posted_data_fifo_real_full & dma_write_data_fifo_wren)
|
||||
// p_data_fifo_overflow <= 1'b1;
|
||||
// else
|
||||
// p_data_fifo_overflow <= p_data_fifo_overflow;
|
||||
// end
|
||||
// always@(posedge clk) begin
|
||||
// if (rst_tx)
|
||||
// p_data_fifo_underflow <= 1'b0;
|
||||
// else if (posted_data_fifo_empty & posted_data_fifo_rden)
|
||||
// p_data_fifo_underflow <= 1'b1;
|
||||
// else
|
||||
// p_data_fifo_underflow <= p_data_fifo_underflow;
|
||||
// end
|
||||
// always@(posedge clk) begin
|
||||
// if (rst_tx)
|
||||
// cmp_hdr_fifo_overflow <= 1'b0;
|
||||
// else if (comp_hdr_fifo_full & comp_fifo_wren)
|
||||
// cmp_hdr_fifo_overflow <= 1'b1;
|
||||
// else
|
||||
// cmp_hdr_fifo_overflow <= cmp_hdr_fifo_overflow;
|
||||
// end
|
||||
// always@(posedge clk) begin
|
||||
// if (rst_tx)
|
||||
// cmp_hdr_fifo_underflow <= 1'b0;
|
||||
// else if (comp_hdr_fifo_empty & comp_hdr_fifo_rden)
|
||||
// cmp_hdr_fifo_underflow <= 1'b1;
|
||||
// else
|
||||
// cmp_hdr_fifo_underflow <= cmp_hdr_fifo_underflow;
|
||||
// end
|
||||
// always@(posedge clk) begin
|
||||
// if (rst_tx)
|
||||
// np_hdr_fifo_overflow <= 1'b0;
|
||||
// else if (non_posted_hdr_fifo_full & non_posted_fifo_wren)
|
||||
// np_hdr_fifo_overflow <= 1'b1;
|
||||
// else
|
||||
// np_hdr_fifo_overflow <= np_hdr_fifo_overflow;
|
||||
// end
|
||||
// always@(posedge clk) begin
|
||||
// if (rst_tx)
|
||||
// np_hdr_fifo_underflow <= 1'b0;
|
||||
// else if (non_posted_hdr_fifo_empty & non_posted_hdr_fifo_rden)
|
||||
// np_hdr_fifo_underflow <= 1'b1;
|
||||
// else
|
||||
// np_hdr_fifo_underflow <= np_hdr_fifo_underflow;
|
||||
// end
|
||||
|
||||
/// Jiansong: timing solution, what does it mean?
|
||||
// //register and dup wr_dma_start_one for 250 MHz timing;
|
||||
// (*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg wr_dma_start_one_reg1,
|
||||
// wr_dma_start_one_reg2;
|
||||
//// reg wr_dma_start_one_reg1;
|
||||
|
||||
/// Jiansong: why the depth is 128? Performance consideration?
|
||||
/// Jiansong: full signal is never used
|
||||
// Fifo is a 64 x 128 coregen fifo made out of distributed ram
|
||||
a64_128_distram_fifo a64_128_distram_fifo_p(
|
||||
.clk(clk),
|
||||
.rst(rst_tx),
|
||||
//interface to posted_pkt_gen
|
||||
.din(posted_fifo_data),
|
||||
.wr_en(posted_fifo_wren),
|
||||
//// .full(posted_hdr_fifo_full),
|
||||
.full(posted_fifo_full),
|
||||
//interface to tx_trn_sm
|
||||
.dout(posted_hdr_fifo),
|
||||
.rd_en(posted_hdr_fifo_rden),
|
||||
.empty(posted_hdr_fifo_empty)
|
||||
);
|
||||
|
||||
/// Jiansong: full signal is never used
|
||||
//Fifo is a 64 x 64 coregen fifo made out of distributed ram
|
||||
a64_64_distram_fifo a64_64_distram_fifo_np(
|
||||
.clk(clk),
|
||||
.rst(rst_tx),
|
||||
//inteface to non_posted_pkt_gen
|
||||
.din(non_posted_fifo_data),
|
||||
.wr_en(non_posted_fifo_wren),
|
||||
.full(non_posted_hdr_fifo_full),
|
||||
//interface to tx_trn_sm
|
||||
.dout(non_posted_hdr_fifo),
|
||||
.rd_en(non_posted_hdr_fifo_rden),
|
||||
.empty(non_posted_hdr_fifo_empty)
|
||||
);
|
||||
|
||||
// Instantiate the completer packet generator
|
||||
completer_pkt_gen completer_pkt_gen_inst (
|
||||
.clk(clk),
|
||||
.rst(rst_tx),
|
||||
//interface to RX Engine (except comp_id from PCIe block)
|
||||
.bar_hit(bar_hit[6:0]),
|
||||
.comp_req(MRd & header_fields_valid),
|
||||
.MEM_addr(MEM_addr[31:0]),
|
||||
.MEM_req_id(MEM_req_id[15:0]),
|
||||
.comp_id(pcie_id[15:0]), //req_id becomes completer id
|
||||
.MEM_tag(MEM_tag[7:0]),
|
||||
//inteface to completion header fifo (a64_64_distram_fifo_comp)
|
||||
.comp_fifo_wren(comp_fifo_wren),
|
||||
.comp_fifo_data(comp_fifo_data[63:0])
|
||||
);
|
||||
|
||||
//Fifo is a 64 x 64 coregen fifo made out of distributed ram
|
||||
a64_64_distram_fifo a64_64_distram_fifo_comp(
|
||||
.clk(clk),
|
||||
.rst(rst_tx),
|
||||
//interface to completer_pkt_gen
|
||||
.din(comp_fifo_data[63:0]),
|
||||
.wr_en(comp_fifo_wren),
|
||||
.full(comp_hdr_fifo_full),
|
||||
//interface to tx_trn_sm
|
||||
.dout(comp_hdr_fifo),
|
||||
.rd_en(comp_hdr_fifo_rden),
|
||||
.empty(comp_hdr_fifo_empty)
|
||||
);
|
||||
|
||||
/// Jiansong: Data TRN DMA Write FIFO, pending
|
||||
//Instantiate the Data TRN DMA Write FIFO
|
||||
//This is an 4KB FIFO constructed of BRAM
|
||||
//Provides buffering for RX data and RX descriptor
|
||||
data_trn_dma_write_fifo data_trn_dma_write_fifo_inst(
|
||||
.din (dma_write_data_fifo_data),
|
||||
.rd_en (posted_data_fifo_rden),
|
||||
.rst (rst_tx),
|
||||
.clk (clk),
|
||||
.wr_en (dma_write_data_fifo_wren),
|
||||
.dout (posted_data_fifo_data),
|
||||
.empty (posted_data_fifo_empty),
|
||||
.full (posted_data_fifo_real_full),
|
||||
.prog_full (dma_write_data_fifo_full)
|
||||
);
|
||||
|
||||
//Instantiate the TRN interface state machine
|
||||
tx_trn_sm tx_trn_sm_inst (
|
||||
.clk(clk),
|
||||
// .rst_in(rst),
|
||||
// .hostreset_in(hostreset),
|
||||
.full_rst(full_rst),
|
||||
.soft_rst(soft_rst),
|
||||
.rst_out(rst_tx),
|
||||
//interface to the header fifos
|
||||
.posted_hdr_fifo(posted_hdr_fifo),
|
||||
.posted_hdr_fifo_rden(posted_hdr_fifo_rden),
|
||||
.posted_hdr_fifo_empty(posted_hdr_fifo_empty),
|
||||
.nonposted_hdr_fifo(non_posted_hdr_fifo),
|
||||
.nonposted_hdr_fifo_rden(non_posted_hdr_fifo_rden),
|
||||
.nonposted_hdr_fifo_empty(non_posted_hdr_fifo_empty),
|
||||
.comp_hdr_fifo(comp_hdr_fifo),
|
||||
.comp_hdr_fifo_empty(comp_hdr_fifo_empty),
|
||||
.comp_hdr_fifo_rden(comp_hdr_fifo_rden),
|
||||
/// Jiansong: posted data fifo interface
|
||||
.posted_data_fifo_data(posted_data_fifo_data),
|
||||
.posted_data_fifo_rden(posted_data_fifo_rden),
|
||||
.posted_data_fifo_empty(posted_data_fifo_empty),
|
||||
|
||||
.Mrd_data_addr(Mrd_data_addr),
|
||||
.Mrd_data_in(Mrd_data_in),
|
||||
|
||||
//interface to PCIe Endpoint Block Plus TX TRN
|
||||
.trn_td(trn_td[63:0]), //O [63:0]
|
||||
.trn_trem_n(trn_trem_n[7:0]), //O [7:0]
|
||||
.trn_tsof_n(trn_tsof_n), //O
|
||||
.trn_teof_n(trn_teof_n), //O
|
||||
.trn_tsrc_rdy_n(trn_tsrc_rdy_n), //O
|
||||
.trn_tsrc_dsc_n(trn_tsrc_dsc_n), //O
|
||||
.trn_tdst_rdy_n(trn_tdst_rdy_n), //I
|
||||
.trn_tdst_dsc_n(trn_tdst_dsc_n), //I
|
||||
.trn_terrfwd_n(trn_terrfwd_n), //O
|
||||
.trn_tbuf_av(trn_tbuf_av[2:0]), //I [3:0]
|
||||
/// Jiansong: input from rx_monitor
|
||||
.rd_dma_start(rd_dma_start),
|
||||
.dmarxs(dmarxs)
|
||||
// .np_rx_cnt_qw(np_rx_cnt_qw),
|
||||
// .transferstart (transferstart),
|
||||
// .Wait_for_TX_desc(Wait_for_TX_desc)
|
||||
// debug interface
|
||||
// .Debug21RX2(Debug21RX2),
|
||||
// .Debug25RX6(Debug25RX6)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,943 @@
|
|||
/*+--------------------------------------------------------------------------
|
||||
Copyright (c) 2015, Microsoft Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Microsoft Research Asia
|
||||
// Engineer: Jiansong Zhang
|
||||
//
|
||||
// Create Date: 21:39:39 06/01/2009
|
||||
// Design Name:
|
||||
// Module Name: tx_trn_sm
|
||||
// Project Name: Sora
|
||||
// Target Devices: Virtex5 LX50T
|
||||
// Tool versions: ISE10.1.03
|
||||
// Description:
|
||||
// Purpose: Transmit TRN State Machine module. Interfaces to the Endpoint
|
||||
// Block Plus and transmits packtets out of the TRN interface. Drains the
|
||||
// packets out of FIFOs.
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
// Modified by jiansong zhang, 2009-6-18
|
||||
// (1) delete dma write done generation logic -------------- done
|
||||
// (2) modification on scheduling
|
||||
// (3) register/memory read logic -------------------------- done
|
||||
//
|
||||
// semiduplex scheduling to slove possible interlock problem on
|
||||
// north-bridge/memory-controller
|
||||
// (1) add np_tx_cnt logic --------------------------------- done
|
||||
// (2) add np_rx_cnt input
|
||||
// (3) scheduling: if ( (np_tx_cnt == np_rx_cnt) && (p_hdr_fifo != empty) )
|
||||
// send p packets;
|
||||
// else if (np_hdr_fifo != empty)
|
||||
// send np packets;
|
||||
// else if (cmp_hdr_fifo != empty)
|
||||
// send cmp packets;
|
||||
// else
|
||||
// IDLE;
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
`include "Sora_config.v"
|
||||
|
||||
module tx_trn_sm(
|
||||
input clk,
|
||||
// input rst_in,
|
||||
// input hostreset_in,
|
||||
input full_rst,
|
||||
input soft_rst,
|
||||
output rst_out,
|
||||
//interface to the header fifos
|
||||
input [63:0] posted_hdr_fifo,
|
||||
output posted_hdr_fifo_rden,
|
||||
input posted_hdr_fifo_empty,
|
||||
input [63:0] nonposted_hdr_fifo,
|
||||
output nonposted_hdr_fifo_rden,
|
||||
input nonposted_hdr_fifo_empty,
|
||||
input [63:0] comp_hdr_fifo,
|
||||
input comp_hdr_fifo_empty,
|
||||
output comp_hdr_fifo_rden,
|
||||
/// Jiansong: posted_data_fifo interface
|
||||
output reg posted_data_fifo_rden,
|
||||
input [63:0] posted_data_fifo_data,
|
||||
// it's used, data fifo should not be empty when it is read
|
||||
input posted_data_fifo_empty,
|
||||
|
||||
/// Jiansong: interface for Mrd, connect to dma control wrapper, don't need request/ack handshake
|
||||
output reg[11:0] Mrd_data_addr, /// Jiansong: 12 bits register address
|
||||
input [31:0] Mrd_data_in,
|
||||
|
||||
//interface to PCIe Endpoint Block Plus TX TRN
|
||||
output reg [63:0] trn_td,
|
||||
output reg [7:0] trn_trem_n,
|
||||
output reg trn_tsof_n,
|
||||
output reg trn_teof_n,
|
||||
output trn_tsrc_rdy_n,
|
||||
output trn_tsrc_dsc_n,
|
||||
input trn_tdst_rdy_n,//if this signal is deasserted (high) must pause all
|
||||
//activity to the TX TRN interface. This signal is
|
||||
//used as a clock enable to much of the circuitry
|
||||
//in this module
|
||||
input trn_tdst_dsc_n,//destination should not discontinue - Endpoint Block
|
||||
//Plus V1.6.1 does not support this signal
|
||||
output trn_terrfwd_n,
|
||||
input [2:0] trn_tbuf_av,
|
||||
/// Jiansong: input from rx_monitor
|
||||
// input [9:0] np_rx_cnt_qw,
|
||||
// input transferstart,
|
||||
// input Wait_for_TX_desc,
|
||||
input rd_dma_start, //indicates the start of a read dma xfer
|
||||
input [12:3] dmarxs //size of the complete transfer
|
||||
// debug interface
|
||||
// output reg [31:0] Debug21RX2,
|
||||
// output reg [31:0] Debug25RX6
|
||||
|
||||
);
|
||||
|
||||
//state machine state definitions for state[19:0]
|
||||
localparam IDLE = 21'b0_0000_0000_0000_0000_0000;
|
||||
localparam GET_P_HD = 21'b0_0000_0000_0000_0000_0001;
|
||||
localparam GET_NP_HD = 21'b0_0000_0000_0000_0000_0010;
|
||||
localparam GET_COMP_HD = 21'b0_0000_0000_0000_0000_0100;
|
||||
localparam SETUP_P_DATA = 21'b0_0000_0000_0000_0000_1000;
|
||||
//// localparam WAIT_FOR_DATA_RDY = 20'b0000_0000_0000_0010_0000;
|
||||
localparam P_WAIT_STATE = 21'b0_0000_0000_0000_0001_0000;
|
||||
localparam P_WAIT_STATE1 = 21'b0_0000_0000_0000_0010_0000;
|
||||
localparam HD1_P_XFER = 21'b0_0000_0000_0000_0100_0000;
|
||||
localparam HD2_P_XFER = 21'b0_0000_0000_0000_1000_0000;
|
||||
localparam DATA_P_XFER = 21'b0_0000_0000_0001_0000_0000;
|
||||
localparam LAST_P_XFER = 21'b0_0000_0000_0010_0000_0000;
|
||||
localparam SETUP_NP = 21'b0_0000_0000_0100_0000_0000;
|
||||
localparam SETUP_COMP_DATA = 21'b0_0000_0000_1000_0000_0000;
|
||||
localparam SETUP_COMP_DATA_WAIT1 = 21'b0_0000_0001_0000_0000_0000;
|
||||
localparam SETUP_COMP_DATA_WAIT2 = 21'b0_0000_0010_0000_0000_0000;
|
||||
localparam HD1_NP_XFER = 21'b0_0000_0100_0000_0000_0000;
|
||||
localparam HD2_NP_XFER = 21'b0_0000_1000_0000_0000_0000;
|
||||
localparam NP_WAIT_STATE = 21'b0_0001_0000_0000_0000_0000;
|
||||
localparam WAIT_FOR_COMP_DATA_RDY = 21'b0_0010_0000_0000_0000_0000;
|
||||
localparam HD1_COMP_XFER = 21'b0_0100_0000_0000_0000_0000;
|
||||
localparam HD2_COMP_XFER = 21'b0_1000_0000_0000_0000_0000;
|
||||
localparam NP_XFER_WAIT = 21'b1_0000_0000_0000_0000_0000;
|
||||
|
||||
//states for addsub_state
|
||||
localparam AS_IDLE = 2'b00;
|
||||
localparam REGISTER_CALC = 2'b01;
|
||||
localparam WAIT_FOR_REG = 2'b10;
|
||||
|
||||
reg [1:0] addsub_state;
|
||||
|
||||
//header fifo signals
|
||||
reg read_posted_header_fifo, read_posted_header_fifo_d1,
|
||||
read_posted_header_fifo_d2;
|
||||
reg read_non_posted_header_fifo, read_non_posted_header_fifo_d1,
|
||||
read_non_posted_header_fifo_d2;
|
||||
reg read_comp_header_fifo, read_comp_header_fifo_d1,
|
||||
read_comp_header_fifo_d2;
|
||||
wire p_trn_fifo_rdy, np_trn_fifo_rdy;
|
||||
//holding registers for TLP headers
|
||||
reg [63:0] p_hd1, p_hd2; //posted headers 1 and 2
|
||||
reg [63:0] np_hd1, np_hd2; //non-posted headers 1 and 2
|
||||
reg [63:0] comp_hd1, comp_hd2; //completer headers 1 and 2
|
||||
//datapath registers
|
||||
reg [31:0] data_reg;
|
||||
reg [9:0] length_countdown;
|
||||
wire [63:0] data_swap;
|
||||
|
||||
/// Jiansong: swap register data
|
||||
wire [31:0] Mrd_data_swap;
|
||||
|
||||
//decoded TLP signals - mainly used for code comprehension
|
||||
wire [1:0] p_fmt;
|
||||
wire [2:0] p_tc;
|
||||
wire [9:0] p_length;
|
||||
wire [1:0] np_fmt;
|
||||
wire [2:0] np_tc;
|
||||
wire [9:0] np_length;
|
||||
////reg p_hd_valid; /// Jiansong: no longer needed
|
||||
|
||||
//main state machine signals
|
||||
reg [20:0] state;
|
||||
////reg posted; //asserted when the state machine is in the posted flow
|
||||
//// //used to qualify the data_stall signal as a CE for many of
|
||||
//// //the blocks that aren't related to the DDR2
|
||||
reg [1:0] data_src_mux;
|
||||
reg trn_tsrc_rdy_n_reg;
|
||||
reg [3:0] priority_count = 4'b1111;
|
||||
wire posted_priority;
|
||||
|
||||
/// Jiansong: pipeline register for a complicated problem when trn_tdst_rdy_n is asserted
|
||||
reg trn_tdst_rdy_n_r2;
|
||||
reg [63:0] data_reg_tdst_problem;
|
||||
reg trn_tdst_rdy_n_r;
|
||||
|
||||
reg rst_reg;
|
||||
|
||||
/// Jiansong: non_posted_length_counter
|
||||
reg add_calc = 0;
|
||||
reg sub_calc = 0;
|
||||
reg add_complete;
|
||||
reg sub_complete;
|
||||
reg [9:0] np_tx_cnt_qw;
|
||||
reg [9:0] np_tx_cnt_qw_new;
|
||||
reg [9:0] np_tx_cnt_qw_add;
|
||||
reg update_np_tx_cnt_qw;
|
||||
reg stay_2x;
|
||||
|
||||
/// Jiansong:
|
||||
wire rd_dma_start_one;
|
||||
reg rd_dma_start_reg;
|
||||
rising_edge_detect rd_dma_start_one_inst(
|
||||
.clk(clk),
|
||||
.rst(rst_reg),
|
||||
.in(rd_dma_start_reg),
|
||||
.one_shot_out(rd_dma_start_one)
|
||||
);
|
||||
//pipe line register for timing purposes
|
||||
always@(posedge clk)
|
||||
rd_dma_start_reg <= rd_dma_start;
|
||||
|
||||
`ifdef sora_simulation
|
||||
// always@(posedge clk) rst_reg <= rst_in;
|
||||
always@(posedge clk) rst_reg <= full_rst;
|
||||
`else
|
||||
always@(posedge clk) rst_reg <= ( full_rst | ((state == IDLE) & soft_rst) );
|
||||
// always@(posedge clk) begin
|
||||
// if(state == IDLE)
|
||||
// rst_reg <= rst_in | hostreset_in;
|
||||
// else
|
||||
// rst_reg <= 1'b0;
|
||||
// end
|
||||
`endif
|
||||
assign rst_out = rst_reg;
|
||||
|
||||
//// debug register
|
||||
//always@(posedge clk)begin
|
||||
// Debug21RX2[19:0] <= state[19:0];
|
||||
// Debug21RX2[29:20] <= length_countdown[9:0];
|
||||
// Debug21RX2[31:30] <= 2'b00;
|
||||
//end
|
||||
//
|
||||
//always@(posedge clk)begin
|
||||
// if (rst_reg)
|
||||
// Debug25RX6 <= 32'h0000_0000;
|
||||
// else if (posted_data_fifo_rden)
|
||||
// Debug25RX6 <= Debug25RX6 + 32'h0000_0001;
|
||||
// else
|
||||
// Debug25RX6 <= Debug25RX6;
|
||||
//end
|
||||
|
||||
//tie off to pcie trn tx
|
||||
assign trn_tsrc_dsc_n = 1'b1; /// Jiansong: transmit source discontinue
|
||||
assign trn_terrfwd_n = 1'b1; /// Jiansong: error?
|
||||
|
||||
//if there is a data_stall need to pause the TX TRN interface
|
||||
////assign trn_tsrc_rdy_n = (data_stall & posted) | trn_tsrc_rdy_n_reg;
|
||||
assign trn_tsrc_rdy_n = trn_tsrc_rdy_n_reg;
|
||||
|
||||
/// Jiansong: need modification? big-endian for 64 bit data? Don't modify
|
||||
// swap byte ordering of data to big-endian per PCIe Base spec
|
||||
////assign data_swap[63:0] = {data[7:0],data[15:8],
|
||||
//// data[23:16],data[31:24],
|
||||
//// data[39:32],data[47:40],
|
||||
//// data[55:48],data[63:56]};
|
||||
assign data_swap[63:0] = {posted_data_fifo_data[7:0],posted_data_fifo_data[15:8],
|
||||
posted_data_fifo_data[23:16],posted_data_fifo_data[31:24],
|
||||
posted_data_fifo_data[39:32],posted_data_fifo_data[47:40],
|
||||
posted_data_fifo_data[55:48],posted_data_fifo_data[63:56]};
|
||||
////assign data_swap[63:0] = {posted_data_fifo_data[39:32],posted_data_fifo_data[47:40],
|
||||
//// posted_data_fifo_data[55:48],posted_data_fifo_data[63:56],
|
||||
//// posted_data_fifo_data[7:0],posted_data_fifo_data[15:8],
|
||||
//// posted_data_fifo_data[23:16],posted_data_fifo_data[31:24]};
|
||||
|
||||
/// Jiansong: swap register read / memory read data
|
||||
assign Mrd_data_swap[31:0] = {Mrd_data_in[7:0],Mrd_data_in[15:8],
|
||||
Mrd_data_in[23:16],Mrd_data_in[31:24]};
|
||||
|
||||
// output logic from statemachine that controls read of the posted packet fifo
|
||||
// read the two headers from the posted fifo and store in registers
|
||||
// the signal that kicks off the read is a single-cycle signal from
|
||||
// the state machine
|
||||
// read_posted_header_fifo
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)begin
|
||||
read_posted_header_fifo_d1 <= 1'b0;
|
||||
read_posted_header_fifo_d2 <= 1'b0;
|
||||
//// end else if(~trn_tdst_rdy_n & ~data_stall)begin
|
||||
// end else if(~trn_tdst_rdy_n)begin
|
||||
end else begin
|
||||
/// Jiansong: pipeline the fifo rden signal
|
||||
read_posted_header_fifo_d1 <= read_posted_header_fifo;
|
||||
read_posted_header_fifo_d2 <= read_posted_header_fifo_d1;
|
||||
end
|
||||
end
|
||||
|
||||
//stretch read enable to two clocks and qualify with trn_tdst_rdy_n
|
||||
assign posted_hdr_fifo_rden = (read_posted_header_fifo_d1
|
||||
| read_posted_header_fifo);
|
||||
// & ~trn_tdst_rdy_n;
|
||||
//// & ~trn_tdst_rdy_n
|
||||
//// & ~data_stall;
|
||||
|
||||
|
||||
// use the read enable signals to enable registers p_hd1 and p_hd2
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)begin
|
||||
p_hd1[63:0] <= 64'h0000000000000000;
|
||||
//// end else if(~trn_tdst_rdy_n & ~data_stall)begin
|
||||
// end else if(~trn_tdst_rdy_n) begin
|
||||
end else begin
|
||||
if(read_posted_header_fifo_d1)begin
|
||||
p_hd1 <= posted_hdr_fifo;
|
||||
end else begin
|
||||
p_hd1 <= p_hd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)begin
|
||||
p_hd2[63:0] <= 64'h0000000000000000;
|
||||
//// end else if(~trn_tdst_rdy_n & ~data_stall)begin
|
||||
// end else if(~trn_tdst_rdy_n)begin
|
||||
end else begin
|
||||
if(read_posted_header_fifo_d2)begin
|
||||
p_hd2 <= posted_hdr_fifo;
|
||||
end else begin
|
||||
p_hd2 <= p_hd2;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//assign signals for reading clarity
|
||||
assign p_fmt[1:0] = p_hd1[62:61]; //format field
|
||||
assign p_tc[2:0] = p_hd1[54:52]; //traffic class field
|
||||
assign p_length[9:0] = p_hd1[41:32]; //DW length field
|
||||
|
||||
assign p_trn_fifo_rdy = trn_tbuf_av[1];
|
||||
|
||||
|
||||
// output logic from statemachine that controls read of the
|
||||
// non_posted packet fifo
|
||||
// read the two headers from the non posted fifo and store in registers
|
||||
// the signal that kicks off the read is a single-cycle signal from the
|
||||
// state machine
|
||||
// read_posted_header_fifo
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)begin
|
||||
read_non_posted_header_fifo_d1 <= 1'b0;
|
||||
read_non_posted_header_fifo_d2 <= 1'b0;
|
||||
// end else if(~trn_tdst_rdy_n) begin
|
||||
end else begin
|
||||
/// Jiansong: pipeline the fifo rden signal
|
||||
read_non_posted_header_fifo_d1 <= read_non_posted_header_fifo;
|
||||
read_non_posted_header_fifo_d2 <= read_non_posted_header_fifo_d1;
|
||||
end
|
||||
end
|
||||
|
||||
//stretch read enable to two clocks and qualify with trn_tdst_rdy_n
|
||||
assign nonposted_hdr_fifo_rden = (read_non_posted_header_fifo_d1
|
||||
| read_non_posted_header_fifo);
|
||||
// & ~trn_tdst_rdy_n;
|
||||
|
||||
// use the read enable signals to enable registers np_hd1 and np_hd2
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)begin
|
||||
np_hd1[63:0] <= 64'h0000000000000000;
|
||||
// end else if(~trn_tdst_rdy_n)begin
|
||||
end else begin
|
||||
if(read_non_posted_header_fifo_d1)begin
|
||||
np_hd1 <= nonposted_hdr_fifo;
|
||||
end else begin
|
||||
np_hd1 <= np_hd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)begin
|
||||
np_hd2[63:0] <= 64'h0000000000000000;
|
||||
// end else if(~trn_tdst_rdy_n)begin
|
||||
end else begin
|
||||
if(read_non_posted_header_fifo_d2)begin
|
||||
np_hd2 <= nonposted_hdr_fifo;
|
||||
end else begin
|
||||
np_hd2 <= np_hd2;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//assign signals for reading clarity
|
||||
assign np_fmt[1:0] = np_hd1[62:61]; //format field
|
||||
assign np_tc[2:0] = np_hd1[54:52]; //traffic class field
|
||||
assign np_length[9:0] = np_hd1[41:32]; //DW length field
|
||||
|
||||
assign np_trn_fifo_rdy = trn_tbuf_av[0];
|
||||
|
||||
// output logic from statemachine that controls read of the comp packet fifo
|
||||
// read the two headers from the comp fifo and store in registers
|
||||
// the signal that kicks off the read is a single-cycle signal from
|
||||
// the state machine
|
||||
// read_comp_header_fifo
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)begin
|
||||
read_comp_header_fifo_d1 <= 1'b0;
|
||||
read_comp_header_fifo_d2 <= 1'b0;
|
||||
//// end else if(~trn_tdst_rdy_n & (~data_stall | ~posted))begin
|
||||
// end else if(~trn_tdst_rdy_n)begin /// pending
|
||||
end else begin
|
||||
read_comp_header_fifo_d1 <= read_comp_header_fifo;
|
||||
read_comp_header_fifo_d2 <= read_comp_header_fifo_d1;
|
||||
end
|
||||
end
|
||||
|
||||
//stretch read enable to two clocks and qualify with trn_tdst_rdy_n
|
||||
assign comp_hdr_fifo_rden = (read_comp_header_fifo_d1
|
||||
| read_comp_header_fifo);
|
||||
// & ~trn_tdst_rdy_n;
|
||||
|
||||
|
||||
// use the read enable signals to enable registers comp_hd1 and comp_hd2
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)begin
|
||||
comp_hd1[63:0] <= 64'h0000000000000000;
|
||||
//// end else if(~trn_tdst_rdy_n & (~data_stall | ~posted))begin
|
||||
// end else if(~trn_tdst_rdy_n)begin /// pending
|
||||
end else begin
|
||||
if(read_comp_header_fifo_d1)begin
|
||||
comp_hd1 <= comp_hdr_fifo;
|
||||
end else begin
|
||||
comp_hd1 <= comp_hd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)begin
|
||||
comp_hd2[63:0] <= 64'h0000000000000000;
|
||||
//// end else if(~trn_tdst_rdy_n & (~data_stall | ~posted))begin
|
||||
// end else if(~trn_tdst_rdy_n)begin /// pending
|
||||
end else begin
|
||||
if(read_comp_header_fifo_d2)begin
|
||||
comp_hd2 <= comp_hdr_fifo;
|
||||
end else begin
|
||||
comp_hd2 <= comp_hd2;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign comp_trn_fifo_rdy = trn_tbuf_av[2];
|
||||
|
||||
//encode data_src
|
||||
//reg_file = BAR_HIT[6:0] = 0000001 -> 01
|
||||
//ROM_BAR = BAR_HIT[6:0] = 1000000 -> 10
|
||||
//DDR2 -> 00 no need to decode as DDR2 not supported as a PCIe target
|
||||
always@(*)begin //// Jiansong: no clock driven, or whatever clock driven
|
||||
case(comp_hd1[63:57])
|
||||
7'b0000001: data_src_mux[1:0] <= 2'b01;
|
||||
7'b1000000: data_src_mux[1:0] <= 2'b10;
|
||||
//// default: data_src_mux[1:0] <= 2'b00;
|
||||
default: data_src_mux[1:0] <= 2'b01;
|
||||
endcase
|
||||
end
|
||||
|
||||
/// Jiansong: pending
|
||||
//countdown to control amount of data tranfer in state machine
|
||||
//count in quadwords since trn_td is 64-bits
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)
|
||||
length_countdown <= 10'b00_0000_0000;
|
||||
//// else if (~trn_tdst_rdy_n & ~data_stall)begin
|
||||
else if (~trn_tdst_rdy_n)begin
|
||||
if(state == HD1_P_XFER)
|
||||
length_countdown <= p_length>>1; //count in quadwords
|
||||
else if(length_countdown != 0)
|
||||
length_countdown <= length_countdown - 1;
|
||||
end else
|
||||
length_countdown <= length_countdown;
|
||||
end
|
||||
|
||||
|
||||
//data_xfer is a state machine output that tells the egress_data_presenter
|
||||
// to transfer data; every clock cycle it is asserted one 64-bit data
|
||||
// is valid on the next cycle - unless data_stall is asserted
|
||||
////assign data_xfer = data_xfer_reg;
|
||||
// data steering logic
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)begin
|
||||
// data_reg <= 64'h0000000000000000;
|
||||
data_reg[31:0] <= 32'h0000_0000;
|
||||
//// end else if(~trn_tdst_rdy_n & (~data_stall | ~posted)) begin
|
||||
end else if(~trn_tdst_rdy_n) begin
|
||||
data_reg[31:0] <= data_swap[31:0];
|
||||
end
|
||||
end
|
||||
|
||||
/// Jiansong: this register is added the rden delay problem when trn_tdst_rdy_n is deasserted
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)begin
|
||||
data_reg_tdst_problem <= 64'h0000000000000000;
|
||||
end else if(~trn_tdst_rdy_n_r)begin
|
||||
data_reg_tdst_problem <= data_swap;
|
||||
end
|
||||
end
|
||||
|
||||
//mux the trn_td[63:0] - dependent on what state the main state machine is in
|
||||
always@(posedge clk)begin
|
||||
if(rst_reg)
|
||||
trn_td <= 0;
|
||||
//// else if(~trn_tdst_rdy_n & (~data_stall | ~posted))begin
|
||||
else if(~trn_tdst_rdy_n)begin
|
||||
casex({state,p_fmt[0]})
|
||||
{HD1_P_XFER,1'bx}: begin
|
||||
trn_td <= p_hd1;
|
||||
end
|
||||
{HD2_P_XFER,1'b0}: begin
|
||||
if(trn_tdst_rdy_n_r) /// Jiansong:
|
||||
trn_td <= {p_hd2[63:32],data_reg_tdst_problem[63:32]};
|
||||
else
|
||||
trn_td <= {p_hd2[63:32],data_swap[63:32]};
|
||||
end
|
||||
{HD2_P_XFER,1'b1}: begin
|
||||
trn_td <= p_hd2[63:0];
|
||||
end
|
||||
{DATA_P_XFER,1'b0},{LAST_P_XFER,1'b0}: begin
|
||||
if(trn_tdst_rdy_n_r) /// Jiansong:
|
||||
trn_td[63:0] <= {data_reg[31:0],data_reg_tdst_problem[63:32]};
|
||||
else if(trn_tdst_rdy_n_r2)
|
||||
trn_td[63:0] <= {data_reg_tdst_problem[31:0],data_swap[63:32]};
|
||||
else
|
||||
trn_td[63:0] <= {data_reg[31:0],data_swap[63:32]};
|
||||
end
|
||||
{DATA_P_XFER,1'b1},{LAST_P_XFER,1'b1}: begin
|
||||
if(trn_tdst_rdy_n_r) /// Jiansong:
|
||||
trn_td[63:0] <= data_reg_tdst_problem[63:0];
|
||||
else
|
||||
trn_td[63:0] <= data_swap[63:0];
|
||||
end
|
||||
{HD1_NP_XFER,1'bx}: begin
|
||||
trn_td <= np_hd1;
|
||||
end
|
||||
{HD2_NP_XFER,1'bx}: begin
|
||||
trn_td <= np_hd2;
|
||||
end
|
||||
{HD1_COMP_XFER,1'bx}: begin
|
||||
trn_td <= {comp_hd1[31:0],comp_hd2[63:32]};
|
||||
end
|
||||
{HD2_COMP_XFER,1'bx}: begin
|
||||
//// trn_td <= {comp_hd2[31:0],data_reg[63:32]};
|
||||
/// Jiansong: rom_bar, keep the old design, but don't know what's it for
|
||||
if (data_src_mux[1:0] == 2'b10) begin
|
||||
trn_td <= {comp_hd2[31:0],32'h00000000};
|
||||
end else if (data_src_mux[1:0] == 2'b01) begin
|
||||
trn_td <= {comp_hd2[31:0],Mrd_data_swap};
|
||||
end else begin
|
||||
trn_td <= {comp_hd2[31:0],Mrd_data_swap};
|
||||
end
|
||||
end
|
||||
default: begin
|
||||
trn_td <= 0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
/// Jiansong: priority is modified
|
||||
/// in sora, round-robin will be used for posted, non-posted
|
||||
/// and completion scheduling
|
||||
//////Priority signal for posted and non-posted requests
|
||||
//////When operating in full duplex mode the state machine
|
||||
//////will do 8 posted requests followed by 8 non-posted requests
|
||||
//////Note: this ordering assumes that the posted and non-posted
|
||||
//////requests do not depend on each other.
|
||||
//////Once inside the V-5 PCIe Block, strict ordering will be
|
||||
//////followed. Also, note that completions are given
|
||||
//////lowest priority. In order to avoid completion time-outs,
|
||||
//////read requests from the host should not occur during a DMA
|
||||
//////transaction.
|
||||
//////If this is not possible, than the completion queue may need
|
||||
//////higher priority.
|
||||
|
||||
/// Jiansong: pipeline registers
|
||||
always@(posedge clk)begin
|
||||
trn_tdst_rdy_n_r2 <= trn_tdst_rdy_n_r;
|
||||
trn_tdst_rdy_n_r <= trn_tdst_rdy_n;
|
||||
end
|
||||
|
||||
// bulk of TX TRN state machine
|
||||
always@(posedge clk)begin
|
||||
// if(rst_in)begin
|
||||
if(rst_reg)begin
|
||||
trn_tsrc_rdy_n_reg <= 1'b1;
|
||||
trn_tsof_n <= 1'b1;
|
||||
trn_teof_n <= 1'b1;
|
||||
trn_trem_n[7:0] <= 8'b11111111;
|
||||
posted_data_fifo_rden <= 1'b0;
|
||||
read_posted_header_fifo <= 1'b0;
|
||||
read_non_posted_header_fifo <= 1'b0;
|
||||
read_comp_header_fifo <= 1'b0;
|
||||
state <= IDLE;
|
||||
//// //use trn_tdst_rdy_n and data_stall as clock enable - for data_stall
|
||||
//// //only CE if in the posted flow
|
||||
//// end else if(~trn_tdst_rdy_n & (~data_stall | ~posted))begin
|
||||
// use trn_tdst_rdy_n as clock enable
|
||||
end else if(trn_tdst_rdy_n)begin
|
||||
// if(trn_tdst_rdy_n)begin
|
||||
/// Jiansong: deassert the rden, write enable signals if PCIe core is not ready
|
||||
posted_data_fifo_rden <= 1'b0;
|
||||
read_posted_header_fifo <= 1'b0;
|
||||
read_non_posted_header_fifo <= 1'b0;
|
||||
read_comp_header_fifo <= 1'b0;
|
||||
//// end else if(~trn_tdst_rdy_n)begin
|
||||
end else begin
|
||||
case(state)
|
||||
IDLE: begin
|
||||
// if (hostreset_in) begin
|
||||
// trn_tsrc_rdy_n_reg <= 1'b1;
|
||||
// trn_tsof_n <= 1'b1;
|
||||
// trn_teof_n <= 1'b1;
|
||||
// trn_trem_n[7:0] <= 8'b11111111;
|
||||
// posted_data_fifo_rden <= 1'b0;
|
||||
// read_posted_header_fifo <= 1'b0;
|
||||
// read_non_posted_header_fifo <= 1'b0;
|
||||
// read_comp_header_fifo <= 1'b0;
|
||||
// state <= IDLE;
|
||||
// end else begin
|
||||
trn_tsrc_rdy_n_reg <= 1'b1;
|
||||
trn_tsof_n <= 1'b1;
|
||||
trn_teof_n <= 1'b1;
|
||||
trn_trem_n[7:0] <= 8'b11111111;
|
||||
posted_data_fifo_rden <= 1'b0;
|
||||
read_posted_header_fifo <= 1'b0;
|
||||
read_non_posted_header_fifo <= 1'b0;
|
||||
read_comp_header_fifo <= 1'b0;
|
||||
|
||||
// if ( (np_rx_cnt_qw == np_tx_cnt_qw) && (~posted_hdr_fifo_empty) && ~Wait_for_TX_desc)
|
||||
if (~posted_hdr_fifo_empty)
|
||||
state <= GET_P_HD;
|
||||
else if (~nonposted_hdr_fifo_empty)
|
||||
state <= GET_NP_HD;
|
||||
else if (~comp_hdr_fifo_empty)
|
||||
state <= GET_COMP_HD;
|
||||
else
|
||||
state <= IDLE;
|
||||
|
||||
// end
|
||||
end
|
||||
|
||||
GET_P_HD: begin
|
||||
read_posted_header_fifo <= 1'b1; //get the headers ready
|
||||
trn_tsrc_rdy_n_reg <= 1'b1;
|
||||
trn_trem_n[7:0] <= 8'b11111111;
|
||||
trn_teof_n <= 1'b1;
|
||||
state <= SETUP_P_DATA;
|
||||
end
|
||||
GET_NP_HD: begin
|
||||
read_non_posted_header_fifo <= 1'b1; //get the headers ready
|
||||
trn_tsrc_rdy_n_reg <= 1'b1;
|
||||
trn_trem_n[7:0] <= 8'b11111111;
|
||||
trn_teof_n <= 1'b1;
|
||||
state <= SETUP_NP;
|
||||
end
|
||||
GET_COMP_HD: begin
|
||||
read_comp_header_fifo <= 1'b1; //get the headers ready
|
||||
trn_tsrc_rdy_n_reg <= 1'b1;
|
||||
trn_trem_n[7:0] <= 8'b11111111;
|
||||
trn_teof_n <= 1'b1;
|
||||
state <= SETUP_COMP_DATA_WAIT1;
|
||||
end
|
||||
|
||||
/// Jiansong: pending, make it simpler
|
||||
//start of completer transaction flow
|
||||
SETUP_COMP_DATA_WAIT1: begin //wait state for comp_hd1
|
||||
read_comp_header_fifo <= 1'b0;
|
||||
state <= SETUP_COMP_DATA_WAIT2;
|
||||
end
|
||||
SETUP_COMP_DATA_WAIT2: begin //wait state for comp_hd2
|
||||
state <= SETUP_COMP_DATA;
|
||||
end
|
||||
SETUP_COMP_DATA: begin
|
||||
Mrd_data_addr[11:0] <= {comp_hd1[41:32],2'b00};
|
||||
if(comp_trn_fifo_rdy)//make sure the completion fifo in the PCIe
|
||||
//block is ready
|
||||
state <= WAIT_FOR_COMP_DATA_RDY;
|
||||
else
|
||||
state <= SETUP_COMP_DATA;
|
||||
end
|
||||
/// Jiansong: wait one more cycle for reg data ready, maybe not necessary
|
||||
WAIT_FOR_COMP_DATA_RDY: begin
|
||||
state <= HD1_COMP_XFER;
|
||||
end
|
||||
|
||||
HD1_COMP_XFER: begin //transfer first header
|
||||
trn_tsof_n <= 1'b0;
|
||||
trn_tsrc_rdy_n_reg <= 1'b0;
|
||||
trn_trem_n[7:0] <= 8'b00000000;
|
||||
state <= HD2_COMP_XFER;
|
||||
end
|
||||
HD2_COMP_XFER: begin //transfer second header + 1 DW of data
|
||||
trn_tsrc_rdy_n_reg <= 1'b0;
|
||||
trn_tsof_n <= 1'b1;
|
||||
trn_teof_n <= 1'b0;
|
||||
state <= IDLE;
|
||||
end
|
||||
|
||||
//start of posted transaction flow
|
||||
SETUP_P_DATA: begin
|
||||
read_posted_header_fifo <= 1'b0;
|
||||
posted_data_fifo_rden <= 1'b0;
|
||||
state <= P_WAIT_STATE;
|
||||
end
|
||||
P_WAIT_STATE : begin /// Jiansong: wait one more cycle for hdr ready
|
||||
read_posted_header_fifo <= 1'b0;
|
||||
posted_data_fifo_rden <= 1'b0;
|
||||
state <= P_WAIT_STATE1;
|
||||
end
|
||||
P_WAIT_STATE1 : begin
|
||||
//wait for the egress data_presenter to have data ready then start
|
||||
//transmitting the first posted header
|
||||
trn_teof_n <= 1'b1;
|
||||
if(p_trn_fifo_rdy & ~posted_data_fifo_empty) begin //make sure posted fifo in PCIe block is ready
|
||||
/// Jiansong: read data fifo?
|
||||
if(p_fmt[0] == 0)begin //3DW
|
||||
posted_data_fifo_rden <= 1'b1;
|
||||
end else begin //4DW
|
||||
posted_data_fifo_rden <= 1'b0;
|
||||
end
|
||||
state <= HD1_P_XFER;
|
||||
end else begin
|
||||
posted_data_fifo_rden <= 1'b0;
|
||||
state <= P_WAIT_STATE1;
|
||||
end
|
||||
end
|
||||
HD1_P_XFER: begin //transfer first header
|
||||
trn_tsof_n <= 1'b0; //assert SOF
|
||||
trn_teof_n <= 1'b1;
|
||||
trn_tsrc_rdy_n_reg <= 1'b0;
|
||||
trn_trem_n[7:0] <= 8'b00000000;
|
||||
posted_data_fifo_rden <= 1'b1;
|
||||
state <= HD2_P_XFER;
|
||||
end
|
||||
HD2_P_XFER: begin //transfer second header (+1 DW of data for 3DW)
|
||||
trn_tsrc_rdy_n_reg <= 1'b0;
|
||||
trn_tsof_n <= 1'b1; //deassert SOF
|
||||
/// Jiansong: RX desc is so short (2 cycles) that we need specially consider it
|
||||
if (p_fmt[0] == 0 && p_length <= 10'h004)
|
||||
posted_data_fifo_rden <= 1'b0;
|
||||
else
|
||||
posted_data_fifo_rden <= 1'b1;
|
||||
state <= DATA_P_XFER;
|
||||
|
||||
end
|
||||
// DATA_P_XFER state for packets with more than 1 DW
|
||||
// for this design the next step up will always be 128B or 32DW
|
||||
DATA_P_XFER: begin
|
||||
trn_tsrc_rdy_n_reg <= 1'b0;
|
||||
//use a counter to figure out when we are almost done and
|
||||
//jump to LAST_P_XFER when we reach the penultimate data cycle
|
||||
if(length_countdown != 1)begin
|
||||
state <= DATA_P_XFER;
|
||||
end else begin
|
||||
state <= LAST_P_XFER;
|
||||
end
|
||||
//figure out when to deassert data_xfer_reg based on whether
|
||||
//this a 3DW or 4DW header posted TLP
|
||||
if(p_fmt[0] == 0)begin //3DW case
|
||||
if(length_countdown <=2)
|
||||
posted_data_fifo_rden <= 1'b0;
|
||||
else
|
||||
posted_data_fifo_rden <= 1'b1;
|
||||
end else begin //4DW case
|
||||
if(length_countdown <=1)
|
||||
posted_data_fifo_rden <= 1'b0;
|
||||
else
|
||||
posted_data_fifo_rden <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
LAST_P_XFER: begin
|
||||
trn_tsrc_rdy_n_reg <= 1'b0;
|
||||
trn_teof_n <= 1'b0;//assert EOF
|
||||
posted_data_fifo_rden <= 1'b0;
|
||||
read_posted_header_fifo <= 1'b0;
|
||||
//assert the correct remainder bits dependent on 3DW or 4DW TLP
|
||||
//headers
|
||||
if(p_fmt[0] == 0) //0 for 3dw, 1 for 4dw header
|
||||
trn_trem_n[7:0] <= 8'b00001111;
|
||||
else
|
||||
trn_trem_n[7:0] <= 8'b00000000;
|
||||
|
||||
state <= IDLE;
|
||||
end
|
||||
|
||||
//start of the non-posted transaction flow
|
||||
SETUP_NP: begin
|
||||
read_non_posted_header_fifo <= 1'b0;
|
||||
state <= NP_WAIT_STATE;
|
||||
end
|
||||
//NP_WAIT_STATE state needed to let np_hd1 and np_hd2 to catch up
|
||||
NP_WAIT_STATE:begin
|
||||
if(np_trn_fifo_rdy)
|
||||
state <= HD1_NP_XFER;
|
||||
else
|
||||
state <= NP_WAIT_STATE;
|
||||
end
|
||||
HD1_NP_XFER: begin //transfer first header
|
||||
trn_tsof_n <= 1'b0; //assert SOF
|
||||
trn_tsrc_rdy_n_reg <= 1'b0;
|
||||
trn_trem_n[7:0] <= 8'b00000000;
|
||||
state <= HD2_NP_XFER;
|
||||
end
|
||||
HD2_NP_XFER: begin //transfer second header + 1 DW of data
|
||||
trn_tsrc_rdy_n_reg <= 1'b0;
|
||||
trn_tsof_n <= 1'b1; //deassert EOF
|
||||
trn_teof_n <= 1'b0; //assert EOF
|
||||
if(np_fmt[0] == 0) //0 for 3dw, 1 for 4dw header
|
||||
trn_trem_n[7:0] <= 8'b00001111;
|
||||
else
|
||||
trn_trem_n[7:0] <= 8'b00000000;
|
||||
|
||||
state <= NP_XFER_WAIT;
|
||||
end
|
||||
NP_XFER_WAIT : begin /// Jiansong: add one cycle into NP xfer to support
|
||||
state <= IDLE; /// semiduplex scheduling
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// /// Jiansong: logic to maintain np_tx_cnt_qw
|
||||
// always@(posedge clk)begin
|
||||
// if (rst_reg | (~transferstart))
|
||||
// add_calc <= 1'b0;
|
||||
// else if(rd_dma_start_one) //set the bit
|
||||
// add_calc <= 1'b1;
|
||||
// else if (add_complete) //reset the bit
|
||||
// add_calc <= 1'b0;
|
||||
// end
|
||||
// always@(posedge clk)begin
|
||||
// if (rst_reg | (~transferstart) | Wait_for_TX_desc)
|
||||
// sub_calc <= 1'b0;
|
||||
// else if(read_non_posted_header_fifo_d1) //set the bit, fliter out TX des
|
||||
// sub_calc <= 1'b1;
|
||||
// else if (sub_complete) //reset the bit
|
||||
// sub_calc <= 1'b0;
|
||||
// end
|
||||
// always@(posedge clk) np_tx_cnt_qw_add[9:0] <= dmarxs[12:3];
|
||||
// always@(posedge clk)begin
|
||||
// if(rst_reg | (~transferstart) | Wait_for_TX_desc)begin
|
||||
// np_tx_cnt_qw[9:0] <= 0;
|
||||
// end else if(update_np_tx_cnt_qw)begin
|
||||
// np_tx_cnt_qw[9:0] <= np_tx_cnt_qw_new[9:0];
|
||||
// end
|
||||
// end
|
||||
// always@(posedge clk)begin
|
||||
// if(rst_reg | (~transferstart) | Wait_for_TX_desc)begin
|
||||
// np_tx_cnt_qw_new[9:0] <= 0;
|
||||
// update_np_tx_cnt_qw <= 1'b0;
|
||||
// add_complete <= 1'b0;
|
||||
// sub_complete <= 1'b0;
|
||||
// stay_2x <= 1'b0;
|
||||
// addsub_state <= AS_IDLE;
|
||||
// end else begin
|
||||
// case(addsub_state)
|
||||
// AS_IDLE: begin
|
||||
// update_np_tx_cnt_qw <= 1'b0;
|
||||
// if(add_calc)begin
|
||||
// //if add_calc is asserted then add the current value (*_now) to
|
||||
// //the incoming dma xfer size (*_reg)
|
||||
// np_tx_cnt_qw_new[9:0] <= np_tx_cnt_qw[9:0]
|
||||
// + np_tx_cnt_qw_add[9:0];
|
||||
// //make sure to stay in this state for two clock cycles
|
||||
// if(~stay_2x)begin
|
||||
// addsub_state <= AS_IDLE;
|
||||
// add_complete <= 1'b0;
|
||||
// update_np_tx_cnt_qw <= 1'b0;
|
||||
// stay_2x <= 1'b1;
|
||||
// //then update the current value (dmawxs_div8_now)
|
||||
// end else begin
|
||||
// addsub_state <= REGISTER_CALC;
|
||||
// add_complete <= 1'b1;//clear add_calc
|
||||
// update_np_tx_cnt_qw <= 1'b1;
|
||||
// stay_2x <= 1'b0;
|
||||
// end
|
||||
// end else if (sub_calc)begin
|
||||
// //if sub_calc is asserted then subtract the dw_length field
|
||||
// //from the incoming completion packet from the current value
|
||||
// np_tx_cnt_qw_new[9:0] <= np_tx_cnt_qw[9:0]
|
||||
// - {1'b0, np_length[9:1]};
|
||||
// //likewise make sure to stat in this state for two clocks
|
||||
// if(~stay_2x)begin
|
||||
// addsub_state <= AS_IDLE;
|
||||
// sub_complete <= 1'b0;
|
||||
// update_np_tx_cnt_qw <= 1'b0;
|
||||
// stay_2x <= 1'b1;
|
||||
// //then update the current value (dmawxs_div8_now)
|
||||
// end else begin
|
||||
// addsub_state <= REGISTER_CALC;
|
||||
// sub_complete <= 1'b1;//clear sub_calc
|
||||
// update_np_tx_cnt_qw <= 1'b1;
|
||||
// stay_2x <= 1'b0;
|
||||
// end
|
||||
// end else begin
|
||||
// np_tx_cnt_qw_new[9:0] <= np_tx_cnt_qw[9:0];
|
||||
// addsub_state <= AS_IDLE;
|
||||
// sub_complete <= 1'b0;
|
||||
// add_complete <= 1'b0;
|
||||
// stay_2x <= 1'b0;
|
||||
// end
|
||||
// end
|
||||
// REGISTER_CALC:begin
|
||||
// sub_complete <= 1'b0;
|
||||
// add_complete <= 1'b0;
|
||||
// addsub_state <= WAIT_FOR_REG;
|
||||
// update_np_tx_cnt_qw <= 1'b1;
|
||||
// stay_2x <= 1'b0;
|
||||
// end
|
||||
// WAIT_FOR_REG:begin
|
||||
// update_np_tx_cnt_qw <= 1'b0;
|
||||
// stay_2x <= 1'b0;
|
||||
// addsub_state <= AS_IDLE;
|
||||
// end
|
||||
// default:begin
|
||||
// np_tx_cnt_qw_new[9:0] <= 0;
|
||||
// update_np_tx_cnt_qw <= 1'b0;
|
||||
// add_complete <= 1'b0;
|
||||
// sub_complete <= 1'b0;
|
||||
// stay_2x <= 1'b0;
|
||||
// addsub_state <= AS_IDLE;
|
||||
// end
|
||||
// endcase
|
||||
// end
|
||||
// end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,498 @@
|
|||
|
||||
###############################################################################
|
||||
# Define Device, Package And Speed Grade
|
||||
###############################################################################
|
||||
CONFIG PART = XC5VLX50T-FF1136-1;
|
||||
|
||||
###############################################################################
|
||||
# User Time Names / User Time Groups / Time Specs
|
||||
###############################################################################
|
||||
###############################################################################
|
||||
# User Physical Constraints
|
||||
###############################################################################
|
||||
|
||||
###############################################################################
|
||||
# Pinout and Related I/O Constraints
|
||||
###############################################################################
|
||||
#
|
||||
# SYS reset (input) signal. The sys_reset_n signal should be
|
||||
# obtained from the PCI Express interface if possible. For
|
||||
# slot based form factors, a system reset signal is usually
|
||||
# present on the connector. For cable based form factors, a
|
||||
# system reset signal may not be available. In this case, the
|
||||
# system reset signal must be generated locally by some form of
|
||||
# supervisory circuit. You may change the IOSTANDARD and LOC
|
||||
# to suit your requirements and VCCO voltage banking rules.
|
||||
#wo#NET "sys_reset_n" LOC = AE14 | IOSTANDARD = "LVCMOS25" | PULLUP | NODELAY;
|
||||
NET "sys_reset_n" LOC = K21 | IOSTANDARD = "LVCMOS33" | PULLUP | NODELAY;
|
||||
|
||||
#
|
||||
# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
|
||||
# signals are the PCI Express reference clock. Virtex-5 GTP
|
||||
# Transceiver architecture requires the use of a dedicated clock
|
||||
# resources (FPGA input pins) associated with each GTP Transceiver Tile.
|
||||
# To use these pins an IBUFDS primitive (refclk_ibuf) is
|
||||
# instantiated in user's design.
|
||||
# Please refer to the Virtex-5 GTP Transceiver User Guide
|
||||
# (UG196) for guidelines regarding clock resource selection.
|
||||
#
|
||||
NET "pcie_sys_clk_p" LOC = "Y4" ; #KL: changed the name from sys_clk_p
|
||||
NET "pcie_sys_clk_n" LOC = "Y3" ; #KL: changed the name from sys_clk_n
|
||||
INST "refclk_ibuf" DIFF_TERM = "TRUE" ;
|
||||
|
||||
#
|
||||
# Transceiver instance placement. This constraint selects the
|
||||
# transceivers to be used, which also dictates the pinout for the
|
||||
# transmit and receive differential pairs. Please refer to the
|
||||
# Virtex-5 GTP Transceiver User Guide (UG196) for more
|
||||
# information.
|
||||
#
|
||||
#KL: changed the ordering of the GTP LOCs to match the ML555
|
||||
# PCIe Lanes 0, 1
|
||||
#INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTP_DUAL_X0Y3; // PCIe v1.9
|
||||
INST "ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTP_DUAL_X0Y3; // PCIe v1.14
|
||||
|
||||
# PCIe Lanes 2, 3
|
||||
#INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" LOC = GTP_DUAL_X0Y2; // PCIe v1.9
|
||||
INST "ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" LOC = GTP_DUAL_X0Y2; // PCIe v1.14
|
||||
|
||||
# PCIe Lanes 4, 5
|
||||
#INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i" LOC = GTP_DUAL_X0Y1;
|
||||
|
||||
# PCIe Lanes 6, 7
|
||||
#INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i" LOC = GTP_DUAL_X0Y0;
|
||||
|
||||
###############################################################################
|
||||
# Physical Constraints
|
||||
###############################################################################
|
||||
#
|
||||
# BlockRAM placement
|
||||
#
|
||||
#INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X1Y9 ;
|
||||
#INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X1Y8 ;
|
||||
#INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X1Y7 ;
|
||||
#INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X1Y6 ;
|
||||
#INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst" LOC = RAMB36_X1Y5 ;
|
||||
|
||||
#
|
||||
# Timing critical placements
|
||||
#
|
||||
#INST "ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/tx_bridge/tx_bridge/shift_pipe1" LOC = "SLICE_X59Y36" ;
|
||||
#INST "ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/completion_available" LOC = "SLICE_X58Y26" ;
|
||||
#INST "ep/BU2/U0/pcie_ep0/pcie_blk_if/cf_bridge/management_interface/mgmt_rdata_d1_3" LOC = "SLICE_X59Y25" ;
|
||||
|
||||
###############################################################################
|
||||
# Timing Constraints
|
||||
###############################################################################
|
||||
#
|
||||
# Timing requirements and related constraints.
|
||||
#
|
||||
NET "sys_clk_c" PERIOD = 10ns;
|
||||
|
||||
#NET "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_refclk_out[0]" TNM_NET = "MGTCLK" ; // pcie v1.9
|
||||
NET "ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_refclk_out[0]" TNM_NET = "MGTCLK" ; // pcie v1.14
|
||||
|
||||
TIMESPEC "TS_MGTCLK" = PERIOD "MGTCLK" 100.00 MHz HIGH 50 % ;
|
||||
|
||||
###############################################################################
|
||||
# End of contraints from Endpoint Block Plus
|
||||
###############################################################################
|
||||
###################################################
|
||||
## Additional Timing Constraints
|
||||
###################################################
|
||||
## SYS_CLK is the DDR2 clock - 200 MHz
|
||||
#NET "ddr2_cntrl_inst/u_infrastructure/sys_clk_ibufg" TNM_NET = "SYS_CLK";
|
||||
NET "ddr2_cntrl_inst/u_infrastructure/sys_clk" TNM_NET = "SYS_CLK";
|
||||
#TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 5 ns HIGH 50 %;
|
||||
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 7.5 ns HIGH 50 %;
|
||||
## SYS_CLK_200 is for the idelay - 200 MHz
|
||||
NET "ddr2_cntrl_inst/u_infrastructure/clk200_ibufg" TNM_NET = "SYS_CLK_200";
|
||||
TIMESPEC "TS_SYS_CLK_200" = PERIOD "SYS_CLK_200" 5 ns HIGH 50 %;
|
||||
#TIMESPEC "TS_SYS_CLK_200" = PERIOD "SYS_CLK_200" 7.5 ns HIGH 50 %;
|
||||
|
||||
# timing constrain for posted packet scheduler
|
||||
NET "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_inst/clk" TNM_NET = "POSTED_CLK";
|
||||
TIMESPEC "TS_POSTED_CLK" = PERIOD "POSTED_CLK" 8ns HIGH 50%;
|
||||
|
||||
# timing constrain for pcie_dma_wrapper
|
||||
NET "pcie_dma_wrapper_inst/clk" TNM_NET = "PCIE_DMA_CLK";
|
||||
TIMESPEC "TS_PCIE_DMA_CLK" = PERIOD "PCIE_DMA_CLK" 8ns HIGH 50%;
|
||||
|
||||
# timing constrain for Sora_FRL module
|
||||
NET "Sora_FRL_RCB_inst/RCB_FRL_RX_inst/CLKDIV" TNM_NET = "LVDS_RX_CLK";
|
||||
TIMESPEC "TS_LVDS_RX_CLK" = PERIOD "LVDS_RX_CLK" 12.5ns HIGH 50%;
|
||||
|
||||
# timing constrain for Sora_FRL module
|
||||
NET "Sora_FRL_RCB_inst/RCB_FRL_RX_MSG_inst/CLKDIV" TNM_NET = "LVDS_RX_MSG_CLK";
|
||||
TIMESPEC "TS_LVDS_RX_MSG_CLK" = PERIOD "LVDS_RX_MSG_CLK" 12.5ns HIGH 50%;
|
||||
|
||||
# timing constrain for Sora_FRL module
|
||||
NET "Sora_FRL_RCB_inst/RCB_FRL_TX_inst/CLKDIV" TNM_NET = "LVDS_TX_CLK";
|
||||
TIMESPEC "TS_LVDS_TX_CLK" = PERIOD "LVDS_TX_CLK" 12.5ns HIGH 50%;
|
||||
|
||||
# timing constrain for Sora_FRL module
|
||||
NET "Sora_FRL_RCB_inst/RCB_FRL_TX_MSG_inst/CLKDIV" TNM_NET = "LVDS_TX_MSG_CLK";
|
||||
TIMESPEC "TS_LVDS_TX_MSG_CLK" = PERIOD "LVDS_TX_MSG_CLK" 12.5ns HIGH 50%;
|
||||
|
||||
## Multi-cycle paths
|
||||
#Multi-cycle paths for tx_trn_sm adder/subtractor
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/rx_trn_monitor_inst/dma*_div8_reg*" TNM=FFS "TNM_DMARDIV8_REG_SRC";
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/rx_trn_monitor_inst/dma*_div8_now*" TNM=FFS "TNM_DMARDIV8_NOW_SRC";
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/rx_trn_monitor_inst/addsub_state*" TNM=FFS "TNM_RADDSUB_STATE_SRC";
|
||||
TIMEGRP "DMARDIV8_2X_SRC" = "TNM_DMARDIV8_REG_SRC" "TNM_DMARDIV8_NOW_SRC" "TNM_RADDSUB_STATE_SRC";
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/rx_trn_monitor_inst/dma*_div8_reg_new*" TNM=FFS "TNM_DMARDIV8_REGNEW_DEST";
|
||||
TIMESPEC "TS_DMARDIV8_2X" = FROM "DMARDIV8_2X_SRC" TO "TNM_DMARDIV8_REGNEW_DEST" "TS_MGTCLK"*1.25; ## 2/5 for 250MHz * 2 for multicycle
|
||||
|
||||
#Multi-cycle paths for tx_trn_sm adder/subtractor
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/tx_trn_sm_inst/dma*_div8_reg*" TNM=FFS "TNM_DMAWDIV8_REG_SRC";
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/tx_trn_sm_inst/dma*_div8_now*" TNM=FFS "TNM_DMAWDIV8_NOW_SRC";
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/tx_trn_sm_inst/addsub_state*" TNM=FFS "TNM_WADDSUB_STATE_SRC";
|
||||
##TIMEGRP "DMAWDIV8_2X_SRC" = "TNM_DMAWDIV8_REG_SRC" "TNM_DMAWDIV8_NOW_SRC" "TNM_WADDSUB_STATE_SRC";
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/tx_trn_sm_inst/dma*_div8_reg_new*" TNM=FFS "TNM_DMAWDIV8_REGNEW_DEST";
|
||||
##TIMESPEC "TS_DMAWDIV8_2X" = FROM "DMAWDIV8_2X_SRC" TO "TNM_DMAWDIV8_REGNEW_DEST" "TS_MGTCLK"*1.25; ## 2/5 for 250MHz * 2 for multicycle
|
||||
|
||||
#Multi-cycle paths for posted slicer adder
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/posted_pkt_gen_inst/posted_pkt_slicer_inst/four_kb_xfer*" TNM=FFS "TNM_PFKB_SRC";
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/posted_pkt_gen_inst/posted_pkt_slicer_inst/dma*_reg*" TNM=FFS "TNM_PDMAREG_SRC";
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/posted_pkt_gen_inst/posted_pkt_slicer_inst/state*" TNM=FFS "TNM_PSTATE_SRC";
|
||||
##TIMEGRP "POSTED_2X_SRC" = "TNM_PFKB_SRC" "TNM_PDMAREG_SRC" "TNM_PSTATE_SRC";
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/posted_pkt_gen_inst/posted_pkt_slicer_inst/dma*_new*" TNM=FFS "TNM_PDMANEW_DEST";
|
||||
##TIMESPEC "TS_POSTED_2X" = FROM "POSTED_2X_SRC" TO "TNM_PDMANEW_DEST" "TS_MGTCLK"*1.25; ## 2/5 for 250MHz * 2 for multicycle
|
||||
|
||||
#Multi-cycle paths for non-posted slicer adder
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/four_kb_xfer*" TNM=FFS "TNM_NFKB_SRC";
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/dma*_reg*" TNM=FFS "TNM_NDMAREG_SRC";
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/state*" TNM=FFS "TNM_NSTATE_SRC";
|
||||
##TIMEGRP "NONPOSTED_2X_SRC" = "TNM_NFKB_SRC" "TNM_NDMAREG_SRC" "TNM_NSTATE_SRC";
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/dma*_new*" TNM=FFS "TNM_NDMANEW_DEST";
|
||||
##TIMESPEC "TS_NONPOSTED_2X" = FROM "NONPOSTED_2X_SRC" TO "TNM_NDMANEW_DEST" "TS_MGTCLK"*1.25; ## 2/5 for 250MHz * 2 for multicycle
|
||||
INST "pcie_dma_wrapper_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/four_kb_xfer*" TNM=FFS "TNM_NFKB_SRC";
|
||||
INST "pcie_dma_wrapper_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/dma*_reg*" TNM=FFS "TNM_NDMAREG_SRC";
|
||||
INST "pcie_dma_wrapper_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/state*" TNM=FFS "TNM_NSTATE_SRC";
|
||||
TIMEGRP "NONPOSTED_2X_SRC" = "TNM_NFKB_SRC" "TNM_NDMAREG_SRC" "TNM_NSTATE_SRC";
|
||||
INST "pcie_dma_wrapper_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/dma*_new*" TNM=FFS "TNM_NDMANEW_DEST";
|
||||
TIMESPEC "TS_NONPOSTED_2X" = FROM "NONPOSTED_2X_SRC" TO "TNM_NDMANEW_DEST" "TS_MGTCLK"*1.25; ## 2/5 for 250MHz * 2 for multicycle
|
||||
|
||||
# Multi-cycle paths for large xfers shim adder
|
||||
##INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/state_1*" TNM=FFS "TNM_STATE_1_SRC";
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/state_3*" TNM=FFS "TNM_STATE_3_SRC";
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/dma*_now*" TNM=FFS "TNM_DMANOW_SRC";
|
||||
##TIMEGRP "LARGE_XFER_2X_SRC" = "TNM_STATE_1_SRC" "TNM_STATE_3_SRC" "TNM_DMANOW_SRC";
|
||||
TIMEGRP "LARGE_XFER_2X_SRC" = "TNM_STATE_3_SRC" "TNM_DMANOW_SRC";
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/dma*_next*" TNM=FFS "TNM_DMANEXT_DEST";
|
||||
TIMESPEC "TS_DMAREG_DMANEXT" = FROM "LARGE_XFER_2X_SRC" TO "TNM_DMANEXT_DEST" "TS_MGTCLK"*1.25; ## 2/5 for 250MHz * 2 for multicycle
|
||||
|
||||
# Jiansong: added
|
||||
# Multi-cycle paths for large xfers shim adder
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/TX_state_1*" TNM=FFS "TNM_TX_STATE_1_SRC";
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/TX_*_now*" TNM=FFS "TNM_TXNOW_SRC";
|
||||
TIMEGRP "TX_LARGE_XFER_2X_SRC" = "TNM_TX_STATE_1_SRC" "TNM_TXNOW_SRC";
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/TX_*_next*" TNM=FFS "TNM_TXNEXT_DEST";
|
||||
TIMESPEC "TS_TXREG_TXNEXT" = FROM "TX_LARGE_XFER_2X_SRC" TO "TNM_TXNEXT_DEST" "TS_MGTCLK"*1.25; ## 2/5 for 250MHz * 2 for multicycle
|
||||
|
||||
# Jiansong: added for poset_packet_scheduler
|
||||
# Multi-cycle paths for posted scheduler adder
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_inst/RXBuf*" TNM=FFS "TNM_NRXB_SRC";
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_inst/dmawad_now*" TNM=FFS "TNM_NDWNW_SRC";
|
||||
TIMEGRP "POSTED_2X_SRC" = "TNM_NRXB_SRC" "TNM_NDWNW_SRC";
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_inst/dmawad_next*" TNM=FFS "TNM_NDWNT_DEST";
|
||||
TIMESPEC "TS_POSTED_2X" = FROM "POSTED_2X_SRC" TO "TNM_NDWNT_DEST" "TS_MGTCLK"*1.25; ## 2/5 for 250MHz * 2 for multicycle
|
||||
|
||||
#Tig'ed nets - these are static signals
|
||||
NET "trn_lnk_up_n_c" TIG;
|
||||
NET "phy_init_initialization_done" TIG;
|
||||
|
||||
INST "max_read_req_reg*" TIG;
|
||||
INST "max_pay_size_reg*" TIG;
|
||||
INST "pcie_id_reg*" TIG;
|
||||
|
||||
################################################################################
|
||||
# PIN Location and I/O STANDARDS
|
||||
################################################################################
|
||||
################################################################################
|
||||
##
|
||||
## Global Clock inputs
|
||||
## FPGA Bank 3: Vcco = 2.5 Volts
|
||||
##
|
||||
## Note: Use DIFF_TERM attribute on LVDS clock inputs as the ML555 DOES NOT
|
||||
## provide 100 ohm terminators on the circuit board assembly
|
||||
################################################################################
|
||||
NET "CLK200_P" LOC = J16 | DIFF_TERM = TRUE; ## ICS1 PLL LVDS
|
||||
NET "CLK200_N" LOC = J17 | DIFF_TERM = TRUE;
|
||||
NET "SYS_CLK_P" LOC = H14 | DIFF_TERM = TRUE; ## ICS2 PLL LVDS
|
||||
NET "SYS_CLK_N" LOC = H15 | DIFF_TERM = TRUE;
|
||||
|
||||
# LEDs
|
||||
# Indicates that the PCIe endpoint has successfully completed link training
|
||||
# with the downstream port connected to it
|
||||
NET "LED_link_up_and_phy_init_initialization_done_n" LOC = L21 | IOSTANDARD = "LVCMOS33";
|
||||
NET "Sora_FRL_done_n" LOC = L20 | IOSTANDARD = "LVCMOS33";
|
||||
NET "Radio_RX_blink" LOC = L15 | IOSTANDARD = "LVCMOS33";
|
||||
NET "Radio_TX_n" LOC = L16 | IOSTANDARD = "LVCMOS33";
|
||||
#NET "RXEnable_n" LOC = L20 | IOSTANDARD = "LVCMOS33";
|
||||
#NET "phy_init_initialization_done_n" LOC = L21 | IOSTANDARD = "LVCMOS33";
|
||||
#NET "LED_link_up_n" LOC = L20 | IOSTANDARD = "LVCMOS33";
|
||||
#NET "LED_clock" LOC = L15 | IOSTANDARD = "LVCMOS33";
|
||||
#NET "LED_clock_1" LOC = L16 | IOSTANDARD = "LVCMOS33";
|
||||
|
||||
#INST "RXEnable_n_OBUF" DRIVE = 24;
|
||||
INST "LED_link_up_and_phy_init_initialization_done_n_OBUF" DRIVE = 24;
|
||||
INST "Sora_FRL_done_n_OBUF" DRIVE = 24;
|
||||
INST "Radio_RX_blink_OBUF" DRIVE = 24;
|
||||
INST "Radio_TX_n_OBUF" DRIVE = 24;
|
||||
#INST "LED_link_up_n_OBUF" DRIVE = 24;
|
||||
#INST "DDR2_phy_init_n_OBUF" DRIVE = 24;
|
||||
#INST "LED_clock_OBUF" DRIVE = 24;
|
||||
#INST "LED_clock_1_OBUF" DRIVE = 24;
|
||||
|
||||
#Clock ICS load
|
||||
NET "nPLOAD_1" LOC = "K12" | IOSTANDARD = "LVCMOS33";
|
||||
NET "nPLOAD_2" LOC = "K23" | IOSTANDARD = "LVCMOS33";
|
||||
|
||||
###############################################################################
|
||||
# Location Constraints for Sora_FRL
|
||||
###############################################################################
|
||||
|
||||
NET "Sora_FRL_CLK_I_p" LOC = N33;
|
||||
NET "Sora_FRL_CLK_I_n" LOC = M33;
|
||||
NET "Sora_FRL_DATA_IN_p[3]" LOC = L33;
|
||||
NET "Sora_FRL_DATA_IN_n[3]" LOC = M32;
|
||||
NET "Sora_FRL_DATA_IN_p[2]" LOC = K31;
|
||||
NET "Sora_FRL_DATA_IN_n[2]" LOC = L31;
|
||||
NET "Sora_FRL_DATA_IN_p[1]" LOC = K33;
|
||||
NET "Sora_FRL_DATA_IN_n[1]" LOC = K32;
|
||||
NET "Sora_FRL_DATA_IN_p[0]" LOC = G33;
|
||||
NET "Sora_FRL_DATA_IN_n[0]" LOC = F34;
|
||||
NET "Sora_FRL_MSG_IN_p" LOC = F33;
|
||||
NET "Sora_FRL_MSG_IN_n" LOC = E34;
|
||||
NET "Sora_FRL_STATUS_IN_p" LOC = K18;
|
||||
NET "Sora_FRL_STATUS_IN_n" LOC = J19;
|
||||
|
||||
NET "Sora_FRL_CLK_O_p" LOC = C34;
|
||||
NET "Sora_FRL_CLK_O_n" LOC = D34;
|
||||
NET "Sora_FRL_DATA_OUT_p[3]" LOC = B33;
|
||||
NET "Sora_FRL_DATA_OUT_n[3]" LOC = C33;
|
||||
NET "Sora_FRL_DATA_OUT_p[2]" LOC = B32;
|
||||
NET "Sora_FRL_DATA_OUT_n[2]" LOC = A33;
|
||||
NET "Sora_FRL_DATA_OUT_p[1]" LOC = C32;
|
||||
NET "Sora_FRL_DATA_OUT_n[1]" LOC = D32;
|
||||
NET "Sora_FRL_DATA_OUT_p[0]" LOC = E32;
|
||||
NET "Sora_FRL_DATA_OUT_n[0]" LOC = E33;
|
||||
NET "Sora_FRL_MSG_OUT_p" LOC = G32;
|
||||
NET "Sora_FRL_MSG_OUT_n" LOC = H32;
|
||||
NET "Sora_FRL_STATUS_OUT_p" LOC = J32;
|
||||
NET "Sora_FRL_STATUS_OUT_n" LOC = H33;
|
||||
|
||||
################################################################################
|
||||
# I/O STANDARDS for Sora_FRL
|
||||
################################################################################
|
||||
NET "Sora_FRL_CLK_O_p" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_CLK_O_n" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_DATA_IN_p[0]" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_DATA_IN_n[0]" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_DATA_IN_p[1]" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_DATA_IN_n[1]" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_DATA_IN_p[2]" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_DATA_IN_n[2]" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_DATA_IN_p[3]" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_DATA_IN_n[3]" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_MSG_IN_p" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_MSG_IN_n" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_STATUS_IN_p" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_STATUS_IN_n" IOSTANDARD = LVDS_25;
|
||||
|
||||
NET "Sora_FRL_CLK_I_p" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_CLK_I_n" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_DATA_OUT_p[0]" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_DATA_OUT_n[0]" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_DATA_OUT_p[1]" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_DATA_OUT_n[1]" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_DATA_OUT_p[2]" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_DATA_OUT_n[2]" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_DATA_OUT_p[3]" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_DATA_OUT_n[3]" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_MSG_OUT_p" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_MSG_OUT_n" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_STATUS_OUT_p" IOSTANDARD = LVDS_25;
|
||||
NET "Sora_FRL_STATUS_OUT_n" IOSTANDARD = LVDS_25;
|
||||
|
||||
################################################################################
|
||||
# I/O STANDARDS for DDR2
|
||||
################################################################################
|
||||
NET "DDR2_DQ[*]" IOSTANDARD = SSTL18_II;
|
||||
NET "DDR2_A[*]" IOSTANDARD = SSTL18_II;
|
||||
NET "DDR2_BA[*]" IOSTANDARD = SSTL18_II;
|
||||
NET "DDR2_RAS_N" IOSTANDARD = SSTL18_II;
|
||||
NET "DDR2_CAS_N" IOSTANDARD = SSTL18_II;
|
||||
NET "DDR2_WE_N" IOSTANDARD = SSTL18_II;
|
||||
#NET "DDR2_RESET_N" IOSTANDARD = LVCMOS25;
|
||||
NET "DDR2_CS_N" IOSTANDARD = SSTL18_II;
|
||||
NET "DDR2_ODT" IOSTANDARD = SSTL18_II;
|
||||
NET "DDR2_CKE" IOSTANDARD = SSTL18_II;
|
||||
NET "DDR2_DM[*]" IOSTANDARD = SSTL18_II;
|
||||
NET "SYS_CLK_P" IOSTANDARD = LVDS_25;
|
||||
NET "SYS_CLK_N" IOSTANDARD = LVDS_25;
|
||||
NET "CLK200_P" IOSTANDARD = LVDS_25;
|
||||
NET "CLK200_N" IOSTANDARD = LVDS_25;
|
||||
NET "DDR2_DQS[*]" IOSTANDARD = DIFF_SSTL18_II_DCI;
|
||||
NET "DDR2_DQS_N[*]" IOSTANDARD = DIFF_SSTL18_II_DCI;
|
||||
NET "DDR2_CK[*]" IOSTANDARD = DIFF_SSTL18_II;
|
||||
NET "DDR2_CK_N[*]" IOSTANDARD = DIFF_SSTL18_II;
|
||||
|
||||
################################################################################
|
||||
# Location Constraints for DDR2
|
||||
################################################################################
|
||||
NET "DDR2_DQ[0]" LOC = "W24" ; #Bank 12
|
||||
NET "DDR2_DQ[1]" LOC = "V24" ; #Bank 12
|
||||
NET "DDR2_DQ[2]" LOC = "Y26" ; #Bank 12
|
||||
NET "DDR2_DQ[3]" LOC = "W26" ; #Bank 12
|
||||
NET "DDR2_DQ[4]" LOC = "V25" ; #Bank 12
|
||||
NET "DDR2_DQ[5]" LOC = "W25" ; #Bank 12
|
||||
NET "DDR2_DQ[6]" LOC = "Y27" ; #Bank 12
|
||||
NET "DDR2_DQ[7]" LOC = "W27" ; #Bank 12
|
||||
NET "DDR2_DQ[8]" LOC = "V28" ; #Bank 12
|
||||
NET "DDR2_DQ[9]" LOC = "V27" ; #Bank 12
|
||||
NET "DDR2_DQ[10]" LOC = "W31" ; #Bank 12
|
||||
NET "DDR2_DQ[11]" LOC = "Y31" ; #Bank 12
|
||||
NET "DDR2_DQ[12]" LOC = "W29" ; #Bank 12
|
||||
NET "DDR2_DQ[13]" LOC = "V29" ; #Bank 12
|
||||
NET "DDR2_DQ[14]" LOC = "Y28" ; #Bank 12
|
||||
NET "DDR2_DQ[15]" LOC = "Y29" ; #Bank 12
|
||||
NET "DDR2_DQ[16]" LOC = "AC29"; #Bank 12
|
||||
NET "DDR2_DQ[17]" LOC = "AF31"; #Bank 12
|
||||
NET "DDR2_DQ[18]" LOC = "AJ31"; #Bank 12
|
||||
NET "DDR2_DQ[19]" LOC = "AK31"; #Bank 12
|
||||
NET "DDR2_DQ[20]" LOC = "AF29"; #Bank 12
|
||||
NET "DDR2_DQ[21]" LOC = "AF30"; #Bank 12
|
||||
NET "DDR2_DQ[22]" LOC = "AJ30"; #Bank 12
|
||||
NET "DDR2_DQ[23]" LOC = "AH30"; #Bank 12
|
||||
NET "DDR2_DQ[24]" LOC = "AA25"; #Bank 18
|
||||
NET "DDR2_DQ[25]" LOC = "AA26"; #Bank 18
|
||||
NET "DDR2_DQ[26]" LOC = "AB27"; #Bank 18
|
||||
NET "DDR2_DQ[27]" LOC = "AC27"; #Bank 18
|
||||
NET "DDR2_DQ[28]" LOC = "Y24"; #Bank 18
|
||||
NET "DDR2_DQ[29]" LOC = "AA24"; #Bank 18
|
||||
NET "DDR2_DQ[30]" LOC = "AB25"; #Bank 18
|
||||
NET "DDR2_DQ[31]" LOC = "AB26"; #Bank 18
|
||||
NET "DDR2_DQ[32]" LOC = "AB28"; #Bank 18
|
||||
NET "DDR2_DQ[33]" LOC = "AA28"; #Bank 18
|
||||
NET "DDR2_DQ[34]" LOC = "AG28"; #Bank 18
|
||||
NET "DDR2_DQ[35]" LOC = "AH28"; #Bank 18
|
||||
NET "DDR2_DQ[36]" LOC = "AK26"; #Bank 18
|
||||
NET "DDR2_DQ[37]" LOC = "AF28"; #Bank 18
|
||||
NET "DDR2_DQ[38]" LOC = "AE28"; #Bank 18
|
||||
NET "DDR2_DQ[39]" LOC = "AJ27"; #Bank 18
|
||||
NET "DDR2_DQ[40]" LOC = "AG25"; #Bank 18
|
||||
NET "DDR2_DQ[41]" LOC = "AG27"; #Bank 18
|
||||
NET "DDR2_DQ[42]" LOC = "AE27"; #Bank 18
|
||||
NET "DDR2_DQ[43]" LOC = "AE26"; #Bank 18
|
||||
NET "DDR2_DQ[44]" LOC = "AC25"; #Bank 18
|
||||
NET "DDR2_DQ[45]" LOC = "AC24"; #Bank 18
|
||||
NET "DDR2_DQ[46]" LOC = "AD26"; #Bank 18
|
||||
NET "DDR2_DQ[47]" LOC = "AD25"; #Bank 18
|
||||
NET "DDR2_DQ[48]" LOC = "AN14"; #Bank 20
|
||||
NET "DDR2_DQ[49]" LOC = "AP14"; #Bank 20
|
||||
NET "DDR2_DQ[50]" LOC = "AB10"; #Bank 20
|
||||
NET "DDR2_DQ[51]" LOC = "AA10"; #Bank 20
|
||||
NET "DDR2_DQ[52]" LOC = "AN13"; #Bank 20
|
||||
NET "DDR2_DQ[53]" LOC = "AM13"; #Bank 20
|
||||
NET "DDR2_DQ[54]" LOC = "AA8"; #Bank 20
|
||||
NET "DDR2_DQ[55]" LOC = "AA9"; #Bank 20
|
||||
NET "DDR2_DQ[56]" LOC = "AC8"; #Bank 20
|
||||
NET "DDR2_DQ[57]" LOC = "AB8"; #Bank 20
|
||||
NET "DDR2_DQ[58]" LOC = "AM12"; #Bank 20
|
||||
NET "DDR2_DQ[59]" LOC = "AM11"; #Bank 20
|
||||
NET "DDR2_DQ[60]" LOC = "AC10"; #Bank 20
|
||||
NET "DDR2_DQ[61]" LOC = "AC9"; #Bank 20
|
||||
NET "DDR2_DQ[62]" LOC = "AK9"; #Bank 20
|
||||
NET "DDR2_DQ[63]" LOC = "AF9"; #Bank 20
|
||||
NET "DDR2_A[12]" LOC = "AH19"; #Bank 18
|
||||
NET "DDR2_A[11]" LOC = "AH20"; #Bank 18
|
||||
NET "DDR2_A[10]" LOC = "AG15"; #Bank 18
|
||||
NET "DDR2_A[9]" LOC = "AH15"; #Bank 20
|
||||
NET "DDR2_A[8]" LOC = "AG20"; #Bank 20
|
||||
NET "DDR2_A[7]" LOC = "AG16"; #Bank 20
|
||||
NET "DDR2_A[6]" LOC = "AH17"; #Bank 22
|
||||
NET "DDR2_A[5]" LOC = "AH22"; #Bank 22
|
||||
NET "DDR2_A[4]" LOC = "AG22"; #Bank 22
|
||||
NET "DDR2_A[3]" LOC = "AG17"; #Bank 22
|
||||
NET "DDR2_A[2]" LOC = "AH18"; #Bank 22
|
||||
NET "DDR2_A[1]" LOC = "AF18"; #Bank 22
|
||||
NET "DDR2_A[0]" LOC = "AE18"; #Bank 22
|
||||
NET "DDR2_BA[1]" LOC = "AH13"; #Bank 22
|
||||
NET "DDR2_BA[0]" LOC = "AH14"; #Bank 22
|
||||
NET "DDR2_RAS_N" LOC = "AG13"; #Bank 22
|
||||
NET "DDR2_CAS_N" LOC = "AH12"; #Bank 22
|
||||
NET "DDR2_WE_N" LOC = "AF19"; #Bank 22
|
||||
#NET "DDR2_RESET_N" LOC = "U7"; #Bank 22 output signal
|
||||
NET "DDR2_CS_N" LOC = "AG18"; #Bank 22
|
||||
NET "DDR2_ODT" LOC = "AG30"; #Bank 22
|
||||
NET "DDR2_CKE" LOC = "AG8"; #Bank 22
|
||||
NET "DDR2_DM[0]" LOC = "V30"; #Bank 12
|
||||
NET "DDR2_DM[1]" LOC = "AD30"; #Bank 12
|
||||
NET "DDR2_DM[2]" LOC = "AH29"; #Bank 12
|
||||
NET "DDR2_DM[3]" LOC = "AC28"; #Bank 18
|
||||
NET "DDR2_DM[4]" LOC = "AF24"; #Bank 18
|
||||
NET "DDR2_DM[5]" LOC = "AD24"; #Bank 18
|
||||
NET "DDR2_DM[6]" LOC = "AP12"; #Bank 20
|
||||
NET "DDR2_DM[7]" LOC = "AJ9"; #Bank 20
|
||||
NET "DDR2_DQS[0]" LOC = "AB31"; #Bank 12
|
||||
NET "DDR2_DQS_N[0]" LOC = "AA31"; #Bank 12
|
||||
NET "DDR2_DQS[1]" LOC = "AB30"; #Bank 12
|
||||
NET "DDR2_DQS_N[1]" LOC = "AC30"; #Bank 12
|
||||
NET "DDR2_DQS[2]" LOC = "AA29"; #Bank 12
|
||||
NET "DDR2_DQS_N[2]" LOC = "AA30"; #Bank 12
|
||||
NET "DDR2_DQS[3]" LOC = "AK29"; #Bank 18
|
||||
NET "DDR2_DQS_N[3]" LOC = "AJ29"; #Bank 18
|
||||
NET "DDR2_DQS[4]" LOC = "AK28"; #Bank 18
|
||||
NET "DDR2_DQS_N[4]" LOC = "AK27"; #Bank 18
|
||||
NET "DDR2_DQS[5]" LOC = "AH27"; #Bank 18
|
||||
NET "DDR2_DQS_N[5]" LOC = "AJ26"; #Bank 18
|
||||
NET "DDR2_DQS[6]" LOC = "AD10"; #Bank 20
|
||||
NET "DDR2_DQS_N[6]" LOC = "AD11"; #Bank 20
|
||||
NET "DDR2_DQS[7]" LOC = "AK11"; #Bank 20
|
||||
NET "DDR2_DQS_N[7]" LOC = "AJ11"; #Bank 20
|
||||
NET "DDR2_CK[0]" LOC = "AH9" ; #Bank 12
|
||||
NET "DDR2_CK_N[0]" LOC = "AH10" ; #Bank 12
|
||||
NET "DDR2_CK[1]" LOC = "AG10" ; #Bank 12
|
||||
NET "DDR2_CK_N[1]" LOC = "AG11" ; #Bank 12
|
||||
|
||||
###################################################
|
||||
## Floorplanned location constrains - non-I/O
|
||||
###################################################
|
||||
# PLL specification LOCs
|
||||
INST "ddr2_cntrl_inst/u_infrastructure/u_dcm_base" LOC = DCM_ADV_X0Y6;
|
||||
|
||||
##Floorplan some of the blockrams
|
||||
|
||||
#Egress fifo BRAMS
|
||||
##AREA_GROUP "pblock_egress_fifos" RANGE=RAMB36_X0Y6:RAMB36_X0Y11;
|
||||
##INST "dma_ddr2_if_inst/egress_fifo_wrapper_inst/egress_fifo_a" AREA_GROUP = "pblock_egress_fifos";
|
||||
##INST "dma_ddr2_if_inst/egress_fifo_wrapper_inst/egress_fifo_b" AREA_GROUP = "pblock_egress_fifos";
|
||||
|
||||
#Ingress fifo BRAMS
|
||||
#INST "dma_ddr2_if_inst/ingress_fifo_a" LOC = "RAMB36_X0Y3";
|
||||
#INST "dma_ddr2_if_inst/ingress_fifo_b" LOC = "RAMB36_X0Y4";
|
||||
|
||||
#DDR2 controller fifo BRAMS
|
||||
INST "ddr2_cntrl_inst/u_ddr2_top_0/u_mem_if_top_0/u_usr_top_0/u_backend_fifos_0/gen_wdf[1].u_usr_wr_fifo/u_wdf" LOC = "RAMB36_X0Y2";
|
||||
INST "ddr2_cntrl_inst/u_ddr2_top_0/u_mem_if_top_0/u_usr_top_0/u_backend_fifos_0/gen_wdf[0].u_usr_wr_fifo/u_wdf" LOC = "RAMB36_X0Y5";
|
||||
INST "ddr2_cntrl_inst/u_ddr2_top_0/u_mem_if_top_0/u_usr_top_0/u_backend_fifos_0/u_usr_addr_fifo_0/u_af" LOC = "RAMB36_X0Y7";
|
||||
|
||||
#RX Engine fifo BRAMS
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/data_trn_mem_fifo_inst/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[3].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP" LOC = "RAMB36_X1Y4";
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/data_trn_mem_fifo_inst/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[2].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP" LOC = "RAMB36_X1Y3";
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/data_trn_mem_fifo_inst/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP" LOC = "RAMB36_X1Y1";
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/data_trn_mem_fifo_inst/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP" LOC = "RAMB36_X1Y2";
|
||||
|
||||
# PlanAhead generated physical constraints
|
||||
AREA_GROUP "pblock_r6_mem_cntrl" RANGE=SLICE_X12Y0:SLICE_X49Y9,
|
||||
SLICE_X0Y0:SLICE_X11Y49,
|
||||
SLICE_X12Y30:SLICE_X23Y44;
|
||||
AREA_GROUP "pblock_r6_mem_cntrl" RANGE=RAMB36_X0Y0:RAMB36_X0Y9,
|
||||
RAMB36_X1Y0:RAMB36_X1Y1;
|
||||
INST "ddr2_cntrl_inst" AREA_GROUP = "pblock_r6_mem_cntrl";
|
||||
|
||||
#AREA_GROUP "pblock_dma_ctrl_wrapper" RANGE=SLICE_X0Y50:SLICE_X19Y89;
|
||||
AREA_GROUP "pblock_dma_ctrl_wrapper" RANGE=SLICE_X0Y50:SLICE_X25Y95;
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst" AREA_GROUP = "pblock_dma_ctrl_wrapper";
|
||||
|
|
@ -0,0 +1,798 @@
|
|||
###############################################################################
|
||||
## 2007-2008 Xilinx, Inc. All Rights Reserved.
|
||||
## Confidential and proprietary information of Xilinx, Inc.
|
||||
###############################################################################
|
||||
## ____ ____
|
||||
## / /\/ /
|
||||
## /___/ \ / Vendor: Xilinx
|
||||
## \ \ \/ Version: 1.1
|
||||
## \ \ Filename: pcie_dma_top_x8_plus.ucf
|
||||
## / / Date Last Modified: May. 15th, 2008
|
||||
## /___/ /\ Date Created: Apr. 1st, 2008
|
||||
## \ \ / \
|
||||
## \___\/\___\
|
||||
##
|
||||
## Device: Virtex-5 LXT
|
||||
## Purpose: Endpoint Block Plus to DDR2 DMA Initiator User Constraints File
|
||||
## Reference: XAPP859
|
||||
## Revision History:
|
||||
## Rev 1.0 - First created, Kraig Lund, Apr. 1 2008.
|
||||
## Rev 1.1 - Changed instance names of RX Engine Fifo Brams - necessary
|
||||
## because the Fifo Generato LogiCore was updated to latest version
|
||||
## (Rev 4.3) May 15th, 2008
|
||||
## Removed CLK_0_FROM_MEM_CTRL_DCM pin (this was a debug pin and
|
||||
## was not necessary for the design to work properly. May29th, 2008
|
||||
##
|
||||
## Modified by Jiansong Zhang:
|
||||
## PCIe x4, 125MHz user logic
|
||||
## 133MHz DDR
|
||||
## work on RCBv1.1.3
|
||||
## plus warp radio
|
||||
##
|
||||
###############################################################################
|
||||
# Define Device, Package And Speed Grade
|
||||
###############################################################################
|
||||
CONFIG PART = XC5VLX50T-FF1136-1;
|
||||
|
||||
###############################################################################
|
||||
# User Time Names / User Time Groups / Time Specs
|
||||
###############################################################################
|
||||
###############################################################################
|
||||
# User Physical Constraints
|
||||
###############################################################################
|
||||
|
||||
###############################################################################
|
||||
# Pinout and Related I/O Constraints
|
||||
###############################################################################
|
||||
#
|
||||
# SYS reset (input) signal. The sys_reset_n signal should be
|
||||
# obtained from the PCI Express interface if possible. For
|
||||
# slot based form factors, a system reset signal is usually
|
||||
# present on the connector. For cable based form factors, a
|
||||
# system reset signal may not be available. In this case, the
|
||||
# system reset signal must be generated locally by some form of
|
||||
# supervisory circuit. You may change the IOSTANDARD and LOC
|
||||
# to suit your requirements and VCCO voltage banking rules.
|
||||
#
|
||||
#NET "sys_reset_n" LOC = AE14 | IOSTANDARD = "LVCMOS25" | PULLUP | NODELAY;
|
||||
NET "sys_reset_n" LOC = K21 | IOSTANDARD = "LVCMOS33" | PULLUP | NODELAY;
|
||||
|
||||
#
|
||||
# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
|
||||
# signals are the PCI Express reference clock. Virtex-5 GTP
|
||||
# Transceiver architecture requires the use of a dedicated clock
|
||||
# resources (FPGA input pins) associated with each GTP Transceiver Tile.
|
||||
# To use these pins an IBUFDS primitive (refclk_ibuf) is
|
||||
# instantiated in user's design.
|
||||
# Please refer to the Virtex-5 GTP Transceiver User Guide
|
||||
# (UG196) for guidelines regarding clock resource selection.
|
||||
#
|
||||
NET "pcie_sys_clk_p" LOC = "Y4" ; #KL: changed the name from sys_clk_p
|
||||
NET "pcie_sys_clk_n" LOC = "Y3" ; #KL: changed the name from sys_clk_n
|
||||
INST "refclk_ibuf" DIFF_TERM = "TRUE" ;
|
||||
|
||||
#
|
||||
# Transceiver instance placement. This constraint selects the
|
||||
# transceivers to be used, which also dictates the pinout for the
|
||||
# transmit and receive differential pairs. Please refer to the
|
||||
# Virtex-5 GTP Transceiver User Guide (UG196) for more
|
||||
# information.
|
||||
#
|
||||
#KL: changed the ordering of the GTP LOCs to match the ML555
|
||||
# PCIe Lanes 0, 1
|
||||
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTP_DUAL_X0Y3;
|
||||
|
||||
# PCIe Lanes 2, 3
|
||||
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" LOC = GTP_DUAL_X0Y2;
|
||||
|
||||
# PCIe Lanes 4, 5
|
||||
#INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i" LOC = GTP_DUAL_X0Y1;
|
||||
|
||||
# PCIe Lanes 6, 7
|
||||
#INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i" LOC = GTP_DUAL_X0Y0;
|
||||
|
||||
###############################################################################
|
||||
# Physical Constraints
|
||||
###############################################################################
|
||||
#
|
||||
# BlockRAM placement
|
||||
#
|
||||
INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X1Y9 ;
|
||||
INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X1Y8 ;
|
||||
INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X1Y7 ;
|
||||
INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X1Y6 ;
|
||||
INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst" LOC = RAMB36_X1Y5 ;
|
||||
|
||||
#
|
||||
# Timing critical placements
|
||||
#
|
||||
INST "ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/tx_bridge/tx_bridge/shift_pipe1" LOC = "SLICE_X59Y36" ;
|
||||
INST "ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/completion_available" LOC = "SLICE_X58Y26" ;
|
||||
INST "ep/BU2/U0/pcie_ep0/pcie_blk_if/cf_bridge/management_interface/mgmt_rdata_d1_3" LOC = "SLICE_X59Y25" ;
|
||||
|
||||
###############################################################################
|
||||
# Timing Constraints
|
||||
###############################################################################
|
||||
#
|
||||
# Timing requirements and related constraints.
|
||||
#
|
||||
NET "sys_clk_c" PERIOD = 10ns;
|
||||
|
||||
NET "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_refclk_out[0]" TNM_NET = "MGTCLK" ;
|
||||
|
||||
TIMESPEC "TS_MGTCLK" = PERIOD "MGTCLK" 100.00 MHz HIGH 50 % ;
|
||||
|
||||
###############################################################################
|
||||
# End of contraints from Endpoint Block Plus
|
||||
###############################################################################
|
||||
###################################################
|
||||
## Additional Timing Constraints
|
||||
###################################################
|
||||
## SYS_CLK is the DDR2 clock - 200 MHz
|
||||
#NET "ddr2_cntrl_inst/u_infrastructure/sys_clk_ibufg" TNM_NET = "SYS_CLK";
|
||||
NET "ddr2_cntrl_inst/u_infrastructure/sys_clk" TNM_NET = "SYS_CLK";
|
||||
#TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 5 ns HIGH 50 %;
|
||||
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 7.5 ns HIGH 50 %;
|
||||
## SYS_CLK_200 is for the idelay - 200 MHz
|
||||
NET "ddr2_cntrl_inst/u_infrastructure/clk200_ibufg" TNM_NET = "SYS_CLK_200";
|
||||
TIMESPEC "TS_SYS_CLK_200" = PERIOD "SYS_CLK_200" 5 ns HIGH 50 %;
|
||||
#TIMESPEC "TS_SYS_CLK_200" = PERIOD "SYS_CLK_200" 7.5 ns HIGH 50 %;
|
||||
|
||||
# timing constrain for radio
|
||||
NET "WARP_radio_module_inst/data_clk" TNM_NET = "RADIO_DATA_CLK";
|
||||
TIMESPEC "TS_RADIO_DATA_CLK" = PERIOD "RADIO_DATA_CLK" 20ns HIGH 50%;
|
||||
|
||||
## timing constrain for Sora_radio_interpretation, needed if abstrated radio registers are used
|
||||
#NET "Sora_Radio_Interpretation_for_WARP_inst/clk" TNM_NET = "SORA_RADIO_INTERPRETATION_CLK";
|
||||
#TIMESPEC "TS_SORA_RADIO_INTERPRETATION_CLK" = PERIOD "SORA_RADIO_INTERPRETATION_CLK" 20ns HIGH 50%;
|
||||
#
|
||||
## timing constrain for Channel_radio_interpretation, needed if abstrated radio registers are used
|
||||
#NET "Channel_Radio_Interpretation_for_WARP_inst/clk" TNM_NET = "Channel_RADIO_INTERPRETATION_CLK";
|
||||
#TIMESPEC "TS_Channel_RADIO_INTERPRETATION_CLK" = PERIOD "Channel_RADIO_INTERPRETATION_CLK" 20ns HIGH 50%;
|
||||
|
||||
# timing constrain for spi
|
||||
NET "WARP_radio_module_inst/spi_clk" TNM_NET = "RADIO_SPI_CLK";
|
||||
TIMESPEC "TS_RADIO_SPI_CLK" = PERIOD "RADIO_SPI_CLK" 80ns HIGH 50%;
|
||||
|
||||
# timing constrain for posted packet scheduler
|
||||
NET "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_inst/clk" TNM_NET = "POSTED_CLK";
|
||||
TIMESPEC "TS_POSTED_CLK" = PERIOD "POSTED_CLK" 8ns HIGH 50%;
|
||||
|
||||
# timing constrain for pcie_dma_wrapper
|
||||
NET "pcie_dma_wrapper_inst/clk" TNM_NET = "PCIE_DMA_CLK";
|
||||
TIMESPEC "TS_PCIE_DMA_CLK" = PERIOD "PCIE_DMA_CLK" 8ns HIGH 50%;
|
||||
|
||||
## Multi-cycle paths
|
||||
#Multi-cycle paths for tx_trn_sm adder/subtractor
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/rx_trn_monitor_inst/dma*_div8_reg*" TNM=FFS "TNM_DMARDIV8_REG_SRC";
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/rx_trn_monitor_inst/dma*_div8_now*" TNM=FFS "TNM_DMARDIV8_NOW_SRC";
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/rx_trn_monitor_inst/addsub_state*" TNM=FFS "TNM_RADDSUB_STATE_SRC";
|
||||
TIMEGRP "DMARDIV8_2X_SRC" = "TNM_DMARDIV8_REG_SRC" "TNM_DMARDIV8_NOW_SRC" "TNM_RADDSUB_STATE_SRC";
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/rx_trn_monitor_inst/dma*_div8_reg_new*" TNM=FFS "TNM_DMARDIV8_REGNEW_DEST";
|
||||
TIMESPEC "TS_DMARDIV8_2X" = FROM "DMARDIV8_2X_SRC" TO "TNM_DMARDIV8_REGNEW_DEST" "TS_MGTCLK"*1.25; ## 2/5 for 250MHz * 2 for multicycle
|
||||
|
||||
#Multi-cycle paths for tx_trn_sm adder/subtractor
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/tx_trn_sm_inst/dma*_div8_reg*" TNM=FFS "TNM_DMAWDIV8_REG_SRC";
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/tx_trn_sm_inst/dma*_div8_now*" TNM=FFS "TNM_DMAWDIV8_NOW_SRC";
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/tx_trn_sm_inst/addsub_state*" TNM=FFS "TNM_WADDSUB_STATE_SRC";
|
||||
##TIMEGRP "DMAWDIV8_2X_SRC" = "TNM_DMAWDIV8_REG_SRC" "TNM_DMAWDIV8_NOW_SRC" "TNM_WADDSUB_STATE_SRC";
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/tx_trn_sm_inst/dma*_div8_reg_new*" TNM=FFS "TNM_DMAWDIV8_REGNEW_DEST";
|
||||
##TIMESPEC "TS_DMAWDIV8_2X" = FROM "DMAWDIV8_2X_SRC" TO "TNM_DMAWDIV8_REGNEW_DEST" "TS_MGTCLK"*1.25; ## 2/5 for 250MHz * 2 for multicycle
|
||||
|
||||
#Multi-cycle paths for posted slicer adder
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/posted_pkt_gen_inst/posted_pkt_slicer_inst/four_kb_xfer*" TNM=FFS "TNM_PFKB_SRC";
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/posted_pkt_gen_inst/posted_pkt_slicer_inst/dma*_reg*" TNM=FFS "TNM_PDMAREG_SRC";
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/posted_pkt_gen_inst/posted_pkt_slicer_inst/state*" TNM=FFS "TNM_PSTATE_SRC";
|
||||
##TIMEGRP "POSTED_2X_SRC" = "TNM_PFKB_SRC" "TNM_PDMAREG_SRC" "TNM_PSTATE_SRC";
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/posted_pkt_gen_inst/posted_pkt_slicer_inst/dma*_new*" TNM=FFS "TNM_PDMANEW_DEST";
|
||||
##TIMESPEC "TS_POSTED_2X" = FROM "POSTED_2X_SRC" TO "TNM_PDMANEW_DEST" "TS_MGTCLK"*1.25; ## 2/5 for 250MHz * 2 for multicycle
|
||||
|
||||
#Multi-cycle paths for non-posted slicer adder
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/four_kb_xfer*" TNM=FFS "TNM_NFKB_SRC";
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/dma*_reg*" TNM=FFS "TNM_NDMAREG_SRC";
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/state*" TNM=FFS "TNM_NSTATE_SRC";
|
||||
##TIMEGRP "NONPOSTED_2X_SRC" = "TNM_NFKB_SRC" "TNM_NDMAREG_SRC" "TNM_NSTATE_SRC";
|
||||
##INST "pcie_dma_wrapper_inst/tx_engine_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/dma*_new*" TNM=FFS "TNM_NDMANEW_DEST";
|
||||
##TIMESPEC "TS_NONPOSTED_2X" = FROM "NONPOSTED_2X_SRC" TO "TNM_NDMANEW_DEST" "TS_MGTCLK"*1.25; ## 2/5 for 250MHz * 2 for multicycle
|
||||
INST "pcie_dma_wrapper_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/four_kb_xfer*" TNM=FFS "TNM_NFKB_SRC";
|
||||
INST "pcie_dma_wrapper_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/dma*_reg*" TNM=FFS "TNM_NDMAREG_SRC";
|
||||
INST "pcie_dma_wrapper_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/state*" TNM=FFS "TNM_NSTATE_SRC";
|
||||
TIMEGRP "NONPOSTED_2X_SRC" = "TNM_NFKB_SRC" "TNM_NDMAREG_SRC" "TNM_NSTATE_SRC";
|
||||
INST "pcie_dma_wrapper_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/dma*_new*" TNM=FFS "TNM_NDMANEW_DEST";
|
||||
TIMESPEC "TS_NONPOSTED_2X" = FROM "NONPOSTED_2X_SRC" TO "TNM_NDMANEW_DEST" "TS_MGTCLK"*1.25; ## 2/5 for 250MHz * 2 for multicycle
|
||||
|
||||
# Multi-cycle paths for large xfers shim adder
|
||||
##INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/state_1*" TNM=FFS "TNM_STATE_1_SRC";
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/state_3*" TNM=FFS "TNM_STATE_3_SRC";
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/dma*_now*" TNM=FFS "TNM_DMANOW_SRC";
|
||||
##TIMEGRP "LARGE_XFER_2X_SRC" = "TNM_STATE_1_SRC" "TNM_STATE_3_SRC" "TNM_DMANOW_SRC";
|
||||
TIMEGRP "LARGE_XFER_2X_SRC" = "TNM_STATE_3_SRC" "TNM_DMANOW_SRC";
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/dma*_next*" TNM=FFS "TNM_DMANEXT_DEST";
|
||||
TIMESPEC "TS_DMAREG_DMANEXT" = FROM "LARGE_XFER_2X_SRC" TO "TNM_DMANEXT_DEST" "TS_MGTCLK"*1.25; ## 2/5 for 250MHz * 2 for multicycle
|
||||
|
||||
# Jiansong: added
|
||||
# Multi-cycle paths for large xfers shim adder
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/TX_state_1*" TNM=FFS "TNM_TX_STATE_1_SRC";
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/TX_*_now*" TNM=FFS "TNM_TXNOW_SRC";
|
||||
TIMEGRP "TX_LARGE_XFER_2X_SRC" = "TNM_TX_STATE_1_SRC" "TNM_TXNOW_SRC";
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/TX_*_next*" TNM=FFS "TNM_TXNEXT_DEST";
|
||||
TIMESPEC "TS_TXREG_TXNEXT" = FROM "TX_LARGE_XFER_2X_SRC" TO "TNM_TXNEXT_DEST" "TS_MGTCLK"*1.25; ## 2/5 for 250MHz * 2 for multicycle
|
||||
|
||||
# Jiansong: added for poset_packet_scheduler
|
||||
# Multi-cycle paths for posted scheduler adder
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_inst/RXBuf*" TNM=FFS "TNM_NRXB_SRC";
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_inst/dmawad_now*" TNM=FFS "TNM_NDWNW_SRC";
|
||||
TIMEGRP "POSTED_2X_SRC" = "TNM_NRXB_SRC" "TNM_NDWNW_SRC";
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_inst/dmawad_next*" TNM=FFS "TNM_NDWNT_DEST";
|
||||
TIMESPEC "TS_POSTED_2X" = FROM "POSTED_2X_SRC" TO "TNM_NDWNT_DEST" "TS_MGTCLK"*1.25; ## 2/5 for 250MHz * 2 for multicycle
|
||||
|
||||
#Tig'ed nets - these are static signals
|
||||
NET "trn_lnk_up_n_c" TIG;
|
||||
NET "phy_init_initialization_done" TIG;
|
||||
|
||||
INST "max_read_req_reg*" TIG;
|
||||
INST "max_pay_size_reg*" TIG;
|
||||
INST "pcie_id_reg*" TIG;
|
||||
|
||||
################################################################################
|
||||
# PIN Location and I/O STANDARDS
|
||||
################################################################################
|
||||
################################################################################
|
||||
##
|
||||
## Global Clock inputs
|
||||
## FPGA Bank 3: Vcco = 2.5 Volts
|
||||
##
|
||||
## Note: Use DIFF_TERM attribute on LVDS clock inputs as the ML555 DOES NOT
|
||||
## provide 100 ohm terminators on the circuit board assembly
|
||||
################################################################################
|
||||
NET CLK200_P LOC = J16 | DIFF_TERM = TRUE; ## ICS1 PLL LVDS
|
||||
NET CLK200_N LOC = J17 | DIFF_TERM = TRUE;
|
||||
NET "SYS_CLK_P" LOC = H14 | DIFF_TERM = TRUE; ## ICS2 PLL LVDS
|
||||
NET "SYS_CLK_N" LOC = H15 | DIFF_TERM = TRUE;
|
||||
|
||||
# LEDs
|
||||
# Indicates that the PCIe endpoint has successfully completed link training
|
||||
# with the downstream port connected to it
|
||||
#NET "LED_link_up_and_phy_init_initialization_done_n" LOC = L21 | IOSTANDARD = "LVCMOS33";
|
||||
#NET "Radio_LO_Lock_n" LOC = L20 | IOSTANDARD = "LVCMOS33";
|
||||
NET "phy_init_initialization_done_n" LOC = L21 | IOSTANDARD = "LVCMOS33";
|
||||
NET "LED_link_up_n" LOC = L20 | IOSTANDARD = "LVCMOS33";
|
||||
NET "Radio_RX_blink" LOC = L15 | IOSTANDARD = "LVCMOS33";
|
||||
NET "Radio_TX_n" LOC = L16 | IOSTANDARD = "LVCMOS33";
|
||||
#NET "RXEnable_n" LOC = L21 | IOSTANDARD = "LVCMOS33";
|
||||
#NET "LED_clock" LOC = L15 | IOSTANDARD = "LVCMOS33";
|
||||
#NET "LED_clock_1" LOC = L16 | IOSTANDARD = "LVCMOS33";
|
||||
|
||||
#INST "RXEnable_n_OBUF" DRIVE = 24;
|
||||
#INST "LED_link_up_and_phy_init_initialization_done_n_OBUF" DRIVE = 24;
|
||||
#INST "Radio_LO_Lock_n_OBUF" DRIVE = 24;
|
||||
INST "LED_link_up_n_OBUF" DRIVE = 24;
|
||||
INST "DDR2_phy_init_n_OBUF" DRIVE = 24;
|
||||
INST "Radio_RX_blink_OBUF" DRIVE = 24;
|
||||
INST "Radio_TX_n_OBUF" DRIVE = 24;
|
||||
#INST "LED_clock_OBUF" DRIVE = 24;
|
||||
#INST "LED_clock_1_OBUF" DRIVE = 24;
|
||||
|
||||
#Clock ICS load
|
||||
NET "nPLOAD_1" LOC = "K12" | IOSTANDARD = "LVCMOS33";
|
||||
NET "nPLOAD_2" LOC = "K23" | IOSTANDARD = "LVCMOS33";
|
||||
|
||||
NET "RF_DAC_SPI_SDO" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_DAC_SPI_SDI" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_DAC_SPI_CLK" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_DAC_SPI_CSB" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_DAC_RESET" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_DAC_I_DATA[*]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_DAC_Q_DATA[*]" IOSTANDARD = LVCMOS25;
|
||||
#NET "RF_DAC_I_DATA[7]" IOSTANDARD = LVCMOS25;
|
||||
#NET "RF_DAC_I_DATA[0]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_I_DATA[1]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_I_DATA[2]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_I_DATA[3]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_I_DATA[4]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_I_DATA[5]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_I_DATA[6]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_I_DATA[8]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_I_DATA[9]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_I_DATA[10]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_I_DATA[11]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_I_DATA[12]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_I_DATA[13]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_I_DATA[14]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_I_DATA[15]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_Q_DATA[2]" IOSTANDARD = LVCMOS25;
|
||||
#NET "RF_DAC_Q_DATA[10]" IOSTANDARD = LVCMOS25;
|
||||
#NET "RF_DAC_Q_DATA[0]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_Q_DATA[1]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_Q_DATA[3]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_Q_DATA[4]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_Q_DATA[5]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_Q_DATA[6]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_Q_DATA[7]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_Q_DATA[8]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_Q_DATA[9]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_Q_DATA[11]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_Q_DATA[12]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_Q_DATA[13]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_Q_DATA[14]" IOSTANDARD = LVCMOS33;
|
||||
#NET "RF_DAC_Q_DATA[15]" IOSTANDARD = LVCMOS33;
|
||||
NET "RF_DAC_PLLLOCK" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_RSSI_SLEEP" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_RSSI_OTR" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_RSSI_HIZ" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_RSSI_CLK" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_RSSI_CLAMP" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_RSSI_DATA[*]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_RADIO_TXEN" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_RADIO_RXEN" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_RADIO_SHDN_N" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_RADIO_RXHP" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_RADIO_SPI_SDI" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_RADIO_SPI_CSB" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_RADIO_SPI_CLK" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_RADIO_GAIN[*]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_RADIO_LD" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_PWDNA" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_PWDNB" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_OTRA" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_OTRB" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DFS" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DCS" IOSTANDARD = LVCMOS25;
|
||||
#NET "RF_ADC_DATA_A[*]" IOSTANDARD = LVCMOS25;
|
||||
#NET "RF_ADC_DATA_B[*]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_A[5]" IOSTANDARD = LVCMOS25; # must be LVCMOS25
|
||||
NET "RF_ADC_DATA_A[0]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_A[1]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_A[2]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_A[3]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_A[4]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_A[6]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_A[7]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_A[8]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_A[9]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_A[10]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_A[11]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_A[12]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_A[13]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_B[5]" IOSTANDARD = LVCMOS25; # must be LVCMOS25
|
||||
NET "RF_ADC_DATA_B[0]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_B[1]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_B[2]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_B[3]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_B[4]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_B[6]" IOSTANDARD = LVCMOS33; # must be LVCMOS33
|
||||
NET "RF_ADC_DATA_B[7]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_B[8]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_B[9]" IOSTANDARD = LVCMOS33; # must be LVCMOS33
|
||||
NET "RF_ADC_DATA_B[10]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_B[11]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_B[12]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_ADC_DATA_B[13]" IOSTANDARD = LVCMOS25;
|
||||
#NET "RF_DIPSW[*]" IOSTANDARD = LVCMOS33;
|
||||
NET "RF_LED[*]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_CLK_N" IOSTANDARD = LVCMOS25; # single channel clock
|
||||
NET "RF_CLK_P" IOSTANDARD = LVCMOS25;
|
||||
#NET "RF_CLK_N" IOSTANDARD = LVDS_25; # differential clock
|
||||
#NET "RF_CLK_P" IOSTANDARD = LVDS_25;
|
||||
NET "RF_ANTSW[*]" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_5PA_EN_N" IOSTANDARD = LVCMOS25;
|
||||
NET "RF_24PA_EN_N" IOSTANDARD = LVCMOS25;
|
||||
|
||||
### these warp gpios allocation is different on RCBv1.0 and RCBv1.1.3
|
||||
#### WARP on RCB v1.0 ###
|
||||
#NET "RF_DAC_SPI_SDO" LOC = "P32";
|
||||
#NET "RF_DAC_SPI_SDI" LOC = "L34";
|
||||
#NET "RF_DAC_SPI_CLK" LOC = "H34";
|
||||
#NET "RF_DAC_SPI_CSB" LOC = "U30";
|
||||
#NET "RF_DAC_RESET" LOC = "H30";
|
||||
#NET "RF_DAC_Q_DATA[15]" LOC = "G6";
|
||||
#NET "RF_DAC_Q_DATA[14]" LOC = "E6";
|
||||
#NET "RF_DAC_Q_DATA[13]" LOC = "F5";
|
||||
#NET "RF_DAC_Q_DATA[12]" LOC = "M7";
|
||||
#NET "RF_DAC_Q_DATA[11]" LOC = "H7";
|
||||
#NET "RF_DAC_Q_DATA[10]" LOC = "T9";
|
||||
#NET "RF_DAC_Q_DATA[9]" LOC = "T10";
|
||||
#NET "RF_DAC_Q_DATA[8]" LOC = "R11";
|
||||
#NET "RF_DAC_Q_DATA[7]" LOC = "R9";
|
||||
#NET "RF_DAC_Q_DATA[6]" LOC = "T8";
|
||||
#NET "RF_DAC_Q_DATA[5]" LOC = "N8";
|
||||
#NET "RF_DAC_Q_DATA[4]" LOC = "R7";
|
||||
#NET "RF_DAC_Q_DATA[3]" LOC = "U32";
|
||||
#NET "RF_DAC_Q_DATA[2]" LOC = "T33";
|
||||
#NET "RF_DAC_Q_DATA[1]" LOC = "P34";
|
||||
#NET "RF_DAC_Q_DATA[0]" LOC = "R33";
|
||||
#NET "RF_DAC_PLLLOCK" LOC = "H5";
|
||||
#NET "RF_DAC_I_DATA[15]" LOC = "J6";
|
||||
#NET "RF_DAC_I_DATA[14]" LOC = "G8";
|
||||
#NET "RF_DAC_I_DATA[13]" LOC = "F9";
|
||||
#NET "RF_DAC_I_DATA[12]" LOC = "E9";
|
||||
#NET "RF_DAC_I_DATA[11]" LOC = "F10";
|
||||
#NET "RF_DAC_I_DATA[10]" LOC = "F11";
|
||||
#NET "RF_DAC_I_DATA[9]" LOC = "G11";
|
||||
#NET "RF_DAC_I_DATA[8]" LOC = "B13";
|
||||
#NET "RF_DAC_I_DATA[7]" LOC = "D12";
|
||||
#NET "RF_DAC_I_DATA[6]" LOC = "H10";
|
||||
#NET "RF_DAC_I_DATA[5]" LOC = "J10";
|
||||
#NET "RF_DAC_I_DATA[4]" LOC = "K11";
|
||||
#NET "RF_DAC_I_DATA[3]" LOC = "L10";
|
||||
#NET "RF_DAC_I_DATA[2]" LOC = "M8";
|
||||
#NET "RF_DAC_I_DATA[1]" LOC = "D11";
|
||||
#NET "RF_DAC_I_DATA[0]" LOC = "A13";
|
||||
#NET "RF_RSSI_SLEEP" LOC = "G32";
|
||||
#NET "RF_RSSI_OTR" LOC = "K31";
|
||||
#NET "RF_RSSI_HIZ" LOC = "E32";
|
||||
#NET "RF_RSSI_DATA[9]" LOC = "L33";
|
||||
#NET "RF_RSSI_DATA[8]" LOC = "N33";
|
||||
#NET "RF_RSSI_DATA[7]" LOC = "K33";
|
||||
#NET "RF_RSSI_DATA[6]" LOC = "G33";
|
||||
#NET "RF_RSSI_DATA[5]" LOC = "C32";
|
||||
#NET "RF_RSSI_DATA[4]" LOC = "B32";
|
||||
#NET "RF_RSSI_DATA[3]" LOC = "B33";
|
||||
#NET "RF_RSSI_DATA[2]" LOC = "C34";
|
||||
##NET "RF_RSSI_DATA[1]" LOC = "K18"; //disable this pin, it's a PCB bug, voltage for this bank is 2.5v when this IO requires 3.3V
|
||||
#NET "RF_RSSI_DATA[0]" LOC = "F33";
|
||||
#NET "RF_RSSI_CLK" LOC = "P31";
|
||||
#NET "RF_RSSI_CLAMP" LOC = "J32";
|
||||
#NET "RF_RADIO_TXEN" LOC = "N29";
|
||||
#NET "RF_RADIO_RXEN" LOC = "J30";
|
||||
#NET "RF_RADIO_SHDN_N" LOC = "L30";
|
||||
#NET "RF_RADIO_RXHP" LOC = "E29";
|
||||
#NET "RF_RADIO_SPI_SDI" LOC = "L29";
|
||||
#NET "RF_RADIO_SPI_CSB" LOC = "F31";
|
||||
#NET "RF_RADIO_SPI_CLK" LOC = "R28";
|
||||
#NET "RF_RADIO_LD" LOC = "G30";
|
||||
#NET "RF_RADIO_GAIN[6]" LOC = "M28";
|
||||
#NET "RF_RADIO_GAIN[5]" LOC = "K28";
|
||||
#NET "RF_RADIO_GAIN[4]" LOC = "AD32";
|
||||
#NET "RF_RADIO_GAIN[3]" LOC = "U33";
|
||||
#NET "RF_RADIO_GAIN[2]" LOC = "V32";
|
||||
#NET "RF_RADIO_GAIN[1]" LOC = "W34";
|
||||
#NET "RF_RADIO_GAIN[0]" LOC = "Y32";
|
||||
#NET "RF_LED[2]" LOC = "AN32";
|
||||
#NET "RF_LED[1]" LOC = "AN34";
|
||||
#NET "RF_LED[0]" LOC = "AM33";
|
||||
#NET "RF_CLK_N" LOC = "W9";
|
||||
#NET "RF_CLK_P" LOC = "W10";
|
||||
##NET "RF_DIPSW[3]" LOC = "";
|
||||
##NET "RF_DIPSW[2]" LOC = "";
|
||||
##NET "RF_DIPSW[1]" LOC = "";
|
||||
##NET "RF_DIPSW[0]" LOC = "";
|
||||
#NET "RF_ANTSW[1]" LOC = "AH34";
|
||||
#NET "RF_ANTSW[0]" LOC = "AJ32";
|
||||
#NET "RF_ADC_PWDNA" LOC = "AF33";
|
||||
#NET "RF_ADC_PWDNB" LOC = "P7";
|
||||
#NET "RF_ADC_OTRA" LOC = "AC32";
|
||||
#NET "RF_ADC_OTRB" LOC = "AA6";
|
||||
#NET "RF_ADC_DFS" LOC = "T31";
|
||||
#NET "RF_ADC_DCS" LOC = "T28";
|
||||
#NET "RF_ADC_DATA_B[13]" LOC = "AJ7";
|
||||
#NET "RF_ADC_DATA_B[12]" LOC = "AC7";
|
||||
#NET "RF_ADC_DATA_B[11]" LOC = "AD6";
|
||||
#NET "RF_ADC_DATA_B[10]" LOC = "Y11";
|
||||
#NET "RF_ADC_DATA_B[9]" LOC = "AB6";
|
||||
#NET "RF_ADC_DATA_B[8]" LOC = "AK7";
|
||||
#NET "RF_ADC_DATA_B[7]" LOC = "V10";
|
||||
#NET "RF_ADC_DATA_B[6]" LOC = "AE7";
|
||||
#NET "RF_ADC_DATA_B[5]" LOC = "V8";
|
||||
#NET "RF_ADC_DATA_B[4]" LOC = "K7";
|
||||
#NET "RF_ADC_DATA_B[3]" LOC = "M6";
|
||||
#NET "RF_ADC_DATA_B[2]" LOC = "L4";
|
||||
#NET "RF_ADC_DATA_B[1]" LOC = "N5";
|
||||
#NET "RF_ADC_DATA_B[0]" LOC = "R6";
|
||||
#NET "RF_ADC_DATA_A[13]" LOC = "AC33";
|
||||
#NET "RF_ADC_DATA_A[12]" LOC = "AC34";
|
||||
#NET "RF_ADC_DATA_A[11]" LOC = "AF34";
|
||||
#NET "RF_ADC_DATA_A[10]" LOC = "AG32";
|
||||
#NET "RF_ADC_DATA_A[9]" LOC = "AG33";
|
||||
#NET "RF_ADC_DATA_A[8]" LOC = "W7";
|
||||
#NET "RF_ADC_DATA_A[7]" LOC = "Y8";
|
||||
#NET "RF_ADC_DATA_A[6]" LOC = "AH5";
|
||||
#NET "RF_ADC_DATA_A[5]" LOC = "AD4";
|
||||
#NET "RF_ADC_DATA_A[4]" LOC = "AA5";
|
||||
#NET "RF_ADC_DATA_A[3]" LOC = "W6";
|
||||
#NET "RF_ADC_DATA_A[2]" LOC = "AC4";
|
||||
#NET "RF_ADC_DATA_A[1]" LOC = "AG5";
|
||||
#NET "RF_ADC_DATA_A[0]" LOC = "K8";
|
||||
#NET "RF_5PA_EN_N" LOC = "AL34";
|
||||
#NET "RF_24PA_EN_N" LOC = "AK34";
|
||||
|
||||
### WARP on RCB v1.1.3 ###
|
||||
NET "RF_DAC_SPI_SDO" LOC = "T34";
|
||||
NET "RF_DAC_SPI_SDI" LOC = "V33";
|
||||
NET "RF_DAC_SPI_CLK" LOC = "V34";
|
||||
NET "RF_DAC_SPI_CSB" LOC = "W32";
|
||||
NET "RF_DAC_RESET" LOC = "P30";
|
||||
NET "RF_DAC_Q_DATA[15]" LOC = "E11";
|
||||
NET "RF_DAC_Q_DATA[14]" LOC = "G10";
|
||||
NET "RF_DAC_Q_DATA[13]" LOC = "E8";
|
||||
NET "RF_DAC_Q_DATA[12]" LOC = "F8";
|
||||
NET "RF_DAC_Q_DATA[11]" LOC = "H8";
|
||||
NET "RF_DAC_Q_DATA[10]" LOC = "H13"; ### FPGA 2.5V out to DAC 3.3V input pin, it should work
|
||||
NET "RF_DAC_Q_DATA[9]" LOC = "L8";
|
||||
NET "RF_DAC_Q_DATA[8]" LOC = "L11";
|
||||
NET "RF_DAC_Q_DATA[7]" LOC = "J11";
|
||||
NET "RF_DAC_Q_DATA[6]" LOC = "H9";
|
||||
NET "RF_DAC_Q_DATA[5]" LOC = "C12";
|
||||
NET "RF_DAC_Q_DATA[4]" LOC = "J9";
|
||||
NET "RF_DAC_Q_DATA[3]" LOC = "C13";
|
||||
NET "RF_DAC_Q_DATA[2]" LOC = "J21"; ### FPGA 2.5V out to DAC 3.3V input pin, it should work
|
||||
NET "RF_DAC_Q_DATA[1]" LOC = "L28";
|
||||
NET "RF_DAC_Q_DATA[0]" LOC = "AE32";
|
||||
NET "RF_DAC_PLLLOCK" LOC = "G12";
|
||||
NET "RF_DAC_I_DATA[15]" LOC = "T29";
|
||||
NET "RF_DAC_I_DATA[14]" LOC = "R31";
|
||||
NET "RF_DAC_I_DATA[13]" LOC = "M33";
|
||||
NET "RF_DAC_I_DATA[12]" LOC = "M32";
|
||||
NET "RF_DAC_I_DATA[11]" LOC = "L31";
|
||||
NET "RF_DAC_I_DATA[10]" LOC = "K32";
|
||||
NET "RF_DAC_I_DATA[9]" LOC = "F34";
|
||||
NET "RF_DAC_I_DATA[8]" LOC = "E34";
|
||||
NET "RF_DAC_I_DATA[7]" LOC = "J19"; ### FPGA 2.5V out to DAC 3.3V input pin, it should work
|
||||
NET "RF_DAC_I_DATA[6]" LOC = "H33";
|
||||
NET "RF_DAC_I_DATA[5]" LOC = "H32";
|
||||
NET "RF_DAC_I_DATA[4]" LOC = "E33";
|
||||
NET "RF_DAC_I_DATA[3]" LOC = "D32";
|
||||
NET "RF_DAC_I_DATA[2]" LOC = "A33";
|
||||
NET "RF_DAC_I_DATA[1]" LOC = "C33";
|
||||
NET "RF_DAC_I_DATA[0]" LOC = "D34";
|
||||
#NET "RF_RSSI_SLEEP" LOC = ""; ### not connected
|
||||
#NET "RF_RSSI_OTR" LOC = ""; ### not connected
|
||||
#NET "RF_RSSI_HIZ" LOC = ""; ### not connected
|
||||
#NET "RF_RSSI_DATA[9]" LOC = ""; ### not connected
|
||||
#NET "RF_RSSI_DATA[8]" LOC = ""; ### not connected
|
||||
#NET "RF_RSSI_DATA[7]" LOC = ""; ### not connected
|
||||
#NET "RF_RSSI_DATA[6]" LOC = ""; ### not connected
|
||||
#NET "RF_RSSI_DATA[5]" LOC = ""; ### not connected
|
||||
#NET "RF_RSSI_DATA[4]" LOC = ""; ### not connected
|
||||
#NET "RF_RSSI_DATA[3]" LOC = ""; ### not connected
|
||||
#NET "RF_RSSI_DATA[2]" LOC = ""; ### not connected
|
||||
##NET "RF_RSSI_DATA[1]" LOC = ""; ### ADC 3.3V data out to FPGA 2.5V input pin, it should work
|
||||
#NET "RF_RSSI_DATA[0]" LOC = ""; ### not connected
|
||||
#NET "RF_RSSI_CLK" LOC = ""; ### not connected
|
||||
#NET "RF_RSSI_CLAMP" LOC = ""; ### not connected
|
||||
NET "RF_RADIO_TXEN" LOC = "M30";
|
||||
NET "RF_RADIO_RXEN" LOC = "T6";
|
||||
NET "RF_RADIO_SHDN_N" LOC = "P7";
|
||||
NET "RF_RADIO_RXHP" LOC = "R6";
|
||||
NET "RF_RADIO_SPI_SDI" LOC = "J31";
|
||||
NET "RF_RADIO_SPI_CSB" LOC = "J29";
|
||||
NET "RF_RADIO_SPI_CLK" LOC = "F29";
|
||||
NET "RF_RADIO_LD" LOC = "P31";
|
||||
NET "RF_RADIO_GAIN[6]" LOC = "K7";
|
||||
NET "RF_RADIO_GAIN[5]" LOC = "K6";
|
||||
NET "RF_RADIO_GAIN[4]" LOC = "M6";
|
||||
NET "RF_RADIO_GAIN[3]" LOC = "M5";
|
||||
NET "RF_RADIO_GAIN[2]" LOC = "L4";
|
||||
NET "RF_RADIO_GAIN[1]" LOC = "L5";
|
||||
NET "RF_RADIO_GAIN[0]" LOC = "N5";
|
||||
NET "RF_LED[2]" LOC = "H27";
|
||||
NET "RF_LED[1]" LOC = "E26";
|
||||
NET "RF_LED[0]" LOC = "E27";
|
||||
NET "RF_CLK_N" LOC = "W9";
|
||||
NET "RF_CLK_P" LOC = "W10";
|
||||
#NET "RF_DIPSW[3]" LOC = "";
|
||||
#NET "RF_DIPSW[2]" LOC = "";
|
||||
#NET "RF_DIPSW[1]" LOC = "";
|
||||
#NET "RF_DIPSW[0]" LOC = "";
|
||||
NET "RF_ANTSW[1]" LOC = "G26";
|
||||
NET "RF_ANTSW[0]" LOC = "G25";
|
||||
NET "RF_ADC_PWDNA" LOC = "H25";
|
||||
NET "RF_ADC_PWDNB" LOC = "J7";
|
||||
NET "RF_ADC_OTRA" LOC = "H24";
|
||||
NET "RF_ADC_OTRB" LOC = "G28";
|
||||
NET "RF_ADC_DFS" LOC = "H7";
|
||||
NET "RF_ADC_DCS" LOC = "P6";
|
||||
NET "RF_ADC_DATA_B[13]" LOC = "U28";
|
||||
NET "RF_ADC_DATA_B[12]" LOC = "T24";
|
||||
NET "RF_ADC_DATA_B[11]" LOC = "K26";
|
||||
NET "RF_ADC_DATA_B[10]" LOC = "J26";
|
||||
NET "RF_ADC_DATA_B[9]" LOC = "K14";
|
||||
NET "RF_ADC_DATA_B[8]" LOC = "R27";
|
||||
NET "RF_ADC_DATA_B[7]" LOC = "F28";
|
||||
NET "RF_ADC_DATA_B[6]" LOC = "H22";
|
||||
NET "RF_ADC_DATA_B[5]" LOC = "G16"; ### ADC 3.3V data out to FPGA 2.5V input pin, it should work
|
||||
NET "RF_ADC_DATA_B[4]" LOC = "AJ6";
|
||||
NET "RF_ADC_DATA_B[3]" LOC = "AG7";
|
||||
NET "RF_ADC_DATA_B[2]" LOC = "U8";
|
||||
NET "RF_ADC_DATA_B[1]" LOC = "AF6";
|
||||
NET "RF_ADC_DATA_B[0]" LOC = "V9";
|
||||
NET "RF_ADC_DATA_A[13]" LOC = "J25";
|
||||
NET "RF_ADC_DATA_A[12]" LOC = "N30";
|
||||
NET "RF_ADC_DATA_A[11]" LOC = "M26";
|
||||
NET "RF_ADC_DATA_A[10]" LOC = "E13";
|
||||
NET "RF_ADC_DATA_A[9]" LOC = "G13";
|
||||
NET "RF_ADC_DATA_A[8]" LOC = "N9";
|
||||
NET "RF_ADC_DATA_A[7]" LOC = "L9";
|
||||
NET "RF_ADC_DATA_A[6]" LOC = "P24";
|
||||
NET "RF_ADC_DATA_A[5]" LOC = "L18"; ### ADC 3.3V data out to FPGA 2.5V input pin, it should work
|
||||
NET "RF_ADC_DATA_A[4]" LOC = "M27";
|
||||
NET "RF_ADC_DATA_A[3]" LOC = "P27";
|
||||
NET "RF_ADC_DATA_A[2]" LOC = "N25";
|
||||
NET "RF_ADC_DATA_A[1]" LOC = "T25";
|
||||
NET "RF_ADC_DATA_A[0]" LOC = "T26";
|
||||
NET "RF_5PA_EN_N" LOC = "F25";
|
||||
NET "RF_24PA_EN_N" LOC = "F26";
|
||||
|
||||
################################################################################
|
||||
# I/O STANDARDS for DDR2
|
||||
################################################################################
|
||||
NET "DDR2_DQ[*]" IOSTANDARD = SSTL18_II;
|
||||
NET "DDR2_A[*]" IOSTANDARD = SSTL18_II;
|
||||
NET "DDR2_BA[*]" IOSTANDARD = SSTL18_II;
|
||||
NET "DDR2_RAS_N" IOSTANDARD = SSTL18_II;
|
||||
NET "DDR2_CAS_N" IOSTANDARD = SSTL18_II;
|
||||
NET "DDR2_WE_N" IOSTANDARD = SSTL18_II;
|
||||
#NET "DDR2_RESET_N" IOSTANDARD = LVCMOS25;
|
||||
NET "DDR2_CS_N" IOSTANDARD = SSTL18_II;
|
||||
NET "DDR2_ODT" IOSTANDARD = SSTL18_II;
|
||||
NET "DDR2_CKE" IOSTANDARD = SSTL18_II;
|
||||
NET "DDR2_DM[*]" IOSTANDARD = SSTL18_II;
|
||||
NET "SYS_CLK_P" IOSTANDARD = LVDS_25;
|
||||
NET "SYS_CLK_N" IOSTANDARD = LVDS_25;
|
||||
NET "CLK200_P" IOSTANDARD = LVDS_25;
|
||||
NET "CLK200_N" IOSTANDARD = LVDS_25;
|
||||
NET "DDR2_DQS[*]" IOSTANDARD = DIFF_SSTL18_II_DCI;
|
||||
NET "DDR2_DQS_N[*]" IOSTANDARD = DIFF_SSTL18_II_DCI;
|
||||
NET "DDR2_CK[*]" IOSTANDARD = DIFF_SSTL18_II;
|
||||
NET "DDR2_CK_N[*]" IOSTANDARD = DIFF_SSTL18_II;
|
||||
|
||||
################################################################################
|
||||
# Location Constraints for DDR2
|
||||
################################################################################
|
||||
NET "DDR2_DQ[0]" LOC = "W24" ; #Bank 12
|
||||
NET "DDR2_DQ[1]" LOC = "V24" ; #Bank 12
|
||||
NET "DDR2_DQ[2]" LOC = "Y26" ; #Bank 12
|
||||
NET "DDR2_DQ[3]" LOC = "W26" ; #Bank 12
|
||||
NET "DDR2_DQ[4]" LOC = "V25" ; #Bank 12
|
||||
NET "DDR2_DQ[5]" LOC = "W25" ; #Bank 12
|
||||
NET "DDR2_DQ[6]" LOC = "Y27" ; #Bank 12
|
||||
NET "DDR2_DQ[7]" LOC = "W27" ; #Bank 12
|
||||
NET "DDR2_DQ[8]" LOC = "V28" ; #Bank 12
|
||||
NET "DDR2_DQ[9]" LOC = "V27" ; #Bank 12
|
||||
NET "DDR2_DQ[10]" LOC = "W31" ; #Bank 12
|
||||
NET "DDR2_DQ[11]" LOC = "Y31" ; #Bank 12
|
||||
NET "DDR2_DQ[12]" LOC = "W29" ; #Bank 12
|
||||
NET "DDR2_DQ[13]" LOC = "V29" ; #Bank 12
|
||||
NET "DDR2_DQ[14]" LOC = "Y28" ; #Bank 12
|
||||
NET "DDR2_DQ[15]" LOC = "Y29" ; #Bank 12
|
||||
NET "DDR2_DQ[16]" LOC = "AC29"; #Bank 12
|
||||
NET "DDR2_DQ[17]" LOC = "AF31"; #Bank 12
|
||||
NET "DDR2_DQ[18]" LOC = "AJ31"; #Bank 12
|
||||
NET "DDR2_DQ[19]" LOC = "AK31"; #Bank 12
|
||||
NET "DDR2_DQ[20]" LOC = "AF29"; #Bank 12
|
||||
NET "DDR2_DQ[21]" LOC = "AF30"; #Bank 12
|
||||
NET "DDR2_DQ[22]" LOC = "AJ30"; #Bank 12
|
||||
NET "DDR2_DQ[23]" LOC = "AH30"; #Bank 12
|
||||
NET "DDR2_DQ[24]" LOC = "AA25"; #Bank 18
|
||||
NET "DDR2_DQ[25]" LOC = "AA26"; #Bank 18
|
||||
NET "DDR2_DQ[26]" LOC = "AB27"; #Bank 18
|
||||
NET "DDR2_DQ[27]" LOC = "AC27"; #Bank 18
|
||||
NET "DDR2_DQ[28]" LOC = "Y24"; #Bank 18
|
||||
NET "DDR2_DQ[29]" LOC = "AA24"; #Bank 18
|
||||
NET "DDR2_DQ[30]" LOC = "AB25"; #Bank 18
|
||||
NET "DDR2_DQ[31]" LOC = "AB26"; #Bank 18
|
||||
NET "DDR2_DQ[32]" LOC = "AB28"; #Bank 18
|
||||
NET "DDR2_DQ[33]" LOC = "AA28"; #Bank 18
|
||||
NET "DDR2_DQ[34]" LOC = "AG28"; #Bank 18
|
||||
NET "DDR2_DQ[35]" LOC = "AH28"; #Bank 18
|
||||
NET "DDR2_DQ[36]" LOC = "AK26"; #Bank 18
|
||||
NET "DDR2_DQ[37]" LOC = "AF28"; #Bank 18
|
||||
NET "DDR2_DQ[38]" LOC = "AE28"; #Bank 18
|
||||
NET "DDR2_DQ[39]" LOC = "AJ27"; #Bank 18
|
||||
NET "DDR2_DQ[40]" LOC = "AG25"; #Bank 18
|
||||
NET "DDR2_DQ[41]" LOC = "AG27"; #Bank 18
|
||||
NET "DDR2_DQ[42]" LOC = "AE27"; #Bank 18
|
||||
NET "DDR2_DQ[43]" LOC = "AE26"; #Bank 18
|
||||
NET "DDR2_DQ[44]" LOC = "AC25"; #Bank 18
|
||||
NET "DDR2_DQ[45]" LOC = "AC24"; #Bank 18
|
||||
NET "DDR2_DQ[46]" LOC = "AD26"; #Bank 18
|
||||
NET "DDR2_DQ[47]" LOC = "AD25"; #Bank 18
|
||||
NET "DDR2_DQ[48]" LOC = "AN14"; #Bank 20
|
||||
NET "DDR2_DQ[49]" LOC = "AP14"; #Bank 20
|
||||
NET "DDR2_DQ[50]" LOC = "AB10"; #Bank 20
|
||||
NET "DDR2_DQ[51]" LOC = "AA10"; #Bank 20
|
||||
NET "DDR2_DQ[52]" LOC = "AN13"; #Bank 20
|
||||
NET "DDR2_DQ[53]" LOC = "AM13"; #Bank 20
|
||||
NET "DDR2_DQ[54]" LOC = "AA8"; #Bank 20
|
||||
NET "DDR2_DQ[55]" LOC = "AA9"; #Bank 20
|
||||
NET "DDR2_DQ[56]" LOC = "AC8"; #Bank 20
|
||||
NET "DDR2_DQ[57]" LOC = "AB8"; #Bank 20
|
||||
NET "DDR2_DQ[58]" LOC = "AM12"; #Bank 20
|
||||
NET "DDR2_DQ[59]" LOC = "AM11"; #Bank 20
|
||||
NET "DDR2_DQ[60]" LOC = "AC10"; #Bank 20
|
||||
NET "DDR2_DQ[61]" LOC = "AC9"; #Bank 20
|
||||
NET "DDR2_DQ[62]" LOC = "AK9"; #Bank 20
|
||||
NET "DDR2_DQ[63]" LOC = "AF9"; #Bank 20
|
||||
NET "DDR2_A[12]" LOC = "AH19"; #Bank 18
|
||||
NET "DDR2_A[11]" LOC = "AH20"; #Bank 18
|
||||
NET "DDR2_A[10]" LOC = "AG15"; #Bank 18
|
||||
NET "DDR2_A[9]" LOC = "AH15"; #Bank 20
|
||||
NET "DDR2_A[8]" LOC = "AG20"; #Bank 20
|
||||
NET "DDR2_A[7]" LOC = "AG16"; #Bank 20
|
||||
NET "DDR2_A[6]" LOC = "AH17"; #Bank 22
|
||||
NET "DDR2_A[5]" LOC = "AH22"; #Bank 22
|
||||
NET "DDR2_A[4]" LOC = "AG22"; #Bank 22
|
||||
NET "DDR2_A[3]" LOC = "AG17"; #Bank 22
|
||||
NET "DDR2_A[2]" LOC = "AH18"; #Bank 22
|
||||
NET "DDR2_A[1]" LOC = "AF18"; #Bank 22
|
||||
NET "DDR2_A[0]" LOC = "AE18"; #Bank 22
|
||||
NET "DDR2_BA[1]" LOC = "AH13"; #Bank 22
|
||||
NET "DDR2_BA[0]" LOC = "AH14"; #Bank 22
|
||||
NET "DDR2_RAS_N" LOC = "AG13"; #Bank 22
|
||||
NET "DDR2_CAS_N" LOC = "AH12"; #Bank 22
|
||||
NET "DDR2_WE_N" LOC = "AF19"; #Bank 22
|
||||
#NET "DDR2_RESET_N" LOC = "U7"; #Bank 22 output signal
|
||||
NET "DDR2_CS_N" LOC = "AG18"; #Bank 22
|
||||
NET "DDR2_ODT" LOC = "AG30"; #Bank 22
|
||||
NET "DDR2_CKE" LOC = "AG8"; #Bank 22
|
||||
NET "DDR2_DM[0]" LOC = "V30"; #Bank 12
|
||||
NET "DDR2_DM[1]" LOC = "AD30"; #Bank 12
|
||||
NET "DDR2_DM[2]" LOC = "AH29"; #Bank 12
|
||||
NET "DDR2_DM[3]" LOC = "AC28"; #Bank 18
|
||||
NET "DDR2_DM[4]" LOC = "AF24"; #Bank 18
|
||||
NET "DDR2_DM[5]" LOC = "AD24"; #Bank 18
|
||||
NET "DDR2_DM[6]" LOC = "AP12"; #Bank 20
|
||||
NET "DDR2_DM[7]" LOC = "AJ9"; #Bank 20
|
||||
NET "DDR2_DQS[0]" LOC = "AB31"; #Bank 12
|
||||
NET "DDR2_DQS_N[0]" LOC = "AA31"; #Bank 12
|
||||
NET "DDR2_DQS[1]" LOC = "AB30"; #Bank 12
|
||||
NET "DDR2_DQS_N[1]" LOC = "AC30"; #Bank 12
|
||||
NET "DDR2_DQS[2]" LOC = "AA29"; #Bank 12
|
||||
NET "DDR2_DQS_N[2]" LOC = "AA30"; #Bank 12
|
||||
NET "DDR2_DQS[3]" LOC = "AK29"; #Bank 18
|
||||
NET "DDR2_DQS_N[3]" LOC = "AJ29"; #Bank 18
|
||||
NET "DDR2_DQS[4]" LOC = "AK28"; #Bank 18
|
||||
NET "DDR2_DQS_N[4]" LOC = "AK27"; #Bank 18
|
||||
NET "DDR2_DQS[5]" LOC = "AH27"; #Bank 18
|
||||
NET "DDR2_DQS_N[5]" LOC = "AJ26"; #Bank 18
|
||||
NET "DDR2_DQS[6]" LOC = "AD10"; #Bank 20
|
||||
NET "DDR2_DQS_N[6]" LOC = "AD11"; #Bank 20
|
||||
NET "DDR2_DQS[7]" LOC = "AK11"; #Bank 20
|
||||
NET "DDR2_DQS_N[7]" LOC = "AJ11"; #Bank 20
|
||||
NET "DDR2_CK[0]" LOC = "AH9" ; #Bank 12
|
||||
NET "DDR2_CK_N[0]" LOC = "AH10" ; #Bank 12
|
||||
NET "DDR2_CK[1]" LOC = "AG10" ; #Bank 12
|
||||
NET "DDR2_CK_N[1]" LOC = "AG11" ; #Bank 12
|
||||
|
||||
###################################################
|
||||
## Floorplanned location constrains - non-I/O
|
||||
###################################################
|
||||
#temp
|
||||
# PLL specification LOCs
|
||||
INST "ddr2_cntrl_inst/u_infrastructure/u_dcm_base" LOC = DCM_ADV_X0Y6;
|
||||
|
||||
##Floorplan some of the blockrams
|
||||
|
||||
#Egress fifo BRAMS
|
||||
##AREA_GROUP "pblock_egress_fifos" RANGE=RAMB36_X0Y6:RAMB36_X0Y11;
|
||||
##INST "dma_ddr2_if_inst/egress_fifo_wrapper_inst/egress_fifo_a" AREA_GROUP = "pblock_egress_fifos";
|
||||
##INST "dma_ddr2_if_inst/egress_fifo_wrapper_inst/egress_fifo_b" AREA_GROUP = "pblock_egress_fifos";
|
||||
|
||||
#Ingress fifo BRAMS
|
||||
#INST "dma_ddr2_if_inst/ingress_fifo_a" LOC = "RAMB36_X0Y3";
|
||||
#INST "dma_ddr2_if_inst/ingress_fifo_b" LOC = "RAMB36_X0Y4";
|
||||
|
||||
#temp
|
||||
#DDR2 controller fifo BRAMS
|
||||
INST "ddr2_cntrl_inst/u_ddr2_top_0/u_mem_if_top_0/u_usr_top_0/u_backend_fifos_0/gen_wdf[1].u_usr_wr_fifo/u_wdf" LOC = "RAMB36_X0Y2";
|
||||
INST "ddr2_cntrl_inst/u_ddr2_top_0/u_mem_if_top_0/u_usr_top_0/u_backend_fifos_0/gen_wdf[0].u_usr_wr_fifo/u_wdf" LOC = "RAMB36_X0Y5";
|
||||
INST "ddr2_cntrl_inst/u_ddr2_top_0/u_mem_if_top_0/u_usr_top_0/u_backend_fifos_0/u_usr_addr_fifo_0/u_af" LOC = "RAMB36_X0Y7";
|
||||
|
||||
#RX Engine fifo BRAMS
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/data_trn_mem_fifo_inst/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[3].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP" LOC = "RAMB36_X1Y4";
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/data_trn_mem_fifo_inst/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[2].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP" LOC = "RAMB36_X1Y3";
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/data_trn_mem_fifo_inst/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP" LOC = "RAMB36_X1Y1";
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/data_trn_mem_fifo_inst/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP" LOC = "RAMB36_X1Y2";
|
||||
|
||||
#temp
|
||||
# PlanAhead generated physical constraints
|
||||
AREA_GROUP "pblock_r6_mem_cntrl" RANGE=SLICE_X12Y0:SLICE_X49Y9,
|
||||
SLICE_X0Y0:SLICE_X11Y49,
|
||||
SLICE_X12Y30:SLICE_X23Y44;
|
||||
AREA_GROUP "pblock_r6_mem_cntrl" RANGE=RAMB36_X0Y0:RAMB36_X0Y9,
|
||||
RAMB36_X1Y0:RAMB36_X1Y1;
|
||||
INST "ddr2_cntrl_inst" AREA_GROUP = "pblock_r6_mem_cntrl";
|
||||
|
||||
#AREA_GROUP "pblock_dma_ctrl_wrapper" RANGE=SLICE_X0Y50:SLICE_X19Y89;
|
||||
AREA_GROUP "pblock_dma_ctrl_wrapper" RANGE=SLICE_X0Y50:SLICE_X25Y95;
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst" AREA_GROUP = "pblock_dma_ctrl_wrapper";
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
###############################################################################
|
||||
## 2007-2008 Xilinx, Inc. All Rights Reserved.
|
||||
## Confidential and proprietary information of Xilinx, Inc.
|
||||
###############################################################################
|
||||
## ____ ____
|
||||
## / /\/ /
|
||||
## /___/ \ / Vendor: Xilinx
|
||||
## \ \ \/ Version: 1.0
|
||||
## \ \ Filename: pcie_dma_top.xcf
|
||||
## / / Date Last Modified: Apr. 1st, 2008
|
||||
## /___/ /\ Date Created: Apr. 1st, 2008
|
||||
## \ \ / \
|
||||
## \___\/\___\
|
||||
##
|
||||
## Device: Virtex-5 LXT
|
||||
## Purpose: Endpoint Block Plus to DDR2 DMA Initiator XST User Constraints File
|
||||
## Reference: XAPP859
|
||||
## Revision History:
|
||||
## Rev 1.0 - First created, Kraig Lund, Apr. 1 2008.
|
||||
###############################################################################
|
||||
################################################################################
|
||||
# Define Device, Package, and Speed Grade
|
||||
################################################################################
|
||||
#
|
||||
# CONFIG PART = XC5VLX50T-FF1136 ;
|
||||
#
|
||||
################################################################################
|
||||
|
||||
# Timing specifications common to all board/chip
|
||||
|
||||
NET "trn_clk_c" TNM_NET = "USR_PCIE_CLK";
|
||||
#TIMESPEC "TS_USR_PCIE_CLK" = PERIOD "USR_PCIE_CLK" 4 ns HIGH 50 %;
|
||||
TIMESPEC "TS_USR_PCIE_CLK" = PERIOD "USR_PCIE_CLK" 8 ns HIGH 50 %;
|
||||
|
||||
NET "SYS_CLK_P" TNM_NET = "SYS_CLK";
|
||||
#TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 4 ns HIGH 50 %;
|
||||
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 8 ns HIGH 50 %;
|
||||
|
||||
NET "trn_clk_c" TNM_NET = "TRN_CLK";
|
||||
#TIMESPEC "TS_TRN_CLK" = PERIOD "TRN_CLK" 4 ns HIGH 50 %;
|
||||
TIMESPEC "TS_TRN_CLK" = PERIOD "TRN_CLK" 8 ns HIGH 50 %;
|
||||
|
||||
## Multi-cycle paths
|
||||
#Multi-cycle paths for tx_trn_sm adder/subtractor
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/rx_trn_monitor_inst/dma*_div8_reg*" TNM=FFS "TNM_DMARDIV8_REG_SRC";
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/rx_trn_monitor_inst/dma*_div8_now*" TNM=FFS "TNM_DMARDIV8_NOW_SRC";
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/rx_trn_monitor_inst/addsub_state*" TNM=FFS "TNM_RADDSUB_STATE_SRC";
|
||||
TIMEGRP "DMARDIV8_2X_SRC" = "TNM_DMARDIV8_REG_SRC" "TNM_DMARDIV8_NOW_SRC" "TNM_RADDSUB_STATE_SRC";
|
||||
INST "pcie_dma_wrapper_inst/rx_engine_inst/rx_trn_monitor_inst/dma*_div8_reg_new*" TNM=FFS "TNM_DMARDIV8_REGNEW_DEST";
|
||||
TIMESPEC "TS_DMARDIV8_2X" = FROM "DMARDIV8_2X_SRC" TO "TNM_DMARDIV8_REGNEW_DEST" "TS_TRN_CLK"*2;
|
||||
|
||||
# Jiansong: disabled
|
||||
#Multi-cycle paths for tx_trn_sm adder/subtractor
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/tx_trn_sm_inst/dma*_div8_reg*" TNM=FFS "TNM_DMAWDIV8_REG_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/tx_trn_sm_inst/dma*_div8_now*" TNM=FFS "TNM_DMAWDIV8_NOW_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/tx_trn_sm_inst/addsub_state*" TNM=FFS "TNM_WADDSUB_STATE_SRC";
|
||||
#TIMEGRP "DMAWDIV8_2X_SRC" = "TNM_DMAWDIV8_REG_SRC" "TNM_DMAWDIV8_NOW_SRC" "TNM_WADDSUB_STATE_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/tx_trn_sm_inst/dma*_div8_reg_new*" TNM=FFS "TNM_DMAWDIV8_REGNEW_DEST";
|
||||
#TIMESPEC "TS_DMAWDIV8_2X" = FROM "DMAWDIV8_2X_SRC" TO "TNM_DMAWDIV8_REGNEW_DEST" "TS_TRN_CLK"*2;
|
||||
|
||||
# Jiansong: disabled
|
||||
#Multi-cycle paths for posted slicer adder
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/posted_pkt_gen_inst/posted_pkt_slicer_inst/four_kb_xfer*" TNM=FFS "TNM_PFKB_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/posted_pkt_gen_inst/posted_pkt_slicer_inst/dma*_reg*" TNM=FFS "TNM_PDMAREG_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/posted_pkt_gen_inst/posted_pkt_slicer_inst/state*" TNM=FFS "TNM_PSTATE_SRC";
|
||||
#TIMEGRP "POSTED_2X_SRC" = "TNM_PFKB_SRC" "TNM_PDMAREG_SRC" "TNM_PSTATE_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/posted_pkt_gen_inst/posted_pkt_slicer_inst/dma*_new*" TNM=FFS "TNM_PDMANEW_DEST";
|
||||
#TIMESPEC "TS_POSTED_2X" = FROM "POSTED_2X_SRC" TO "TNM_PDMANEW_DEST" "TS_TRN_CLK"*2;
|
||||
|
||||
# Jiansong: modified
|
||||
#Multi-cycle paths for non-posted slicer adder#INST "pcie_dma_wrapper_inst/tx_engine_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/four_kb_xfer*" TNM=FFS "TNM_NFKB_SRC";
|
||||
INST "pcie_dma_wrapper_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/four_kb_xfer*" TNM=FFS "TNM_NFKB_SRC";
|
||||
INST "pcie_dma_wrapper_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/dma*_reg*" TNM=FFS "TNM_NDMAREG_SRC";
|
||||
INST "pcie_dma_wrapper_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/state*" TNM=FFS "TNM_NSTATE_SRC";
|
||||
TIMEGRP "NONPOSTED_2X_SRC" = "TNM_NFKB_SRC" "TNM_NDMAREG_SRC" "TNM_NSTATE_SRC";
|
||||
INST "pcie_dma_wrapper_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/dma*_new*" TNM=FFS "TNM_NDMANEW_DEST";
|
||||
TIMESPEC "TS_NONPOSTED_2X" = FROM "NONPOSTED_2X_SRC" TO "TNM_NDMANEW_DEST" "TS_TRN_CLK"*2;
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/four_kb_xfer*" TNM=FFS "TNM_NFKB_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/dma*_reg*" TNM=FFS "TNM_NDMAREG_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/state*" TNM=FFS "TNM_NSTATE_SRC";
|
||||
#TIMEGRP "NONPOSTED_2X_SRC" = "TNM_NFKB_SRC" "TNM_NDMAREG_SRC" "TNM_NSTATE_SRC";
|
||||
#INST "pcie_dma_wrapper_inst/tx_engine_inst/non_posted_pkt_gen_inst/non_posted_pkt_slicer_inst/dma*_new*" TNM=FFS "TNM_NDMANEW_DEST";
|
||||
#TIMESPEC "TS_NONPOSTED_2X" = FROM "NONPOSTED_2X_SRC" TO "TNM_NDMANEW_DEST" "TS_TRN_CLK"*2;
|
||||
|
||||
# Jiansong: added for poset_packet_scheduler
|
||||
# Multi-cycle paths for posted scheduler adder
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_inst/RXBuf*" TNM=FFS "TNM_NRXB_SRC";
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_inst/dmawad_now*" TNM=FFS "TNM_NDWNW_SRC";
|
||||
TIMEGRP "POSTED_2X_SRC" = "TNM_NRXB_SRC" "TNM_NDWNW_SRC";
|
||||
INST "pcie_dma_wrapper_inst/posted_pkt_gen_inst/posted_pkt_scheduler_inst/dmawad_next*" TNM=FFS "TNM_NDWNT_DEST";
|
||||
TIMESPEC "TS_POSTED_2X" = FROM "POSTED_2X_SRC" TO "TNM_NDWNT_DEST" "TS_TRN_CLK"*2;
|
||||
|
||||
# Jiansong: modified
|
||||
# Multi-cycle paths for large xfers shim adder
|
||||
#INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/state_1*" TNM=FFS "TNM_STATE_1_SRC";
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/state_3*" TNM=FFS "TNM_STATE_3_SRC";
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/dma*_now*" TNM=FFS "TNM_DMANOW_SRC";
|
||||
#TIMEGRP "LARGE_XFER_2X_SRC" = "TNM_STATE_1_SRC" "TNM_STATE_3_SRC" "TNM_DMANOW_SRC";
|
||||
TIMEGRP "LARGE_XFER_2X_SRC" = "TNM_STATE_3_SRC" "TNM_DMANOW_SRC";
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/dma*_next*" TNM=FFS "TNM_DMANEXT_DEST";
|
||||
TIMESPEC "TS_DMAREG_DMANEXT" = FROM "LARGE_XFER_2X_SRC" TO "TNM_DMANEXT_DEST" "TS_TRN_CLK"*2;
|
||||
|
||||
# Jiansong: added
|
||||
# Multi-cycle paths for large xfers shim adder
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/TX_state_1*" TNM=FFS "TNM_TX_STATE_1_SRC";
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/TX_*_now*" TNM=FFS "TNM_TXNOW_SRC";
|
||||
TIMEGRP "TX_LARGE_XFER_2X_SRC" = "TNM_TX_STATE_1_SRC" "TNM_TXNOW_SRC";
|
||||
INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/TX_*_next*" TNM=FFS "TNM_TXNEXT_DEST";
|
||||
TIMESPEC "TS_TXREG_TXNEXT" = FROM "TX_LARGE_XFER_2X_SRC" TO "TNM_TXNEXT_DEST" "TS_TRN_CLK"*2;
|
||||
|
||||
# Jiansong: added, used for WARP radio register version
|
||||
# Multi-cycle paths from radio module to host registers
|
||||
# INST "WARP_Radio_module_inst/host_*" TNM=FFS "TNM_RADIOHOST_SRC";
|
||||
# TIMEGRP "RADIO_WARP_SRC" = "TNM_RADIOHOST_SRC";
|
||||
# INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/WARP_*" TNM=FFS "TNM_WARP_DEST";
|
||||
# TIMESPEC "TS_RADIO_INTERFACE" = FROM "RADIO_WARP_SRC" TO "TNM_WARP_DEST" "TS_TRN_CLK"*3;
|
||||
|
||||
# Jiansong: added, used for SORA radio register version
|
||||
# Multi-cycle paths from radio module to host registers
|
||||
# INST "Sora_Radio_Interpretation_for_WARP_inst/host_*" TNM=FFS "TNM_ABS_RADIOHOST_SRC";
|
||||
# TIMEGRP "ABS_RADIO_SORA_SRC" = "TNM_ABS_RADIOHOST_SRC";
|
||||
# INST "pcie_dma_wrapper_inst/dma_ctrl_wrapper_inst/dma_ctrl_status_reg_file_inst/SORA_*" TNM=FFS "TNM_ABS_SORA_DEST";
|
||||
# TIMESPEC "TS_ABS_RADIO_INTERFACE" = FROM "ABS_RADIO_SORA_SRC" TO "TNM_ABS_SORA_DEST" "TS_TRN_CLK"*3;
|
||||
|
||||
#Tig'ed nets - these are static signals
|
||||
NET "trn_lnk_up_n_c" TIG;
|
||||
NET "phy_init_initialization_done" TIG;
|
||||
|
||||
INST "max_read_req_reg*" TIG;
|
||||
INST "max_pay_size_reg*" TIG;
|
||||
INST "pcie_id_reg*" TIG;
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,691 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="12.3" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_CRC_gen.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/non_posted_pkt_gen.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_TX_MSG.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/rx_trn_monitor.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/tx_engine.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../ip_cores/coregen_memories/a64_128_distram_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/dma_ctrl_status_reg_file.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../ip_cores/coregen_memories/RX_data_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../ip_cores/coregen_memories/ingress_addr_cntrl_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../ip_cores/coregen_memories/dualport_32x32_compram.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_RESOURCE_SHARING_CONTROL.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../ip_cores/coregen_memories/egress_addr_cntrl_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../ip_cores/coregen_memories/data_trn_dma_write_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_data_check.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_TX.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../ip_cores/coregen_memories/a64_64_distram_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_STATUS_IN.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/Clock_module_FRL.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_COUNT_TO_64.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/Sora_FRL_RCB.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_OSERDES.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../ip_cores/pcie_endpoint_plus_x8_250/endpoint_blk_plus_v1_8.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_OSERDES_MSG.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/dma_ddr2_if.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/non_posted_pkt_builder.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/rx_engine.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/tag_generator.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="pcie_dma_top.xcf" xil_pn:type="FILE_USERDOC"/>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/completer_pkt_gen.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_count_to_16x.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/rx_trn_data_fsm.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_fifo_MSG.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/posted_pkt_builder.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../ip_cores/coregen_memories/Egress_data_FIFO.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../ip_cores/pcie_endpoint_plus_x8_250/endpoint_blk_plus_v1_9.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_LED_Clock.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/pcie_dma_wrapper.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/Sora_RCB.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_RX_MSG.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_TrainingPattern.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/dma_ctrl_wrapper.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/rising_edge_detect.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/posted_pkt_gen_sora.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/non_posted_pkt_slicer.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/tx_trn_sm.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/posted_pkt_scheduler.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../ip_cores/coregen_memories/data_trn_mem_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../ip_cores/coregen_memories/ingress_data_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/performance_counter.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="Sora_RCB_FRL_x4_plus_133MDDR_RCBv1.1.3.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_DDR_8TO1_16CHAN_RX.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/internal_dma_ctrl.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/rx_mem_data_fsm.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_BIT_ALIGN_MACHINE.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/completion_timeout.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../ip_cores/coregen_memories/xfer_trn_mem_fifo.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_STATUS_OUT.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/read_req_wrapper.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/pending_comp_ram_32x1.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/edge_detect.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_RX.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_count_to_128.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../ip_cores/pcie_endpoint_plus_x8_250/endpoint_blk_plus_v1_14/source/endpoint_blk_plus_v1_14.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="../../ip_cores/ddr2_memory_interface/rtl/mem_interface_top.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector virtex5" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add File to project" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Pads" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Advanced FSM Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Array Bounds Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Constrain" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Baud rate" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="0" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SmartModels (PPC, MGT) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Busy" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Configuration Pin CS" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Configuration Pin DIn" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Configuration Pin RdWr" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Configuration Rate" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="20" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Convert Tristates To Logic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cores Search Directories" xil_pn:value="../../ip_cores/coregen_memories|../../ip_cores/pcie_endpoint_plus_x8_250" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Default Enum Encoding Goal" xil_pn:value="default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc5vlx50t" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Virtex5" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable I/O insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Display Incremental Messages" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="EDIF" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Enhanced Design Summary" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Continue on Impossible" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fallback Reconfiguration" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fanout Guide" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Full Case" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Generate Detailed Package Parasitics" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate UCF from RTL Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Clock Delay 0 (Binary String)" xil_pn:value="11111" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Clock Delay 1 (Binary String)" xil_pn:value="11111" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Clock Delay 2 (Binary String)" xil_pn:value="11111" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Clock Delay 3 (Binary String)" xil_pn:value="11111" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Start View" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="AbstractSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|Sora_RCB" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="../../rtl/Sora_RCB.v" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Sora_RCB" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Float" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="JTAG to System Monitor Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="Soft" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load Setting File" xil_pn:value="Default" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Load Timing Specification Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macro Search Path" xil_pn:value="../../ip_cores/coregen_memories|../../ip_cores/pcie_endpoint_plus_x8_250|../../ip_cores/coregen_DCMs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="50" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ModelSim Post-Fit UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Multiplier Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="On" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Critical Paths" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Critical Paths Synthesis" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="400" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Number of Start/End Points" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Summary Paths" xil_pn:value="10" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="High" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Speed" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Base Name" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="Sora_RCB" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="ff1136" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Parallel Case" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pipelining" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Continue on Impossible" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Sora_RCB_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="Sora_RCB_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Sora_RCB_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Sora_RCB_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Push Tristates across Process/Block Boundaries" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Distributed" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Distributed" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Set/Reset (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="pcie_dma_top" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Clock Frequencies" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Critical Paths" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Report Missing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Timing Summary" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Timing Violations" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Error Report" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing Precision" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing Synthesis" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retiming" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Retiming" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SelectMAP Abort Sequence" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb/pcie_dma_top_i/ep/pcie_ep0/pcie_blk_if" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.pcie_blk_if" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setting Output File" xil_pn:value="Default" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show Clock Domain Crossing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show Net Fan Out" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE Verilog" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Simulator Path" xil_pn:value="C:/modeltech_6.5a/win32" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-1" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Symbolic FSM Compiler" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Constraints File" xil_pn:value="pcie_dma_top.xcf" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Sysgen Instantiation Template Target Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Transform Set/Reset on DFFs to Latches" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tri-state Buffer Transformation Mode" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Update modelsim.ini File for Xilinx SmartModel Use" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Do File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use FSM Explorer Data" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Safe FSM" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Syntax Precision" xil_pn:value="VHDL 93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Include Directories" xil_pn:value="../../rtl|../../rtl/pcie_userapp_wrapper/pcie_dma_engine" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Standard" xil_pn:value="Verilog 2001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events) virtex5" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value virtex5" xil_pn:value="0x000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Mapped VHDL Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Mapped Verilog Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Vendor Constraint File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|Channel_Radio_Interpretation_for_WARP" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="pcie_dma_top" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_HdlTemplateLang" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_HdlTemplateName" xil_pn:value="pcie_dma_top.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="Module|tb" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Module|tb" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="Module|tb" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="Module|tb" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-05-06T18:23:49" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="298A696652A9471F84137E7FCE17784C" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
<file xil_pn:name="../../rtl/pcie_userapp_wrapper/pcie_dma_engine/Sora_config.v" xil_pn:type="FILE_VERILOG"/>
|
||||
<file xil_pn:name="../../rtl/PCIe_setting.v" xil_pn:type="FILE_VERILOG"/>
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
XILINX-XDB 0.1 STUB 0.1 ASCII
|
||||
XILINX-XDM V1.4e
|
||||
$82x4>7<881:;6??.0,377=6>11::*fI0G20?411:2;S=6::;4,5<71<I[IC[DT>7:CQS_YHFESTOL]LAEKMCZEKC820M_YU_NLO]ZEKC@DTIUZJROCO50=FZ^PTCCBV_BNHMKYQIE_N=o5NRVX\KKJ^WMIFS^YFTBJJJBYDDB;;7L\XZ^MMH\YCL[UH<<>4ASUY[JHKQVNO^RM>109BVR\XGGFRSIJ]_BNH53=FZ^PTCCBV_EFQ[@B@MDEOI<84ASUY[JHKQVNO^RHCIQDOKU753HX\VRAALX]G@WYNF@^:;6O]W[]LJI_XLMXT^H]JTU[SA43<I[]QSB@CY^DA[@^SM[DJ@<<4ASUY[JHKQVCE_YQAUL34?DTPRVEE@TQ]EBMMBLAXX@DX=85NRVX\KKJ^W[OXIYQCOFK@57=FZ^PTCCBV_SGWEWAB\820M_YU_NLO]ZPFD@NTHK]PMNFFe>GT[FIT[DZGf:CT^ZEKCK_MXT^J1048ER\XKEAIYKZVPD3\JJCCA];87LYU_BNH[JSSX\^TXT^Jc:CT^Z@KG^^R\H64AVX\TDTSl2K\VR]VNUJWKJJ33K_MK95LLJ2;?FJL8VH^Jh5LLJ2\FP@@W@DXX55LLJ2\KPR13JF@=5>9;BNH62623JF@>U64CMI1\4>7=2IGG4>:;BNH@S?<KEAOZRLZFg9@HNBQWK_MKRGASUa8GIMC^VNBZDJJ9:AOOAPXG\^>7NBDFC:8GIMAJVCE96MCKGZ;?FJLNQ;3<n5LLJD[[AOQAMOn7NBDFY]NQIRNXES>7NBDIO32?FJLAGUOE[GKE^@Z[7><KEABBRGAc:AOOLHXXLXBCIk4CMIJJZUUKV^R\H?=;BNHKPRXXAKXIR]GIGV`?FJLWOONHOOLK89@KHKN\]OO;6M]E@VF@34<L3Vfuiky\GRDEY~fxy2>5R]`r`]eqij[phz{487Psnpb[454EmnyPk~ha]ks[fiumzVhckheo]GGHu[LJGT=:8BI^32IJ(i~?0HLJKR59GGIM03MIFSLJYc:F@IZGC^VCE_Y?<;EAN[DSSGJKGEO\NTHMM51=CKDU[I_H@RLCMG@YJGMO87IKAd:FFWNCPWHNAY^Z>2:FEWZ@UMX_NBNWPMNFF6>BN;2NG@<<4DMN\BWCV]LDHURC@DD08@J2<L[NR=85KUU[\G\EKMVID^_KLTHMM7>BPM>1OS[OCUDc8BDESG[STFK;4F@NPA<=AJVYDY_MJc:DFAADFKBUIYK74FHL\QKOS[11MCXZPSUPb?CIR\V_EEY]n;GMVPZPFD\O?7EGHH09J<>OI\LXEMA?>;KKWP@TXAGZ^XRZVPD48HJGCMM<0@BMDEEc8HJELMMUDYY74M@Z\WUCBL:1FDW94M^TBHPC03GO_[B\D4:LLJ@7<G=1DHI\7;NRSKVOSMk1[DL]J_RJJBQ?<X@DCM^LZS`9SMKOTOGNNH55_IOUJ@QN?3YXBAYW_E028TWIWWYCEE^OLTHTF1>VTKEA=7]]KOOG7?UUBF11[_D@LDDA0?WUS>2XXXRGAb:QJC@^SM[DJ@l5\IL]GASODM?1XECICEb9PPDTS]YU\MDZm;R[MGMTHFF_X=?5\YRVFIZU^FJBYCCAZS29WKU2<\[_N46[\E^@VBB?<]ZOTNXHHS49UM@Q6?2\B^YKW5c9[ERYQM[YBCC?k;YKOMK^*PMH+<#?/SUWA$5(6(HYHED=4XRV5?]beW@n:<6Vkm^ObnjtQm{ybcc??;Yfn[Hoig{\n~~g`n49X4?6Z>2Q;6<;R5:Y3>3[33hx|v>5kcl58r`tndfmi7{k}shmm$4(79;1so8xcx42w)c`69:<&=pNOp2;8DE~393L187?tS529<g<?m3;8>5h93;:;<`}i0?0:7c68:59'<0<?;2wX?k47b;:f>4550o<8657=4:Q6b?>e21o1=><7f719<<cf3Z9m65l58d8277>a>:035ko4d9`94?7=9rY?<76m:9g9564?n?91456j;wV;4?6=93;14v];0;:a>=c=9:83j;=589:f?g1d290;6>47{%c9<f=#:903h6*=1;:e?!4521>0(5<53:`71?6=910;6=u+6d870>"e2;n0(n488:&f>72<,8<1;55+1681?!742?20(k4=4:&24?4?3-;:6?:4$0092<=#9=0:7)?::6c8 4>===1/=44:4:&2e?333-9n6:5+3187?!512;1/?:47;%1:>02<,:h156*<c;7g?!5c2?<0(9857e9'02<1:2.?579m;%6b>0d<,=n19o5+5184`>"2:380(8=55:&61?3c3-?<6;=4$4;926=#=h0;7);j:4:8 32=02.=m7?4$6;911=#?l0<j6*k:79'5c<3k2.:n7;m;%54>=7<a:21<7*9d;:;?!0a2>n07d==:18'2a<?02.=j79k;:k76?6=,?n14l5+6b84`>"1j3=o76g;b;29 3b=001/:n48d:&5f?1c32c>=7>5$7f9<==#>j0<h65f4983>!0c2120(;m57e98m15=83.=h767;%4`>2b<3`=?6=4+6e8;<>"1n3=o76g82;29 3b=011/:n48d:9j36<72-<o6564$7a93a=<a>:1<7*9d;:;?!0d2>n07b<;:18'2a<?02.=j79k;%3g>75<,8o19;54o3a94?"1l32376a=8;29 3b=0110c?750;&5`?>?32e9h7>5$7f9<==#>o0<h6*>d;00?>i5i3:1(;j58998k7d=83.=h767;:m00?6=,?n14554o2794?"1l32376a;f;29 3b=0110c9k50;&5`?>>3-<i6:j4;n43>5<#>m0346*9f;5g?>i093:1(;j58998yg4129096=4?{%4f>75<a<i1<7*9d;:;?!0a2>n07b88:18'2a<?02.=j79k;:a6c<72;0;6=u+6d817>o2k3:1(;j5899'2c<0l21d::4?:%4g>=><,?l1;i54}r1b>5<6s4>>6>64$6491f=z{:91<7<t=57977=::?0=;6*>c;04?xu0=3:1=v3;5;57?!112<i0q~<::1818222;>01?855b9~w7c=838p19;52e9>6c<2k2wx:<4?:0y>00<182.<:788;|q05?6=9r79j788;%55>31<uz8<6=4?{%55>31<utd957>51zm6d<728qvb?l50;3xyk4d290:wp`=d;295~{i:l0;6<urn3d94?7|ug9;6=4>{|~yEFDs:31:nk<3`a4yEFEs9wKL]ur@A
|
||||
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