2020-05-15 13:43:39 +03:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Ingenic JZ47xx remoteproc driver
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* Copyright 2019, Paul Cercueil <paul@crapouillou.net>
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/remoteproc.h>
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#include "remoteproc_internal.h"
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#define REG_AUX_CTRL 0x0
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#define REG_AUX_MSG_ACK 0x10
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#define REG_AUX_MSG 0x14
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#define REG_CORE_MSG_ACK 0x18
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#define REG_CORE_MSG 0x1C
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#define AUX_CTRL_SLEEP BIT(31)
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#define AUX_CTRL_MSG_IRQ_EN BIT(3)
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#define AUX_CTRL_NMI_RESETS BIT(2)
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#define AUX_CTRL_NMI BIT(1)
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#define AUX_CTRL_SW_RESET BIT(0)
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2021-01-23 17:29:56 +03:00
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static bool auto_boot;
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module_param(auto_boot, bool, 0400);
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MODULE_PARM_DESC(auto_boot,
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"Auto-boot the remote processor [default=false]");
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2020-05-15 13:43:39 +03:00
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struct vpu_mem_map {
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const char *name;
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unsigned int da;
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};
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struct vpu_mem_info {
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const struct vpu_mem_map *map;
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unsigned long len;
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void __iomem *base;
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};
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static const struct vpu_mem_map vpu_mem_map[] = {
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{ "tcsm0", 0x132b0000 },
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{ "tcsm1", 0xf4000000 },
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{ "sram", 0x132f0000 },
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};
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/**
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* struct vpu - Ingenic VPU remoteproc private structure
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* @irq: interrupt number
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* @clks: pointers to the VPU and AUX clocks
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* @aux_base: raw pointer to the AUX interface registers
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* @mem_info: array of struct vpu_mem_info, which contain the mapping info of
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* each of the external memories
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* @dev: private pointer to the device
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*/
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struct vpu {
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int irq;
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struct clk_bulk_data clks[2];
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void __iomem *aux_base;
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struct vpu_mem_info mem_info[ARRAY_SIZE(vpu_mem_map)];
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struct device *dev;
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};
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2020-06-30 19:31:17 +03:00
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static int ingenic_rproc_prepare(struct rproc *rproc)
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{
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struct vpu *vpu = rproc->priv;
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int ret;
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/* The clocks must be enabled for the firmware to be loaded in TCSM */
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ret = clk_bulk_prepare_enable(ARRAY_SIZE(vpu->clks), vpu->clks);
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if (ret)
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dev_err(vpu->dev, "Unable to start clocks: %d\n", ret);
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return ret;
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}
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static int ingenic_rproc_unprepare(struct rproc *rproc)
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{
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struct vpu *vpu = rproc->priv;
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clk_bulk_disable_unprepare(ARRAY_SIZE(vpu->clks), vpu->clks);
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return 0;
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}
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2020-05-15 13:43:39 +03:00
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static int ingenic_rproc_start(struct rproc *rproc)
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{
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struct vpu *vpu = rproc->priv;
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u32 ctrl;
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enable_irq(vpu->irq);
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/* Reset the AUX and enable message IRQ */
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ctrl = AUX_CTRL_NMI_RESETS | AUX_CTRL_NMI | AUX_CTRL_MSG_IRQ_EN;
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writel(ctrl, vpu->aux_base + REG_AUX_CTRL);
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return 0;
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}
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static int ingenic_rproc_stop(struct rproc *rproc)
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{
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struct vpu *vpu = rproc->priv;
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disable_irq(vpu->irq);
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/* Keep AUX in reset mode */
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writel(AUX_CTRL_SW_RESET, vpu->aux_base + REG_AUX_CTRL);
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return 0;
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}
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static void ingenic_rproc_kick(struct rproc *rproc, int vqid)
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{
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struct vpu *vpu = rproc->priv;
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writel(vqid, vpu->aux_base + REG_CORE_MSG);
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}
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2021-03-06 14:24:19 +03:00
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static void *ingenic_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
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2020-05-15 13:43:39 +03:00
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{
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struct vpu *vpu = rproc->priv;
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void __iomem *va = NULL;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(vpu_mem_map); i++) {
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const struct vpu_mem_info *info = &vpu->mem_info[i];
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const struct vpu_mem_map *map = info->map;
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if (da >= map->da && (da + len) < (map->da + info->len)) {
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va = info->base + (da - map->da);
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break;
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}
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}
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return (__force void *)va;
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}
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2020-11-08 02:36:29 +03:00
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static const struct rproc_ops ingenic_rproc_ops = {
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2020-06-30 19:31:17 +03:00
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.prepare = ingenic_rproc_prepare,
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.unprepare = ingenic_rproc_unprepare,
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2020-05-15 13:43:39 +03:00
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.start = ingenic_rproc_start,
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.stop = ingenic_rproc_stop,
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.kick = ingenic_rproc_kick,
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.da_to_va = ingenic_rproc_da_to_va,
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};
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static irqreturn_t vpu_interrupt(int irq, void *data)
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{
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struct rproc *rproc = data;
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struct vpu *vpu = rproc->priv;
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u32 vring;
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vring = readl(vpu->aux_base + REG_AUX_MSG);
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/* Ack the interrupt */
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writel(0, vpu->aux_base + REG_AUX_MSG_ACK);
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return rproc_vq_interrupt(rproc, vring);
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}
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static int ingenic_rproc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct resource *mem;
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struct rproc *rproc;
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struct vpu *vpu;
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unsigned int i;
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int ret;
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rproc = devm_rproc_alloc(dev, "ingenic-vpu",
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&ingenic_rproc_ops, NULL, sizeof(*vpu));
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if (!rproc)
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return -ENOMEM;
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2021-01-23 17:29:56 +03:00
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rproc->auto_boot = auto_boot;
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2020-05-15 13:43:39 +03:00
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vpu = rproc->priv;
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vpu->dev = &pdev->dev;
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platform_set_drvdata(pdev, vpu);
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mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aux");
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vpu->aux_base = devm_ioremap_resource(dev, mem);
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if (IS_ERR(vpu->aux_base)) {
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dev_err(dev, "Failed to ioremap\n");
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return PTR_ERR(vpu->aux_base);
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}
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for (i = 0; i < ARRAY_SIZE(vpu_mem_map); i++) {
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mem = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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vpu_mem_map[i].name);
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vpu->mem_info[i].base = devm_ioremap_resource(dev, mem);
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if (IS_ERR(vpu->mem_info[i].base)) {
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ret = PTR_ERR(vpu->mem_info[i].base);
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dev_err(dev, "Failed to ioremap\n");
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return ret;
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}
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vpu->mem_info[i].len = resource_size(mem);
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vpu->mem_info[i].map = &vpu_mem_map[i];
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}
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vpu->clks[0].id = "vpu";
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vpu->clks[1].id = "aux";
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ret = devm_clk_bulk_get(dev, ARRAY_SIZE(vpu->clks), vpu->clks);
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if (ret) {
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dev_err(dev, "Failed to get clocks\n");
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return ret;
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}
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vpu->irq = platform_get_irq(pdev, 0);
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if (vpu->irq < 0)
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return vpu->irq;
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ret = devm_request_irq(dev, vpu->irq, vpu_interrupt, 0, "VPU", rproc);
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if (ret < 0) {
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dev_err(dev, "Failed to request IRQ\n");
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return ret;
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}
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disable_irq(vpu->irq);
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ret = devm_rproc_add(dev, rproc);
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if (ret) {
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dev_err(dev, "Failed to register remote processor\n");
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2020-06-30 19:31:17 +03:00
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return ret;
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2020-05-15 13:43:39 +03:00
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}
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2020-06-30 19:31:17 +03:00
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return 0;
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2020-05-15 13:43:39 +03:00
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}
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static const struct of_device_id ingenic_rproc_of_matches[] = {
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{ .compatible = "ingenic,jz4770-vpu-rproc", },
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{}
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};
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MODULE_DEVICE_TABLE(of, ingenic_rproc_of_matches);
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static struct platform_driver ingenic_rproc_driver = {
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.probe = ingenic_rproc_probe,
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.driver = {
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.name = "ingenic-vpu",
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.of_match_table = ingenic_rproc_of_matches,
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},
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};
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module_platform_driver(ingenic_rproc_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
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MODULE_DESCRIPTION("Ingenic JZ47xx Remote Processor control driver");
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