2005-04-17 02:20:36 +04:00
|
|
|
/*
|
|
|
|
|
* Support for common PCI multi-I/O cards (which is most of them)
|
|
|
|
|
*
|
|
|
|
|
* Copyright (C) 2001 Tim Waugh <twaugh@redhat.com>
|
|
|
|
|
*
|
|
|
|
|
* This program is free software; you can redistribute it and/or
|
|
|
|
|
* modify it under the terms of the GNU General Public License
|
|
|
|
|
* as published by the Free Software Foundation; either version
|
|
|
|
|
* 2 of the License, or (at your option) any later version.
|
|
|
|
|
*
|
|
|
|
|
*
|
|
|
|
|
* Multi-function PCI cards are supposed to present separate logical
|
|
|
|
|
* devices on the bus. A common thing to do seems to be to just use
|
|
|
|
|
* one logical device with lots of base address registers for both
|
|
|
|
|
* parallel ports and serial ports. This driver is for dealing with
|
|
|
|
|
* that.
|
|
|
|
|
*
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#include <linux/types.h>
|
|
|
|
|
#include <linux/module.h>
|
|
|
|
|
#include <linux/init.h>
|
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 11:04:11 +03:00
|
|
|
#include <linux/slab.h>
|
2005-04-17 02:20:36 +04:00
|
|
|
#include <linux/pci.h>
|
2009-04-07 18:30:57 +04:00
|
|
|
#include <linux/interrupt.h>
|
2005-04-17 02:20:36 +04:00
|
|
|
#include <linux/parport.h>
|
|
|
|
|
#include <linux/parport_pc.h>
|
|
|
|
|
#include <linux/8250_pci.h>
|
|
|
|
|
|
|
|
|
|
enum parport_pc_pci_cards {
|
|
|
|
|
titan_110l = 0,
|
|
|
|
|
titan_210l,
|
|
|
|
|
netmos_9xx5_combo,
|
2005-06-23 11:09:55 +04:00
|
|
|
netmos_9855,
|
parport: netmos 9845 & 9855 1P4S fixes
netmos serial/parallel adapters come in different flavour differing only
by the number of parallel and serial ports, which are encoded in the
subdevice ID.
Last fix of Christian Pellegrin for 9855 2P2S broke support for 9855 1P4S,
and works only by side-effect for the first parallel port of a 2P2S, as
this first parallel port is found by reading the second addr entry of
(struct parport_pc_pci) cards[netmos_9855], which is not initialized, and
hence has value 0, which happens to be the BAR of the first parallel port.
netmos_9xx5_combo entry in (struct parport_pc_pci) cards[], which is used
for a 9845 1P4S must also be fixed for the parallel port support when
there are 4 serial ports because this entry currently gives 2 as BAR index
for the parallel port. Actually, in this case, BAR 2 is the 3rd serial
port while the parallel port is at BAR 4.
I fixed 9845 1P4S and 9855 1P4S support, while preserving 9855 2P2S support,
- by creating a netmos_9855_2p entry and using it for 9855 boards with 2
parallel ports : 9855 2P2S and 9855 2P0S boards,
- and by allowing netmos_parallel_init to change not only the number of
parallel ports (0 or 1), but making it also change the BAR index of the
parallel port when the serial ports are before the parallel port.
PS: the netmos_9855_2p entry in (struct pciserial_board)
pci_parport_serial_boards[] is needed because netmos_parallel_init has no
clean way to replace FL_BASE2 by FL_BASE4 in the description of the serial
ports in function of the number of parallel ports on the card.
Tested with 9845 1P4S, 9855 1P4S and 9855 2P2S boards.
Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Tested-by: Christian Pellegrin <chripell@fsfe.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-04-03 03:58:53 +04:00
|
|
|
netmos_9855_2p,
|
Basic support for Moschip 9900 family I/O chips
Add I/O based support for serial and parallel ports of the following
chips:
Vendor: Moschip (0x9710)
Parts (device IDs)
* 9900 (0x9900)
* 9904 (0x9904
* 9901 (0x9912, also sold as 9912)
* 9922 (0x9922)
On all chips but the 9900, a single port is provided per PCI subdevice
(subvendor-ID 0xA000, subdevice-IDs 0x1000 for serial, 0x2000 for
parallel with proper class codes). In cascading configurations, the
9900 provides two devices per subdevice, with subvendor-ID 0xA000 and
subdevice-IDs 0x30ps where p is the number of parallel ports and s the
number of serial ports.
Basic testing was only done on the serial part of a 9912 to the point
where it can be used for a serial kernel console, and advanced features
are completely untested. It is possible to reduce functionality of the
chips by adding a configuration EEPROM, and the datasheet [1] is
inconsistent w.r.t subdevices in the 4s+2s1p and 2s1p+4s
configurations. The subdevice-ID 0x3012 should likely read 0x3011 with
a serial port in function 3, which would be consistent with the BAR
layouts. For now, the drivers ignore subdevices with ID 0x1000 and no
class code.
The parallel ports are integrated in parport_serial even for purely
parallel parts to reduce the footprint of the patch.
[1] http://www.moschip.com/data/products/MCS9900/MCS9900_Datasheet.pdf
Signed-off-by: Nicos Gollan <gtdev@spearhead.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-05-05 23:00:37 +04:00
|
|
|
netmos_9900,
|
|
|
|
|
netmos_9900_2p,
|
|
|
|
|
netmos_99xx_1p,
|
2005-04-17 02:20:36 +04:00
|
|
|
avlab_1s1p,
|
|
|
|
|
avlab_1s2p,
|
|
|
|
|
avlab_2s1p,
|
|
|
|
|
siig_1s1p_10x,
|
|
|
|
|
siig_2s1p_10x,
|
|
|
|
|
siig_2p1s_20x,
|
|
|
|
|
siig_1s1p_20x,
|
|
|
|
|
siig_2s1p_20x,
|
2011-05-29 23:08:04 +04:00
|
|
|
timedia_4078a,
|
|
|
|
|
timedia_4079h,
|
|
|
|
|
timedia_4085h,
|
|
|
|
|
timedia_4088a,
|
|
|
|
|
timedia_4089a,
|
|
|
|
|
timedia_4095a,
|
|
|
|
|
timedia_4096a,
|
|
|
|
|
timedia_4078u,
|
|
|
|
|
timedia_4079a,
|
|
|
|
|
timedia_4085u,
|
|
|
|
|
timedia_4079r,
|
|
|
|
|
timedia_4079s,
|
|
|
|
|
timedia_4079d,
|
|
|
|
|
timedia_4079e,
|
|
|
|
|
timedia_4079f,
|
|
|
|
|
timedia_9079a,
|
|
|
|
|
timedia_9079b,
|
|
|
|
|
timedia_9079c,
|
2014-05-24 22:24:51 +04:00
|
|
|
wch_ch353_1s1p,
|
2012-09-04 18:56:12 +04:00
|
|
|
wch_ch353_2s1p,
|
2014-11-06 14:36:31 +03:00
|
|
|
wch_ch382_2s1p,
|
2013-01-28 12:49:20 +04:00
|
|
|
sunix_2s1p,
|
2005-04-17 02:20:36 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* each element directly indexed from enum list, above */
|
|
|
|
|
struct parport_pc_pci {
|
|
|
|
|
int numports;
|
|
|
|
|
struct { /* BAR (base address registers) numbers in the config
|
|
|
|
|
space header */
|
|
|
|
|
int lo;
|
|
|
|
|
int hi; /* -1 if not there, >6 for offset-method (max
|
|
|
|
|
BAR is 6) */
|
|
|
|
|
} addr[4];
|
|
|
|
|
|
|
|
|
|
/* If set, this is called immediately after pci_enable_device.
|
|
|
|
|
* If it returns non-zero, no probing will take place and the
|
|
|
|
|
* ports will not be used. */
|
|
|
|
|
int (*preinit_hook) (struct pci_dev *pdev, struct parport_pc_pci *card,
|
|
|
|
|
int autoirq, int autodma);
|
|
|
|
|
|
|
|
|
|
/* If set, this is called after probing for ports. If 'failed'
|
|
|
|
|
* is non-zero we couldn't use any of the ports. */
|
|
|
|
|
void (*postinit_hook) (struct pci_dev *pdev,
|
|
|
|
|
struct parport_pc_pci *card, int failed);
|
|
|
|
|
};
|
|
|
|
|
|
2012-12-22 01:23:14 +04:00
|
|
|
static int netmos_parallel_init(struct pci_dev *dev, struct parport_pc_pci *par,
|
|
|
|
|
int autoirq, int autodma)
|
2005-04-17 02:20:36 +04:00
|
|
|
{
|
2009-02-12 00:04:40 +03:00
|
|
|
/* the rule described below doesn't hold for this device */
|
|
|
|
|
if (dev->device == PCI_DEVICE_ID_NETMOS_9835 &&
|
|
|
|
|
dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
|
|
|
|
|
dev->subsystem_device == 0x0299)
|
|
|
|
|
return -ENODEV;
|
Basic support for Moschip 9900 family I/O chips
Add I/O based support for serial and parallel ports of the following
chips:
Vendor: Moschip (0x9710)
Parts (device IDs)
* 9900 (0x9900)
* 9904 (0x9904
* 9901 (0x9912, also sold as 9912)
* 9922 (0x9922)
On all chips but the 9900, a single port is provided per PCI subdevice
(subvendor-ID 0xA000, subdevice-IDs 0x1000 for serial, 0x2000 for
parallel with proper class codes). In cascading configurations, the
9900 provides two devices per subdevice, with subvendor-ID 0xA000 and
subdevice-IDs 0x30ps where p is the number of parallel ports and s the
number of serial ports.
Basic testing was only done on the serial part of a 9912 to the point
where it can be used for a serial kernel console, and advanced features
are completely untested. It is possible to reduce functionality of the
chips by adding a configuration EEPROM, and the datasheet [1] is
inconsistent w.r.t subdevices in the 4s+2s1p and 2s1p+4s
configurations. The subdevice-ID 0x3012 should likely read 0x3011 with
a serial port in function 3, which would be consistent with the BAR
layouts. For now, the drivers ignore subdevices with ID 0x1000 and no
class code.
The parallel ports are integrated in parport_serial even for purely
parallel parts to reduce the footprint of the patch.
[1] http://www.moschip.com/data/products/MCS9900/MCS9900_Datasheet.pdf
Signed-off-by: Nicos Gollan <gtdev@spearhead.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-05-05 23:00:37 +04:00
|
|
|
|
|
|
|
|
if (dev->device == PCI_DEVICE_ID_NETMOS_9912) {
|
|
|
|
|
par->numports = 1;
|
|
|
|
|
} else {
|
|
|
|
|
/*
|
|
|
|
|
* Netmos uses the subdevice ID to indicate the number of parallel
|
|
|
|
|
* and serial ports. The form is 0x00PS, where <P> is the number of
|
|
|
|
|
* parallel ports and <S> is the number of serial ports.
|
|
|
|
|
*/
|
|
|
|
|
par->numports = (dev->subsystem_device & 0xf0) >> 4;
|
|
|
|
|
if (par->numports > ARRAY_SIZE(par->addr))
|
|
|
|
|
par->numports = ARRAY_SIZE(par->addr);
|
|
|
|
|
}
|
|
|
|
|
|
2005-04-17 02:20:36 +04:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2012-12-22 01:23:14 +04:00
|
|
|
static struct parport_pc_pci cards[] = {
|
2005-04-17 02:20:36 +04:00
|
|
|
/* titan_110l */ { 1, { { 3, -1 }, } },
|
|
|
|
|
/* titan_210l */ { 1, { { 3, -1 }, } },
|
|
|
|
|
/* netmos_9xx5_combo */ { 1, { { 2, -1 }, }, netmos_parallel_init },
|
parport: netmos 9845 & 9855 1P4S fixes
netmos serial/parallel adapters come in different flavour differing only
by the number of parallel and serial ports, which are encoded in the
subdevice ID.
Last fix of Christian Pellegrin for 9855 2P2S broke support for 9855 1P4S,
and works only by side-effect for the first parallel port of a 2P2S, as
this first parallel port is found by reading the second addr entry of
(struct parport_pc_pci) cards[netmos_9855], which is not initialized, and
hence has value 0, which happens to be the BAR of the first parallel port.
netmos_9xx5_combo entry in (struct parport_pc_pci) cards[], which is used
for a 9845 1P4S must also be fixed for the parallel port support when
there are 4 serial ports because this entry currently gives 2 as BAR index
for the parallel port. Actually, in this case, BAR 2 is the 3rd serial
port while the parallel port is at BAR 4.
I fixed 9845 1P4S and 9855 1P4S support, while preserving 9855 2P2S support,
- by creating a netmos_9855_2p entry and using it for 9855 boards with 2
parallel ports : 9855 2P2S and 9855 2P0S boards,
- and by allowing netmos_parallel_init to change not only the number of
parallel ports (0 or 1), but making it also change the BAR index of the
parallel port when the serial ports are before the parallel port.
PS: the netmos_9855_2p entry in (struct pciserial_board)
pci_parport_serial_boards[] is needed because netmos_parallel_init has no
clean way to replace FL_BASE2 by FL_BASE4 in the description of the serial
ports in function of the number of parallel ports on the card.
Tested with 9845 1P4S, 9855 1P4S and 9855 2P2S boards.
Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Tested-by: Christian Pellegrin <chripell@fsfe.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-04-03 03:58:53 +04:00
|
|
|
/* netmos_9855 */ { 1, { { 0, -1 }, }, netmos_parallel_init },
|
|
|
|
|
/* netmos_9855_2p */ { 2, { { 0, -1 }, { 2, -1 }, } },
|
Basic support for Moschip 9900 family I/O chips
Add I/O based support for serial and parallel ports of the following
chips:
Vendor: Moschip (0x9710)
Parts (device IDs)
* 9900 (0x9900)
* 9904 (0x9904
* 9901 (0x9912, also sold as 9912)
* 9922 (0x9922)
On all chips but the 9900, a single port is provided per PCI subdevice
(subvendor-ID 0xA000, subdevice-IDs 0x1000 for serial, 0x2000 for
parallel with proper class codes). In cascading configurations, the
9900 provides two devices per subdevice, with subvendor-ID 0xA000 and
subdevice-IDs 0x30ps where p is the number of parallel ports and s the
number of serial ports.
Basic testing was only done on the serial part of a 9912 to the point
where it can be used for a serial kernel console, and advanced features
are completely untested. It is possible to reduce functionality of the
chips by adding a configuration EEPROM, and the datasheet [1] is
inconsistent w.r.t subdevices in the 4s+2s1p and 2s1p+4s
configurations. The subdevice-ID 0x3012 should likely read 0x3011 with
a serial port in function 3, which would be consistent with the BAR
layouts. For now, the drivers ignore subdevices with ID 0x1000 and no
class code.
The parallel ports are integrated in parport_serial even for purely
parallel parts to reduce the footprint of the patch.
[1] http://www.moschip.com/data/products/MCS9900/MCS9900_Datasheet.pdf
Signed-off-by: Nicos Gollan <gtdev@spearhead.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-05-05 23:00:37 +04:00
|
|
|
/* netmos_9900 */ {1, { { 3, 4 }, }, netmos_parallel_init },
|
|
|
|
|
/* netmos_9900_2p */ {2, { { 0, 1 }, { 3, 4 }, } },
|
|
|
|
|
/* netmos_99xx_1p */ {1, { { 0, 1 }, } },
|
2005-04-17 02:20:36 +04:00
|
|
|
/* avlab_1s1p */ { 1, { { 1, 2}, } },
|
|
|
|
|
/* avlab_1s2p */ { 2, { { 1, 2}, { 3, 4 },} },
|
|
|
|
|
/* avlab_2s1p */ { 1, { { 2, 3}, } },
|
|
|
|
|
/* siig_1s1p_10x */ { 1, { { 3, 4 }, } },
|
|
|
|
|
/* siig_2s1p_10x */ { 1, { { 4, 5 }, } },
|
|
|
|
|
/* siig_2p1s_20x */ { 2, { { 1, 2 }, { 3, 4 }, } },
|
|
|
|
|
/* siig_1s1p_20x */ { 1, { { 1, 2 }, } },
|
|
|
|
|
/* siig_2s1p_20x */ { 1, { { 2, 3 }, } },
|
2011-05-29 23:08:04 +04:00
|
|
|
/* timedia_4078a */ { 1, { { 2, -1 }, } },
|
|
|
|
|
/* timedia_4079h */ { 1, { { 2, 3 }, } },
|
|
|
|
|
/* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
|
|
|
|
|
/* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
|
|
|
|
|
/* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
|
|
|
|
|
/* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
|
|
|
|
|
/* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
|
|
|
|
|
/* timedia_4078u */ { 1, { { 2, -1 }, } },
|
|
|
|
|
/* timedia_4079a */ { 1, { { 2, 3 }, } },
|
|
|
|
|
/* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
|
|
|
|
|
/* timedia_4079r */ { 1, { { 2, 3 }, } },
|
|
|
|
|
/* timedia_4079s */ { 1, { { 2, 3 }, } },
|
|
|
|
|
/* timedia_4079d */ { 1, { { 2, 3 }, } },
|
|
|
|
|
/* timedia_4079e */ { 1, { { 2, 3 }, } },
|
|
|
|
|
/* timedia_4079f */ { 1, { { 2, 3 }, } },
|
|
|
|
|
/* timedia_9079a */ { 1, { { 2, 3 }, } },
|
|
|
|
|
/* timedia_9079b */ { 1, { { 2, 3 }, } },
|
|
|
|
|
/* timedia_9079c */ { 1, { { 2, 3 }, } },
|
2014-05-24 22:24:51 +04:00
|
|
|
/* wch_ch353_1s1p*/ { 1, { { 1, -1}, } },
|
2012-09-04 18:56:12 +04:00
|
|
|
/* wch_ch353_2s1p*/ { 1, { { 2, -1}, } },
|
2014-11-06 14:36:31 +03:00
|
|
|
/* wch_ch382_2s1p*/ { 1, { { 2, -1}, } },
|
2013-01-28 12:49:20 +04:00
|
|
|
/* sunix_2s1p */ { 1, { { 3, -1 }, } },
|
2005-04-17 02:20:36 +04:00
|
|
|
};
|
|
|
|
|
|
2013-01-28 12:49:20 +04:00
|
|
|
#define PCI_VENDOR_ID_SUNIX 0x1fd4
|
|
|
|
|
#define PCI_DEVICE_ID_SUNIX_1999 0x1999
|
|
|
|
|
|
2005-04-17 02:20:36 +04:00
|
|
|
static struct pci_device_id parport_serial_pci_tbl[] = {
|
|
|
|
|
/* PCI cards */
|
|
|
|
|
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_110L,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_110l },
|
|
|
|
|
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_210L,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_210l },
|
|
|
|
|
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9735,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
|
|
|
|
|
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9745,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
|
|
|
|
|
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
|
|
|
|
|
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9845,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
|
parport: netmos 9845 & 9855 1P4S fixes
netmos serial/parallel adapters come in different flavour differing only
by the number of parallel and serial ports, which are encoded in the
subdevice ID.
Last fix of Christian Pellegrin for 9855 2P2S broke support for 9855 1P4S,
and works only by side-effect for the first parallel port of a 2P2S, as
this first parallel port is found by reading the second addr entry of
(struct parport_pc_pci) cards[netmos_9855], which is not initialized, and
hence has value 0, which happens to be the BAR of the first parallel port.
netmos_9xx5_combo entry in (struct parport_pc_pci) cards[], which is used
for a 9845 1P4S must also be fixed for the parallel port support when
there are 4 serial ports because this entry currently gives 2 as BAR index
for the parallel port. Actually, in this case, BAR 2 is the 3rd serial
port while the parallel port is at BAR 4.
I fixed 9845 1P4S and 9855 1P4S support, while preserving 9855 2P2S support,
- by creating a netmos_9855_2p entry and using it for 9855 boards with 2
parallel ports : 9855 2P2S and 9855 2P0S boards,
- and by allowing netmos_parallel_init to change not only the number of
parallel ports (0 or 1), but making it also change the BAR index of the
parallel port when the serial ports are before the parallel port.
PS: the netmos_9855_2p entry in (struct pciserial_board)
pci_parport_serial_boards[] is needed because netmos_parallel_init has no
clean way to replace FL_BASE2 by FL_BASE4 in the description of the serial
ports in function of the number of parallel ports on the card.
Tested with 9845 1P4S, 9855 1P4S and 9855 2P2S boards.
Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Tested-by: Christian Pellegrin <chripell@fsfe.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-04-03 03:58:53 +04:00
|
|
|
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
|
|
|
|
|
0x1000, 0x0020, 0, 0, netmos_9855_2p },
|
|
|
|
|
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
|
|
|
|
|
0x1000, 0x0022, 0, 0, netmos_9855_2p },
|
2005-04-17 02:20:36 +04:00
|
|
|
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
|
2005-06-23 11:09:55 +04:00
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9855 },
|
Basic support for Moschip 9900 family I/O chips
Add I/O based support for serial and parallel ports of the following
chips:
Vendor: Moschip (0x9710)
Parts (device IDs)
* 9900 (0x9900)
* 9904 (0x9904
* 9901 (0x9912, also sold as 9912)
* 9922 (0x9922)
On all chips but the 9900, a single port is provided per PCI subdevice
(subvendor-ID 0xA000, subdevice-IDs 0x1000 for serial, 0x2000 for
parallel with proper class codes). In cascading configurations, the
9900 provides two devices per subdevice, with subvendor-ID 0xA000 and
subdevice-IDs 0x30ps where p is the number of parallel ports and s the
number of serial ports.
Basic testing was only done on the serial part of a 9912 to the point
where it can be used for a serial kernel console, and advanced features
are completely untested. It is possible to reduce functionality of the
chips by adding a configuration EEPROM, and the datasheet [1] is
inconsistent w.r.t subdevices in the 4s+2s1p and 2s1p+4s
configurations. The subdevice-ID 0x3012 should likely read 0x3011 with
a serial port in function 3, which would be consistent with the BAR
layouts. For now, the drivers ignore subdevices with ID 0x1000 and no
class code.
The parallel ports are integrated in parport_serial even for purely
parallel parts to reduce the footprint of the patch.
[1] http://www.moschip.com/data/products/MCS9900/MCS9900_Datasheet.pdf
Signed-off-by: Nicos Gollan <gtdev@spearhead.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-05-05 23:00:37 +04:00
|
|
|
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
|
|
|
|
|
0xA000, 0x3011, 0, 0, netmos_9900 },
|
|
|
|
|
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
|
|
|
|
|
0xA000, 0x3012, 0, 0, netmos_9900 },
|
|
|
|
|
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
|
|
|
|
|
0xA000, 0x3020, 0, 0, netmos_9900_2p },
|
|
|
|
|
{ PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
|
|
|
|
|
0xA000, 0x2000, 0, 0, netmos_99xx_1p },
|
2005-04-17 02:20:36 +04:00
|
|
|
/* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
|
2006-03-20 23:08:22 +03:00
|
|
|
{ PCI_VENDOR_ID_AFAVLAB, 0x2110,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
|
|
|
|
|
{ PCI_VENDOR_ID_AFAVLAB, 0x2111,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
|
|
|
|
|
{ PCI_VENDOR_ID_AFAVLAB, 0x2112,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
|
|
|
|
|
{ PCI_VENDOR_ID_AFAVLAB, 0x2140,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
|
|
|
|
|
{ PCI_VENDOR_ID_AFAVLAB, 0x2141,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
|
|
|
|
|
{ PCI_VENDOR_ID_AFAVLAB, 0x2142,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
|
|
|
|
|
{ PCI_VENDOR_ID_AFAVLAB, 0x2160,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
|
|
|
|
|
{ PCI_VENDOR_ID_AFAVLAB, 0x2161,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
|
|
|
|
|
{ PCI_VENDOR_ID_AFAVLAB, 0x2162,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
|
2005-04-17 02:20:36 +04:00
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_550,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
|
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_650,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
|
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_850,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
|
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_550,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
|
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_650,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
|
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_850,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
|
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_550,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
|
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_650,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
|
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_850,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
|
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_550,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
|
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_650,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x },
|
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_850,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x },
|
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_550,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
|
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_650,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
|
|
|
|
|
{ PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_850,
|
|
|
|
|
PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
|
2011-05-29 23:08:04 +04:00
|
|
|
/* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
|
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
|
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
|
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
|
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
|
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
|
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
|
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
|
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
|
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
|
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
|
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
|
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
|
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
|
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
|
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
|
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
|
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
|
|
|
|
|
{ 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
|
2013-01-28 12:49:20 +04:00
|
|
|
|
2012-09-04 18:56:12 +04:00
|
|
|
/* WCH CARDS */
|
2014-05-24 22:24:51 +04:00
|
|
|
{ 0x4348, 0x5053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, wch_ch353_1s1p},
|
2012-09-04 18:56:12 +04:00
|
|
|
{ 0x4348, 0x7053, 0x4348, 0x3253, 0, 0, wch_ch353_2s1p},
|
2014-11-06 14:36:31 +03:00
|
|
|
{ 0x1c00, 0x3250, 0x1c00, 0x3250, 0, 0, wch_ch382_2s1p},
|
2013-01-28 12:49:20 +04:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* More SUNIX variations. At least one of these has part number
|
|
|
|
|
* '5079A but subdevice 0x102. That board reports 0x0708 as
|
|
|
|
|
* its PCI Class.
|
|
|
|
|
*/
|
|
|
|
|
{ PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, PCI_VENDOR_ID_SUNIX,
|
|
|
|
|
0x0102, 0, 0, sunix_2s1p },
|
|
|
|
|
|
2005-04-17 02:20:36 +04:00
|
|
|
{ 0, } /* terminate list */
|
|
|
|
|
};
|
|
|
|
|
MODULE_DEVICE_TABLE(pci,parport_serial_pci_tbl);
|
|
|
|
|
|
2005-07-27 14:41:18 +04:00
|
|
|
/*
|
|
|
|
|
* This table describes the serial "geometry" of these boards. Any
|
|
|
|
|
* quirks for these can be found in drivers/serial/8250_pci.c
|
|
|
|
|
*
|
|
|
|
|
* Cards not tested are marked n/t
|
|
|
|
|
* If you have one of these cards and it works for you, please tell me..
|
|
|
|
|
*/
|
2012-12-22 01:23:14 +04:00
|
|
|
static struct pciserial_board pci_parport_serial_boards[] = {
|
2005-07-27 14:41:18 +04:00
|
|
|
[titan_110l] = {
|
|
|
|
|
.flags = FL_BASE1 | FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[titan_210l] = {
|
|
|
|
|
.flags = FL_BASE1 | FL_BASE_BARS,
|
|
|
|
|
.num_ports = 2,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[netmos_9xx5_combo] = {
|
|
|
|
|
.flags = FL_BASE0 | FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 115200,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[netmos_9855] = {
|
parport: netmos 9845 & 9855 1P4S fixes
netmos serial/parallel adapters come in different flavour differing only
by the number of parallel and serial ports, which are encoded in the
subdevice ID.
Last fix of Christian Pellegrin for 9855 2P2S broke support for 9855 1P4S,
and works only by side-effect for the first parallel port of a 2P2S, as
this first parallel port is found by reading the second addr entry of
(struct parport_pc_pci) cards[netmos_9855], which is not initialized, and
hence has value 0, which happens to be the BAR of the first parallel port.
netmos_9xx5_combo entry in (struct parport_pc_pci) cards[], which is used
for a 9845 1P4S must also be fixed for the parallel port support when
there are 4 serial ports because this entry currently gives 2 as BAR index
for the parallel port. Actually, in this case, BAR 2 is the 3rd serial
port while the parallel port is at BAR 4.
I fixed 9845 1P4S and 9855 1P4S support, while preserving 9855 2P2S support,
- by creating a netmos_9855_2p entry and using it for 9855 boards with 2
parallel ports : 9855 2P2S and 9855 2P0S boards,
- and by allowing netmos_parallel_init to change not only the number of
parallel ports (0 or 1), but making it also change the BAR index of the
parallel port when the serial ports are before the parallel port.
PS: the netmos_9855_2p entry in (struct pciserial_board)
pci_parport_serial_boards[] is needed because netmos_parallel_init has no
clean way to replace FL_BASE2 by FL_BASE4 in the description of the serial
ports in function of the number of parallel ports on the card.
Tested with 9845 1P4S, 9855 1P4S and 9855 2P2S boards.
Signed-off-by: Philippe De Muyter <phdm@macqel.be>
Tested-by: Christian Pellegrin <chripell@fsfe.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2009-04-03 03:58:53 +04:00
|
|
|
.flags = FL_BASE2 | FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 115200,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[netmos_9855_2p] = {
|
2008-02-06 12:37:44 +03:00
|
|
|
.flags = FL_BASE4 | FL_BASE_BARS,
|
2005-07-27 14:41:18 +04:00
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 115200,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
Basic support for Moschip 9900 family I/O chips
Add I/O based support for serial and parallel ports of the following
chips:
Vendor: Moschip (0x9710)
Parts (device IDs)
* 9900 (0x9900)
* 9904 (0x9904
* 9901 (0x9912, also sold as 9912)
* 9922 (0x9922)
On all chips but the 9900, a single port is provided per PCI subdevice
(subvendor-ID 0xA000, subdevice-IDs 0x1000 for serial, 0x2000 for
parallel with proper class codes). In cascading configurations, the
9900 provides two devices per subdevice, with subvendor-ID 0xA000 and
subdevice-IDs 0x30ps where p is the number of parallel ports and s the
number of serial ports.
Basic testing was only done on the serial part of a 9912 to the point
where it can be used for a serial kernel console, and advanced features
are completely untested. It is possible to reduce functionality of the
chips by adding a configuration EEPROM, and the datasheet [1] is
inconsistent w.r.t subdevices in the 4s+2s1p and 2s1p+4s
configurations. The subdevice-ID 0x3012 should likely read 0x3011 with
a serial port in function 3, which would be consistent with the BAR
layouts. For now, the drivers ignore subdevices with ID 0x1000 and no
class code.
The parallel ports are integrated in parport_serial even for purely
parallel parts to reduce the footprint of the patch.
[1] http://www.moschip.com/data/products/MCS9900/MCS9900_Datasheet.pdf
Signed-off-by: Nicos Gollan <gtdev@spearhead.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-05-05 23:00:37 +04:00
|
|
|
[netmos_9900] = { /* n/t */
|
|
|
|
|
.flags = FL_BASE0 | FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 115200,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[netmos_9900_2p] = { /* parallel only */ /* n/t */
|
|
|
|
|
.flags = FL_BASE0,
|
|
|
|
|
.num_ports = 0,
|
|
|
|
|
.base_baud = 115200,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[netmos_99xx_1p] = { /* parallel only */ /* n/t */
|
|
|
|
|
.flags = FL_BASE0,
|
|
|
|
|
.num_ports = 0,
|
|
|
|
|
.base_baud = 115200,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
2005-07-27 14:41:18 +04:00
|
|
|
[avlab_1s1p] = { /* n/t */
|
|
|
|
|
.flags = FL_BASE0 | FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 115200,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[avlab_1s2p] = { /* n/t */
|
|
|
|
|
.flags = FL_BASE0 | FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 115200,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[avlab_2s1p] = { /* n/t */
|
|
|
|
|
.flags = FL_BASE0 | FL_BASE_BARS,
|
|
|
|
|
.num_ports = 2,
|
|
|
|
|
.base_baud = 115200,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[siig_1s1p_10x] = {
|
|
|
|
|
.flags = FL_BASE2,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 460800,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[siig_2s1p_10x] = {
|
|
|
|
|
.flags = FL_BASE2,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[siig_2p1s_20x] = {
|
|
|
|
|
.flags = FL_BASE0,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[siig_1s1p_20x] = {
|
|
|
|
|
.flags = FL_BASE0,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[siig_2s1p_20x] = {
|
|
|
|
|
.flags = FL_BASE0,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
2011-05-29 23:08:04 +04:00
|
|
|
[timedia_4078a] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[timedia_4079h] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[timedia_4085h] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[timedia_4088a] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[timedia_4089a] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[timedia_4095a] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[timedia_4096a] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[timedia_4078u] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[timedia_4079a] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[timedia_4085u] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[timedia_4079r] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[timedia_4079s] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[timedia_4079d] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[timedia_4079e] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[timedia_4079f] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[timedia_9079a] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[timedia_9079b] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
|
|
|
|
[timedia_9079c] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
2014-05-24 22:24:51 +04:00
|
|
|
[wch_ch353_1s1p] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 1,
|
|
|
|
|
.base_baud = 115200,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
2012-09-04 18:56:12 +04:00
|
|
|
[wch_ch353_2s1p] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 2,
|
|
|
|
|
.base_baud = 115200,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
2014-11-06 14:36:31 +03:00
|
|
|
[wch_ch382_2s1p] = {
|
|
|
|
|
.flags = FL_BASE0,
|
|
|
|
|
.num_ports = 2,
|
|
|
|
|
.base_baud = 115200,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
.first_offset = 0xC0,
|
|
|
|
|
},
|
2013-01-28 12:49:20 +04:00
|
|
|
[sunix_2s1p] = {
|
|
|
|
|
.flags = FL_BASE0|FL_BASE_BARS,
|
|
|
|
|
.num_ports = 2,
|
|
|
|
|
.base_baud = 921600,
|
|
|
|
|
.uart_offset = 8,
|
|
|
|
|
},
|
2005-04-17 02:20:36 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct parport_serial_private {
|
2005-07-27 14:41:18 +04:00
|
|
|
struct serial_private *serial;
|
2005-04-17 02:20:36 +04:00
|
|
|
int num_par;
|
|
|
|
|
struct parport *port[PARPORT_MAX];
|
|
|
|
|
struct parport_pc_pci par;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Register the serial port(s) of a PCI card. */
|
2012-12-22 01:23:14 +04:00
|
|
|
static int serial_register(struct pci_dev *dev, const struct pci_device_id *id)
|
2005-04-17 02:20:36 +04:00
|
|
|
{
|
|
|
|
|
struct parport_serial_private *priv = pci_get_drvdata (dev);
|
2005-07-27 14:41:18 +04:00
|
|
|
struct pciserial_board *board;
|
|
|
|
|
struct serial_private *serial;
|
2005-04-17 02:20:36 +04:00
|
|
|
|
2005-07-27 14:41:18 +04:00
|
|
|
board = &pci_parport_serial_boards[id->driver_data];
|
Basic support for Moschip 9900 family I/O chips
Add I/O based support for serial and parallel ports of the following
chips:
Vendor: Moschip (0x9710)
Parts (device IDs)
* 9900 (0x9900)
* 9904 (0x9904
* 9901 (0x9912, also sold as 9912)
* 9922 (0x9922)
On all chips but the 9900, a single port is provided per PCI subdevice
(subvendor-ID 0xA000, subdevice-IDs 0x1000 for serial, 0x2000 for
parallel with proper class codes). In cascading configurations, the
9900 provides two devices per subdevice, with subvendor-ID 0xA000 and
subdevice-IDs 0x30ps where p is the number of parallel ports and s the
number of serial ports.
Basic testing was only done on the serial part of a 9912 to the point
where it can be used for a serial kernel console, and advanced features
are completely untested. It is possible to reduce functionality of the
chips by adding a configuration EEPROM, and the datasheet [1] is
inconsistent w.r.t subdevices in the 4s+2s1p and 2s1p+4s
configurations. The subdevice-ID 0x3012 should likely read 0x3011 with
a serial port in function 3, which would be consistent with the BAR
layouts. For now, the drivers ignore subdevices with ID 0x1000 and no
class code.
The parallel ports are integrated in parport_serial even for purely
parallel parts to reduce the footprint of the patch.
[1] http://www.moschip.com/data/products/MCS9900/MCS9900_Datasheet.pdf
Signed-off-by: Nicos Gollan <gtdev@spearhead.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-05-05 23:00:37 +04:00
|
|
|
|
|
|
|
|
if (board->num_ports == 0)
|
|
|
|
|
return 0;
|
|
|
|
|
|
2005-07-27 14:41:18 +04:00
|
|
|
serial = pciserial_init_ports(dev, board);
|
2005-04-17 02:20:36 +04:00
|
|
|
|
2005-07-27 14:41:18 +04:00
|
|
|
if (IS_ERR(serial))
|
|
|
|
|
return PTR_ERR(serial);
|
2005-04-17 02:20:36 +04:00
|
|
|
|
2005-07-27 14:41:18 +04:00
|
|
|
priv->serial = serial;
|
|
|
|
|
return 0;
|
2005-04-17 02:20:36 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Register the parallel port(s) of a PCI card. */
|
2012-12-22 01:23:14 +04:00
|
|
|
static int parport_register(struct pci_dev *dev, const struct pci_device_id *id)
|
2005-04-17 02:20:36 +04:00
|
|
|
{
|
|
|
|
|
struct parport_pc_pci *card;
|
|
|
|
|
struct parport_serial_private *priv = pci_get_drvdata (dev);
|
2006-03-05 03:31:22 +03:00
|
|
|
int n, success = 0;
|
2005-04-17 02:20:36 +04:00
|
|
|
|
|
|
|
|
priv->par = cards[id->driver_data];
|
|
|
|
|
card = &priv->par;
|
|
|
|
|
if (card->preinit_hook &&
|
|
|
|
|
card->preinit_hook (dev, card, PARPORT_IRQ_NONE, PARPORT_DMA_NONE))
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
|
|
for (n = 0; n < card->numports; n++) {
|
|
|
|
|
struct parport *port;
|
|
|
|
|
int lo = card->addr[n].lo;
|
|
|
|
|
int hi = card->addr[n].hi;
|
|
|
|
|
unsigned long io_lo, io_hi;
|
2009-04-07 18:30:57 +04:00
|
|
|
int irq;
|
2005-04-17 02:20:36 +04:00
|
|
|
|
|
|
|
|
if (priv->num_par == ARRAY_SIZE (priv->port)) {
|
|
|
|
|
printk (KERN_WARNING
|
2006-02-03 14:04:02 +03:00
|
|
|
"parport_serial: %s: only %zu parallel ports "
|
2005-04-17 02:20:36 +04:00
|
|
|
"supported (%d reported)\n", pci_name (dev),
|
2006-02-03 14:04:02 +03:00
|
|
|
ARRAY_SIZE(priv->port), card->numports);
|
2005-04-17 02:20:36 +04:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
io_lo = pci_resource_start (dev, lo);
|
|
|
|
|
io_hi = 0;
|
|
|
|
|
if ((hi >= 0) && (hi <= 6))
|
|
|
|
|
io_hi = pci_resource_start (dev, hi);
|
|
|
|
|
else if (hi > 6)
|
|
|
|
|
io_lo += hi; /* Reinterpret the meaning of
|
|
|
|
|
"hi" as an offset (see SYBA
|
|
|
|
|
def.) */
|
|
|
|
|
/* TODO: test if sharing interrupts works */
|
2009-04-07 18:30:57 +04:00
|
|
|
irq = dev->irq;
|
|
|
|
|
if (irq == IRQ_NONE) {
|
|
|
|
|
dev_dbg(&dev->dev,
|
|
|
|
|
"PCI parallel port detected: I/O at %#lx(%#lx)\n",
|
|
|
|
|
io_lo, io_hi);
|
|
|
|
|
irq = PARPORT_IRQ_NONE;
|
|
|
|
|
} else {
|
|
|
|
|
dev_dbg(&dev->dev,
|
|
|
|
|
"PCI parallel port detected: I/O at %#lx(%#lx), IRQ %d\n",
|
|
|
|
|
io_lo, io_hi, irq);
|
|
|
|
|
}
|
|
|
|
|
port = parport_pc_probe_port (io_lo, io_hi, irq,
|
|
|
|
|
PARPORT_DMA_NONE, &dev->dev, IRQF_SHARED);
|
2005-04-17 02:20:36 +04:00
|
|
|
if (port) {
|
|
|
|
|
priv->port[priv->num_par++] = port;
|
|
|
|
|
success = 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (card->postinit_hook)
|
|
|
|
|
card->postinit_hook (dev, card, !success);
|
|
|
|
|
|
2006-03-05 03:31:22 +03:00
|
|
|
return 0;
|
2005-04-17 02:20:36 +04:00
|
|
|
}
|
|
|
|
|
|
2012-12-22 01:23:14 +04:00
|
|
|
static int parport_serial_pci_probe(struct pci_dev *dev,
|
|
|
|
|
const struct pci_device_id *id)
|
2005-04-17 02:20:36 +04:00
|
|
|
{
|
|
|
|
|
struct parport_serial_private *priv;
|
|
|
|
|
int err;
|
|
|
|
|
|
some kmalloc/memset ->kzalloc (tree wide)
Transform some calls to kmalloc/memset to a single kzalloc (or kcalloc).
Here is a short excerpt of the semantic patch performing
this transformation:
@@
type T2;
expression x;
identifier f,fld;
expression E;
expression E1,E2;
expression e1,e2,e3,y;
statement S;
@@
x =
- kmalloc
+ kzalloc
(E1,E2)
... when != \(x->fld=E;\|y=f(...,x,...);\|f(...,x,...);\|x=E;\|while(...) S\|for(e1;e2;e3) S\)
- memset((T2)x,0,E1);
@@
expression E1,E2,E3;
@@
- kzalloc(E1 * E2,E3)
+ kcalloc(E1,E2,E3)
[akpm@linux-foundation.org: get kcalloc args the right way around]
Signed-off-by: Yoann Padioleau <padator@wanadoo.fr>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Acked-by: Russell King <rmk@arm.linux.org.uk>
Cc: Bryan Wu <bryan.wu@analog.com>
Acked-by: Jiri Slaby <jirislaby@gmail.com>
Cc: Dave Airlie <airlied@linux.ie>
Acked-by: Roland Dreier <rolandd@cisco.com>
Cc: Jiri Kosina <jkosina@suse.cz>
Acked-by: Dmitry Torokhov <dtor@mail.ru>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Acked-by: Pierre Ossman <drzeus-list@drzeus.cx>
Cc: Jeff Garzik <jeff@garzik.org>
Cc: "David S. Miller" <davem@davemloft.net>
Acked-by: Greg KH <greg@kroah.com>
Cc: James Bottomley <James.Bottomley@steeleye.com>
Cc: "Antonino A. Daplas" <adaplas@pol.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-07-19 12:49:03 +04:00
|
|
|
priv = kzalloc (sizeof *priv, GFP_KERNEL);
|
2005-04-17 02:20:36 +04:00
|
|
|
if (!priv)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
pci_set_drvdata (dev, priv);
|
|
|
|
|
|
|
|
|
|
err = pci_enable_device (dev);
|
|
|
|
|
if (err) {
|
|
|
|
|
kfree (priv);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (parport_register (dev, id)) {
|
|
|
|
|
kfree (priv);
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (serial_register (dev, id)) {
|
|
|
|
|
int i;
|
|
|
|
|
for (i = 0; i < priv->num_par; i++)
|
|
|
|
|
parport_pc_unregister_port (priv->port[i]);
|
|
|
|
|
kfree (priv);
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2012-12-22 01:23:14 +04:00
|
|
|
static void parport_serial_pci_remove(struct pci_dev *dev)
|
2005-04-17 02:20:36 +04:00
|
|
|
{
|
|
|
|
|
struct parport_serial_private *priv = pci_get_drvdata (dev);
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
// Serial ports
|
2005-07-27 14:41:18 +04:00
|
|
|
if (priv->serial)
|
|
|
|
|
pciserial_remove_ports(priv->serial);
|
2005-04-17 02:20:36 +04:00
|
|
|
|
|
|
|
|
// Parallel ports
|
|
|
|
|
for (i = 0; i < priv->num_par; i++)
|
|
|
|
|
parport_pc_unregister_port (priv->port[i]);
|
|
|
|
|
|
|
|
|
|
kfree (priv);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2006-09-29 13:00:16 +04:00
|
|
|
#ifdef CONFIG_PM
|
2005-07-27 14:41:18 +04:00
|
|
|
static int parport_serial_pci_suspend(struct pci_dev *dev, pm_message_t state)
|
|
|
|
|
{
|
|
|
|
|
struct parport_serial_private *priv = pci_get_drvdata(dev);
|
|
|
|
|
|
|
|
|
|
if (priv->serial)
|
|
|
|
|
pciserial_suspend_ports(priv->serial);
|
|
|
|
|
|
|
|
|
|
/* FIXME: What about parport? */
|
|
|
|
|
|
|
|
|
|
pci_save_state(dev);
|
|
|
|
|
pci_set_power_state(dev, pci_choose_state(dev, state));
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int parport_serial_pci_resume(struct pci_dev *dev)
|
|
|
|
|
{
|
|
|
|
|
struct parport_serial_private *priv = pci_get_drvdata(dev);
|
2007-05-08 11:29:01 +04:00
|
|
|
int err;
|
2005-07-27 14:41:18 +04:00
|
|
|
|
|
|
|
|
pci_set_power_state(dev, PCI_D0);
|
|
|
|
|
pci_restore_state(dev);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The device may have been disabled. Re-enable it.
|
|
|
|
|
*/
|
2007-05-08 11:29:01 +04:00
|
|
|
err = pci_enable_device(dev);
|
|
|
|
|
if (err) {
|
|
|
|
|
printk(KERN_ERR "parport_serial: %s: error enabling "
|
|
|
|
|
"device for resume (%d)\n", pci_name(dev), err);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
2005-07-27 14:41:18 +04:00
|
|
|
|
|
|
|
|
if (priv->serial)
|
|
|
|
|
pciserial_resume_ports(priv->serial);
|
|
|
|
|
|
|
|
|
|
/* FIXME: What about parport? */
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2006-09-29 13:00:16 +04:00
|
|
|
#endif
|
2005-07-27 14:41:18 +04:00
|
|
|
|
2005-04-17 02:20:36 +04:00
|
|
|
static struct pci_driver parport_serial_pci_driver = {
|
|
|
|
|
.name = "parport_serial",
|
|
|
|
|
.id_table = parport_serial_pci_tbl,
|
|
|
|
|
.probe = parport_serial_pci_probe,
|
2012-12-22 01:23:14 +04:00
|
|
|
.remove = parport_serial_pci_remove,
|
2006-09-29 13:00:16 +04:00
|
|
|
#ifdef CONFIG_PM
|
2005-07-27 14:41:18 +04:00
|
|
|
.suspend = parport_serial_pci_suspend,
|
|
|
|
|
.resume = parport_serial_pci_resume,
|
2006-09-29 13:00:16 +04:00
|
|
|
#endif
|
2005-04-17 02:20:36 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static int __init parport_serial_init (void)
|
|
|
|
|
{
|
2005-11-30 03:00:35 +03:00
|
|
|
return pci_register_driver (&parport_serial_pci_driver);
|
2005-04-17 02:20:36 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __exit parport_serial_exit (void)
|
|
|
|
|
{
|
|
|
|
|
pci_unregister_driver (&parport_serial_pci_driver);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Tim Waugh <twaugh@redhat.com>");
|
|
|
|
|
MODULE_DESCRIPTION("Driver for common parallel+serial multi-I/O PCI cards");
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
|
|
|
|
|
|
module_init(parport_serial_init);
|
|
|
|
|
module_exit(parport_serial_exit);
|
