2005-04-17 02:20:36 +04:00
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/*
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* linux/arch/arm/mm/flush.c
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*
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* Copyright (C) 1995-2002 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/pagemap.h>
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2010-12-15 23:14:45 +03:00
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#include <linux/highmem.h>
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2005-04-17 02:20:36 +04:00
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#include <asm/cacheflush.h>
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2008-08-10 21:10:19 +04:00
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#include <asm/cachetype.h>
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2010-03-30 00:46:02 +04:00
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#include <asm/highmem.h>
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2009-11-05 16:29:36 +03:00
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#include <asm/smp_plat.h>
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2005-05-10 20:31:43 +04:00
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#include <asm/tlbflush.h>
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2013-05-17 15:33:28 +04:00
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#include <linux/hugetlb.h>
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2005-05-10 20:31:43 +04:00
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2006-08-21 20:06:38 +04:00
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#include "mm.h"
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ARM: move heavy barrier support out of line
The existing memory barrier macro causes a significant amount of code
to be inserted inline at every call site. For example, in
gpio_set_irq_type(), we have this for mb():
c0344c08: f57ff04e dsb st
c0344c0c: e59f8190 ldr r8, [pc, #400] ; c0344da4 <gpio_set_irq_type+0x230>
c0344c10: e3590004 cmp r9, #4
c0344c14: e5983014 ldr r3, [r8, #20]
c0344c18: 0a000054 beq c0344d70 <gpio_set_irq_type+0x1fc>
c0344c1c: e3530000 cmp r3, #0
c0344c20: 0a000004 beq c0344c38 <gpio_set_irq_type+0xc4>
c0344c24: e50b2030 str r2, [fp, #-48] ; 0xffffffd0
c0344c28: e50bc034 str ip, [fp, #-52] ; 0xffffffcc
c0344c2c: e12fff33 blx r3
c0344c30: e51bc034 ldr ip, [fp, #-52] ; 0xffffffcc
c0344c34: e51b2030 ldr r2, [fp, #-48] ; 0xffffffd0
c0344c38: e5963004 ldr r3, [r6, #4]
Moving the outer_cache_sync() call out of line reduces the impact of
the barrier:
c0344968: f57ff04e dsb st
c034496c: e35a0004 cmp sl, #4
c0344970: e50b2030 str r2, [fp, #-48] ; 0xffffffd0
c0344974: 0a000044 beq c0344a8c <gpio_set_irq_type+0x1b8>
c0344978: ebf363dd bl c001d8f4 <arm_heavy_mb>
c034497c: e5953004 ldr r3, [r5, #4]
This should reduce the cache footprint of this code. Overall, this
results in a reduction of around 20K in the kernel size:
text data bss dec hex filename
10773970 667392 10369656 21811018 14ccf4a ../build/imx6/vmlinux-old
10754219 667392 10369656 21791267 14c8223 ../build/imx6/vmlinux-new
Another advantage to this approach is that we can finally resolve the
issue of SoCs which have their own memory barrier requirements within
multiplatform kernels (such as OMAP.) Here, the bus interconnects
need additional handling to ensure that writes become visible in the
correct order (eg, between dma_map() operations, writes to DMA
coherent memory, and MMIO accesses.)
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-06-02 01:44:46 +03:00
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#ifdef CONFIG_ARM_HEAVY_MB
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2015-06-03 15:10:16 +03:00
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void (*soc_mb)(void);
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ARM: move heavy barrier support out of line
The existing memory barrier macro causes a significant amount of code
to be inserted inline at every call site. For example, in
gpio_set_irq_type(), we have this for mb():
c0344c08: f57ff04e dsb st
c0344c0c: e59f8190 ldr r8, [pc, #400] ; c0344da4 <gpio_set_irq_type+0x230>
c0344c10: e3590004 cmp r9, #4
c0344c14: e5983014 ldr r3, [r8, #20]
c0344c18: 0a000054 beq c0344d70 <gpio_set_irq_type+0x1fc>
c0344c1c: e3530000 cmp r3, #0
c0344c20: 0a000004 beq c0344c38 <gpio_set_irq_type+0xc4>
c0344c24: e50b2030 str r2, [fp, #-48] ; 0xffffffd0
c0344c28: e50bc034 str ip, [fp, #-52] ; 0xffffffcc
c0344c2c: e12fff33 blx r3
c0344c30: e51bc034 ldr ip, [fp, #-52] ; 0xffffffcc
c0344c34: e51b2030 ldr r2, [fp, #-48] ; 0xffffffd0
c0344c38: e5963004 ldr r3, [r6, #4]
Moving the outer_cache_sync() call out of line reduces the impact of
the barrier:
c0344968: f57ff04e dsb st
c034496c: e35a0004 cmp sl, #4
c0344970: e50b2030 str r2, [fp, #-48] ; 0xffffffd0
c0344974: 0a000044 beq c0344a8c <gpio_set_irq_type+0x1b8>
c0344978: ebf363dd bl c001d8f4 <arm_heavy_mb>
c034497c: e5953004 ldr r3, [r5, #4]
This should reduce the cache footprint of this code. Overall, this
results in a reduction of around 20K in the kernel size:
text data bss dec hex filename
10773970 667392 10369656 21811018 14ccf4a ../build/imx6/vmlinux-old
10754219 667392 10369656 21791267 14c8223 ../build/imx6/vmlinux-new
Another advantage to this approach is that we can finally resolve the
issue of SoCs which have their own memory barrier requirements within
multiplatform kernels (such as OMAP.) Here, the bus interconnects
need additional handling to ensure that writes become visible in the
correct order (eg, between dma_map() operations, writes to DMA
coherent memory, and MMIO accesses.)
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-06-02 01:44:46 +03:00
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void arm_heavy_mb(void)
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{
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#ifdef CONFIG_OUTER_CACHE_SYNC
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if (outer_cache.sync)
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outer_cache.sync();
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#endif
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2015-06-03 15:10:16 +03:00
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if (soc_mb)
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soc_mb();
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ARM: move heavy barrier support out of line
The existing memory barrier macro causes a significant amount of code
to be inserted inline at every call site. For example, in
gpio_set_irq_type(), we have this for mb():
c0344c08: f57ff04e dsb st
c0344c0c: e59f8190 ldr r8, [pc, #400] ; c0344da4 <gpio_set_irq_type+0x230>
c0344c10: e3590004 cmp r9, #4
c0344c14: e5983014 ldr r3, [r8, #20]
c0344c18: 0a000054 beq c0344d70 <gpio_set_irq_type+0x1fc>
c0344c1c: e3530000 cmp r3, #0
c0344c20: 0a000004 beq c0344c38 <gpio_set_irq_type+0xc4>
c0344c24: e50b2030 str r2, [fp, #-48] ; 0xffffffd0
c0344c28: e50bc034 str ip, [fp, #-52] ; 0xffffffcc
c0344c2c: e12fff33 blx r3
c0344c30: e51bc034 ldr ip, [fp, #-52] ; 0xffffffcc
c0344c34: e51b2030 ldr r2, [fp, #-48] ; 0xffffffd0
c0344c38: e5963004 ldr r3, [r6, #4]
Moving the outer_cache_sync() call out of line reduces the impact of
the barrier:
c0344968: f57ff04e dsb st
c034496c: e35a0004 cmp sl, #4
c0344970: e50b2030 str r2, [fp, #-48] ; 0xffffffd0
c0344974: 0a000044 beq c0344a8c <gpio_set_irq_type+0x1b8>
c0344978: ebf363dd bl c001d8f4 <arm_heavy_mb>
c034497c: e5953004 ldr r3, [r5, #4]
This should reduce the cache footprint of this code. Overall, this
results in a reduction of around 20K in the kernel size:
text data bss dec hex filename
10773970 667392 10369656 21811018 14ccf4a ../build/imx6/vmlinux-old
10754219 667392 10369656 21791267 14c8223 ../build/imx6/vmlinux-new
Another advantage to this approach is that we can finally resolve the
issue of SoCs which have their own memory barrier requirements within
multiplatform kernels (such as OMAP.) Here, the bus interconnects
need additional handling to ensure that writes become visible in the
correct order (eg, between dma_map() operations, writes to DMA
coherent memory, and MMIO accesses.)
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-06-02 01:44:46 +03:00
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}
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EXPORT_SYMBOL(arm_heavy_mb);
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#endif
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2005-05-10 20:31:43 +04:00
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#ifdef CONFIG_CPU_CACHE_VIPT
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2005-09-08 18:32:23 +04:00
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2005-09-30 19:07:04 +04:00
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static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
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{
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2011-07-02 17:46:27 +04:00
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unsigned long to = FLUSH_ALIAS_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
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2006-03-11 01:26:47 +03:00
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const int zero = 0;
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2005-09-30 19:07:04 +04:00
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2011-07-02 18:20:44 +04:00
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set_top_pte(to, pfn_pte(pfn, PAGE_KERNEL));
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2005-09-30 19:07:04 +04:00
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asm( "mcrr p15, 0, %1, %0, c14\n"
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2009-10-25 01:36:36 +04:00
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" mcr p15, 0, %2, c7, c10, 4"
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2005-09-30 19:07:04 +04:00
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:
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2014-11-29 04:54:27 +03:00
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: "r" (to), "r" (to + PAGE_SIZE - 1), "r" (zero)
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2005-09-30 19:07:04 +04:00
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: "cc");
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}
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2010-09-13 19:19:41 +04:00
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static void flush_icache_alias(unsigned long pfn, unsigned long vaddr, unsigned long len)
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{
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2011-07-02 18:20:44 +04:00
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unsigned long va = FLUSH_ALIAS_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
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2010-09-13 19:19:41 +04:00
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unsigned long offset = vaddr & (PAGE_SIZE - 1);
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unsigned long to;
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2011-07-02 18:20:44 +04:00
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set_top_pte(va, pfn_pte(pfn, PAGE_KERNEL));
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to = va + offset;
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2010-09-13 19:19:41 +04:00
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flush_icache_range(to, to + len);
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}
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2005-09-08 18:32:23 +04:00
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void flush_cache_mm(struct mm_struct *mm)
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{
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if (cache_is_vivt()) {
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2009-10-25 13:40:02 +03:00
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vivt_flush_cache_mm(mm);
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2005-09-08 18:32:23 +04:00
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return;
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}
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if (cache_is_vipt_aliasing()) {
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asm( "mcr p15, 0, %0, c7, c14, 0\n"
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2009-10-25 01:36:36 +04:00
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" mcr p15, 0, %0, c7, c10, 4"
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2005-09-08 18:32:23 +04:00
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:
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: "r" (0)
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: "cc");
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}
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}
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void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
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{
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if (cache_is_vivt()) {
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2009-10-25 13:40:02 +03:00
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vivt_flush_cache_range(vma, start, end);
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2005-09-08 18:32:23 +04:00
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return;
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}
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if (cache_is_vipt_aliasing()) {
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asm( "mcr p15, 0, %0, c7, c14, 0\n"
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2009-10-25 01:36:36 +04:00
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" mcr p15, 0, %0, c7, c10, 4"
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2005-09-08 18:32:23 +04:00
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:
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: "r" (0)
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: "cc");
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}
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2009-10-25 16:35:13 +03:00
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2009-10-25 17:12:27 +03:00
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if (vma->vm_flags & VM_EXEC)
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2009-10-25 16:35:13 +03:00
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__flush_icache_all();
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2005-09-08 18:32:23 +04:00
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}
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void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
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{
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if (cache_is_vivt()) {
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2009-10-25 13:40:02 +03:00
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vivt_flush_cache_page(vma, user_addr, pfn);
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2005-09-08 18:32:23 +04:00
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return;
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}
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2009-10-25 01:58:40 +04:00
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if (cache_is_vipt_aliasing()) {
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2005-09-08 18:32:23 +04:00
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flush_pfn_alias(pfn, user_addr);
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2009-10-25 01:58:40 +04:00
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__flush_icache_all();
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}
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2009-10-25 16:35:13 +03:00
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if (vma->vm_flags & VM_EXEC && icache_is_vivt_asid_tagged())
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__flush_icache_all();
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2005-09-08 18:32:23 +04:00
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}
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2010-09-13 19:19:41 +04:00
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2009-11-05 16:29:36 +03:00
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#else
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2010-09-13 19:19:41 +04:00
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#define flush_pfn_alias(pfn,vaddr) do { } while (0)
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#define flush_icache_alias(pfn,vaddr,len) do { } while (0)
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2009-11-05 16:29:36 +03:00
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#endif
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2006-09-02 21:43:20 +04:00
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2014-04-29 07:20:52 +04:00
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#define FLAG_PA_IS_EXEC 1
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#define FLAG_PA_CORE_IN_MM 2
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2009-11-05 16:29:36 +03:00
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static void flush_ptrace_access_other(void *args)
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{
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__flush_icache_all();
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}
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2014-04-29 07:20:52 +04:00
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static inline
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void __flush_ptrace_access(struct page *page, unsigned long uaddr, void *kaddr,
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unsigned long len, unsigned int flags)
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2006-09-02 21:43:20 +04:00
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{
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if (cache_is_vivt()) {
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2014-04-29 07:20:52 +04:00
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if (flags & FLAG_PA_CORE_IN_MM) {
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2009-11-05 16:29:36 +03:00
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unsigned long addr = (unsigned long)kaddr;
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__cpuc_coherent_kern_range(addr, addr + len);
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}
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2006-09-02 21:43:20 +04:00
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return;
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}
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if (cache_is_vipt_aliasing()) {
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flush_pfn_alias(page_to_pfn(page), uaddr);
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2009-10-25 01:58:40 +04:00
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__flush_icache_all();
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2006-09-02 21:43:20 +04:00
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return;
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}
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2010-09-13 19:19:41 +04:00
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/* VIPT non-aliasing D-cache */
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2014-04-29 07:20:52 +04:00
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if (flags & FLAG_PA_IS_EXEC) {
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2006-09-02 21:43:20 +04:00
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unsigned long addr = (unsigned long)kaddr;
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2010-09-13 19:19:41 +04:00
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if (icache_is_vipt_aliasing())
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flush_icache_alias(page_to_pfn(page), uaddr, len);
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else
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__cpuc_coherent_kern_range(addr, addr + len);
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2009-11-05 16:29:36 +03:00
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if (cache_ops_need_broadcast())
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smp_call_function(flush_ptrace_access_other,
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NULL, 1);
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2006-09-02 21:43:20 +04:00
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}
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}
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2009-11-05 16:29:36 +03:00
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2014-04-29 07:20:52 +04:00
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static
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void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
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unsigned long uaddr, void *kaddr, unsigned long len)
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{
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unsigned int flags = 0;
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if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)))
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flags |= FLAG_PA_CORE_IN_MM;
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if (vma->vm_flags & VM_EXEC)
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flags |= FLAG_PA_IS_EXEC;
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__flush_ptrace_access(page, uaddr, kaddr, len, flags);
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}
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void flush_uprobe_xol_access(struct page *page, unsigned long uaddr,
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void *kaddr, unsigned long len)
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{
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unsigned int flags = FLAG_PA_CORE_IN_MM|FLAG_PA_IS_EXEC;
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__flush_ptrace_access(page, uaddr, kaddr, len, flags);
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}
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2009-11-05 16:29:36 +03:00
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/*
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* Copy user data from/to a page which is mapped into a different
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* processes address space. Really, we want to allow our "user
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* space" model to handle this.
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*
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* Note that this code needs to run on the current CPU.
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*/
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void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long uaddr, void *dst, const void *src,
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unsigned long len)
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{
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#ifdef CONFIG_SMP
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preempt_disable();
|
2005-05-10 20:31:43 +04:00
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#endif
|
2009-11-05 16:29:36 +03:00
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memcpy(dst, src, len);
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flush_ptrace_access(vma, page, uaddr, dst, len);
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#ifdef CONFIG_SMP
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preempt_enable();
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#endif
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}
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2005-04-17 02:20:36 +04:00
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2005-06-20 12:51:03 +04:00
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void __flush_dcache_page(struct address_space *mapping, struct page *page)
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2005-04-17 02:20:36 +04:00
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{
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/*
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|
|
* Writeback any data associated with the kernel mapping of this
|
|
|
|
* page. This ensures that data in the physical page is mutually
|
|
|
|
* coherent with the kernels mapping.
|
|
|
|
*/
|
2010-03-30 00:46:02 +04:00
|
|
|
if (!PageHighMem(page)) {
|
2013-05-17 15:33:28 +04:00
|
|
|
size_t page_size = PAGE_SIZE << compound_order(page);
|
|
|
|
__cpuc_flush_dcache_area(page_address(page), page_size);
|
2010-03-30 00:46:02 +04:00
|
|
|
} else {
|
2013-05-17 15:33:28 +04:00
|
|
|
unsigned long i;
|
2013-04-05 06:16:14 +04:00
|
|
|
if (cache_is_vipt_nonaliasing()) {
|
2013-05-17 15:33:28 +04:00
|
|
|
for (i = 0; i < (1 << compound_order(page)); i++) {
|
2013-12-16 20:25:52 +04:00
|
|
|
void *addr = kmap_atomic(page + i);
|
2013-04-05 06:16:14 +04:00
|
|
|
__cpuc_flush_dcache_area(addr, PAGE_SIZE);
|
2013-05-17 15:33:28 +04:00
|
|
|
kunmap_atomic(addr);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
for (i = 0; i < (1 << compound_order(page)); i++) {
|
2013-12-16 20:25:52 +04:00
|
|
|
void *addr = kmap_high_get(page + i);
|
2013-05-17 15:33:28 +04:00
|
|
|
if (addr) {
|
|
|
|
__cpuc_flush_dcache_area(addr, PAGE_SIZE);
|
2013-12-16 20:25:52 +04:00
|
|
|
kunmap_high(page + i);
|
2013-05-17 15:33:28 +04:00
|
|
|
}
|
2013-04-05 06:16:14 +04:00
|
|
|
}
|
2010-03-30 00:46:02 +04:00
|
|
|
}
|
|
|
|
}
|
2005-04-17 02:20:36 +04:00
|
|
|
|
|
|
|
/*
|
2005-06-20 12:51:03 +04:00
|
|
|
* If this is a page cache page, and we have an aliasing VIPT cache,
|
|
|
|
* we only need to do one flush - which would be at the relevant
|
2005-05-10 20:31:43 +04:00
|
|
|
* userspace colour, which is congruent with page->index.
|
|
|
|
*/
|
2009-10-25 02:05:34 +04:00
|
|
|
if (mapping && cache_is_vipt_aliasing())
|
2005-06-20 12:51:03 +04:00
|
|
|
flush_pfn_alias(page_to_pfn(page),
|
mm, fs: get rid of PAGE_CACHE_* and page_cache_{get,release} macros
PAGE_CACHE_{SIZE,SHIFT,MASK,ALIGN} macros were introduced *long* time
ago with promise that one day it will be possible to implement page
cache with bigger chunks than PAGE_SIZE.
This promise never materialized. And unlikely will.
We have many places where PAGE_CACHE_SIZE assumed to be equal to
PAGE_SIZE. And it's constant source of confusion on whether
PAGE_CACHE_* or PAGE_* constant should be used in a particular case,
especially on the border between fs and mm.
Global switching to PAGE_CACHE_SIZE != PAGE_SIZE would cause to much
breakage to be doable.
Let's stop pretending that pages in page cache are special. They are
not.
The changes are pretty straight-forward:
- <foo> << (PAGE_CACHE_SHIFT - PAGE_SHIFT) -> <foo>;
- <foo> >> (PAGE_CACHE_SHIFT - PAGE_SHIFT) -> <foo>;
- PAGE_CACHE_{SIZE,SHIFT,MASK,ALIGN} -> PAGE_{SIZE,SHIFT,MASK,ALIGN};
- page_cache_get() -> get_page();
- page_cache_release() -> put_page();
This patch contains automated changes generated with coccinelle using
script below. For some reason, coccinelle doesn't patch header files.
I've called spatch for them manually.
The only adjustment after coccinelle is revert of changes to
PAGE_CAHCE_ALIGN definition: we are going to drop it later.
There are few places in the code where coccinelle didn't reach. I'll
fix them manually in a separate patch. Comments and documentation also
will be addressed with the separate patch.
virtual patch
@@
expression E;
@@
- E << (PAGE_CACHE_SHIFT - PAGE_SHIFT)
+ E
@@
expression E;
@@
- E >> (PAGE_CACHE_SHIFT - PAGE_SHIFT)
+ E
@@
@@
- PAGE_CACHE_SHIFT
+ PAGE_SHIFT
@@
@@
- PAGE_CACHE_SIZE
+ PAGE_SIZE
@@
@@
- PAGE_CACHE_MASK
+ PAGE_MASK
@@
expression E;
@@
- PAGE_CACHE_ALIGN(E)
+ PAGE_ALIGN(E)
@@
expression E;
@@
- page_cache_get(E)
+ get_page(E)
@@
expression E;
@@
- page_cache_release(E)
+ put_page(E)
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Acked-by: Michal Hocko <mhocko@suse.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-04-01 15:29:47 +03:00
|
|
|
page->index << PAGE_SHIFT);
|
2005-06-20 12:51:03 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __flush_dcache_aliases(struct address_space *mapping, struct page *page)
|
|
|
|
{
|
|
|
|
struct mm_struct *mm = current->active_mm;
|
|
|
|
struct vm_area_struct *mpnt;
|
|
|
|
pgoff_t pgoff;
|
2005-05-10 20:31:43 +04:00
|
|
|
|
2005-04-17 02:20:36 +04:00
|
|
|
/*
|
|
|
|
* There are possible user space mappings of this page:
|
|
|
|
* - VIVT cache: we need to also write back and invalidate all user
|
|
|
|
* data in the current VM view associated with this page.
|
|
|
|
* - aliasing VIPT: we only need to find one mapping of this page.
|
|
|
|
*/
|
mm, fs: get rid of PAGE_CACHE_* and page_cache_{get,release} macros
PAGE_CACHE_{SIZE,SHIFT,MASK,ALIGN} macros were introduced *long* time
ago with promise that one day it will be possible to implement page
cache with bigger chunks than PAGE_SIZE.
This promise never materialized. And unlikely will.
We have many places where PAGE_CACHE_SIZE assumed to be equal to
PAGE_SIZE. And it's constant source of confusion on whether
PAGE_CACHE_* or PAGE_* constant should be used in a particular case,
especially on the border between fs and mm.
Global switching to PAGE_CACHE_SIZE != PAGE_SIZE would cause to much
breakage to be doable.
Let's stop pretending that pages in page cache are special. They are
not.
The changes are pretty straight-forward:
- <foo> << (PAGE_CACHE_SHIFT - PAGE_SHIFT) -> <foo>;
- <foo> >> (PAGE_CACHE_SHIFT - PAGE_SHIFT) -> <foo>;
- PAGE_CACHE_{SIZE,SHIFT,MASK,ALIGN} -> PAGE_{SIZE,SHIFT,MASK,ALIGN};
- page_cache_get() -> get_page();
- page_cache_release() -> put_page();
This patch contains automated changes generated with coccinelle using
script below. For some reason, coccinelle doesn't patch header files.
I've called spatch for them manually.
The only adjustment after coccinelle is revert of changes to
PAGE_CAHCE_ALIGN definition: we are going to drop it later.
There are few places in the code where coccinelle didn't reach. I'll
fix them manually in a separate patch. Comments and documentation also
will be addressed with the separate patch.
virtual patch
@@
expression E;
@@
- E << (PAGE_CACHE_SHIFT - PAGE_SHIFT)
+ E
@@
expression E;
@@
- E >> (PAGE_CACHE_SHIFT - PAGE_SHIFT)
+ E
@@
@@
- PAGE_CACHE_SHIFT
+ PAGE_SHIFT
@@
@@
- PAGE_CACHE_SIZE
+ PAGE_SIZE
@@
@@
- PAGE_CACHE_MASK
+ PAGE_MASK
@@
expression E;
@@
- PAGE_CACHE_ALIGN(E)
+ PAGE_ALIGN(E)
@@
expression E;
@@
- page_cache_get(E)
+ get_page(E)
@@
expression E;
@@
- page_cache_release(E)
+ put_page(E)
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Acked-by: Michal Hocko <mhocko@suse.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-04-01 15:29:47 +03:00
|
|
|
pgoff = page->index;
|
2005-04-17 02:20:36 +04:00
|
|
|
|
|
|
|
flush_dcache_mmap_lock(mapping);
|
2012-10-09 03:31:25 +04:00
|
|
|
vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
|
2005-04-17 02:20:36 +04:00
|
|
|
unsigned long offset;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If this VMA is not in our MM, we can ignore it.
|
|
|
|
*/
|
|
|
|
if (mpnt->vm_mm != mm)
|
|
|
|
continue;
|
|
|
|
if (!(mpnt->vm_flags & VM_MAYSHARE))
|
|
|
|
continue;
|
|
|
|
offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
|
|
|
|
flush_cache_page(mpnt, mpnt->vm_start + offset, page_to_pfn(page));
|
|
|
|
}
|
|
|
|
flush_dcache_mmap_unlock(mapping);
|
|
|
|
}
|
|
|
|
|
2010-09-13 18:58:06 +04:00
|
|
|
#if __LINUX_ARM_ARCH__ >= 6
|
|
|
|
void __sync_icache_dcache(pte_t pteval)
|
|
|
|
{
|
|
|
|
unsigned long pfn;
|
|
|
|
struct page *page;
|
|
|
|
struct address_space *mapping;
|
|
|
|
|
|
|
|
if (cache_is_vipt_nonaliasing() && !pte_exec(pteval))
|
|
|
|
/* only flush non-aliasing VIPT caches for exec mappings */
|
|
|
|
return;
|
|
|
|
pfn = pte_pfn(pteval);
|
|
|
|
if (!pfn_valid(pfn))
|
|
|
|
return;
|
|
|
|
|
|
|
|
page = pfn_to_page(pfn);
|
|
|
|
if (cache_is_vipt_aliasing())
|
mm: fix races between swapoff and flush dcache
Thanks to commit 4b3ef9daa4fc ("mm/swap: split swap cache into 64MB
trunks"), after swapoff the address_space associated with the swap
device will be freed. So page_mapping() users which may touch the
address_space need some kind of mechanism to prevent the address_space
from being freed during accessing.
The dcache flushing functions (flush_dcache_page(), etc) in architecture
specific code may access the address_space of swap device for anonymous
pages in swap cache via page_mapping() function. But in some cases
there are no mechanisms to prevent the swap device from being swapoff,
for example,
CPU1 CPU2
__get_user_pages() swapoff()
flush_dcache_page()
mapping = page_mapping()
... exit_swap_address_space()
... kvfree(spaces)
mapping_mapped(mapping)
The address space may be accessed after being freed.
But from cachetlb.txt and Russell King, flush_dcache_page() only care
about file cache pages, for anonymous pages, flush_anon_page() should be
used. The implementation of flush_dcache_page() in all architectures
follows this too. They will check whether page_mapping() is NULL and
whether mapping_mapped() is true to determine whether to flush the
dcache immediately. And they will use interval tree (mapping->i_mmap)
to find all user space mappings. While mapping_mapped() and
mapping->i_mmap isn't used by anonymous pages in swap cache at all.
So, to fix the race between swapoff and flush dcache, __page_mapping()
is add to return the address_space for file cache pages and NULL
otherwise. All page_mapping() invoking in flush dcache functions are
replaced with page_mapping_file().
[akpm@linux-foundation.org: simplify page_mapping_file(), per Mike]
Link: http://lkml.kernel.org/r/20180305083634.15174-1-ying.huang@intel.com
Signed-off-by: "Huang, Ying" <ying.huang@intel.com>
Reviewed-by: Andrew Morton <akpm@linux-foundation.org>
Cc: Minchan Kim <minchan@kernel.org>
Cc: Michal Hocko <mhocko@suse.com>
Cc: Johannes Weiner <hannes@cmpxchg.org>
Cc: Mel Gorman <mgorman@techsingularity.net>
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: Chen Liqin <liqin.linux@gmail.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: "James E.J. Bottomley" <jejb@parisc-linux.org>
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Chris Zankel <chris@zankel.net>
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Ley Foon Tan <lftan@altera.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Mike Rapoport <rppt@linux.vnet.ibm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2018-04-06 02:24:39 +03:00
|
|
|
mapping = page_mapping_file(page);
|
2010-09-13 18:58:06 +04:00
|
|
|
else
|
|
|
|
mapping = NULL;
|
|
|
|
|
|
|
|
if (!test_and_set_bit(PG_dcache_clean, &page->flags))
|
|
|
|
__flush_dcache_page(mapping, page);
|
2011-05-16 18:41:15 +04:00
|
|
|
|
|
|
|
if (pte_exec(pteval))
|
2010-09-13 18:58:06 +04:00
|
|
|
__flush_icache_all();
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2005-04-17 02:20:36 +04:00
|
|
|
/*
|
|
|
|
* Ensure cache coherency between kernel mapping and userspace mapping
|
|
|
|
* of this page.
|
|
|
|
*
|
|
|
|
* We have three cases to consider:
|
|
|
|
* - VIPT non-aliasing cache: fully coherent so nothing required.
|
|
|
|
* - VIVT: fully aliasing, so we need to handle every alias in our
|
|
|
|
* current VM view.
|
|
|
|
* - VIPT aliasing: need to handle one alias in our current VM view.
|
|
|
|
*
|
|
|
|
* If we need to handle aliasing:
|
|
|
|
* If the page only exists in the page cache and there are no user
|
|
|
|
* space mappings, we can be lazy and remember that we may have dirty
|
|
|
|
* kernel cache lines for later. Otherwise, we assume we have
|
|
|
|
* aliasing mappings.
|
2005-11-30 19:02:54 +03:00
|
|
|
*
|
2011-05-16 14:25:21 +04:00
|
|
|
* Note that we disable the lazy flush for SMP configurations where
|
|
|
|
* the cache maintenance operations are not automatically broadcasted.
|
2005-04-17 02:20:36 +04:00
|
|
|
*/
|
|
|
|
void flush_dcache_page(struct page *page)
|
|
|
|
{
|
2009-10-25 13:23:04 +03:00
|
|
|
struct address_space *mapping;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The zero page is never written to, so never has any dirty
|
|
|
|
* cache lines, and therefore never needs to be flushed.
|
|
|
|
*/
|
|
|
|
if (page == ZERO_PAGE(0))
|
|
|
|
return;
|
|
|
|
|
2016-11-08 11:21:19 +03:00
|
|
|
if (!cache_ops_need_broadcast() && cache_is_vipt_nonaliasing()) {
|
|
|
|
if (test_bit(PG_dcache_clean, &page->flags))
|
|
|
|
clear_bit(PG_dcache_clean, &page->flags);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
mm: fix races between swapoff and flush dcache
Thanks to commit 4b3ef9daa4fc ("mm/swap: split swap cache into 64MB
trunks"), after swapoff the address_space associated with the swap
device will be freed. So page_mapping() users which may touch the
address_space need some kind of mechanism to prevent the address_space
from being freed during accessing.
The dcache flushing functions (flush_dcache_page(), etc) in architecture
specific code may access the address_space of swap device for anonymous
pages in swap cache via page_mapping() function. But in some cases
there are no mechanisms to prevent the swap device from being swapoff,
for example,
CPU1 CPU2
__get_user_pages() swapoff()
flush_dcache_page()
mapping = page_mapping()
... exit_swap_address_space()
... kvfree(spaces)
mapping_mapped(mapping)
The address space may be accessed after being freed.
But from cachetlb.txt and Russell King, flush_dcache_page() only care
about file cache pages, for anonymous pages, flush_anon_page() should be
used. The implementation of flush_dcache_page() in all architectures
follows this too. They will check whether page_mapping() is NULL and
whether mapping_mapped() is true to determine whether to flush the
dcache immediately. And they will use interval tree (mapping->i_mmap)
to find all user space mappings. While mapping_mapped() and
mapping->i_mmap isn't used by anonymous pages in swap cache at all.
So, to fix the race between swapoff and flush dcache, __page_mapping()
is add to return the address_space for file cache pages and NULL
otherwise. All page_mapping() invoking in flush dcache functions are
replaced with page_mapping_file().
[akpm@linux-foundation.org: simplify page_mapping_file(), per Mike]
Link: http://lkml.kernel.org/r/20180305083634.15174-1-ying.huang@intel.com
Signed-off-by: "Huang, Ying" <ying.huang@intel.com>
Reviewed-by: Andrew Morton <akpm@linux-foundation.org>
Cc: Minchan Kim <minchan@kernel.org>
Cc: Michal Hocko <mhocko@suse.com>
Cc: Johannes Weiner <hannes@cmpxchg.org>
Cc: Mel Gorman <mgorman@techsingularity.net>
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: Chen Liqin <liqin.linux@gmail.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: "James E.J. Bottomley" <jejb@parisc-linux.org>
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Chris Zankel <chris@zankel.net>
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Ley Foon Tan <lftan@altera.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Mike Rapoport <rppt@linux.vnet.ibm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2018-04-06 02:24:39 +03:00
|
|
|
mapping = page_mapping_file(page);
|
2005-04-17 02:20:36 +04:00
|
|
|
|
2010-09-13 18:58:37 +04:00
|
|
|
if (!cache_ops_need_broadcast() &&
|
2016-01-16 03:53:46 +03:00
|
|
|
mapping && !page_mapcount(page))
|
2010-09-13 18:57:36 +04:00
|
|
|
clear_bit(PG_dcache_clean, &page->flags);
|
2010-09-13 18:58:37 +04:00
|
|
|
else {
|
2005-04-17 02:20:36 +04:00
|
|
|
__flush_dcache_page(mapping, page);
|
2005-06-20 12:51:03 +04:00
|
|
|
if (mapping && cache_is_vivt())
|
|
|
|
__flush_dcache_aliases(mapping, page);
|
2008-06-13 13:28:36 +04:00
|
|
|
else if (mapping)
|
|
|
|
__flush_icache_all();
|
2010-09-13 18:57:36 +04:00
|
|
|
set_bit(PG_dcache_clean, &page->flags);
|
2005-06-20 12:51:03 +04:00
|
|
|
}
|
2005-04-17 02:20:36 +04:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(flush_dcache_page);
|
2013-06-11 00:10:12 +04:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Ensure cache coherency for the kernel mapping of this page. We can
|
|
|
|
* assume that the page is pinned via kmap.
|
|
|
|
*
|
|
|
|
* If the page only exists in the page cache and there are no user
|
|
|
|
* space mappings, this is a no-op since the page was already marked
|
|
|
|
* dirty at creation. Otherwise, we need to flush the dirty kernel
|
|
|
|
* cache lines directly.
|
|
|
|
*/
|
|
|
|
void flush_kernel_dcache_page(struct page *page)
|
|
|
|
{
|
|
|
|
if (cache_is_vivt() || cache_is_vipt_aliasing()) {
|
|
|
|
struct address_space *mapping;
|
|
|
|
|
mm: fix races between swapoff and flush dcache
Thanks to commit 4b3ef9daa4fc ("mm/swap: split swap cache into 64MB
trunks"), after swapoff the address_space associated with the swap
device will be freed. So page_mapping() users which may touch the
address_space need some kind of mechanism to prevent the address_space
from being freed during accessing.
The dcache flushing functions (flush_dcache_page(), etc) in architecture
specific code may access the address_space of swap device for anonymous
pages in swap cache via page_mapping() function. But in some cases
there are no mechanisms to prevent the swap device from being swapoff,
for example,
CPU1 CPU2
__get_user_pages() swapoff()
flush_dcache_page()
mapping = page_mapping()
... exit_swap_address_space()
... kvfree(spaces)
mapping_mapped(mapping)
The address space may be accessed after being freed.
But from cachetlb.txt and Russell King, flush_dcache_page() only care
about file cache pages, for anonymous pages, flush_anon_page() should be
used. The implementation of flush_dcache_page() in all architectures
follows this too. They will check whether page_mapping() is NULL and
whether mapping_mapped() is true to determine whether to flush the
dcache immediately. And they will use interval tree (mapping->i_mmap)
to find all user space mappings. While mapping_mapped() and
mapping->i_mmap isn't used by anonymous pages in swap cache at all.
So, to fix the race between swapoff and flush dcache, __page_mapping()
is add to return the address_space for file cache pages and NULL
otherwise. All page_mapping() invoking in flush dcache functions are
replaced with page_mapping_file().
[akpm@linux-foundation.org: simplify page_mapping_file(), per Mike]
Link: http://lkml.kernel.org/r/20180305083634.15174-1-ying.huang@intel.com
Signed-off-by: "Huang, Ying" <ying.huang@intel.com>
Reviewed-by: Andrew Morton <akpm@linux-foundation.org>
Cc: Minchan Kim <minchan@kernel.org>
Cc: Michal Hocko <mhocko@suse.com>
Cc: Johannes Weiner <hannes@cmpxchg.org>
Cc: Mel Gorman <mgorman@techsingularity.net>
Cc: Dave Hansen <dave.hansen@intel.com>
Cc: Chen Liqin <liqin.linux@gmail.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: "James E.J. Bottomley" <jejb@parisc-linux.org>
Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Chris Zankel <chris@zankel.net>
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Ley Foon Tan <lftan@altera.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Mike Rapoport <rppt@linux.vnet.ibm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2018-04-06 02:24:39 +03:00
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mapping = page_mapping_file(page);
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2013-06-11 00:10:12 +04:00
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if (!mapping || mapping_mapped(mapping)) {
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void *addr;
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addr = page_address(page);
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/*
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* kmap_atomic() doesn't set the page virtual
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* address for highmem pages, and
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* kunmap_atomic() takes care of cache
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* flushing already.
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*/
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if (!IS_ENABLED(CONFIG_HIGHMEM) || addr)
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__cpuc_flush_dcache_area(addr, PAGE_SIZE);
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}
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}
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}
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EXPORT_SYMBOL(flush_kernel_dcache_page);
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2006-12-31 02:17:40 +03:00
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/*
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* Flush an anonymous page so that users of get_user_pages()
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* can safely access the data. The expected sequence is:
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*
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* get_user_pages()
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* -> flush_anon_page
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* memcpy() to/from page
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* if written to page, flush_dcache_page()
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*/
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void __flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr)
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{
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unsigned long pfn;
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/* VIPT non-aliasing caches need do nothing */
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if (cache_is_vipt_nonaliasing())
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return;
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/*
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* Write back and invalidate userspace mapping.
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*/
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pfn = page_to_pfn(page);
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if (cache_is_vivt()) {
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flush_cache_page(vma, vmaddr, pfn);
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} else {
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/*
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* For aliasing VIPT, we can flush an alias of the
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* userspace address only.
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*/
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flush_pfn_alias(pfn, vmaddr);
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2009-10-25 01:58:40 +04:00
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__flush_icache_all();
|
2006-12-31 02:17:40 +03:00
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}
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/*
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* Invalidate kernel mapping. No data should be contained
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* in this mapping of the page. FIXME: this is overkill
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* since we actually ask for a write-back and invalidate.
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*/
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2009-11-26 15:56:21 +03:00
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__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
|
2006-12-31 02:17:40 +03:00
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}
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