2019-01-30 22:15:19 +03:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for Intel(R) 10nm server memory controller.
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* Copyright (c) 2019, Intel Corporation.
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*
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*/
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#include <linux/kernel.h>
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#include <asm/cpu_device_id.h>
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#include <asm/intel-family.h>
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#include <asm/mce.h>
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#include "edac_module.h"
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#include "skx_common.h"
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#define I10NM_REVISION "v0.0.3"
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#define EDAC_MOD_STR "i10nm_edac"
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/* Debug macros */
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#define i10nm_printk(level, fmt, arg...) \
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edac_printk(level, "i10nm", fmt, ##arg)
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#define I10NM_GET_SCK_BAR(d, reg) \
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pci_read_config_dword((d)->uracu, 0xd0, &(reg))
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#define I10NM_GET_IMC_BAR(d, i, reg) \
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pci_read_config_dword((d)->uracu, 0xd8 + (i) * 4, &(reg))
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#define I10NM_GET_DIMMMTR(m, i, j) \
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(*(u32 *)((m)->mbase + 0x2080c + (i) * 0x4000 + (j) * 4))
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#define I10NM_GET_MCDDRTCFG(m, i, j) \
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(*(u32 *)((m)->mbase + 0x20970 + (i) * 0x4000 + (j) * 4))
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#define I10NM_GET_SCK_MMIO_BASE(reg) (GET_BITFIELD(reg, 0, 28) << 23)
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#define I10NM_GET_IMC_MMIO_OFFSET(reg) (GET_BITFIELD(reg, 0, 10) << 12)
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#define I10NM_GET_IMC_MMIO_SIZE(reg) ((GET_BITFIELD(reg, 13, 23) - \
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GET_BITFIELD(reg, 0, 10) + 1) << 12)
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static struct list_head *i10nm_edac_list;
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static struct pci_dev *pci_get_dev_wrapper(int dom, unsigned int bus,
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unsigned int dev, unsigned int fun)
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{
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struct pci_dev *pdev;
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pdev = pci_get_domain_bus_and_slot(dom, bus, PCI_DEVFN(dev, fun));
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if (!pdev) {
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edac_dbg(2, "No device %02x:%02x.%x\n",
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bus, dev, fun);
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return NULL;
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}
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if (unlikely(pci_enable_device(pdev) < 0)) {
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edac_dbg(2, "Failed to enable device %02x:%02x.%x\n",
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bus, dev, fun);
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return NULL;
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}
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pci_dev_get(pdev);
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return pdev;
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}
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static int i10nm_get_all_munits(void)
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{
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struct pci_dev *mdev;
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void __iomem *mbase;
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unsigned long size;
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struct skx_dev *d;
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int i, j = 0;
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u32 reg, off;
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u64 base;
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list_for_each_entry(d, i10nm_edac_list, list) {
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d->util_all = pci_get_dev_wrapper(d->seg, d->bus[1], 29, 1);
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if (!d->util_all)
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return -ENODEV;
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d->uracu = pci_get_dev_wrapper(d->seg, d->bus[0], 0, 1);
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if (!d->uracu)
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return -ENODEV;
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if (I10NM_GET_SCK_BAR(d, reg)) {
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i10nm_printk(KERN_ERR, "Failed to socket bar\n");
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return -ENODEV;
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}
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base = I10NM_GET_SCK_MMIO_BASE(reg);
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edac_dbg(2, "socket%d mmio base 0x%llx (reg 0x%x)\n",
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j++, base, reg);
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for (i = 0; i < I10NM_NUM_IMC; i++) {
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mdev = pci_get_dev_wrapper(d->seg, d->bus[0],
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12 + i, 0);
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if (i == 0 && !mdev) {
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i10nm_printk(KERN_ERR, "No IMC found\n");
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return -ENODEV;
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}
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if (!mdev)
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continue;
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d->imc[i].mdev = mdev;
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if (I10NM_GET_IMC_BAR(d, i, reg)) {
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i10nm_printk(KERN_ERR, "Failed to get mc bar\n");
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return -ENODEV;
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}
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off = I10NM_GET_IMC_MMIO_OFFSET(reg);
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size = I10NM_GET_IMC_MMIO_SIZE(reg);
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edac_dbg(2, "mc%d mmio base 0x%llx size 0x%lx (reg 0x%x)\n",
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i, base + off, size, reg);
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mbase = ioremap(base + off, size);
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if (!mbase) {
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i10nm_printk(KERN_ERR, "Failed to ioremap 0x%llx\n",
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base + off);
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return -ENODEV;
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}
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d->imc[i].mbase = mbase;
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}
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}
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return 0;
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}
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2020-04-24 15:18:33 +03:00
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static struct res_config i10nm_cfg0 = {
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2020-04-24 15:18:14 +03:00
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.type = I10NM,
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.decs_did = 0x3452,
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.busno_cfg_offset = 0xcc,
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};
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2020-04-24 15:18:33 +03:00
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static struct res_config i10nm_cfg1 = {
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.type = I10NM,
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.decs_did = 0x3452,
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.busno_cfg_offset = 0xd0,
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};
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2019-01-30 22:15:19 +03:00
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static const struct x86_cpu_id i10nm_cpuids[] = {
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2020-04-24 15:18:33 +03:00
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &i10nm_cfg0),
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X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &i10nm_cfg0),
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X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &i10nm_cfg1),
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2020-03-20 16:13:55 +03:00
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{}
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2019-01-30 22:15:19 +03:00
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};
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MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);
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static bool i10nm_check_ecc(struct skx_imc *imc, int chan)
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{
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u32 mcmtr;
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mcmtr = *(u32 *)(imc->mbase + 0x20ef8 + chan * 0x4000);
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edac_dbg(1, "ch%d mcmtr reg %x\n", chan, mcmtr);
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return !!GET_BITFIELD(mcmtr, 2, 2);
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}
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static int i10nm_get_dimm_config(struct mem_ctl_info *mci)
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{
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struct skx_pvt *pvt = mci->pvt_info;
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struct skx_imc *imc = pvt->imc;
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struct dimm_info *dimm;
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u32 mtr, mcddrtcfg;
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int i, j, ndimms;
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for (i = 0; i < I10NM_NUM_CHANNELS; i++) {
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if (!imc->mbase)
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continue;
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ndimms = 0;
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for (j = 0; j < I10NM_NUM_DIMMS; j++) {
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EDAC: Replace EDAC_DIMM_PTR() macro with edac_get_dimm() function
The EDAC_DIMM_PTR() macro takes 3 arguments from struct mem_ctl_info.
Clean up this interface to only pass the mci struct and replace this
macro with a new function edac_get_dimm().
Also introduce an edac_get_dimm_by_index() function for later use.
This allows it to get a DIMM pointer only by a given index. This can
be useful if the DIMM's position within the layers of the memory
controller or the exact size of the layers are unknown.
Small style changes made for some hunks after applying the semantic
patch.
Semantic patch used:
@@ expression mci, a, b,c; @@
-EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, a, b, c)
+edac_get_dimm(mci, a, b, c)
[ bp: Touchups. ]
Signed-off-by: Robert Richter <rrichter@marvell.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Jason Baron <jbaron@akamai.com>
Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Tony Luck <tony.luck@intel.com>
Link: https://lkml.kernel.org/r/20191106093239.25517-2-rrichter@marvell.com
2019-11-06 12:33:02 +03:00
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dimm = edac_get_dimm(mci, i, j, 0);
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2019-01-30 22:15:19 +03:00
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mtr = I10NM_GET_DIMMMTR(imc, i, j);
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mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i, j);
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edac_dbg(1, "dimmmtr 0x%x mcddrtcfg 0x%x (mc%d ch%d dimm%d)\n",
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mtr, mcddrtcfg, imc->mc, i, j);
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if (IS_DIMM_PRESENT(mtr))
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2020-05-15 15:34:06 +03:00
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ndimms += skx_get_dimm_info(mtr, 0, 0, dimm,
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2019-01-30 22:15:19 +03:00
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imc, i, j);
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else if (IS_NVDIMM_PRESENT(mcddrtcfg, j))
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ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
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EDAC_MOD_STR);
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}
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2019-06-26 09:16:38 +03:00
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if (ndimms && !i10nm_check_ecc(imc, i)) {
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i10nm_printk(KERN_ERR, "ECC is disabled on imc %d channel %d\n",
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imc->mc, i);
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2019-01-30 22:15:19 +03:00
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return -ENODEV;
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}
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}
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return 0;
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}
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static struct notifier_block i10nm_mce_dec = {
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.notifier_call = skx_mce_check_error,
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.priority = MCE_PRIO_EDAC,
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};
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2019-03-22 01:13:39 +03:00
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#ifdef CONFIG_EDAC_DEBUG
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/*
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* Debug feature.
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* Exercise the address decode logic by writing an address to
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* /sys/kernel/debug/edac/i10nm_test/addr.
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*/
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static struct dentry *i10nm_test;
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static int debugfs_u64_set(void *data, u64 val)
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{
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struct mce m;
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pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
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memset(&m, 0, sizeof(m));
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/* ADDRV + MemRd + Unknown channel */
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m.status = MCI_STATUS_ADDRV + 0x90;
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/* One corrected error */
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m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT);
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m.addr = val;
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skx_mce_check_error(NULL, 0, &m);
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return 0;
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}
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DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
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static void setup_i10nm_debug(void)
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{
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i10nm_test = edac_debugfs_create_dir("i10nm_test");
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if (!i10nm_test)
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return;
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if (!edac_debugfs_create_file("addr", 0200, i10nm_test,
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NULL, &fops_u64_wo)) {
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debugfs_remove(i10nm_test);
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i10nm_test = NULL;
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}
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}
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static void teardown_i10nm_debug(void)
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{
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debugfs_remove_recursive(i10nm_test);
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}
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#else
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static inline void setup_i10nm_debug(void) {}
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static inline void teardown_i10nm_debug(void) {}
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#endif /*CONFIG_EDAC_DEBUG*/
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2019-01-30 22:15:19 +03:00
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static int __init i10nm_init(void)
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{
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u8 mc = 0, src_id = 0, node_id = 0;
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const struct x86_cpu_id *id;
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2020-04-24 15:18:14 +03:00
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struct res_config *cfg;
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2019-01-30 22:15:19 +03:00
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const char *owner;
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struct skx_dev *d;
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int rc, i, off[3] = {0xd0, 0xc8, 0xcc};
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u64 tolm, tohm;
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edac_dbg(2, "\n");
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owner = edac_get_owner();
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if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
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return -EBUSY;
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id = x86_match_cpu(i10nm_cpuids);
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if (!id)
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return -ENODEV;
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2020-04-24 15:18:14 +03:00
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cfg = (struct res_config *)id->driver_data;
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2020-04-24 15:18:33 +03:00
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/* Newer steppings have different offset for ATOM_TREMONT_D/ICELAKE_X */
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if (boot_cpu_data.x86_stepping >= 4)
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cfg->busno_cfg_offset = 0xd0;
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2019-01-30 22:15:19 +03:00
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rc = skx_get_hi_lo(0x09a2, off, &tolm, &tohm);
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if (rc)
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return rc;
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2020-04-24 15:18:14 +03:00
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rc = skx_get_all_bus_mappings(cfg, &i10nm_edac_list);
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2019-01-30 22:15:19 +03:00
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if (rc < 0)
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goto fail;
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if (rc == 0) {
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i10nm_printk(KERN_ERR, "No memory controllers found\n");
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return -ENODEV;
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}
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rc = i10nm_get_all_munits();
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if (rc < 0)
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goto fail;
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list_for_each_entry(d, i10nm_edac_list, list) {
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2019-06-26 09:16:55 +03:00
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rc = skx_get_src_id(d, 0xf8, &src_id);
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2019-01-30 22:15:19 +03:00
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if (rc < 0)
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goto fail;
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rc = skx_get_node_id(d, &node_id);
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if (rc < 0)
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goto fail;
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edac_dbg(2, "src_id = %d node_id = %d\n", src_id, node_id);
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for (i = 0; i < I10NM_NUM_IMC; i++) {
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if (!d->imc[i].mdev)
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continue;
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d->imc[i].mc = mc++;
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d->imc[i].lmc = i;
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d->imc[i].src_id = src_id;
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d->imc[i].node_id = node_id;
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rc = skx_register_mci(&d->imc[i], d->imc[i].mdev,
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"Intel_10nm Socket", EDAC_MOD_STR,
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i10nm_get_dimm_config);
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if (rc < 0)
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goto fail;
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}
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}
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|
|
|
|
rc = skx_adxl_get();
|
|
|
|
if (rc)
|
|
|
|
goto fail;
|
|
|
|
|
|
|
|
opstate_init();
|
|
|
|
mce_register_decode_chain(&i10nm_mce_dec);
|
2019-03-22 01:13:39 +03:00
|
|
|
setup_i10nm_debug();
|
2019-01-30 22:15:19 +03:00
|
|
|
|
|
|
|
i10nm_printk(KERN_INFO, "%s\n", I10NM_REVISION);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
|
|
skx_remove();
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit i10nm_exit(void)
|
|
|
|
{
|
|
|
|
edac_dbg(2, "\n");
|
2019-03-22 01:13:39 +03:00
|
|
|
teardown_i10nm_debug();
|
2019-01-30 22:15:19 +03:00
|
|
|
mce_unregister_decode_chain(&i10nm_mce_dec);
|
|
|
|
skx_adxl_put();
|
|
|
|
skx_remove();
|
|
|
|
}
|
|
|
|
|
|
|
|
module_init(i10nm_init);
|
|
|
|
module_exit(i10nm_exit);
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_DESCRIPTION("MC Driver for Intel 10nm server processors");
|