2013-06-25 15:15:10 +04:00
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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2013-08-01 16:13:31 +04:00
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device_type = "cpu";
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2013-06-25 15:15:10 +04:00
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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cpu@1 {
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2013-08-01 16:13:31 +04:00
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device_type = "cpu";
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2013-06-25 15:15:10 +04:00
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compatible = "arm,cortex-a9";
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reg = <1>;
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};
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};
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intc: interrupt-controller@fffe1000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xfffe1000 0x1000>,
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<0xfffe0100 0x100>;
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};
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scu@fffe0000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0xfffe0000 0x1000>;
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};
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timer@fffe0200 {
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interrupt-parent = <&intc>;
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compatible = "arm,cortex-a9-global-timer";
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reg = <0xfffe0200 0x100>;
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interrupts = <1 11 0x04>;
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clocks = <&arm_periph_clk>;
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};
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};
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