487 строки
15 KiB
C
487 строки
15 KiB
C
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/*
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* Copyright 2011 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#include "drmP.h"
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "radeon_drm.h"
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#include "sid.h"
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#include "atom.h"
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/* watermark setup */
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static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
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struct radeon_crtc *radeon_crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *other_mode)
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{
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u32 tmp;
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/*
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* Line Buffer Setup
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* There are 3 line buffers, each one shared by 2 display controllers.
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* DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
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* the display controllers. The paritioning is done via one of four
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* preset allocations specified in bits 21:20:
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* 0 - half lb
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* 2 - whole lb, other crtc must be disabled
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*/
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/* this can get tricky if we have two large displays on a paired group
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* of crtcs. Ideally for multiple large displays we'd assign them to
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* non-linked crtcs for maximum line buffer allocation.
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*/
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if (radeon_crtc->base.enabled && mode) {
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if (other_mode)
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tmp = 0; /* 1/2 */
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else
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tmp = 2; /* whole */
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} else
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tmp = 0;
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WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
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DC_LB_MEMORY_CONFIG(tmp));
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if (radeon_crtc->base.enabled && mode) {
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switch (tmp) {
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case 0:
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default:
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return 4096 * 2;
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case 2:
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return 8192 * 2;
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}
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}
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/* controller not enabled, so no lb used */
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return 0;
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}
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static u32 dce6_get_number_of_dram_channels(struct radeon_device *rdev)
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{
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u32 tmp = RREG32(MC_SHARED_CHMAP);
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switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
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case 0:
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default:
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return 1;
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case 1:
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return 2;
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case 2:
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return 4;
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case 3:
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return 8;
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case 4:
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return 3;
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case 5:
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return 6;
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case 6:
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return 10;
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case 7:
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return 12;
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case 8:
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return 16;
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}
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}
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struct dce6_wm_params {
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u32 dram_channels; /* number of dram channels */
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u32 yclk; /* bandwidth per dram data pin in kHz */
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u32 sclk; /* engine clock in kHz */
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u32 disp_clk; /* display clock in kHz */
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u32 src_width; /* viewport width */
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u32 active_time; /* active display time in ns */
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u32 blank_time; /* blank time in ns */
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bool interlaced; /* mode is interlaced */
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fixed20_12 vsc; /* vertical scale ratio */
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u32 num_heads; /* number of active crtcs */
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u32 bytes_per_pixel; /* bytes per pixel display + overlay */
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u32 lb_size; /* line buffer allocated to pipe */
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u32 vtaps; /* vertical scaler taps */
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};
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static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm)
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{
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/* Calculate raw DRAM Bandwidth */
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fixed20_12 dram_efficiency; /* 0.7 */
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fixed20_12 yclk, dram_channels, bandwidth;
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fixed20_12 a;
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a.full = dfixed_const(1000);
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yclk.full = dfixed_const(wm->yclk);
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yclk.full = dfixed_div(yclk, a);
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dram_channels.full = dfixed_const(wm->dram_channels * 4);
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a.full = dfixed_const(10);
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dram_efficiency.full = dfixed_const(7);
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dram_efficiency.full = dfixed_div(dram_efficiency, a);
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bandwidth.full = dfixed_mul(dram_channels, yclk);
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bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
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return dfixed_trunc(bandwidth);
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}
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static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm)
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{
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/* Calculate DRAM Bandwidth and the part allocated to display. */
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fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
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fixed20_12 yclk, dram_channels, bandwidth;
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fixed20_12 a;
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a.full = dfixed_const(1000);
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yclk.full = dfixed_const(wm->yclk);
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yclk.full = dfixed_div(yclk, a);
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dram_channels.full = dfixed_const(wm->dram_channels * 4);
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a.full = dfixed_const(10);
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disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
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disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
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bandwidth.full = dfixed_mul(dram_channels, yclk);
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bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
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return dfixed_trunc(bandwidth);
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}
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static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm)
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{
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/* Calculate the display Data return Bandwidth */
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fixed20_12 return_efficiency; /* 0.8 */
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fixed20_12 sclk, bandwidth;
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fixed20_12 a;
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a.full = dfixed_const(1000);
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sclk.full = dfixed_const(wm->sclk);
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sclk.full = dfixed_div(sclk, a);
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a.full = dfixed_const(10);
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return_efficiency.full = dfixed_const(8);
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return_efficiency.full = dfixed_div(return_efficiency, a);
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a.full = dfixed_const(32);
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bandwidth.full = dfixed_mul(a, sclk);
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bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
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return dfixed_trunc(bandwidth);
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}
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static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm)
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{
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return 32;
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}
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static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm)
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{
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/* Calculate the DMIF Request Bandwidth */
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fixed20_12 disp_clk_request_efficiency; /* 0.8 */
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fixed20_12 disp_clk, sclk, bandwidth;
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fixed20_12 a, b1, b2;
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u32 min_bandwidth;
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a.full = dfixed_const(1000);
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disp_clk.full = dfixed_const(wm->disp_clk);
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disp_clk.full = dfixed_div(disp_clk, a);
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a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2);
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b1.full = dfixed_mul(a, disp_clk);
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a.full = dfixed_const(1000);
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sclk.full = dfixed_const(wm->sclk);
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sclk.full = dfixed_div(sclk, a);
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a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm));
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b2.full = dfixed_mul(a, sclk);
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a.full = dfixed_const(10);
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disp_clk_request_efficiency.full = dfixed_const(8);
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disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
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min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2));
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a.full = dfixed_const(min_bandwidth);
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bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency);
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return dfixed_trunc(bandwidth);
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}
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static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
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{
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/* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
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u32 dram_bandwidth = dce6_dram_bandwidth(wm);
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u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
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u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
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return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
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}
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static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
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{
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/* Calculate the display mode Average Bandwidth
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* DisplayMode should contain the source and destination dimensions,
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* timing, etc.
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*/
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fixed20_12 bpp;
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fixed20_12 line_time;
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fixed20_12 src_width;
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fixed20_12 bandwidth;
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fixed20_12 a;
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a.full = dfixed_const(1000);
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line_time.full = dfixed_const(wm->active_time + wm->blank_time);
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line_time.full = dfixed_div(line_time, a);
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bpp.full = dfixed_const(wm->bytes_per_pixel);
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src_width.full = dfixed_const(wm->src_width);
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bandwidth.full = dfixed_mul(src_width, bpp);
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bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
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bandwidth.full = dfixed_div(bandwidth, line_time);
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return dfixed_trunc(bandwidth);
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}
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static u32 dce6_latency_watermark(struct dce6_wm_params *wm)
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{
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/* First calcualte the latency in ns */
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u32 mc_latency = 2000; /* 2000 ns. */
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u32 available_bandwidth = dce6_available_bandwidth(wm);
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u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
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u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
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u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
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u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
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(wm->num_heads * cursor_line_pair_return_time);
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u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
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u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
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u32 tmp, dmif_size = 12288;
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fixed20_12 a, b, c;
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if (wm->num_heads == 0)
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return 0;
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a.full = dfixed_const(2);
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b.full = dfixed_const(1);
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if ((wm->vsc.full > a.full) ||
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((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
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(wm->vtaps >= 5) ||
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((wm->vsc.full >= a.full) && wm->interlaced))
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max_src_lines_per_dst_line = 4;
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else
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max_src_lines_per_dst_line = 2;
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a.full = dfixed_const(available_bandwidth);
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b.full = dfixed_const(wm->num_heads);
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a.full = dfixed_div(a, b);
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b.full = dfixed_const(mc_latency + 512);
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c.full = dfixed_const(wm->disp_clk);
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b.full = dfixed_div(b, c);
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c.full = dfixed_const(dmif_size);
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b.full = dfixed_div(c, b);
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tmp = min(dfixed_trunc(a), dfixed_trunc(b));
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b.full = dfixed_const(1000);
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c.full = dfixed_const(wm->disp_clk);
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b.full = dfixed_div(c, b);
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c.full = dfixed_const(wm->bytes_per_pixel);
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b.full = dfixed_mul(b, c);
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lb_fill_bw = min(tmp, dfixed_trunc(b));
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a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
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b.full = dfixed_const(1000);
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c.full = dfixed_const(lb_fill_bw);
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b.full = dfixed_div(c, b);
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a.full = dfixed_div(a, b);
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line_fill_time = dfixed_trunc(a);
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if (line_fill_time < wm->active_time)
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return latency;
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else
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return latency + (line_fill_time - wm->active_time);
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}
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static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
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{
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if (dce6_average_bandwidth(wm) <=
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(dce6_dram_bandwidth_for_display(wm) / wm->num_heads))
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return true;
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else
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return false;
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};
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static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
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{
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if (dce6_average_bandwidth(wm) <=
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(dce6_available_bandwidth(wm) / wm->num_heads))
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return true;
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else
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return false;
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};
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static bool dce6_check_latency_hiding(struct dce6_wm_params *wm)
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{
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u32 lb_partitions = wm->lb_size / wm->src_width;
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u32 line_time = wm->active_time + wm->blank_time;
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u32 latency_tolerant_lines;
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u32 latency_hiding;
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fixed20_12 a;
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a.full = dfixed_const(1);
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if (wm->vsc.full > a.full)
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latency_tolerant_lines = 1;
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else {
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if (lb_partitions <= (wm->vtaps + 1))
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latency_tolerant_lines = 1;
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else
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||
|
|
latency_tolerant_lines = 2;
|
||
|
|
}
|
||
|
|
|
||
|
|
latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
|
||
|
|
|
||
|
|
if (dce6_latency_watermark(wm) <= latency_hiding)
|
||
|
|
return true;
|
||
|
|
else
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void dce6_program_watermarks(struct radeon_device *rdev,
|
||
|
|
struct radeon_crtc *radeon_crtc,
|
||
|
|
u32 lb_size, u32 num_heads)
|
||
|
|
{
|
||
|
|
struct drm_display_mode *mode = &radeon_crtc->base.mode;
|
||
|
|
struct dce6_wm_params wm;
|
||
|
|
u32 pixel_period;
|
||
|
|
u32 line_time = 0;
|
||
|
|
u32 latency_watermark_a = 0, latency_watermark_b = 0;
|
||
|
|
u32 priority_a_mark = 0, priority_b_mark = 0;
|
||
|
|
u32 priority_a_cnt = PRIORITY_OFF;
|
||
|
|
u32 priority_b_cnt = PRIORITY_OFF;
|
||
|
|
u32 tmp, arb_control3;
|
||
|
|
fixed20_12 a, b, c;
|
||
|
|
|
||
|
|
if (radeon_crtc->base.enabled && num_heads && mode) {
|
||
|
|
pixel_period = 1000000 / (u32)mode->clock;
|
||
|
|
line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
|
||
|
|
priority_a_cnt = 0;
|
||
|
|
priority_b_cnt = 0;
|
||
|
|
|
||
|
|
wm.yclk = rdev->pm.current_mclk * 10;
|
||
|
|
wm.sclk = rdev->pm.current_sclk * 10;
|
||
|
|
wm.disp_clk = mode->clock;
|
||
|
|
wm.src_width = mode->crtc_hdisplay;
|
||
|
|
wm.active_time = mode->crtc_hdisplay * pixel_period;
|
||
|
|
wm.blank_time = line_time - wm.active_time;
|
||
|
|
wm.interlaced = false;
|
||
|
|
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
|
||
|
|
wm.interlaced = true;
|
||
|
|
wm.vsc = radeon_crtc->vsc;
|
||
|
|
wm.vtaps = 1;
|
||
|
|
if (radeon_crtc->rmx_type != RMX_OFF)
|
||
|
|
wm.vtaps = 2;
|
||
|
|
wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
|
||
|
|
wm.lb_size = lb_size;
|
||
|
|
wm.dram_channels = dce6_get_number_of_dram_channels(rdev);
|
||
|
|
wm.num_heads = num_heads;
|
||
|
|
|
||
|
|
/* set for high clocks */
|
||
|
|
latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535);
|
||
|
|
/* set for low clocks */
|
||
|
|
/* wm.yclk = low clk; wm.sclk = low clk */
|
||
|
|
latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535);
|
||
|
|
|
||
|
|
/* possibly force display priority to high */
|
||
|
|
/* should really do this at mode validation time... */
|
||
|
|
if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
|
||
|
|
!dce6_average_bandwidth_vs_available_bandwidth(&wm) ||
|
||
|
|
!dce6_check_latency_hiding(&wm) ||
|
||
|
|
(rdev->disp_priority == 2)) {
|
||
|
|
DRM_DEBUG_KMS("force priority to high\n");
|
||
|
|
priority_a_cnt |= PRIORITY_ALWAYS_ON;
|
||
|
|
priority_b_cnt |= PRIORITY_ALWAYS_ON;
|
||
|
|
}
|
||
|
|
|
||
|
|
a.full = dfixed_const(1000);
|
||
|
|
b.full = dfixed_const(mode->clock);
|
||
|
|
b.full = dfixed_div(b, a);
|
||
|
|
c.full = dfixed_const(latency_watermark_a);
|
||
|
|
c.full = dfixed_mul(c, b);
|
||
|
|
c.full = dfixed_mul(c, radeon_crtc->hsc);
|
||
|
|
c.full = dfixed_div(c, a);
|
||
|
|
a.full = dfixed_const(16);
|
||
|
|
c.full = dfixed_div(c, a);
|
||
|
|
priority_a_mark = dfixed_trunc(c);
|
||
|
|
priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
|
||
|
|
|
||
|
|
a.full = dfixed_const(1000);
|
||
|
|
b.full = dfixed_const(mode->clock);
|
||
|
|
b.full = dfixed_div(b, a);
|
||
|
|
c.full = dfixed_const(latency_watermark_b);
|
||
|
|
c.full = dfixed_mul(c, b);
|
||
|
|
c.full = dfixed_mul(c, radeon_crtc->hsc);
|
||
|
|
c.full = dfixed_div(c, a);
|
||
|
|
a.full = dfixed_const(16);
|
||
|
|
c.full = dfixed_div(c, a);
|
||
|
|
priority_b_mark = dfixed_trunc(c);
|
||
|
|
priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* select wm A */
|
||
|
|
arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
|
||
|
|
tmp = arb_control3;
|
||
|
|
tmp &= ~LATENCY_WATERMARK_MASK(3);
|
||
|
|
tmp |= LATENCY_WATERMARK_MASK(1);
|
||
|
|
WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
|
||
|
|
WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
|
||
|
|
(LATENCY_LOW_WATERMARK(latency_watermark_a) |
|
||
|
|
LATENCY_HIGH_WATERMARK(line_time)));
|
||
|
|
/* select wm B */
|
||
|
|
tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
|
||
|
|
tmp &= ~LATENCY_WATERMARK_MASK(3);
|
||
|
|
tmp |= LATENCY_WATERMARK_MASK(2);
|
||
|
|
WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);
|
||
|
|
WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
|
||
|
|
(LATENCY_LOW_WATERMARK(latency_watermark_b) |
|
||
|
|
LATENCY_HIGH_WATERMARK(line_time)));
|
||
|
|
/* restore original selection */
|
||
|
|
WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);
|
||
|
|
|
||
|
|
/* write the priority marks */
|
||
|
|
WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
|
||
|
|
WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
void dce6_bandwidth_update(struct radeon_device *rdev)
|
||
|
|
{
|
||
|
|
struct drm_display_mode *mode0 = NULL;
|
||
|
|
struct drm_display_mode *mode1 = NULL;
|
||
|
|
u32 num_heads = 0, lb_size;
|
||
|
|
int i;
|
||
|
|
|
||
|
|
radeon_update_display_priority(rdev);
|
||
|
|
|
||
|
|
for (i = 0; i < rdev->num_crtc; i++) {
|
||
|
|
if (rdev->mode_info.crtcs[i]->base.enabled)
|
||
|
|
num_heads++;
|
||
|
|
}
|
||
|
|
for (i = 0; i < rdev->num_crtc; i += 2) {
|
||
|
|
mode0 = &rdev->mode_info.crtcs[i]->base.mode;
|
||
|
|
mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
|
||
|
|
lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
|
||
|
|
dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
|
||
|
|
lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
|
||
|
|
dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|