microsoft
/
WSL2-Linux-Kernel
зеркало из https://github.com/microsoft/WSL2-Linux-Kernel.git
1
0
Форкнуть 0
Код Задачи Пакеты Проекты Релизы Вики Активность
WSL2-Linux-Kernel/drivers/iio/adc/xilinx-xadc-core.c

1477 строки
38 KiB
C
Исходник Обычный вид История

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 177 Based on 1 normalized pattern(s): licensed under the gpl 2 extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 135 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528170026.071193225@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-28 19:57:06 +03:00
// SPDX-License-Identifier: GPL-2.0-only
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
/*
* Xilinx XADC driver
*
* Copyright 2013-2014 Analog Devices Inc.
iio: xilinx-xadc: Fix typo in author's name It appears the author of the xilinx-xadc driver can't even spell his own name correctly. Fix that. Reported-by: Lars Möllendorf <lars.moellendorf@plating.de> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-03-09 13:28:47 +03:00
* Author: Lars-Peter Clausen <lars@metafoo.de>
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
*
* Documentation for the parts can be found at:
* - XADC hardmacro: Xilinx UG480
* - ZYNQ XADC interface: Xilinx UG585
* - AXI XADC interface: Xilinx PG019
*/
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
iio: adc: xilinx: use devm_krealloc() instead of kfree() + kcalloc() We now have devm_krealloc() in the kernel Use it indstead of calling kfree() and kcalloc() separately. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-3-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:58 +03:00
#include <linux/overflow.h>
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/events.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include "xilinx-xadc.h"
static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
/* ZYNQ register definitions */
#define XADC_ZYNQ_REG_CFG 0x00
#define XADC_ZYNQ_REG_INTSTS 0x04
#define XADC_ZYNQ_REG_INTMSK 0x08
#define XADC_ZYNQ_REG_STATUS 0x0c
#define XADC_ZYNQ_REG_CFIFO 0x10
#define XADC_ZYNQ_REG_DFIFO 0x14
#define XADC_ZYNQ_REG_CTL 0x18
#define XADC_ZYNQ_CFG_ENABLE BIT(31)
#define XADC_ZYNQ_CFG_CFIFOTH_MASK (0xf << 20)
#define XADC_ZYNQ_CFG_CFIFOTH_OFFSET 20
#define XADC_ZYNQ_CFG_DFIFOTH_MASK (0xf << 16)
#define XADC_ZYNQ_CFG_DFIFOTH_OFFSET 16
#define XADC_ZYNQ_CFG_WEDGE BIT(13)
#define XADC_ZYNQ_CFG_REDGE BIT(12)
#define XADC_ZYNQ_CFG_TCKRATE_MASK (0x3 << 8)
#define XADC_ZYNQ_CFG_TCKRATE_DIV2 (0x0 << 8)
#define XADC_ZYNQ_CFG_TCKRATE_DIV4 (0x1 << 8)
#define XADC_ZYNQ_CFG_TCKRATE_DIV8 (0x2 << 8)
#define XADC_ZYNQ_CFG_TCKRATE_DIV16 (0x3 << 8)
#define XADC_ZYNQ_CFG_IGAP_MASK 0x1f
#define XADC_ZYNQ_CFG_IGAP(x) (x)
#define XADC_ZYNQ_INT_CFIFO_LTH BIT(9)
#define XADC_ZYNQ_INT_DFIFO_GTH BIT(8)
#define XADC_ZYNQ_INT_ALARM_MASK 0xff
#define XADC_ZYNQ_INT_ALARM_OFFSET 0
#define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK (0xf << 16)
#define XADC_ZYNQ_STATUS_CFIFO_LVL_OFFSET 16
#define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK (0xf << 12)
#define XADC_ZYNQ_STATUS_DFIFO_LVL_OFFSET 12
#define XADC_ZYNQ_STATUS_CFIFOF BIT(11)
#define XADC_ZYNQ_STATUS_CFIFOE BIT(10)
#define XADC_ZYNQ_STATUS_DFIFOF BIT(9)
#define XADC_ZYNQ_STATUS_DFIFOE BIT(8)
#define XADC_ZYNQ_STATUS_OT BIT(7)
#define XADC_ZYNQ_STATUS_ALM(x) BIT(x)
#define XADC_ZYNQ_CTL_RESET BIT(4)
#define XADC_ZYNQ_CMD_NOP 0x00
#define XADC_ZYNQ_CMD_READ 0x01
#define XADC_ZYNQ_CMD_WRITE 0x02
#define XADC_ZYNQ_CMD(cmd, addr, data) (((cmd) << 26) | ((addr) << 16) | (data))
/* AXI register definitions */
#define XADC_AXI_REG_RESET 0x00
#define XADC_AXI_REG_STATUS 0x04
#define XADC_AXI_REG_ALARM_STATUS 0x08
#define XADC_AXI_REG_CONVST 0x0c
#define XADC_AXI_REG_XADC_RESET 0x10
#define XADC_AXI_REG_GIER 0x5c
#define XADC_AXI_REG_IPISR 0x60
#define XADC_AXI_REG_IPIER 0x68
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
/* 7 Series */
#define XADC_7S_AXI_ADC_REG_OFFSET 0x200
/* UltraScale */
#define XADC_US_AXI_ADC_REG_OFFSET 0x400
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
#define XADC_AXI_RESET_MAGIC 0xa
#define XADC_AXI_GIER_ENABLE BIT(31)
#define XADC_AXI_INT_EOS BIT(4)
#define XADC_AXI_INT_ALARM_MASK 0x3c0f
#define XADC_FLAGS_BUFFERED BIT(0)
iio: xilinx-xadc: Make sure not exceed maximum samplerate The XADC supports a samplerate of up to 1MSPS. Unfortunately the hardware does not have a FIFO, which means it generates an interrupt for each conversion sequence. At one 1MSPS this creates an interrupt storm that causes the system to soft-lock. For this reason the driver limits the maximum samplerate to 150kSPS. Currently this check is only done when setting a new samplerate. But it is also possible that the initial samplerate configured in the FPGA bitstream exceeds the limit. In this case when starting to capture data without first changing the samplerate the system can overload. To prevent this check the currently configured samplerate in the probe function and reduce it to the maximum if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver") Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-04-03 16:27:16 +03:00
/*
* The XADC hardware supports a samplerate of up to 1MSPS. Unfortunately it does
* not have a hardware FIFO. Which means an interrupt is generated for each
* conversion sequence. At 1MSPS sample rate the CPU in ZYNQ7000 is completely
* overloaded by the interrupts that it soft-lockups. For this reason the driver
* limits the maximum samplerate 150kSPS. At this rate the CPU is fairly busy,
* but still responsive.
*/
#define XADC_MAX_SAMPLERATE 150000
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
static void xadc_write_reg(struct xadc *xadc, unsigned int reg,
uint32_t val)
{
writel(val, xadc->base + reg);
}
static void xadc_read_reg(struct xadc *xadc, unsigned int reg,
uint32_t *val)
{
*val = readl(xadc->base + reg);
}
/*
* The ZYNQ interface uses two asynchronous FIFOs for communication with the
* XADC. Reads and writes to the XADC register are performed by submitting a
* request to the command FIFO (CFIFO), once the request has been completed the
* result can be read from the data FIFO (DFIFO). The method currently used in
* this driver is to submit the request for a read/write operation, then go to
* sleep and wait for an interrupt that signals that a response is available in
* the data FIFO.
*/
static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd,
unsigned int n)
{
unsigned int i;
for (i = 0; i < n; i++)
xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]);
}
static void xadc_zynq_drain_fifo(struct xadc *xadc)
{
uint32_t status, tmp;
xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
while (!(status & XADC_ZYNQ_STATUS_DFIFOE)) {
xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
}
}
static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask,
unsigned int val)
{
xadc->zynq_intmask &= ~mask;
xadc->zynq_intmask |= val;
xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK,
xadc->zynq_intmask | xadc->zynq_masked_alarm);
}
static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,
uint16_t val)
{
uint32_t cmd[1];
uint32_t tmp;
int ret;
spin_lock_irq(&xadc->lock);
xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
XADC_ZYNQ_INT_DFIFO_GTH);
reinit_completion(&xadc->completion);
cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val);
xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
tmp |= 0 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
spin_unlock_irq(&xadc->lock);
ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
if (ret == 0)
ret = -EIO;
else
ret = 0;
xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
return ret;
}
static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg,
uint16_t *val)
{
uint32_t cmd[2];
uint32_t resp, tmp;
int ret;
cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_READ, reg, 0);
cmd[1] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_NOP, 0, 0);
spin_lock_irq(&xadc->lock);
xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
XADC_ZYNQ_INT_DFIFO_GTH);
xadc_zynq_drain_fifo(xadc);
reinit_completion(&xadc->completion);
xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
tmp |= 1 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
spin_unlock_irq(&xadc->lock);
ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
if (ret == 0)
ret = -EIO;
if (ret < 0)
return ret;
xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
*val = resp & 0xffff;
return 0;
}
static unsigned int xadc_zynq_transform_alarm(unsigned int alarm)
{
return ((alarm & 0x80) >> 4) |
((alarm & 0x78) << 1) |
(alarm & 0x07);
}
/*
* The ZYNQ threshold interrupts are level sensitive. Since we can't make the
* threshold condition go way from within the interrupt handler, this means as
* soon as a threshold condition is present we would enter the interrupt handler
* again and again. To work around this we mask all active thresholds interrupts
* in the interrupt handler and start a timer. In this timer we poll the
* interrupt status and only if the interrupt is inactive we unmask it again.
*/
static void xadc_zynq_unmask_worker(struct work_struct *work)
{
struct xadc *xadc = container_of(work, struct xadc, zynq_unmask_work.work);
unsigned int misc_sts, unmask;
xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &misc_sts);
misc_sts &= XADC_ZYNQ_INT_ALARM_MASK;
spin_lock_irq(&xadc->lock);
/* Clear those bits which are not active anymore */
unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;
xadc->zynq_masked_alarm &= misc_sts;
/* Also clear those which are masked out anyway */
xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;
/* Clear the interrupts before we unmask them */
xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);
xadc_zynq_update_intmsk(xadc, 0, 0);
spin_unlock_irq(&xadc->lock);
/* if still pending some alarm re-trigger the timer */
if (xadc->zynq_masked_alarm) {
schedule_delayed_work(&xadc->zynq_unmask_work,
msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
}
}
static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
{
struct iio_dev *indio_dev = devid;
struct xadc *xadc = iio_priv(indio_dev);
uint32_t status;
xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm);
if (!status)
return IRQ_NONE;
spin_lock(&xadc->lock);
xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);
if (status & XADC_ZYNQ_INT_DFIFO_GTH) {
xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
XADC_ZYNQ_INT_DFIFO_GTH);
complete(&xadc->completion);
}
status &= XADC_ZYNQ_INT_ALARM_MASK;
if (status) {
xadc->zynq_masked_alarm |= status;
/*
* mask the current event interrupt,
* unmask it when the interrupt is no more active.
*/
xadc_zynq_update_intmsk(xadc, 0, 0);
iio: adc: xilinx-xadc: Push interrupts into hardirq context The driver currently registers a pair of irq handlers using request_threaded_irq(), however the synchronization mechanism between the hardirq and the threadedirq handler is a regular spinlock. Unfortunately, this breaks PREEMPT_RT builds, where a spinlock can sleep, and is thus not able to be acquired from a hardirq handler. This patch gets rid of the threaded handler and pushes all interrupt handling into the hardirq context, and uses request_irq(). To validate that this change has no impact on RT performance, here are cyclictest values with no processes running: $ sudo cyclictest -S -m -p 98 policy: fifo: loadavg: 0.00 0.01 0.05 1/174 2539 T: 0 ( 1405) P:98 I:1000 C:167010520 Min: 9 Act: 12 Avg: 12 Max: 75 T: 1 ( 1862) P:98 I:1500 C:111340339 Min: 9 Act: 12 Avg: 12 Max: 73 Then, all xadc raw handles were accessed in a continuous loop via /sys/bus/iio/devices/iio:device0: $ sudo cyclictest -S -m -p 98 policy: fifo: loadavg: 7.84 7.70 7.63 3/182 4260 T: 0 ( 2559) P:98 I:1000 C:241557018 Min: 11 Act: 18 Avg: 21 Max: 74 T: 1 ( 2560) P:98 I:1500 C:161038006 Min: 10 Act: 21 Avg: 20 Max: 73 Signed-off-by: Xander Huff <xander.huff@ni.com> Acked-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2015-08-12 02:00:49 +03:00
xadc_handle_events(indio_dev,
xadc_zynq_transform_alarm(status));
/* unmask the required interrupts in timer. */
schedule_delayed_work(&xadc->zynq_unmask_work,
msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
}
spin_unlock(&xadc->lock);
iio: adc: xilinx-xadc: Push interrupts into hardirq context The driver currently registers a pair of irq handlers using request_threaded_irq(), however the synchronization mechanism between the hardirq and the threadedirq handler is a regular spinlock. Unfortunately, this breaks PREEMPT_RT builds, where a spinlock can sleep, and is thus not able to be acquired from a hardirq handler. This patch gets rid of the threaded handler and pushes all interrupt handling into the hardirq context, and uses request_irq(). To validate that this change has no impact on RT performance, here are cyclictest values with no processes running: $ sudo cyclictest -S -m -p 98 policy: fifo: loadavg: 0.00 0.01 0.05 1/174 2539 T: 0 ( 1405) P:98 I:1000 C:167010520 Min: 9 Act: 12 Avg: 12 Max: 75 T: 1 ( 1862) P:98 I:1500 C:111340339 Min: 9 Act: 12 Avg: 12 Max: 73 Then, all xadc raw handles were accessed in a continuous loop via /sys/bus/iio/devices/iio:device0: $ sudo cyclictest -S -m -p 98 policy: fifo: loadavg: 7.84 7.70 7.63 3/182 4260 T: 0 ( 2559) P:98 I:1000 C:241557018 Min: 11 Act: 18 Avg: 21 Max: 74 T: 1 ( 2560) P:98 I:1500 C:161038006 Min: 10 Act: 21 Avg: 20 Max: 73 Signed-off-by: Xander Huff <xander.huff@ni.com> Acked-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2015-08-12 02:00:49 +03:00
return IRQ_HANDLED;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
}
#define XADC_ZYNQ_TCK_RATE_MAX 50000000
#define XADC_ZYNQ_IGAP_DEFAULT 20
iio: adc: xilinx: limit pcap clock frequency value This patch limits the xadc pcap clock frequency value to be less than 200MHz. This fixes the issue when zynq is booted at higher frequency values, pcap crosses the maximum limit of 200MHz(Fmax) as it is derived from IOPLL. If this limit is crossed it is required to alter the WEDGE and REDGE bits of XADC_CFG register to make timings better in the interface. So to avoid alteration of these bits every time, the pcap value should not cross the Fmax limit. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2018-07-23 18:02:01 +03:00
#define XADC_ZYNQ_PCAP_RATE_MAX 200000000
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
static int xadc_zynq_setup(struct platform_device *pdev,
struct iio_dev *indio_dev, int irq)
{
struct xadc *xadc = iio_priv(indio_dev);
unsigned long pcap_rate;
unsigned int tck_div;
unsigned int div;
unsigned int igap;
unsigned int tck_rate;
iio: adc: xilinx: limit pcap clock frequency value This patch limits the xadc pcap clock frequency value to be less than 200MHz. This fixes the issue when zynq is booted at higher frequency values, pcap crosses the maximum limit of 200MHz(Fmax) as it is derived from IOPLL. If this limit is crossed it is required to alter the WEDGE and REDGE bits of XADC_CFG register to make timings better in the interface. So to avoid alteration of these bits every time, the pcap value should not cross the Fmax limit. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2018-07-23 18:02:01 +03:00
int ret;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
/* TODO: Figure out how to make igap and tck_rate configurable */
igap = XADC_ZYNQ_IGAP_DEFAULT;
tck_rate = XADC_ZYNQ_TCK_RATE_MAX;
xadc->zynq_intmask = ~0;
pcap_rate = clk_get_rate(xadc->clk);
iio: adc: xilinx: Check for return values in clk related functions This patch adds check for return values from clock related functions. This was reported by static code analysis tool. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2018-07-23 18:02:00 +03:00
if (!pcap_rate)
return -EINVAL;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
iio: adc: xilinx: limit pcap clock frequency value This patch limits the xadc pcap clock frequency value to be less than 200MHz. This fixes the issue when zynq is booted at higher frequency values, pcap crosses the maximum limit of 200MHz(Fmax) as it is derived from IOPLL. If this limit is crossed it is required to alter the WEDGE and REDGE bits of XADC_CFG register to make timings better in the interface. So to avoid alteration of these bits every time, the pcap value should not cross the Fmax limit. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2018-07-23 18:02:01 +03:00
if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
ret = clk_set_rate(xadc->clk,
(unsigned long)XADC_ZYNQ_PCAP_RATE_MAX);
if (ret)
return ret;
}
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
if (tck_rate > pcap_rate / 2) {
div = 2;
} else {
div = pcap_rate / tck_rate;
if (pcap_rate / div > XADC_ZYNQ_TCK_RATE_MAX)
div++;
}
if (div <= 3)
tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV2;
else if (div <= 7)
tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV4;
else if (div <= 15)
tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV8;
else
tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV16;
xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, XADC_ZYNQ_CTL_RESET);
xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0);
xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);
xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);
xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |
XADC_ZYNQ_CFG_REDGE | XADC_ZYNQ_CFG_WEDGE |
tck_div | XADC_ZYNQ_CFG_IGAP(igap));
iio: adc: xilinx: limit pcap clock frequency value This patch limits the xadc pcap clock frequency value to be less than 200MHz. This fixes the issue when zynq is booted at higher frequency values, pcap crosses the maximum limit of 200MHz(Fmax) as it is derived from IOPLL. If this limit is crossed it is required to alter the WEDGE and REDGE bits of XADC_CFG register to make timings better in the interface. So to avoid alteration of these bits every time, the pcap value should not cross the Fmax limit. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2018-07-23 18:02:01 +03:00
if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
ret = clk_set_rate(xadc->clk, pcap_rate);
if (ret)
return ret;
}
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
return 0;
}
static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)
{
unsigned int div;
uint32_t val;
xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);
switch (val & XADC_ZYNQ_CFG_TCKRATE_MASK) {
case XADC_ZYNQ_CFG_TCKRATE_DIV4:
div = 4;
break;
case XADC_ZYNQ_CFG_TCKRATE_DIV8:
div = 8;
break;
case XADC_ZYNQ_CFG_TCKRATE_DIV16:
div = 16;
break;
default:
div = 2;
break;
}
return clk_get_rate(xadc->clk) / div;
}
static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)
{
unsigned long flags;
uint32_t status;
/* Move OT to bit 7 */
alarm = ((alarm & 0x08) << 4) | ((alarm & 0xf0) >> 1) | (alarm & 0x07);
spin_lock_irqsave(&xadc->lock, flags);
/* Clear previous interrupts if any. */
xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);
xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK,
~alarm & XADC_ZYNQ_INT_ALARM_MASK);
spin_unlock_irqrestore(&xadc->lock, flags);
}
static const struct xadc_ops xadc_zynq_ops = {
.read = xadc_zynq_read_adc_reg,
.write = xadc_zynq_write_adc_reg,
.setup = xadc_zynq_setup,
.get_dclk_rate = xadc_zynq_get_dclk_rate,
.interrupt_handler = xadc_zynq_interrupt_handler,
.update_alarm = xadc_zynq_update_alarm,
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
.type = XADC_TYPE_S7,
};
static const unsigned int xadc_axi_reg_offsets[] = {
[XADC_TYPE_S7] = XADC_7S_AXI_ADC_REG_OFFSET,
[XADC_TYPE_US] = XADC_US_AXI_ADC_REG_OFFSET,
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
};
static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,
uint16_t *val)
{
uint32_t val32;
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
&val32);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
*val = val32 & 0xffff;
return 0;
}
static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg,
uint16_t val)
{
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
xadc_write_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
val);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
return 0;
}
static int xadc_axi_setup(struct platform_device *pdev,
struct iio_dev *indio_dev, int irq)
{
struct xadc *xadc = iio_priv(indio_dev);
xadc_write_reg(xadc, XADC_AXI_REG_RESET, XADC_AXI_RESET_MAGIC);
xadc_write_reg(xadc, XADC_AXI_REG_GIER, XADC_AXI_GIER_ENABLE);
return 0;
}
static irqreturn_t xadc_axi_interrupt_handler(int irq, void *devid)
{
struct iio_dev *indio_dev = devid;
struct xadc *xadc = iio_priv(indio_dev);
uint32_t status, mask;
unsigned int events;
xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status);
xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask);
status &= mask;
if (!status)
return IRQ_NONE;
if ((status & XADC_AXI_INT_EOS) && xadc->trigger)
iio: Remove timestamp argument from iio_trigger_poll() and iio_trigger_poll_chained() argument has been ignored; adjust drivers accordingly Signed-off-by: Peter Meerwald <pmeerw@pmeerw.net> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-12-06 09:46:00 +03:00
iio_trigger_poll(xadc->trigger);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
if (status & XADC_AXI_INT_ALARM_MASK) {
/*
* The order of the bits in the AXI-XADC status register does
* not match the order of the bits in the XADC alarm enable
* register. xadc_handle_events() expects the events to be in
* the same order as the XADC alarm enable register.
*/
events = (status & 0x000e) >> 1;
events |= (status & 0x0001) << 3;
events |= (status & 0x3c00) >> 6;
xadc_handle_events(indio_dev, events);
}
xadc_write_reg(xadc, XADC_AXI_REG_IPISR, status);
return IRQ_HANDLED;
}
static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)
{
uint32_t val;
unsigned long flags;
/*
* The order of the bits in the AXI-XADC status register does not match
* the order of the bits in the XADC alarm enable register. We get
* passed the alarm mask in the same order as in the XADC alarm enable
* register.
*/
alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) |
((alarm & 0xf0) << 6);
spin_lock_irqsave(&xadc->lock, flags);
xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
val &= ~XADC_AXI_INT_ALARM_MASK;
val |= alarm;
xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
spin_unlock_irqrestore(&xadc->lock, flags);
}
static unsigned long xadc_axi_get_dclk(struct xadc *xadc)
{
return clk_get_rate(xadc->clk);
}
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
static const struct xadc_ops xadc_7s_axi_ops = {
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
.read = xadc_axi_read_adc_reg,
.write = xadc_axi_write_adc_reg,
.setup = xadc_axi_setup,
.get_dclk_rate = xadc_axi_get_dclk,
.update_alarm = xadc_axi_update_alarm,
.interrupt_handler = xadc_axi_interrupt_handler,
.flags = XADC_FLAGS_BUFFERED,
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
.type = XADC_TYPE_S7,
};
static const struct xadc_ops xadc_us_axi_ops = {
.read = xadc_axi_read_adc_reg,
.write = xadc_axi_write_adc_reg,
.setup = xadc_axi_setup,
.get_dclk_rate = xadc_axi_get_dclk,
.update_alarm = xadc_axi_update_alarm,
.interrupt_handler = xadc_axi_interrupt_handler,
.flags = XADC_FLAGS_BUFFERED,
.type = XADC_TYPE_US,
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
};
static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
uint16_t mask, uint16_t val)
{
uint16_t tmp;
int ret;
ret = _xadc_read_adc_reg(xadc, reg, &tmp);
if (ret)
return ret;
return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val);
}
static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
uint16_t mask, uint16_t val)
{
int ret;
mutex_lock(&xadc->mutex);
ret = _xadc_update_adc_reg(xadc, reg, mask, val);
mutex_unlock(&xadc->mutex);
return ret;
}
static unsigned long xadc_get_dclk_rate(struct xadc *xadc)
{
return xadc->ops->get_dclk_rate(xadc);
}
static int xadc_update_scan_mode(struct iio_dev *indio_dev,
const unsigned long *mask)
{
struct xadc *xadc = iio_priv(indio_dev);
iio: adc: xilinx: use devm_krealloc() instead of kfree() + kcalloc() We now have devm_krealloc() in the kernel Use it indstead of calling kfree() and kcalloc() separately. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-3-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:58 +03:00
size_t new_size, n;
void *data;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
n = bitmap_weight(mask, indio_dev->masklength);
iio: adc: xilinx: use devm_krealloc() instead of kfree() + kcalloc() We now have devm_krealloc() in the kernel Use it indstead of calling kfree() and kcalloc() separately. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-3-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:58 +03:00
if (check_mul_overflow(n, sizeof(*xadc->data), &new_size))
return -ENOMEM;
data = devm_krealloc(indio_dev->dev.parent, xadc->data,
new_size, GFP_KERNEL);
if (!data)
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
return -ENOMEM;
iio: adc: xilinx: use devm_krealloc() instead of kfree() + kcalloc() We now have devm_krealloc() in the kernel Use it indstead of calling kfree() and kcalloc() separately. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-3-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:58 +03:00
memset(data, 0, new_size);
xadc->data = data;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
return 0;
}
static unsigned int xadc_scan_index_to_channel(unsigned int scan_index)
{
switch (scan_index) {
case 5:
return XADC_REG_VCCPINT;
case 6:
return XADC_REG_VCCPAUX;
case 7:
return XADC_REG_VCCO_DDR;
case 8:
return XADC_REG_TEMP;
case 9:
return XADC_REG_VCCINT;
case 10:
return XADC_REG_VCCAUX;
case 11:
return XADC_REG_VPVN;
case 12:
return XADC_REG_VREFP;
case 13:
return XADC_REG_VREFN;
case 14:
return XADC_REG_VCCBRAM;
default:
return XADC_REG_VAUX(scan_index - 16);
}
}
static irqreturn_t xadc_trigger_handler(int irq, void *p)
{
struct iio_poll_func *pf = p;
struct iio_dev *indio_dev = pf->indio_dev;
struct xadc *xadc = iio_priv(indio_dev);
unsigned int chan;
int i, j;
if (!xadc->data)
goto out;
j = 0;
for_each_set_bit(i, indio_dev->active_scan_mask,
indio_dev->masklength) {
chan = xadc_scan_index_to_channel(i);
xadc_read_adc_reg(xadc, chan, &xadc->data[j]);
j++;
}
iio_push_to_buffers(indio_dev, xadc->data);
out:
iio_trigger_notify_done(indio_dev->trig);
return IRQ_HANDLED;
}
static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
{
struct xadc *xadc = iio_trigger_get_drvdata(trigger);
unsigned long flags;
unsigned int convst;
unsigned int val;
int ret = 0;
mutex_lock(&xadc->mutex);
if (state) {
iio: xilinx-xadc: Fix typo Fix a typo. 'at the a time' -> 'at a time'. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-04-03 16:27:17 +03:00
/* Only one of the two triggers can be active at a time. */
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
if (xadc->trigger != NULL) {
ret = -EBUSY;
goto err_out;
} else {
xadc->trigger = trigger;
if (trigger == xadc->convst_trigger)
convst = XADC_CONF0_EC;
else
convst = 0;
}
ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC,
convst);
if (ret)
goto err_out;
} else {
xadc->trigger = NULL;
}
spin_lock_irqsave(&xadc->lock, flags);
xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
iio: xilinx-xadc: Fix clearing interrupt when enabling trigger When enabling the trigger and unmasking the end-of-sequence (EOS) interrupt the EOS interrupt should be cleared from the status register. Otherwise it is possible that it was still set from a previous capture. If that is the case the interrupt would fire immediately even though no conversion has been done yet and stale data is being read from the device. The old code only clears the interrupt if the interrupt was previously unmasked. Which does not make much sense since the interrupt is always masked at this point and in addition masking the interrupt does not clear the interrupt from the status register. So the clearing needs to be done unconditionally. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver") Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-04-03 16:27:14 +03:00
xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
if (state)
val |= XADC_AXI_INT_EOS;
else
val &= ~XADC_AXI_INT_EOS;
xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
spin_unlock_irqrestore(&xadc->lock, flags);
err_out:
mutex_unlock(&xadc->mutex);
return ret;
}
static const struct iio_trigger_ops xadc_trigger_ops = {
.set_trigger_state = &xadc_trigger_set_state,
};
static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev,
const char *name)
{
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
struct device *dev = indio_dev->dev.parent;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
struct iio_trigger *trig;
int ret;
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
trig = devm_iio_trigger_alloc(dev, "%s%d-%s", indio_dev->name,
indio_dev->id, name);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
if (trig == NULL)
return ERR_PTR(-ENOMEM);
trig->ops = &xadc_trigger_ops;
iio_trigger_set_drvdata(trig, iio_priv(indio_dev));
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
ret = devm_iio_trigger_register(dev, trig);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
if (ret)
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
return ERR_PTR(ret);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
return trig;
}
static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)
{
uint16_t val;
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
/*
* As per datasheet the power-down bits are don't care in the
* UltraScale, but as per reality setting the power-down bit for the
* non-existing ADC-B powers down the main ADC, so just return and don't
* do anything.
*/
if (xadc->ops->type == XADC_TYPE_US)
return 0;
iio: xilinx-xadc: Fix ADC-B powerdown The check for shutting down the second ADC is inverted. This causes it to be powered down when it should be enabled. As a result channels that are supposed to be handled by the second ADC return invalid conversion results. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver") Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-04-03 16:27:13 +03:00
/* Powerdown the ADC-B when it is not needed. */
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
switch (seq_mode) {
case XADC_CONF1_SEQ_SIMULTANEOUS:
case XADC_CONF1_SEQ_INDEPENDENT:
iio: xilinx-xadc: Fix ADC-B powerdown The check for shutting down the second ADC is inverted. This causes it to be powered down when it should be enabled. As a result channels that are supposed to be handled by the second ADC return invalid conversion results. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver") Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-04-03 16:27:13 +03:00
val = 0;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
break;
default:
iio: xilinx-xadc: Fix ADC-B powerdown The check for shutting down the second ADC is inverted. This causes it to be powered down when it should be enabled. As a result channels that are supposed to be handled by the second ADC return invalid conversion results. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver") Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-04-03 16:27:13 +03:00
val = XADC_CONF2_PD_ADC_B;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
break;
}
return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK,
val);
}
static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
{
unsigned int aux_scan_mode = scan_mode >> 16;
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
/* UltraScale has only one ADC and supports only continuous mode */
if (xadc->ops->type == XADC_TYPE_US)
return XADC_CONF1_SEQ_CONTINUOUS;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)
return XADC_CONF1_SEQ_SIMULTANEOUS;
if ((aux_scan_mode & 0xff00) == 0 ||
(aux_scan_mode & 0x00ff) == 0)
return XADC_CONF1_SEQ_CONTINUOUS;
return XADC_CONF1_SEQ_SIMULTANEOUS;
}
static int xadc_postdisable(struct iio_dev *indio_dev)
{
struct xadc *xadc = iio_priv(indio_dev);
unsigned long scan_mask;
int ret;
int i;
scan_mask = 1; /* Run calibration as part of the sequence */
for (i = 0; i < indio_dev->num_channels; i++)
scan_mask |= BIT(indio_dev->channels[i].scan_index);
/* Enable all channels and calibration */
ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
if (ret)
return ret;
ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
if (ret)
return ret;
ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
XADC_CONF1_SEQ_CONTINUOUS);
if (ret)
return ret;
return xadc_power_adc_b(xadc, XADC_CONF1_SEQ_CONTINUOUS);
}
static int xadc_preenable(struct iio_dev *indio_dev)
{
struct xadc *xadc = iio_priv(indio_dev);
unsigned long scan_mask;
int seq_mode;
int ret;
ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
XADC_CONF1_SEQ_DEFAULT);
if (ret)
goto err;
scan_mask = *indio_dev->active_scan_mask;
seq_mode = xadc_get_seq_mode(xadc, scan_mask);
ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
if (ret)
goto err;
iio: xilinx-xadc: Fix sequencer configuration for aux channels in simultaneous mode The XADC has two internal ADCs. Depending on the mode it is operating in either one or both of them are used. The device manual calls this continuous (one ADC) and simultaneous (both ADCs) mode. The meaning of the sequencing register for the aux channels changes depending on the mode. In continuous mode each bit corresponds to one of the 16 aux channels. And the single ADC will convert them one by one in order. In simultaneous mode the aux channels are split into two groups the first 8 channels are assigned to the first ADC and the other 8 channels to the second ADC. The upper 8 bits of the sequencing register are unused and the lower 8 bits control both ADCs. This means a bit needs to be set if either the corresponding channel from the first group or the second group (or both) are set. Currently the driver does not have the special handling required for simultaneous mode. Add it. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver") Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-04-03 16:27:15 +03:00
/*
* In simultaneous mode the upper and lower aux channels are samples at
* the same time. In this mode the upper 8 bits in the sequencer
* register are don't care and the lower 8 bits control two channels
* each. As such we must set the bit if either the channel in the lower
* group or the upper group is enabled.
*/
if (seq_mode == XADC_CONF1_SEQ_SIMULTANEOUS)
scan_mask = ((scan_mask >> 8) | scan_mask) & 0xff0000;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
if (ret)
goto err;
ret = xadc_power_adc_b(xadc, seq_mode);
if (ret)
goto err;
ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
seq_mode);
if (ret)
goto err;
return 0;
err:
xadc_postdisable(indio_dev);
return ret;
}
iio: adc: xilinx: constify iio_buffer_setup_ops structure The iio_buffer_setup_ops structures are never modified, so declare this one as const, like the others. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2015-11-15 23:00:02 +03:00
static const struct iio_buffer_setup_ops xadc_buffer_ops = {
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
.preenable = &xadc_preenable,
.postdisable = &xadc_postdisable,
};
iio: xilinx-xadc: Make sure not exceed maximum samplerate The XADC supports a samplerate of up to 1MSPS. Unfortunately the hardware does not have a FIFO, which means it generates an interrupt for each conversion sequence. At one 1MSPS this creates an interrupt storm that causes the system to soft-lock. For this reason the driver limits the maximum samplerate to 150kSPS. Currently this check is only done when setting a new samplerate. But it is also possible that the initial samplerate configured in the FPGA bitstream exceeds the limit. In this case when starting to capture data without first changing the samplerate the system can overload. To prevent this check the currently configured samplerate in the probe function and reduce it to the maximum if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver") Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-04-03 16:27:16 +03:00
static int xadc_read_samplerate(struct xadc *xadc)
{
unsigned int div;
uint16_t val16;
int ret;
ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);
if (ret)
return ret;
div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET;
if (div < 2)
div = 2;
return xadc_get_dclk_rate(xadc) / div / 26;
}
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
static int xadc_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val, int *val2, long info)
{
struct xadc *xadc = iio_priv(indio_dev);
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
unsigned int bits = chan->scan_type.realbits;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
uint16_t val16;
int ret;
switch (info) {
case IIO_CHAN_INFO_RAW:
if (iio_buffer_enabled(indio_dev))
return -EBUSY;
ret = xadc_read_adc_reg(xadc, chan->address, &val16);
if (ret < 0)
return ret;
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
val16 >>= chan->scan_type.shift;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
if (chan->scan_type.sign == 'u')
*val = val16;
else
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
*val = sign_extend32(val16, bits - 1);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
return IIO_VAL_INT;
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
case IIO_VOLTAGE:
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
/* V = (val * 3.0) / 2**bits */
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
switch (chan->address) {
case XADC_REG_VCCINT:
case XADC_REG_VCCAUX:
iio: adc: xilinx: Fix VREFP scale The scaling factor for VREFP is 3.0/4096, not 1.0/4096; fix this to get correct readings. Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com> Cc: <stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2015-04-15 22:11:49 +03:00
case XADC_REG_VREFP:
iio: adc: xilinx: Fix VREFN scale The scaling factor for VREFN is 3.0/4096 (not 1.0/4096), just as for VREFP. This is not immediately obvious from the specification (Xilinx UG480), but has been confirmed by Xilinx support. Suggested-by: Hartmut Knaack <knaack.h@gmx.de> Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2015-11-11 23:24:38 +03:00
case XADC_REG_VREFN:
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
case XADC_REG_VCCBRAM:
case XADC_REG_VCCPINT:
case XADC_REG_VCCPAUX:
case XADC_REG_VCCO_DDR:
*val = 3000;
break;
default:
*val = 1000;
break;
}
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
*val2 = chan->scan_type.realbits;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
return IIO_VAL_FRACTIONAL_LOG2;
case IIO_TEMP:
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
/* Temp in C = (val * 503.975) / 2**bits - 273.15 */
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
*val = 503975;
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
*val2 = bits;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
return IIO_VAL_FRACTIONAL_LOG2;
default:
return -EINVAL;
}
case IIO_CHAN_INFO_OFFSET:
/* Only the temperature channel has an offset */
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
*val = -((273150 << bits) / 503975);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
return IIO_VAL_INT;
case IIO_CHAN_INFO_SAMP_FREQ:
iio: xilinx-xadc: Make sure not exceed maximum samplerate The XADC supports a samplerate of up to 1MSPS. Unfortunately the hardware does not have a FIFO, which means it generates an interrupt for each conversion sequence. At one 1MSPS this creates an interrupt storm that causes the system to soft-lock. For this reason the driver limits the maximum samplerate to 150kSPS. Currently this check is only done when setting a new samplerate. But it is also possible that the initial samplerate configured in the FPGA bitstream exceeds the limit. In this case when starting to capture data without first changing the samplerate the system can overload. To prevent this check the currently configured samplerate in the probe function and reduce it to the maximum if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver") Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-04-03 16:27:16 +03:00
ret = xadc_read_samplerate(xadc);
if (ret < 0)
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
return ret;
iio: xilinx-xadc: Make sure not exceed maximum samplerate The XADC supports a samplerate of up to 1MSPS. Unfortunately the hardware does not have a FIFO, which means it generates an interrupt for each conversion sequence. At one 1MSPS this creates an interrupt storm that causes the system to soft-lock. For this reason the driver limits the maximum samplerate to 150kSPS. Currently this check is only done when setting a new samplerate. But it is also possible that the initial samplerate configured in the FPGA bitstream exceeds the limit. In this case when starting to capture data without first changing the samplerate the system can overload. To prevent this check the currently configured samplerate in the probe function and reduce it to the maximum if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver") Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-04-03 16:27:16 +03:00
*val = ret;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
return IIO_VAL_INT;
default:
return -EINVAL;
}
}
iio: xilinx-xadc: Make sure not exceed maximum samplerate The XADC supports a samplerate of up to 1MSPS. Unfortunately the hardware does not have a FIFO, which means it generates an interrupt for each conversion sequence. At one 1MSPS this creates an interrupt storm that causes the system to soft-lock. For this reason the driver limits the maximum samplerate to 150kSPS. Currently this check is only done when setting a new samplerate. But it is also possible that the initial samplerate configured in the FPGA bitstream exceeds the limit. In this case when starting to capture data without first changing the samplerate the system can overload. To prevent this check the currently configured samplerate in the probe function and reduce it to the maximum if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver") Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-04-03 16:27:16 +03:00
static int xadc_write_samplerate(struct xadc *xadc, int val)
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
{
unsigned long clk_rate = xadc_get_dclk_rate(xadc);
unsigned int div;
iio: adc: xilinx: Check for return values in clk related functions This patch adds check for return values from clock related functions. This was reported by static code analysis tool. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2018-07-23 18:02:00 +03:00
if (!clk_rate)
return -EINVAL;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
if (val <= 0)
return -EINVAL;
/* Max. 150 kSPS */
iio: xilinx-xadc: Make sure not exceed maximum samplerate The XADC supports a samplerate of up to 1MSPS. Unfortunately the hardware does not have a FIFO, which means it generates an interrupt for each conversion sequence. At one 1MSPS this creates an interrupt storm that causes the system to soft-lock. For this reason the driver limits the maximum samplerate to 150kSPS. Currently this check is only done when setting a new samplerate. But it is also possible that the initial samplerate configured in the FPGA bitstream exceeds the limit. In this case when starting to capture data without first changing the samplerate the system can overload. To prevent this check the currently configured samplerate in the probe function and reduce it to the maximum if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver") Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-04-03 16:27:16 +03:00
if (val > XADC_MAX_SAMPLERATE)
val = XADC_MAX_SAMPLERATE;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
val *= 26;
/* Min 1MHz */
if (val < 1000000)
val = 1000000;
/*
* We want to round down, but only if we do not exceed the 150 kSPS
* limit.
*/
div = clk_rate / val;
iio: xilinx-xadc: Make sure not exceed maximum samplerate The XADC supports a samplerate of up to 1MSPS. Unfortunately the hardware does not have a FIFO, which means it generates an interrupt for each conversion sequence. At one 1MSPS this creates an interrupt storm that causes the system to soft-lock. For this reason the driver limits the maximum samplerate to 150kSPS. Currently this check is only done when setting a new samplerate. But it is also possible that the initial samplerate configured in the FPGA bitstream exceeds the limit. In this case when starting to capture data without first changing the samplerate the system can overload. To prevent this check the currently configured samplerate in the probe function and reduce it to the maximum if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver") Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-04-03 16:27:16 +03:00
if (clk_rate / div / 26 > XADC_MAX_SAMPLERATE)
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
div++;
if (div < 2)
div = 2;
else if (div > 0xff)
div = 0xff;
return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,
div << XADC_CONF2_DIV_OFFSET);
}
iio: xilinx-xadc: Make sure not exceed maximum samplerate The XADC supports a samplerate of up to 1MSPS. Unfortunately the hardware does not have a FIFO, which means it generates an interrupt for each conversion sequence. At one 1MSPS this creates an interrupt storm that causes the system to soft-lock. For this reason the driver limits the maximum samplerate to 150kSPS. Currently this check is only done when setting a new samplerate. But it is also possible that the initial samplerate configured in the FPGA bitstream exceeds the limit. In this case when starting to capture data without first changing the samplerate the system can overload. To prevent this check the currently configured samplerate in the probe function and reduce it to the maximum if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver") Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-04-03 16:27:16 +03:00
static int xadc_write_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int val, int val2, long info)
{
struct xadc *xadc = iio_priv(indio_dev);
if (info != IIO_CHAN_INFO_SAMP_FREQ)
return -EINVAL;
return xadc_write_samplerate(xadc, val);
}
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
static const struct iio_event_spec xadc_temp_events[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_ENABLE) |
BIT(IIO_EV_INFO_VALUE) |
BIT(IIO_EV_INFO_HYSTERESIS),
},
};
/* Separate values for upper and lower thresholds, but only a shared enabled */
static const struct iio_event_spec xadc_voltage_events[] = {
{
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_RISING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_FALLING,
.mask_separate = BIT(IIO_EV_INFO_VALUE),
}, {
.type = IIO_EV_TYPE_THRESH,
.dir = IIO_EV_DIR_EITHER,
.mask_separate = BIT(IIO_EV_INFO_ENABLE),
},
};
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
#define XADC_CHAN_TEMP(_chan, _scan_index, _addr, _bits) { \
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
.type = IIO_TEMP, \
.indexed = 1, \
.channel = (_chan), \
.address = (_addr), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE) | \
BIT(IIO_CHAN_INFO_OFFSET), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.event_spec = xadc_temp_events, \
.num_event_specs = ARRAY_SIZE(xadc_temp_events), \
.scan_index = (_scan_index), \
.scan_type = { \
.sign = 'u', \
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
.realbits = (_bits), \
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
.storagebits = 16, \
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
.shift = 16 - (_bits), \
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
.endianness = IIO_CPU, \
}, \
}
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
#define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _bits, _ext, _alarm) { \
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
.type = IIO_VOLTAGE, \
.indexed = 1, \
.channel = (_chan), \
.address = (_addr), \
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
BIT(IIO_CHAN_INFO_SCALE), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.event_spec = (_alarm) ? xadc_voltage_events : NULL, \
.num_event_specs = (_alarm) ? ARRAY_SIZE(xadc_voltage_events) : 0, \
.scan_index = (_scan_index), \
.scan_type = { \
iio: adc: xilinx: Fix VREFN sign The VREFN channel is bipolar, not unipolar. Small negative values do occur (e.g., -1mV), and unsigned conversion maps them incorrectly to large positive values (about +1V), so fix this. Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com> Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2015-04-15 22:11:50 +03:00
.sign = ((_addr) == XADC_REG_VREFN) ? 's' : 'u', \
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
.realbits = (_bits), \
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
.storagebits = 16, \
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
.shift = 16 - (_bits), \
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
.endianness = IIO_CPU, \
}, \
.extend_name = _ext, \
}
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
/* 7 Series */
#define XADC_7S_CHAN_TEMP(_chan, _scan_index, _addr) \
XADC_CHAN_TEMP(_chan, _scan_index, _addr, 12)
#define XADC_7S_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 12, _ext, _alarm)
static const struct iio_chan_spec xadc_7s_channels[] = {
XADC_7S_CHAN_TEMP(0, 8, XADC_REG_TEMP),
XADC_7S_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
XADC_7S_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
XADC_7S_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
XADC_7S_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpint", true),
XADC_7S_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpaux", true),
XADC_7S_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccoddr", true),
XADC_7S_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
XADC_7S_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
XADC_7S_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
XADC_7S_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
XADC_7S_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
XADC_7S_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
XADC_7S_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
XADC_7S_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
XADC_7S_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
XADC_7S_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
XADC_7S_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
XADC_7S_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
XADC_7S_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
XADC_7S_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
XADC_7S_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
XADC_7S_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
XADC_7S_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
XADC_7S_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
XADC_7S_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
};
/* UltraScale */
#define XADC_US_CHAN_TEMP(_chan, _scan_index, _addr) \
XADC_CHAN_TEMP(_chan, _scan_index, _addr, 10)
#define XADC_US_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 10, _ext, _alarm)
static const struct iio_chan_spec xadc_us_channels[] = {
XADC_US_CHAN_TEMP(0, 8, XADC_REG_TEMP),
XADC_US_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
XADC_US_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
XADC_US_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
XADC_US_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpsintlp", true),
XADC_US_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpsintfp", true),
XADC_US_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccpsaux", true),
XADC_US_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
XADC_US_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
XADC_US_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
XADC_US_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
XADC_US_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
XADC_US_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
XADC_US_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
XADC_US_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
XADC_US_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
XADC_US_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
XADC_US_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
XADC_US_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
XADC_US_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
XADC_US_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
XADC_US_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
XADC_US_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
XADC_US_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
XADC_US_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
XADC_US_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
};
static const struct iio_info xadc_info = {
.read_raw = &xadc_read_raw,
.write_raw = &xadc_write_raw,
.read_event_config = &xadc_read_event_config,
.write_event_config = &xadc_write_event_config,
.read_event_value = &xadc_read_event_value,
.write_event_value = &xadc_write_event_value,
.update_scan_mode = &xadc_update_scan_mode,
};
static const struct of_device_id xadc_of_match_table[] = {
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
{
.compatible = "xlnx,zynq-xadc-1.00.a",
.data = &xadc_zynq_ops
}, {
.compatible = "xlnx,axi-xadc-1.00.a",
.data = &xadc_7s_axi_ops
}, {
.compatible = "xlnx,system-management-wiz-1.3",
.data = &xadc_us_axi_ops
},
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
{ },
};
MODULE_DEVICE_TABLE(of, xadc_of_match_table);
static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np,
unsigned int *conf)
{
iio: adc: xilinx-xadc: use devm_krealloc() Use the managed variant of krealloc() and shrink the code a bit. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20200824173859.4910-4-brgl@bgdev.pl Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-08-24 20:38:59 +03:00
struct device *dev = indio_dev->dev.parent;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
struct xadc *xadc = iio_priv(indio_dev);
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
const struct iio_chan_spec *channel_templates;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
struct iio_chan_spec *channels, *chan;
struct device_node *chan_node, *child;
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
unsigned int max_channels;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
unsigned int num_channels;
const char *external_mux;
u32 ext_mux_chan;
iio: adc: xilinx: Remove dead code from xadc_zynq_setup This patch removes dead code from xadc_zynq_setup. The condition "if (tck_rate > XADC_ZYNQ_TCK_RATE_MAX)" cannot be true at any point of time. There is also an incompatible parameter used in the code. This patch fixes the same reported by coverity. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2018-07-18 14:12:09 +03:00
u32 reg;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
int ret;
*conf = 0;
ret = of_property_read_string(np, "xlnx,external-mux", &external_mux);
if (ret < 0 || strcasecmp(external_mux, "none") == 0)
xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE;
else if (strcasecmp(external_mux, "single") == 0)
xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE;
else if (strcasecmp(external_mux, "dual") == 0)
xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL;
else
return -EINVAL;
if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) {
ret = of_property_read_u32(np, "xlnx,external-mux-channel",
&ext_mux_chan);
if (ret < 0)
return ret;
if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) {
if (ext_mux_chan == 0)
ext_mux_chan = XADC_REG_VPVN;
else if (ext_mux_chan <= 16)
ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
else
return -EINVAL;
} else {
if (ext_mux_chan > 0 && ext_mux_chan <= 8)
ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
else
return -EINVAL;
}
*conf |= XADC_CONF0_MUX | XADC_CONF0_CHAN(ext_mux_chan);
}
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
if (xadc->ops->type == XADC_TYPE_S7) {
channel_templates = xadc_7s_channels;
max_channels = ARRAY_SIZE(xadc_7s_channels);
} else {
channel_templates = xadc_us_channels;
max_channels = ARRAY_SIZE(xadc_us_channels);
}
channels = devm_kmemdup(dev, channel_templates,
sizeof(channels[0]) * max_channels, GFP_KERNEL);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
if (!channels)
return -ENOMEM;
num_channels = 9;
chan = &channels[9];
chan_node = of_get_child_by_name(np, "xlnx,channels");
if (chan_node) {
for_each_child_of_node(chan_node, child) {
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
if (num_channels >= max_channels) {
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
of_node_put(child);
break;
}
ret = of_property_read_u32(child, "reg", &reg);
if (ret || reg > 16)
continue;
if (of_property_read_bool(child, "xlnx,bipolar"))
chan->scan_type.sign = 's';
if (reg == 0) {
chan->scan_index = 11;
chan->address = XADC_REG_VPVN;
} else {
chan->scan_index = 15 + reg;
iio: adc: xilinx-xadc: assign auxiliary channels address correctly This patch fixes incorrect logic for assigning address to auxiliary channels of xilinx xadc. Signed-off-by: Subbaraya Sundeep Bhatta <sbhatta@xilinx.com> Acked-by: Lars-Peter Clausen <lars@metafoo.de> Cc: Stable@vger.kernel.org Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-11-09 12:55:00 +03:00
chan->address = XADC_REG_VAUX(reg - 1);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
}
num_channels++;
chan++;
}
}
of_node_put(chan_node);
indio_dev->num_channels = num_channels;
iio: adc: xilinx-xadc: use devm_krealloc() Use the managed variant of krealloc() and shrink the code a bit. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20200824173859.4910-4-brgl@bgdev.pl Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-08-24 20:38:59 +03:00
indio_dev->channels = devm_krealloc(dev, channels,
sizeof(*channels) * num_channels,
GFP_KERNEL);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
/* If we can't resize the channels array, just use the original */
if (!indio_dev->channels)
indio_dev->channels = channels;
return 0;
}
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
static const char * const xadc_type_names[] = {
[XADC_TYPE_S7] = "xadc",
[XADC_TYPE_US] = "xilinx-system-monitor",
};
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
static void xadc_clk_disable_unprepare(void *data)
{
struct clk *clk = data;
clk_disable_unprepare(clk);
}
static void xadc_cancel_delayed_work(void *data)
{
struct delayed_work *work = data;
cancel_delayed_work_sync(work);
}
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
static int xadc_probe(struct platform_device *pdev)
{
iio: adc: xilinx: use helper variable for &pdev->dev It's more elegant to use a helper local variable to store the address of the underlying struct device than to dereference pdev everywhere. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-2-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:57 +03:00
struct device *dev = &pdev->dev;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
const struct of_device_id *id;
struct iio_dev *indio_dev;
unsigned int bipolar_mask;
unsigned int conf0;
struct xadc *xadc;
int ret;
int irq;
int i;
iio: adc: xilinx: use helper variable for &pdev->dev It's more elegant to use a helper local variable to store the address of the underlying struct device than to dereference pdev everywhere. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-2-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:57 +03:00
if (!dev->of_node)
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
return -ENODEV;
iio: adc: xilinx: use helper variable for &pdev->dev It's more elegant to use a helper local variable to store the address of the underlying struct device than to dereference pdev everywhere. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-2-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:57 +03:00
id = of_match_node(xadc_of_match_table, dev->of_node);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
if (!id)
return -EINVAL;
irq = platform_get_irq(pdev, 0);
if (irq <= 0)
return -ENXIO;
iio: adc: xilinx: use helper variable for &pdev->dev It's more elegant to use a helper local variable to store the address of the underlying struct device than to dereference pdev everywhere. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-2-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:57 +03:00
indio_dev = devm_iio_device_alloc(dev, sizeof(*xadc));
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
if (!indio_dev)
return -ENOMEM;
xadc = iio_priv(indio_dev);
xadc->ops = id->data;
iio: adc: xilinx: Remove platform_get_irq from xadc_remove function This patch avoids getting irq number in xadc_remove function. Instead store 'irq' in xadc struct and use xadc->irq wherever needed. This patch also resolves a warning reported by coverity where it asks to check return value of platform_get_irq() for any errors in xadc_remove. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2018-07-23 18:02:02 +03:00
xadc->irq = irq;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
init_completion(&xadc->completion);
mutex_init(&xadc->mutex);
spin_lock_init(&xadc->lock);
INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker);
iio: adc: xilinx-xadc: use devm_platform_ioremap_resource Reduces local boilerplate. Suggested by coccinelle. CHECK drivers/iio/adc/xilinx-xadc-core.c drivers/iio/adc/xilinx-xadc-core.c:1184:1-11: WARNING: Use devm_platform_ioremap_resource for xadc -> base Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Manish Narani <manish.narani@xilinx.com> Reviewed-by: Sven Van Asbroeck <TheSven73@gmail.com>
2019-10-13 19:48:48 +03:00
xadc->base = devm_platform_ioremap_resource(pdev, 0);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
if (IS_ERR(xadc->base))
return PTR_ERR(xadc->base);
iio: xilinx-xadc: Add basic support for Ultrascale System Monitor The xilinx-xadc IIO driver currently has support for the XADC in the Xilinx 7 series FPGAs. The system-monitor is the equivalent to the XADC in the Xilinx UltraScale and UltraScale+ FPGAs. The IP designers did a good job at maintaining backwards compatibility and only minor changes are required to add basic support for the system-monitor core. The non backwards compatible changes are: * Register map offset was moved from 0x200 to 0x400 * Only one ADC compared to two in the XADC * 10 bit ADC instead of 12 bit ADC * Two of the channels monitor different supplies Add the necessary logic to accommodate these changes to support the system-monitor in the XADC driver. Note that this patch does not include support for some new features found in the system-monitor like additional alarms, user supply monitoring and secondary system-monitor access. This might be added at a later time. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20200922134624.13191-2-lars@metafoo.de Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-09-22 16:46:24 +03:00
indio_dev->name = xadc_type_names[xadc->ops->type];
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->info = &xadc_info;
iio: adc: xilinx: use helper variable for &pdev->dev It's more elegant to use a helper local variable to store the address of the underlying struct device than to dereference pdev everywhere. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-2-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:57 +03:00
ret = xadc_parse_dt(indio_dev, dev->of_node, &conf0);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
if (ret)
iio: adc: xilinx-xadc: use devm_krealloc() Use the managed variant of krealloc() and shrink the code a bit. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20200824173859.4910-4-brgl@bgdev.pl Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-08-24 20:38:59 +03:00
return ret;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
&iio_pollfunc_store_time,
&xadc_trigger_handler,
&xadc_buffer_ops);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
if (ret)
iio: adc: xilinx-xadc: use devm_krealloc() Use the managed variant of krealloc() and shrink the code a bit. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20200824173859.4910-4-brgl@bgdev.pl Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-08-24 20:38:59 +03:00
return ret;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
if (IS_ERR(xadc->convst_trigger))
return PTR_ERR(xadc->convst_trigger);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev,
"samplerate");
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
if (IS_ERR(xadc->samplerate_trigger))
return PTR_ERR(xadc->samplerate_trigger);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
}
iio: adc: xilinx: use helper variable for &pdev->dev It's more elegant to use a helper local variable to store the address of the underlying struct device than to dereference pdev everywhere. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-2-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:57 +03:00
xadc->clk = devm_clk_get(dev, NULL);
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
if (IS_ERR(xadc->clk))
return PTR_ERR(xadc->clk);
iio: adc: xilinx: Handle return value of clk_prepare_enable clk_prepare_enable() can fail here and we must check its return value. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2017-05-26 09:37:41 +03:00
ret = clk_prepare_enable(xadc->clk);
if (ret)
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
return ret;
ret = devm_add_action_or_reset(dev,
xadc_clk_disable_unprepare, xadc->clk);
if (ret)
return ret;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
iio: xilinx-xadc: Make sure not exceed maximum samplerate The XADC supports a samplerate of up to 1MSPS. Unfortunately the hardware does not have a FIFO, which means it generates an interrupt for each conversion sequence. At one 1MSPS this creates an interrupt storm that causes the system to soft-lock. For this reason the driver limits the maximum samplerate to 150kSPS. Currently this check is only done when setting a new samplerate. But it is also possible that the initial samplerate configured in the FPGA bitstream exceeds the limit. In this case when starting to capture data without first changing the samplerate the system can overload. To prevent this check the currently configured samplerate in the probe function and reduce it to the maximum if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver") Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-04-03 16:27:16 +03:00
/*
* Make sure not to exceed the maximum samplerate since otherwise the
* resulting interrupt storm will soft-lock the system.
*/
if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
ret = xadc_read_samplerate(xadc);
if (ret < 0)
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
return ret;
iio: xilinx-xadc: Make sure not exceed maximum samplerate The XADC supports a samplerate of up to 1MSPS. Unfortunately the hardware does not have a FIFO, which means it generates an interrupt for each conversion sequence. At one 1MSPS this creates an interrupt storm that causes the system to soft-lock. For this reason the driver limits the maximum samplerate to 150kSPS. Currently this check is only done when setting a new samplerate. But it is also possible that the initial samplerate configured in the FPGA bitstream exceeds the limit. In this case when starting to capture data without first changing the samplerate the system can overload. To prevent this check the currently configured samplerate in the probe function and reduce it to the maximum if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver") Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-04-03 16:27:16 +03:00
if (ret > XADC_MAX_SAMPLERATE) {
ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE);
if (ret < 0)
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
return ret;
iio: xilinx-xadc: Make sure not exceed maximum samplerate The XADC supports a samplerate of up to 1MSPS. Unfortunately the hardware does not have a FIFO, which means it generates an interrupt for each conversion sequence. At one 1MSPS this creates an interrupt storm that causes the system to soft-lock. For this reason the driver limits the maximum samplerate to 150kSPS. Currently this check is only done when setting a new samplerate. But it is also possible that the initial samplerate configured in the FPGA bitstream exceeds the limit. In this case when starting to capture data without first changing the samplerate the system can overload. To prevent this check the currently configured samplerate in the probe function and reduce it to the maximum if necessary. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver") Cc: <Stable@vger.kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-04-03 16:27:16 +03:00
}
}
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
ret = devm_request_irq(dev, xadc->irq, xadc->ops->interrupt_handler, 0,
dev_name(dev), indio_dev);
if (ret)
return ret;
ret = devm_add_action_or_reset(dev, xadc_cancel_delayed_work,
&xadc->zynq_unmask_work);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
if (ret)
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
return ret;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
iio: adc: xilinx: Move request_irq before enabling interrupts Enabling the Interrupts before registering the irq handler is a bad idea. This patch corrects the same for XADC driver. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2018-07-23 18:02:03 +03:00
ret = xadc->ops->setup(pdev, indio_dev, xadc->irq);
if (ret)
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
return ret;
iio: adc: xilinx: Move request_irq before enabling interrupts Enabling the Interrupts before registering the irq handler is a bad idea. This patch corrects the same for XADC driver. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2018-07-23 18:02:03 +03:00
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
for (i = 0; i < 16; i++)
xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i),
&xadc->threshold[i]);
ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);
if (ret)
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
return ret;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
bipolar_mask = 0;
for (i = 0; i < indio_dev->num_channels; i++) {
if (indio_dev->channels[i].scan_type.sign == 's')
bipolar_mask |= BIT(indio_dev->channels[i].scan_index);
}
ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask);
if (ret)
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
return ret;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1),
bipolar_mask >> 16);
if (ret)
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
return ret;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
/* Disable all alarms */
iio: adc: xilinx: Check for return values in clk related functions This patch adds check for return values from clock related functions. This was reported by static code analysis tool. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2018-07-23 18:02:00 +03:00
ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_ALARM_MASK,
XADC_CONF1_ALARM_MASK);
if (ret)
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
return ret;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
/* Set thresholds to min/max */
for (i = 0; i < 16; i++) {
/*
* Set max voltage threshold and both temperature thresholds to
* 0xffff, min voltage threshold to 0.
*/
if (i % 8 < 4 || i == 7)
xadc->threshold[i] = 0xffff;
else
xadc->threshold[i] = 0;
iio: adc: xilinx: check return value of xadc_write_adc_reg In function xadc_probe, xadc_write_adc_reg can return an error value when write fails. The fix checks for the return value consistent with other invocations of the latter function. Signed-off-by: Aditya Pakki <pakki001@umn.edu> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2018-12-27 22:54:52 +03:00
ret = xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(i),
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
xadc->threshold[i]);
iio: adc: xilinx: check return value of xadc_write_adc_reg In function xadc_probe, xadc_write_adc_reg can return an error value when write fails. The fix checks for the return value consistent with other invocations of the latter function. Signed-off-by: Aditya Pakki <pakki001@umn.edu> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2018-12-27 22:54:52 +03:00
if (ret)
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
return ret;
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
}
/* Go to non-buffered mode */
xadc_postdisable(indio_dev);
iio: adc: xilinx: use more devres helpers and remove remove() In order to simplify resource management and error paths in probe() and entirely drop the remove() callback - use devres helpers wherever possible. Define devm actions for cancelling the delayed work and disabling the clock. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Tested-by: Anand Ashok Dumbre <anandash@xilinx.com> Reviewed-by: Anand Ashok Dumbre <anandash@xilinx.com> Link: https://lore.kernel.org/r/20201130142759.28216-4-brgl@bgdev.pl Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-11-30 17:27:59 +03:00
return devm_iio_device_register(dev, indio_dev);
iio:adc: Add Xilinx XADC driver The Xilinx XADC is a ADC that can be found in the series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication. Currently two different frontends for the DRP interface exist. One that is only available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The other one is available on all series 7 platforms and is a softmacro with a AXI interface. This driver supports both interfaces and internally has a small abstraction layer that hides the specifics of these interfaces from the main driver logic. The ADC has a couple of internal channels which are used for voltage and temperature monitoring of the FPGA as well as one primary and up to 16 channels auxiliary channels for measuring external voltages. The external auxiliary channels can either be directly connected each to one physical pin on the FPGA or they can make use of an external multiplexer which is responsible for multiplexing the external signals onto one pair of physical pins. The voltage and temperature monitoring channels also have an event capability which allows to generate a interrupt when their value falls below or raises above a set threshold. Buffered sampling mode is supported by the driver, but only for AXI-XADC since the ZYNQ XADC interface does not have capabilities for supporting buffer mode (no end-of-conversion interrupt). If buffered mode is supported the driver will register two triggers. One "xadc-samplerate" trigger which will generate samples with the configured samplerate. And one "xadc-convst" trigger which will generate one sample each time the CONVST (conversion start) signal is asserted. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2014-02-17 18:10:00 +04:00
}
static struct platform_driver xadc_driver = {
.probe = xadc_probe,
.driver = {
.name = "xadc",
.of_match_table = xadc_of_match_table,
},
};
module_platform_driver(xadc_driver);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
MODULE_DESCRIPTION("Xilinx XADC IIO driver");