2005-04-17 02:20:36 +04:00
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/* head-uc-fr555.S: FR555 uc-linux specific bits of initialisation
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*
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* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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2009-04-28 03:37:58 +04:00
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#include <linux/init.h>
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2005-04-17 02:20:36 +04:00
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#include <linux/threads.h>
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#include <linux/linkage.h>
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#include <asm/ptrace.h>
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#include <asm/page.h>
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#include <asm/spr-regs.h>
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#include <asm/mb86943a.h>
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#include "head.inc"
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#define __551_DARS0 0xfeff0100
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#define __551_DARS1 0xfeff0104
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#define __551_DARS2 0xfeff0108
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#define __551_DARS3 0xfeff010c
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#define __551_DAMK0 0xfeff0110
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#define __551_DAMK1 0xfeff0114
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#define __551_DAMK2 0xfeff0118
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#define __551_DAMK3 0xfeff011c
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#define __551_LCR 0xfeff1100
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#define __551_LSBR 0xfeff1c00
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2009-04-28 03:37:58 +04:00
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__INIT
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2005-04-17 02:20:36 +04:00
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.balign 4
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###############################################################################
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#
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# describe the position and layout of the SDRAM controller registers
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#
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# ENTRY: EXIT:
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# GR5 - cacheline size
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# GR11 - displacement of 2nd SDRAM addr reg from GR14
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# GR12 - displacement of 3rd SDRAM addr reg from GR14
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# GR13 - displacement of 4th SDRAM addr reg from GR14
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# GR14 - address of 1st SDRAM addr reg
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# GR15 - amount to shift address by to match SDRAM addr reg
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# GR26 &__head_reference [saved]
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# GR30 LED address [saved]
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# CC0 - T if DARS0 is present
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# CC1 - T if DARS1 is present
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# CC2 - T if DARS2 is present
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# CC3 - T if DARS3 is present
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#
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###############################################################################
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.globl __head_fr555_describe_sdram
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__head_fr555_describe_sdram:
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sethi.p %hi(__551_DARS0),gr14
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setlo %lo(__551_DARS0),gr14
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setlos.p #__551_DARS1-__551_DARS0,gr11
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setlos #__551_DARS2-__551_DARS0,gr12
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setlos.p #__551_DARS3-__551_DARS0,gr13
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setlos #64,gr5 ; cacheline size
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setlos #20,gr15 ; amount to shift addr by
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setlos #0x00ff,gr4
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movgs gr4,cccr ; extant DARS/DAMK regs
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bralr
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###############################################################################
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#
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# rearrange the bus controller registers
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#
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# ENTRY: EXIT:
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# GR26 &__head_reference [saved]
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# GR30 LED address revised LED address
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#
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###############################################################################
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.globl __head_fr555_set_busctl
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__head_fr555_set_busctl:
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LEDS 0x100f
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sethi.p %hi(__551_LSBR),gr10
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setlo %lo(__551_LSBR),gr10
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sethi.p %hi(__551_LCR),gr11
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setlo %lo(__551_LCR),gr11
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# set the bus controller
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sethi.p %hi(__region_CS1),gr4
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setlo %lo(__region_CS1),gr4
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sethi.p %hi(__region_CS1_M),gr5
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setlo %lo(__region_CS1_M),gr5
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sethi.p %hi(__region_CS1_C),gr6
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setlo %lo(__region_CS1_C),gr6
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sti gr4,@(gr10,#1*0x08)
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sti gr5,@(gr10,#1*0x08+0x100)
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sti gr6,@(gr11,#1*0x08)
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sethi.p %hi(__region_CS2),gr4
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setlo %lo(__region_CS2),gr4
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sethi.p %hi(__region_CS2_M),gr5
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setlo %lo(__region_CS2_M),gr5
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sethi.p %hi(__region_CS2_C),gr6
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setlo %lo(__region_CS2_C),gr6
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sti gr4,@(gr10,#2*0x08)
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sti gr5,@(gr10,#2*0x08+0x100)
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sti gr6,@(gr11,#2*0x08)
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sethi.p %hi(__region_CS3),gr4
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setlo %lo(__region_CS3),gr4
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sethi.p %hi(__region_CS3_M),gr5
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setlo %lo(__region_CS3_M),gr5
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sethi.p %hi(__region_CS3_C),gr6
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setlo %lo(__region_CS3_C),gr6
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sti gr4,@(gr10,#3*0x08)
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sti gr5,@(gr10,#3*0x08+0x100)
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sti gr6,@(gr11,#3*0x08)
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sethi.p %hi(__region_CS4),gr4
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setlo %lo(__region_CS4),gr4
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sethi.p %hi(__region_CS4_M),gr5
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setlo %lo(__region_CS4_M),gr5
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sethi.p %hi(__region_CS4_C),gr6
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setlo %lo(__region_CS4_C),gr6
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sti gr4,@(gr10,#4*0x08)
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sti gr5,@(gr10,#4*0x08+0x100)
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sti gr6,@(gr11,#4*0x08)
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sethi.p %hi(__region_CS5),gr4
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setlo %lo(__region_CS5),gr4
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sethi.p %hi(__region_CS5_M),gr5
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setlo %lo(__region_CS5_M),gr5
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sethi.p %hi(__region_CS5_C),gr6
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setlo %lo(__region_CS5_C),gr6
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sti gr4,@(gr10,#5*0x08)
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sti gr5,@(gr10,#5*0x08+0x100)
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sti gr6,@(gr11,#5*0x08)
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sethi.p %hi(__region_CS6),gr4
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setlo %lo(__region_CS6),gr4
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sethi.p %hi(__region_CS6_M),gr5
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setlo %lo(__region_CS6_M),gr5
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sethi.p %hi(__region_CS6_C),gr6
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setlo %lo(__region_CS6_C),gr6
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sti gr4,@(gr10,#6*0x08)
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sti gr5,@(gr10,#6*0x08+0x100)
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sti gr6,@(gr11,#6*0x08)
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sethi.p %hi(__region_CS7),gr4
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setlo %lo(__region_CS7),gr4
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sethi.p %hi(__region_CS7_M),gr5
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setlo %lo(__region_CS7_M),gr5
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sethi.p %hi(__region_CS7_C),gr6
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setlo %lo(__region_CS7_C),gr6
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sti gr4,@(gr10,#7*0x08)
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sti gr5,@(gr10,#7*0x08+0x100)
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sti gr6,@(gr11,#7*0x08)
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membar
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bar
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# adjust LED bank address
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#ifdef CONFIG_MB93091_VDK
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sethi.p %hi(LED_ADDR - 0x20000000 +__region_CS2),gr30
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setlo %lo(LED_ADDR - 0x20000000 +__region_CS2),gr30
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#endif
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bralr
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###############################################################################
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#
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# determine the total SDRAM size
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#
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# ENTRY: EXIT:
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# GR25 - SDRAM size
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# GR26 &__head_reference [saved]
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# GR30 LED address [saved]
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#
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###############################################################################
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.globl __head_fr555_survey_sdram
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__head_fr555_survey_sdram:
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sethi.p %hi(__551_DAMK0),gr11
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setlo %lo(__551_DAMK0),gr11
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sethi.p %hi(__551_DARS0),gr12
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setlo %lo(__551_DARS0),gr12
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sethi.p %hi(0xfff),gr17 ; unused SDRAM AMK value
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setlo %lo(0xfff),gr17
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setlos #0,gr25
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ldi @(gr11,#0x00),gr6 ; DAMK0: bits 11:0 match addr 11:0
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subcc gr6,gr17,gr0,icc0
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beq icc0,#0,__head_no_DCS0
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ldi @(gr12,#0x00),gr4 ; DARS0
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add gr25,gr6,gr25
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addi gr25,#1,gr25
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__head_no_DCS0:
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ldi @(gr11,#0x04),gr6 ; DAMK1: bits 11:0 match addr 11:0
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subcc gr6,gr17,gr0,icc0
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beq icc0,#0,__head_no_DCS1
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ldi @(gr12,#0x04),gr4 ; DARS1
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add gr25,gr6,gr25
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addi gr25,#1,gr25
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__head_no_DCS1:
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ldi @(gr11,#0x8),gr6 ; DAMK2: bits 11:0 match addr 11:0
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subcc gr6,gr17,gr0,icc0
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beq icc0,#0,__head_no_DCS2
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ldi @(gr12,#0x8),gr4 ; DARS2
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add gr25,gr6,gr25
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addi gr25,#1,gr25
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__head_no_DCS2:
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ldi @(gr11,#0xc),gr6 ; DAMK3: bits 11:0 match addr 11:0
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subcc gr6,gr17,gr0,icc0
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beq icc0,#0,__head_no_DCS3
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ldi @(gr12,#0xc),gr4 ; DARS3
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add gr25,gr6,gr25
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addi gr25,#1,gr25
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__head_no_DCS3:
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slli gr25,#20,gr25 ; shift [11:0] -> [31:20]
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bralr
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###############################################################################
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#
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# set the protection map with the I/DAMPR registers
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#
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# ENTRY: EXIT:
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# GR25 SDRAM size saved
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# GR30 LED address saved
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#
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###############################################################################
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.globl __head_fr555_set_protection
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__head_fr555_set_protection:
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movsg lr,gr27
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sethi.p %hi(0xfff00000),gr11
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setlo %lo(0xfff00000),gr11
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# set the I/O region protection registers for FR555
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sethi.p %hi(__region_IO),gr7
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setlo %lo(__region_IO),gr7
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ori gr7,#xAMPRx_SS_512Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr5
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movgs gr0,iampr15
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movgs gr0,iamlr15
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movgs gr5,dampr15
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movgs gr7,damlr15
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# need to tile the remaining IAMPR/DAMPR registers to cover as much of the RAM as possible
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# - start with the highest numbered registers
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sethi.p %hi(__kernel_image_end),gr8
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setlo %lo(__kernel_image_end),gr8
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sethi.p %hi(32768),gr4 ; allow for a maximal allocator bitmap
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setlo %lo(32768),gr4
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add gr8,gr4,gr8
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sethi.p %hi(1024*2048-1),gr4 ; round up to nearest 2MiB
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setlo %lo(1024*2048-1),gr4
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add.p gr8,gr4,gr8
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not gr4,gr4
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and gr8,gr4,gr8
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sethi.p %hi(__page_offset),gr9
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setlo %lo(__page_offset),gr9
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add gr9,gr25,gr9
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# GR8 = base of uncovered RAM
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# GR9 = top of uncovered RAM
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# GR11 - mask for DAMLR/IAMLR regs
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#
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call __head_split_region
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movgs gr4,iampr14
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movgs gr6,iamlr14
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movgs gr5,dampr14
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movgs gr7,damlr14
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call __head_split_region
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movgs gr4,iampr13
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movgs gr6,iamlr13
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movgs gr5,dampr13
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movgs gr7,damlr13
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call __head_split_region
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movgs gr4,iampr12
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movgs gr6,iamlr12
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movgs gr5,dampr12
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movgs gr7,damlr12
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call __head_split_region
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movgs gr4,iampr11
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movgs gr6,iamlr11
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movgs gr5,dampr11
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movgs gr7,damlr11
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call __head_split_region
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movgs gr4,iampr10
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movgs gr6,iamlr10
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movgs gr5,dampr10
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movgs gr7,damlr10
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call __head_split_region
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movgs gr4,iampr9
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movgs gr6,iamlr9
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movgs gr5,dampr9
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movgs gr7,damlr9
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call __head_split_region
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movgs gr4,iampr8
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movgs gr6,iamlr8
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movgs gr5,dampr8
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movgs gr7,damlr8
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call __head_split_region
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movgs gr4,iampr7
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movgs gr6,iamlr7
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movgs gr5,dampr7
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movgs gr7,damlr7
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call __head_split_region
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movgs gr4,iampr6
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movgs gr6,iamlr6
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movgs gr5,dampr6
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movgs gr7,damlr6
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call __head_split_region
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movgs gr4,iampr5
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movgs gr6,iamlr5
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movgs gr5,dampr5
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movgs gr7,damlr5
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call __head_split_region
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movgs gr4,iampr4
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movgs gr6,iamlr4
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movgs gr5,dampr4
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movgs gr7,damlr4
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call __head_split_region
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movgs gr4,iampr3
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movgs gr6,iamlr3
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movgs gr5,dampr3
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movgs gr7,damlr3
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call __head_split_region
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movgs gr4,iampr2
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movgs gr6,iamlr2
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movgs gr5,dampr2
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movgs gr7,damlr2
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call __head_split_region
|
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movgs gr4,iampr1
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movgs gr6,iamlr1
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movgs gr5,dampr1
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movgs gr7,damlr1
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|
# cover kernel core image with kernel-only segment
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|
|
|
sethi.p %hi(__page_offset),gr8
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setlo %lo(__page_offset),gr8
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call __head_split_region
|
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|
#ifdef CONFIG_PROTECT_KERNEL
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|
ori.p gr4,#xAMPRx_S_KERNEL,gr4
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|
ori gr5,#xAMPRx_S_KERNEL,gr5
|
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#endif
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movgs gr4,iampr0
|
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|
movgs gr6,iamlr0
|
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|
movgs gr5,dampr0
|
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|
|
movgs gr7,damlr0
|
|
|
|
|
jmpl @(gr27,gr0)
|
