2012-12-10 20:23:59 +04:00
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Derived from arch/arm/kvm/reset.c
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/errno.h>
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#include <linux/kvm_host.h>
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#include <linux/kvm.h>
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2015-07-07 19:30:02 +03:00
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#include <linux/hw_breakpoint.h>
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2012-12-10 20:23:59 +04:00
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2012-12-07 21:52:03 +04:00
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#include <kvm/arm_arch_timer.h>
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2018-09-26 19:32:43 +03:00
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#include <asm/cpufeature.h>
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2012-12-10 20:23:59 +04:00
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#include <asm/cputype.h>
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#include <asm/ptrace.h>
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#include <asm/kvm_arm.h>
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arm64: kvm: allows kvm cpu hotplug
The current kvm implementation on arm64 does cpu-specific initialization
at system boot, and has no way to gracefully shutdown a core in terms of
kvm. This prevents kexec from rebooting the system at EL2.
This patch adds a cpu tear-down function and also puts an existing cpu-init
code into a separate function, kvm_arch_hardware_disable() and
kvm_arch_hardware_enable() respectively.
We don't need the arm64 specific cpu hotplug hook any more.
Since this patch modifies common code between arm and arm64, one stub
definition, __cpu_reset_hyp_mode(), is added on arm side to avoid
compilation errors.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
[Rebase, added separate VHE init/exit path, changed resets use of
kvm_call_hyp() to the __version, en/disabled hardware in init_subsystems(),
added icache maintenance to __kvm_hyp_reset() and removed lr restore, removed
guest-enter after teardown handling]
Signed-off-by: James Morse <james.morse@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-27 19:47:05 +03:00
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#include <asm/kvm_asm.h>
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2012-12-10 20:23:59 +04:00
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#include <asm/kvm_coproc.h>
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arm64: kvm: allows kvm cpu hotplug
The current kvm implementation on arm64 does cpu-specific initialization
at system boot, and has no way to gracefully shutdown a core in terms of
kvm. This prevents kexec from rebooting the system at EL2.
This patch adds a cpu tear-down function and also puts an existing cpu-init
code into a separate function, kvm_arch_hardware_disable() and
kvm_arch_hardware_enable() respectively.
We don't need the arm64 specific cpu hotplug hook any more.
Since this patch modifies common code between arm and arm64, one stub
definition, __cpu_reset_hyp_mode(), is added on arm side to avoid
compilation errors.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
[Rebase, added separate VHE init/exit path, changed resets use of
kvm_call_hyp() to the __version, en/disabled hardware in init_subsystems(),
added icache maintenance to __kvm_hyp_reset() and removed lr restore, removed
guest-enter after teardown handling]
Signed-off-by: James Morse <james.morse@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-27 19:47:05 +03:00
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#include <asm/kvm_mmu.h>
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2012-12-10 20:23:59 +04:00
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2018-09-26 19:32:52 +03:00
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/* Maximum phys_shift supported for any VM on this host */
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static u32 kvm_ipa_limit;
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2012-12-10 20:23:59 +04:00
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/*
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* ARMv8 Reset Values
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*/
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static const struct kvm_regs default_regs_reset = {
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.regs.pstate = (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT |
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PSR_F_BIT | PSR_D_BIT),
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};
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2013-02-07 14:46:46 +04:00
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static const struct kvm_regs default_regs_reset32 = {
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2018-07-05 17:16:53 +03:00
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.regs.pstate = (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT |
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PSR_AA32_I_BIT | PSR_AA32_F_BIT),
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2013-02-07 14:46:46 +04:00
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};
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static bool cpu_has_32bit_el1(void)
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{
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u64 pfr0;
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2017-03-23 18:14:39 +03:00
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pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
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2013-02-07 14:46:46 +04:00
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return !!(pfr0 & 0x20);
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}
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2015-07-07 19:30:02 +03:00
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/**
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2018-10-12 19:12:48 +03:00
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* kvm_arch_vm_ioctl_check_extension
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2015-07-07 19:30:02 +03:00
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*
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* We currently assume that the number of HW registers is uniform
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* across all CPUs (see cpuinfo_sanity_check).
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*/
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2018-10-12 19:12:48 +03:00
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int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext)
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2012-12-10 20:23:59 +04:00
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{
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int r;
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switch (ext) {
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2013-02-07 14:46:46 +04:00
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case KVM_CAP_ARM_EL1_32BIT:
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r = cpu_has_32bit_el1();
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break;
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2015-07-07 19:30:02 +03:00
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case KVM_CAP_GUEST_DEBUG_HW_BPS:
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r = get_num_brps();
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break;
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case KVM_CAP_GUEST_DEBUG_HW_WPS:
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r = get_num_wrps();
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break;
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2016-01-11 17:46:15 +03:00
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case KVM_CAP_ARM_PMU_V3:
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r = kvm_arm_support_pmu_v3();
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break;
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2018-07-19 18:24:23 +03:00
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case KVM_CAP_ARM_INJECT_SERROR_ESR:
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r = cpus_have_const_cap(ARM64_HAS_RAS_EXTN);
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break;
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2015-07-07 19:30:02 +03:00
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case KVM_CAP_SET_GUEST_DEBUG:
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2016-01-11 15:56:17 +03:00
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case KVM_CAP_VCPU_ATTRIBUTES:
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2015-07-07 19:30:02 +03:00
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r = 1;
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break;
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2018-09-26 19:32:54 +03:00
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case KVM_CAP_ARM_VM_IPA_SIZE:
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r = kvm_ipa_limit;
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break;
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2012-12-10 20:23:59 +04:00
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default:
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r = 0;
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}
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return r;
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}
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/**
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* kvm_reset_vcpu - sets core registers and sys_regs to reset value
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* @vcpu: The VCPU pointer
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*
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* This function finds the right table above and sets the registers on
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2016-05-21 14:53:14 +03:00
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* the virtual CPU struct to their architecturally defined reset
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2012-12-10 20:23:59 +04:00
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* values.
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*/
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int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
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{
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const struct kvm_regs *cpu_reset;
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switch (vcpu->arch.target) {
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default:
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2013-02-07 14:46:46 +04:00
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if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {
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if (!cpu_has_32bit_el1())
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return -EINVAL;
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cpu_reset = &default_regs_reset32;
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} else {
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cpu_reset = &default_regs_reset;
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}
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2012-12-10 20:23:59 +04:00
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break;
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}
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/* Reset core registers */
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memcpy(vcpu_gp_regs(vcpu), cpu_reset, sizeof(*cpu_reset));
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/* Reset system registers */
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kvm_reset_sys_regs(vcpu);
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2015-09-11 06:30:22 +03:00
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/* Reset PMU */
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kvm_pmu_vcpu_reset(vcpu);
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2018-05-29 15:11:18 +03:00
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/* Default workaround setup is enabled (if supported) */
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if (kvm_arm_have_ssbd() == KVM_SSBD_KERNEL)
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vcpu->arch.workaround_flags |= VCPU_WORKAROUND_2_FLAG;
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2012-12-07 21:52:03 +04:00
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/* Reset timer */
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2017-05-02 21:14:06 +03:00
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return kvm_timer_vcpu_reset(vcpu);
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2012-12-10 20:23:59 +04:00
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}
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2018-09-26 19:32:42 +03:00
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2018-09-26 19:32:52 +03:00
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void kvm_set_ipa_limit(void)
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{
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unsigned int ipa_max, pa_max, va_max, parange;
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parange = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1) & 0x7;
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pa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
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/* Clamp the IPA limit to the PA size supported by the kernel */
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ipa_max = (pa_max > PHYS_MASK_SHIFT) ? PHYS_MASK_SHIFT : pa_max;
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/*
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* Since our stage2 table is dependent on the stage1 page table code,
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* we must always honor the following condition:
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*
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* Number of levels in Stage1 >= Number of levels in Stage2.
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*
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* So clamp the ipa limit further down to limit the number of levels.
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* Since we can concatenate upto 16 tables at entry level, we could
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* go upto 4bits above the maximum VA addressible with the current
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* number of levels.
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*/
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va_max = PGDIR_SHIFT + PAGE_SHIFT - 3;
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va_max += 4;
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if (va_max < ipa_max)
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ipa_max = va_max;
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/*
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* If the final limit is lower than the real physical address
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* limit of the CPUs, report the reason.
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*/
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if (ipa_max < pa_max)
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pr_info("kvm: Limiting the IPA size due to kernel %s Address limit\n",
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(va_max < pa_max) ? "Virtual" : "Physical");
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WARN(ipa_max < KVM_PHYS_SHIFT,
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"KVM IPA limit (%d bit) is smaller than default size\n", ipa_max);
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kvm_ipa_limit = ipa_max;
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kvm_info("IPA Size Limit: %dbits\n", kvm_ipa_limit);
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}
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2018-09-26 19:32:43 +03:00
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/*
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* Configure the VTCR_EL2 for this VM. The VTCR value is common
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* across all the physical CPUs on the system. We use system wide
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* sanitised values to fill in different fields, except for Hardware
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* Management of Access Flags. HA Flag is set unconditionally on
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* all CPUs, as it is safe to run with or without the feature and
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* the bit is RES0 on CPUs that don't support it.
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*/
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2018-10-01 15:40:36 +03:00
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int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type)
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2018-09-26 19:32:42 +03:00
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{
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2018-09-26 19:32:43 +03:00
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u64 vtcr = VTCR_EL2_FLAGS;
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u32 parange, phys_shift;
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2018-09-26 19:32:53 +03:00
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u8 lvls;
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2018-09-26 19:32:43 +03:00
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2018-09-26 19:32:54 +03:00
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if (type & ~KVM_VM_TYPE_ARM_IPA_SIZE_MASK)
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2018-09-26 19:32:42 +03:00
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return -EINVAL;
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2018-09-26 19:32:43 +03:00
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2018-09-26 19:32:54 +03:00
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phys_shift = KVM_VM_TYPE_ARM_IPA_SIZE(type);
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if (phys_shift) {
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if (phys_shift > kvm_ipa_limit ||
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phys_shift < 32)
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return -EINVAL;
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} else {
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phys_shift = KVM_PHYS_SHIFT;
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}
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2018-09-26 19:32:43 +03:00
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parange = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1) & 7;
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if (parange > ID_AA64MMFR0_PARANGE_MAX)
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parange = ID_AA64MMFR0_PARANGE_MAX;
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vtcr |= parange << VTCR_EL2_PS_SHIFT;
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vtcr |= VTCR_EL2_T0SZ(phys_shift);
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2018-09-26 19:32:53 +03:00
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/*
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* Use a minimum 2 level page table to prevent splitting
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* host PMD huge pages at stage2.
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*/
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lvls = stage2_pgtable_levels(phys_shift);
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if (lvls < 2)
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lvls = 2;
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vtcr |= VTCR_EL2_LVLS_TO_SL0(lvls);
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2018-09-26 19:32:43 +03:00
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/*
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* Enable the Hardware Access Flag management, unconditionally
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* on all CPUs. The features is RES0 on CPUs without the support
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* and must be ignored by the CPUs.
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*/
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vtcr |= VTCR_EL2_HA;
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/* Set the vmid bits */
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vtcr |= (kvm_get_vmid_bits() == 16) ?
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VTCR_EL2_VS_16BIT :
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VTCR_EL2_VS_8BIT;
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kvm->arch.vtcr = vtcr;
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2018-09-26 19:32:42 +03:00
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return 0;
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}
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