2022-09-05 19:21:32 +03:00
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* SPI core driver for the Ocelot chip family.
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*
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* This driver will handle everything necessary to allow for communication over
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* SPI to the VSC7511, VSC7512, VSC7513 and VSC7514 chips. The main functions
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* are to prepare the chip's SPI interface for a specific bus speed, and a host
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* processor's endianness. This will create and distribute regmaps for any
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* children.
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*
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* Copyright 2021-2022 Innovative Advantage Inc.
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*
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* Author: Colin Foster <colin.foster@in-advantage.com>
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*/
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/export.h>
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#include <linux/ioport.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/spi/spi.h>
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#include <linux/types.h>
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#include <linux/units.h>
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#include "ocelot.h"
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#define REG_DEV_CPUORG_IF_CTRL 0x0000
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#define REG_DEV_CPUORG_IF_CFGSTAT 0x0004
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#define CFGSTAT_IF_NUM_VCORE (0 << 24)
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#define CFGSTAT_IF_NUM_VRAP (1 << 24)
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#define CFGSTAT_IF_NUM_SI (2 << 24)
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#define CFGSTAT_IF_NUM_MIIM (3 << 24)
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#define VSC7512_DEVCPU_ORG_RES_START 0x71000000
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#define VSC7512_DEVCPU_ORG_RES_SIZE 0x38
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#define VSC7512_CHIP_REGS_RES_START 0x71070000
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#define VSC7512_CHIP_REGS_RES_SIZE 0x14
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static const struct resource vsc7512_dev_cpuorg_resource =
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DEFINE_RES_REG_NAMED(VSC7512_DEVCPU_ORG_RES_START,
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VSC7512_DEVCPU_ORG_RES_SIZE,
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"devcpu_org");
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static const struct resource vsc7512_gcb_resource =
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DEFINE_RES_REG_NAMED(VSC7512_CHIP_REGS_RES_START,
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VSC7512_CHIP_REGS_RES_SIZE,
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"devcpu_gcb_chip_regs");
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static int ocelot_spi_initialize(struct device *dev)
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{
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struct ocelot_ddata *ddata = dev_get_drvdata(dev);
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u32 val, check;
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int err;
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val = OCELOT_SPI_BYTE_ORDER;
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/*
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* The SPI address must be big-endian, but we want the payload to match
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* our CPU. These are two bits (0 and 1) but they're repeated such that
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* the write from any configuration will be valid. The four
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* configurations are:
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*
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* 0b00: little-endian, MSB first
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* | 111111 | 22221111 | 33222222 |
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* | 76543210 | 54321098 | 32109876 | 10987654 |
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*
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* 0b01: big-endian, MSB first
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* | 33222222 | 22221111 | 111111 | |
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* | 10987654 | 32109876 | 54321098 | 76543210 |
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*
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* 0b10: little-endian, LSB first
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* | 111111 | 11112222 | 22222233 |
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* | 01234567 | 89012345 | 67890123 | 45678901 |
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*
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* 0b11: big-endian, LSB first
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* | 22222233 | 11112222 | 111111 | |
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* | 45678901 | 67890123 | 89012345 | 01234567 |
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*/
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err = regmap_write(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CTRL, val);
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if (err)
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return err;
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/*
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* Apply the number of padding bytes between a read request and the data
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* payload. Some registers have access times of up to 1us, so if the
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* first payload bit is shifted out too quickly, the read will fail.
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*/
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val = ddata->spi_padding_bytes;
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err = regmap_write(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CFGSTAT, val);
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if (err)
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return err;
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/*
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* After we write the interface configuration, read it back here. This
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* will verify several different things. The first is that the number of
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* padding bytes actually got written correctly. These are found in bits
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* 0:3.
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*
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* The second is that bit 16 is cleared. Bit 16 is IF_CFGSTAT:IF_STAT,
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* and will be set if the register access is too fast. This would be in
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* the condition that the number of padding bytes is insufficient for
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* the SPI bus frequency.
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*
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* The last check is for bits 31:24, which define the interface by which
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* the registers are being accessed. Since we're accessing them via the
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* serial interface, it must return IF_NUM_SI.
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*/
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check = val | CFGSTAT_IF_NUM_SI;
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err = regmap_read(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CFGSTAT, &val);
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if (err)
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return err;
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if (check != val)
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return -ENODEV;
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return 0;
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}
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static const struct regmap_config ocelot_spi_regmap_config = {
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.reg_bits = 24,
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.reg_stride = 4,
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.reg_downshift = 2,
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.val_bits = 32,
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.write_flag_mask = 0x80,
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.use_single_write = true,
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.can_multi_write = false,
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.reg_format_endian = REGMAP_ENDIAN_BIG,
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.val_format_endian = REGMAP_ENDIAN_NATIVE,
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};
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static int ocelot_spi_regmap_bus_read(void *context, const void *reg, size_t reg_size,
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void *val, size_t val_size)
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{
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struct spi_transfer xfers[3] = {0};
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struct device *dev = context;
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struct ocelot_ddata *ddata;
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struct spi_device *spi;
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struct spi_message msg;
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unsigned int index = 0;
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ddata = dev_get_drvdata(dev);
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spi = to_spi_device(dev);
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xfers[index].tx_buf = reg;
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xfers[index].len = reg_size;
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index++;
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if (ddata->spi_padding_bytes) {
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xfers[index].len = ddata->spi_padding_bytes;
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xfers[index].tx_buf = ddata->dummy_buf;
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xfers[index].dummy_data = 1;
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index++;
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}
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xfers[index].rx_buf = val;
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xfers[index].len = val_size;
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index++;
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spi_message_init_with_transfers(&msg, xfers, index);
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return spi_sync(spi, &msg);
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}
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static int ocelot_spi_regmap_bus_write(void *context, const void *data, size_t count)
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{
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struct device *dev = context;
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struct spi_device *spi = to_spi_device(dev);
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return spi_write(spi, data, count);
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}
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static const struct regmap_bus ocelot_spi_regmap_bus = {
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.write = ocelot_spi_regmap_bus_write,
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.read = ocelot_spi_regmap_bus_read,
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};
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struct regmap *ocelot_spi_init_regmap(struct device *dev, const struct resource *res)
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{
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struct regmap_config regmap_config;
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memcpy(®map_config, &ocelot_spi_regmap_config, sizeof(regmap_config));
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regmap_config.name = res->name;
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regmap_config.max_register = resource_size(res) - 1;
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regmap_config.reg_base = res->start;
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return devm_regmap_init(dev, &ocelot_spi_regmap_bus, dev, ®map_config);
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}
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EXPORT_SYMBOL_NS(ocelot_spi_init_regmap, MFD_OCELOT_SPI);
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static int ocelot_spi_probe(struct spi_device *spi)
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{
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struct device *dev = &spi->dev;
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struct ocelot_ddata *ddata;
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struct regmap *r;
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int err;
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ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
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if (!ddata)
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return -ENOMEM;
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spi_set_drvdata(spi, ddata);
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if (spi->max_speed_hz <= 500000) {
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ddata->spi_padding_bytes = 0;
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} else {
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/*
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* Calculation taken from the manual for IF_CFGSTAT:IF_CFG.
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* Register access time is 1us, so we need to configure and send
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* out enough padding bytes between the read request and data
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* transmission that lasts at least 1 microsecond.
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*/
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ddata->spi_padding_bytes = 1 + (spi->max_speed_hz / HZ_PER_MHZ + 2) / 8;
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ddata->dummy_buf = devm_kzalloc(dev, ddata->spi_padding_bytes, GFP_KERNEL);
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if (!ddata->dummy_buf)
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return -ENOMEM;
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}
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spi->bits_per_word = 8;
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err = spi_setup(spi);
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if (err)
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return dev_err_probe(&spi->dev, err, "Error performing SPI setup\n");
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r = ocelot_spi_init_regmap(dev, &vsc7512_dev_cpuorg_resource);
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if (IS_ERR(r))
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return PTR_ERR(r);
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ddata->cpuorg_regmap = r;
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r = ocelot_spi_init_regmap(dev, &vsc7512_gcb_resource);
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if (IS_ERR(r))
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return PTR_ERR(r);
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ddata->gcb_regmap = r;
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/*
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* The chip must be set up for SPI before it gets initialized and reset.
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* This must be done before calling init, and after a chip reset is
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* performed.
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*/
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err = ocelot_spi_initialize(dev);
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if (err)
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return dev_err_probe(dev, err, "Error initializing SPI bus\n");
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err = ocelot_chip_reset(dev);
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if (err)
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return dev_err_probe(dev, err, "Error resetting device\n");
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/*
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* A chip reset will clear the SPI configuration, so it needs to be done
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* again before we can access any registers.
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*/
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err = ocelot_spi_initialize(dev);
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if (err)
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return dev_err_probe(dev, err, "Error initializing SPI bus after reset\n");
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err = ocelot_core_init(dev);
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if (err)
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return dev_err_probe(dev, err, "Error initializing Ocelot core\n");
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return 0;
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}
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static const struct spi_device_id ocelot_spi_ids[] = {
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{ "vsc7512", 0 },
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{ }
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};
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2022-09-22 13:37:03 +03:00
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MODULE_DEVICE_TABLE(spi, ocelot_spi_ids);
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2022-09-05 19:21:32 +03:00
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static const struct of_device_id ocelot_spi_of_match[] = {
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{ .compatible = "mscc,vsc7512" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, ocelot_spi_of_match);
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static struct spi_driver ocelot_spi_driver = {
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.driver = {
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.name = "ocelot-soc",
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.of_match_table = ocelot_spi_of_match,
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},
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.id_table = ocelot_spi_ids,
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.probe = ocelot_spi_probe,
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};
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module_spi_driver(ocelot_spi_driver);
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MODULE_DESCRIPTION("SPI Controlled Ocelot Chip Driver");
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MODULE_AUTHOR("Colin Foster <colin.foster@in-advantage.com>");
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MODULE_LICENSE("Dual MIT/GPL");
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MODULE_IMPORT_NS(MFD_OCELOT);
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