2018-12-18 20:05:55 +03:00
|
|
|
// SPDX-License-Identifier: GPL-2.0
|
|
|
|
/*
|
|
|
|
* Device Tree Source for the RZA2MEVB board
|
|
|
|
*
|
|
|
|
* Copyright (C) 2018 Renesas Electronics
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
|
|
|
|
/dts-v1/;
|
|
|
|
#include "r7s9210.dtsi"
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
|
|
#include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
|
|
|
|
|
|
|
|
/ {
|
|
|
|
model = "RZA2MEVB";
|
|
|
|
compatible = "renesas,rza2mevb", "renesas,r7s9210";
|
|
|
|
|
|
|
|
aliases {
|
|
|
|
serial0 = &scif4;
|
2019-05-06 23:12:36 +03:00
|
|
|
ethernet0 = ðer0;
|
|
|
|
ethernet1 = ðer1;
|
2018-12-18 20:05:55 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
chosen {
|
|
|
|
bootargs = "ignore_loglevel";
|
|
|
|
stdout-path = "serial0:115200n8";
|
|
|
|
};
|
|
|
|
|
|
|
|
memory@40000000 {
|
|
|
|
device_type = "memory";
|
|
|
|
reg = <0x40000000 0x00800000>; /* HyperRAM */
|
|
|
|
};
|
|
|
|
|
|
|
|
lbsc {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
};
|
|
|
|
|
|
|
|
leds {
|
|
|
|
compatible = "gpio-leds";
|
|
|
|
|
|
|
|
red {
|
|
|
|
gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>;
|
|
|
|
};
|
|
|
|
green {
|
|
|
|
gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
/* EXTAL */
|
|
|
|
&extal_clk {
|
|
|
|
clock-frequency = <24000000>; /* 24MHz */
|
|
|
|
};
|
|
|
|
|
|
|
|
/* RTC_X1 */
|
|
|
|
&rtc_x1_clk {
|
|
|
|
clock-frequency = <32768>;
|
|
|
|
};
|
|
|
|
|
|
|
|
&pinctrl {
|
|
|
|
/* Serial Console */
|
|
|
|
scif4_pins: serial4 {
|
|
|
|
pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
|
|
|
|
<RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
|
|
|
|
};
|
2019-04-30 16:23:08 +03:00
|
|
|
|
|
|
|
eth0_pins: eth0 {
|
|
|
|
pinmux = <RZA2_PINMUX(PORTE, 0, 7)>, /* REF50CK0 */
|
|
|
|
<RZA2_PINMUX(PORT6, 1, 7)>, /* RMMI0_TXDEN */
|
|
|
|
<RZA2_PINMUX(PORT6, 2, 7)>, /* RMII0_TXD0 */
|
|
|
|
<RZA2_PINMUX(PORT6, 3, 7)>, /* RMII0_TXD1 */
|
|
|
|
<RZA2_PINMUX(PORTE, 4, 7)>, /* RMII0_CRSDV */
|
|
|
|
<RZA2_PINMUX(PORTE, 1, 7)>, /* RMII0_RXD0 */
|
|
|
|
<RZA2_PINMUX(PORTE, 2, 7)>, /* RMII0_RXD1 */
|
|
|
|
<RZA2_PINMUX(PORTE, 3, 7)>, /* RMII0_RXER */
|
|
|
|
<RZA2_PINMUX(PORTE, 5, 1)>, /* ET0_MDC */
|
|
|
|
<RZA2_PINMUX(PORTE, 6, 1)>, /* ET0_MDIO */
|
|
|
|
<RZA2_PINMUX(PORTL, 0, 5)>; /* IRQ4 */
|
|
|
|
};
|
|
|
|
|
|
|
|
eth1_pins: eth1 {
|
|
|
|
pinmux = <RZA2_PINMUX(PORTK, 3, 7)>, /* REF50CK1 */
|
|
|
|
<RZA2_PINMUX(PORTK, 0, 7)>, /* RMMI1_TXDEN */
|
|
|
|
<RZA2_PINMUX(PORTK, 1, 7)>, /* RMII1_TXD0 */
|
|
|
|
<RZA2_PINMUX(PORTK, 2, 7)>, /* RMII1_TXD1 */
|
|
|
|
<RZA2_PINMUX(PORT3, 2, 7)>, /* RMII1_CRSDV */
|
|
|
|
<RZA2_PINMUX(PORTK, 4, 7)>, /* RMII1_RXD0 */
|
|
|
|
<RZA2_PINMUX(PORT3, 5, 7)>, /* RMII1_RXD1 */
|
|
|
|
<RZA2_PINMUX(PORT3, 1, 7)>, /* RMII1_RXER */
|
|
|
|
<RZA2_PINMUX(PORT3, 3, 1)>, /* ET1_MDC */
|
|
|
|
<RZA2_PINMUX(PORT3, 4, 1)>, /* ET1_MDIO */
|
|
|
|
<RZA2_PINMUX(PORTL, 1, 5)>; /* IRQ5 */
|
|
|
|
};
|
2019-04-30 16:23:09 +03:00
|
|
|
|
|
|
|
sdhi0_pins: sdhi0 {
|
|
|
|
pinmux = <RZA2_PINMUX(PORT5, 0, 3)>, /* SD0_CD */
|
|
|
|
<RZA2_PINMUX(PORT5, 1, 3)>; /* SD0_WP */
|
|
|
|
};
|
|
|
|
|
|
|
|
sdhi1_pins: sdhi1 {
|
|
|
|
pinmux = <RZA2_PINMUX(PORT5, 4, 3)>, /* SD1_CD */
|
|
|
|
<RZA2_PINMUX(PORT5, 5, 3)>; /* SD1_WP */
|
|
|
|
};
|
2018-12-18 20:05:55 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
/* High resolution System tick timers */
|
|
|
|
&ostm0 {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&ostm1 {
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Serial Console */
|
|
|
|
&scif4 {
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&scif4_pins>;
|
|
|
|
|
|
|
|
status = "okay";
|
|
|
|
};
|
2019-04-30 16:23:08 +03:00
|
|
|
|
|
|
|
ðer0 {
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <ð0_pins>;
|
|
|
|
status = "okay";
|
|
|
|
renesas,no-ether-link;
|
|
|
|
phy-handle = <&phy0>;
|
|
|
|
phy0: ethernet-phy@0 {
|
|
|
|
reg = <0>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
ðer1 {
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <ð1_pins>;
|
|
|
|
status = "okay";
|
|
|
|
renesas,no-ether-link;
|
|
|
|
phy-handle = <&phy1>;
|
|
|
|
phy1: ethernet-phy@1 {
|
|
|
|
reg = <0>;
|
|
|
|
};
|
|
|
|
};
|
2019-04-30 16:23:09 +03:00
|
|
|
|
|
|
|
&sdhi0 {
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&sdhi0_pins>;
|
|
|
|
bus-width = <4>;
|
|
|
|
status = "okay";
|
|
|
|
};
|
|
|
|
|
|
|
|
&sdhi1 {
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&sdhi1_pins>;
|
|
|
|
bus-width = <4>;
|
|
|
|
status = "okay";
|
|
|
|
};
|