2009-09-24 04:46:15 +04:00
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/*
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* bfi_cbreg.h crossbow host block register definitions
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*
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* !!! Do not edit. Auto generated. !!!
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*/
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#ifndef __BFI_CBREG_H__
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#define __BFI_CBREG_H__
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#define HOSTFN0_INT_STATUS 0x00014000
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#define __HOSTFN0_INT_STATUS_LVL_MK 0x00f00000
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#define __HOSTFN0_INT_STATUS_LVL_SH 20
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#define __HOSTFN0_INT_STATUS_LVL(_v) ((_v) << __HOSTFN0_INT_STATUS_LVL_SH)
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#define __HOSTFN0_INT_STATUS_P 0x000fffff
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#define HOSTFN0_INT_MSK 0x00014004
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#define HOST_PAGE_NUM_FN0 0x00014008
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#define __HOST_PAGE_NUM_FN 0x000001ff
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#define HOSTFN1_INT_STATUS 0x00014100
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#define __HOSTFN1_INT_STAT_LVL_MK 0x00f00000
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#define __HOSTFN1_INT_STAT_LVL_SH 20
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#define __HOSTFN1_INT_STAT_LVL(_v) ((_v) << __HOSTFN1_INT_STAT_LVL_SH)
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#define __HOSTFN1_INT_STAT_P 0x000fffff
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#define HOSTFN1_INT_MSK 0x00014104
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#define HOST_PAGE_NUM_FN1 0x00014108
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#define APP_PLL_400_CTL_REG 0x00014204
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#define __P_400_PLL_LOCK 0x80000000
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#define __APP_PLL_400_SRAM_USE_100MHZ 0x00100000
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#define __APP_PLL_400_RESET_TIMER_MK 0x000e0000
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#define __APP_PLL_400_RESET_TIMER_SH 17
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#define __APP_PLL_400_RESET_TIMER(_v) ((_v) << __APP_PLL_400_RESET_TIMER_SH)
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#define __APP_PLL_400_LOGIC_SOFT_RESET 0x00010000
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#define __APP_PLL_400_CNTLMT0_1_MK 0x0000c000
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#define __APP_PLL_400_CNTLMT0_1_SH 14
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#define __APP_PLL_400_CNTLMT0_1(_v) ((_v) << __APP_PLL_400_CNTLMT0_1_SH)
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#define __APP_PLL_400_JITLMT0_1_MK 0x00003000
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#define __APP_PLL_400_JITLMT0_1_SH 12
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#define __APP_PLL_400_JITLMT0_1(_v) ((_v) << __APP_PLL_400_JITLMT0_1_SH)
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#define __APP_PLL_400_HREF 0x00000800
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#define __APP_PLL_400_HDIV 0x00000400
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#define __APP_PLL_400_P0_1_MK 0x00000300
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#define __APP_PLL_400_P0_1_SH 8
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#define __APP_PLL_400_P0_1(_v) ((_v) << __APP_PLL_400_P0_1_SH)
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#define __APP_PLL_400_Z0_2_MK 0x000000e0
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#define __APP_PLL_400_Z0_2_SH 5
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#define __APP_PLL_400_Z0_2(_v) ((_v) << __APP_PLL_400_Z0_2_SH)
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#define __APP_PLL_400_RSEL200500 0x00000010
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#define __APP_PLL_400_ENARST 0x00000008
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#define __APP_PLL_400_BYPASS 0x00000004
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#define __APP_PLL_400_LRESETN 0x00000002
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#define __APP_PLL_400_ENABLE 0x00000001
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#define APP_PLL_212_CTL_REG 0x00014208
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#define __P_212_PLL_LOCK 0x80000000
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#define __APP_PLL_212_RESET_TIMER_MK 0x000e0000
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#define __APP_PLL_212_RESET_TIMER_SH 17
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#define __APP_PLL_212_RESET_TIMER(_v) ((_v) << __APP_PLL_212_RESET_TIMER_SH)
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#define __APP_PLL_212_LOGIC_SOFT_RESET 0x00010000
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#define __APP_PLL_212_CNTLMT0_1_MK 0x0000c000
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#define __APP_PLL_212_CNTLMT0_1_SH 14
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#define __APP_PLL_212_CNTLMT0_1(_v) ((_v) << __APP_PLL_212_CNTLMT0_1_SH)
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#define __APP_PLL_212_JITLMT0_1_MK 0x00003000
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#define __APP_PLL_212_JITLMT0_1_SH 12
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#define __APP_PLL_212_JITLMT0_1(_v) ((_v) << __APP_PLL_212_JITLMT0_1_SH)
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#define __APP_PLL_212_HREF 0x00000800
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#define __APP_PLL_212_HDIV 0x00000400
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#define __APP_PLL_212_P0_1_MK 0x00000300
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#define __APP_PLL_212_P0_1_SH 8
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#define __APP_PLL_212_P0_1(_v) ((_v) << __APP_PLL_212_P0_1_SH)
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#define __APP_PLL_212_Z0_2_MK 0x000000e0
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#define __APP_PLL_212_Z0_2_SH 5
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#define __APP_PLL_212_Z0_2(_v) ((_v) << __APP_PLL_212_Z0_2_SH)
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#define __APP_PLL_212_RSEL200500 0x00000010
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#define __APP_PLL_212_ENARST 0x00000008
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#define __APP_PLL_212_BYPASS 0x00000004
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#define __APP_PLL_212_LRESETN 0x00000002
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#define __APP_PLL_212_ENABLE 0x00000001
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#define HOST_SEM0_REG 0x00014230
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#define __HOST_SEMAPHORE 0x00000001
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#define HOST_SEM1_REG 0x00014234
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#define HOST_SEM2_REG 0x00014238
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#define HOST_SEM3_REG 0x0001423c
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#define HOST_SEM0_INFO_REG 0x00014240
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#define HOST_SEM1_INFO_REG 0x00014244
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#define HOST_SEM2_INFO_REG 0x00014248
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#define HOST_SEM3_INFO_REG 0x0001424c
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#define HOSTFN0_LPU0_CMD_STAT 0x00019000
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#define __HOSTFN0_LPU0_MBOX_INFO_MK 0xfffffffe
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#define __HOSTFN0_LPU0_MBOX_INFO_SH 1
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#define __HOSTFN0_LPU0_MBOX_INFO(_v) ((_v) << __HOSTFN0_LPU0_MBOX_INFO_SH)
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#define __HOSTFN0_LPU0_MBOX_CMD_STATUS 0x00000001
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#define LPU0_HOSTFN0_CMD_STAT 0x00019008
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#define __LPU0_HOSTFN0_MBOX_INFO_MK 0xfffffffe
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#define __LPU0_HOSTFN0_MBOX_INFO_SH 1
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#define __LPU0_HOSTFN0_MBOX_INFO(_v) ((_v) << __LPU0_HOSTFN0_MBOX_INFO_SH)
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#define __LPU0_HOSTFN0_MBOX_CMD_STATUS 0x00000001
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#define HOSTFN1_LPU1_CMD_STAT 0x00019014
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#define __HOSTFN1_LPU1_MBOX_INFO_MK 0xfffffffe
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#define __HOSTFN1_LPU1_MBOX_INFO_SH 1
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#define __HOSTFN1_LPU1_MBOX_INFO(_v) ((_v) << __HOSTFN1_LPU1_MBOX_INFO_SH)
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#define __HOSTFN1_LPU1_MBOX_CMD_STATUS 0x00000001
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#define LPU1_HOSTFN1_CMD_STAT 0x0001901c
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#define __LPU1_HOSTFN1_MBOX_INFO_MK 0xfffffffe
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#define __LPU1_HOSTFN1_MBOX_INFO_SH 1
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#define __LPU1_HOSTFN1_MBOX_INFO(_v) ((_v) << __LPU1_HOSTFN1_MBOX_INFO_SH)
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#define __LPU1_HOSTFN1_MBOX_CMD_STATUS 0x00000001
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#define CPE_Q0_DEPTH 0x00010014
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#define CPE_Q0_PI 0x0001001c
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#define CPE_Q0_CI 0x00010020
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#define CPE_Q1_DEPTH 0x00010034
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#define CPE_Q1_PI 0x0001003c
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#define CPE_Q1_CI 0x00010040
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#define CPE_Q2_DEPTH 0x00010054
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#define CPE_Q2_PI 0x0001005c
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#define CPE_Q2_CI 0x00010060
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#define CPE_Q3_DEPTH 0x00010074
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#define CPE_Q3_PI 0x0001007c
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#define CPE_Q3_CI 0x00010080
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#define CPE_Q4_DEPTH 0x00010094
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#define CPE_Q4_PI 0x0001009c
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#define CPE_Q4_CI 0x000100a0
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#define CPE_Q5_DEPTH 0x000100b4
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#define CPE_Q5_PI 0x000100bc
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#define CPE_Q5_CI 0x000100c0
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#define CPE_Q6_DEPTH 0x000100d4
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#define CPE_Q6_PI 0x000100dc
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#define CPE_Q6_CI 0x000100e0
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#define CPE_Q7_DEPTH 0x000100f4
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#define CPE_Q7_PI 0x000100fc
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#define CPE_Q7_CI 0x00010100
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#define RME_Q0_DEPTH 0x00011014
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#define RME_Q0_PI 0x0001101c
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#define RME_Q0_CI 0x00011020
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#define RME_Q1_DEPTH 0x00011034
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#define RME_Q1_PI 0x0001103c
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#define RME_Q1_CI 0x00011040
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#define RME_Q2_DEPTH 0x00011054
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#define RME_Q2_PI 0x0001105c
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#define RME_Q2_CI 0x00011060
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#define RME_Q3_DEPTH 0x00011074
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#define RME_Q3_PI 0x0001107c
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#define RME_Q3_CI 0x00011080
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#define RME_Q4_DEPTH 0x00011094
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#define RME_Q4_PI 0x0001109c
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#define RME_Q4_CI 0x000110a0
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#define RME_Q5_DEPTH 0x000110b4
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#define RME_Q5_PI 0x000110bc
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#define RME_Q5_CI 0x000110c0
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#define RME_Q6_DEPTH 0x000110d4
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#define RME_Q6_PI 0x000110dc
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#define RME_Q6_CI 0x000110e0
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#define RME_Q7_DEPTH 0x000110f4
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#define RME_Q7_PI 0x000110fc
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#define RME_Q7_CI 0x00011100
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#define PSS_CTL_REG 0x00018800
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#define __PSS_I2C_CLK_DIV_MK 0x00030000
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#define __PSS_I2C_CLK_DIV_SH 16
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#define __PSS_I2C_CLK_DIV(_v) ((_v) << __PSS_I2C_CLK_DIV_SH)
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#define __PSS_LMEM_INIT_DONE 0x00001000
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#define __PSS_LMEM_RESET 0x00000200
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#define __PSS_LMEM_INIT_EN 0x00000100
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#define __PSS_LPU1_RESET 0x00000002
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#define __PSS_LPU0_RESET 0x00000001
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2010-09-15 22:50:55 +04:00
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#define PSS_ERR_STATUS_REG 0x00018810
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#define __PSS_LMEM1_CORR_ERR 0x00000800
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2010-03-06 06:34:44 +03:00
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#define __PSS_LMEM0_CORR_ERR 0x00000400
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#define __PSS_LMEM1_UNCORR_ERR 0x00000200
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#define __PSS_LMEM0_UNCORR_ERR 0x00000100
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#define __PSS_BAL_PERR 0x00000080
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#define __PSS_DIP_IF_ERR 0x00000040
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#define __PSS_IOH_IF_ERR 0x00000020
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#define __PSS_TDS_IF_ERR 0x00000010
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#define __PSS_RDS_IF_ERR 0x00000008
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#define __PSS_SGM_IF_ERR 0x00000004
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#define __PSS_LPU1_RAM_ERR 0x00000002
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#define __PSS_LPU0_RAM_ERR 0x00000001
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2010-09-15 22:50:55 +04:00
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#define ERR_SET_REG 0x00018818
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#define __PSS_ERR_STATUS_SET 0x00000fff
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2009-09-24 04:46:15 +04:00
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/*
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* These definitions are either in error/missing in spec. Its auto-generated
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* from hard coded values in regparse.pl.
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*/
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#define __EMPHPOST_AT_4G_MK_FIX 0x0000001c
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#define __EMPHPOST_AT_4G_SH_FIX 0x00000002
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#define __EMPHPRE_AT_4G_FIX 0x00000003
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#define __SFP_TXRATE_EN_FIX 0x00000100
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#define __SFP_RXRATE_EN_FIX 0x00000080
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/*
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* These register definitions are auto-generated from hard coded values
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* in regparse.pl.
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*/
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#define HOSTFN0_LPU_MBOX0_0 0x00019200
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#define HOSTFN1_LPU_MBOX0_8 0x00019260
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#define LPU_HOSTFN0_MBOX0_0 0x00019280
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#define LPU_HOSTFN1_MBOX0_8 0x000192e0
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/*
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* These register mapping definitions are auto-generated from mapping tables
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* in regparse.pl.
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*/
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#define BFA_IOC0_HBEAT_REG HOST_SEM0_INFO_REG
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#define BFA_IOC0_STATE_REG HOST_SEM1_INFO_REG
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#define BFA_IOC1_HBEAT_REG HOST_SEM2_INFO_REG
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#define BFA_IOC1_STATE_REG HOST_SEM3_INFO_REG
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#define BFA_FW_USE_COUNT HOST_SEM4_INFO_REG
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2010-12-14 03:17:11 +03:00
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#define BFA_IOC_FAIL_SYNC HOST_SEM5_INFO_REG
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2009-09-24 04:46:15 +04:00
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#define CPE_Q_DEPTH(__n) \
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(CPE_Q0_DEPTH + (__n) * (CPE_Q1_DEPTH - CPE_Q0_DEPTH))
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#define CPE_Q_PI(__n) \
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(CPE_Q0_PI + (__n) * (CPE_Q1_PI - CPE_Q0_PI))
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#define CPE_Q_CI(__n) \
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(CPE_Q0_CI + (__n) * (CPE_Q1_CI - CPE_Q0_CI))
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#define RME_Q_DEPTH(__n) \
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(RME_Q0_DEPTH + (__n) * (RME_Q1_DEPTH - RME_Q0_DEPTH))
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#define RME_Q_PI(__n) \
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(RME_Q0_PI + (__n) * (RME_Q1_PI - RME_Q0_PI))
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#define RME_Q_CI(__n) \
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(RME_Q0_CI + (__n) * (RME_Q1_CI - RME_Q0_CI))
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#define CPE_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
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#define RME_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
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#define CPE_Q_MASK(__q) ((__q) & 0x3)
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#define RME_Q_MASK(__q) ((__q) & 0x3)
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/*
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* PCI MSI-X vector defines
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*/
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enum {
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BFA_MSIX_CPE_Q0 = 0,
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BFA_MSIX_CPE_Q1 = 1,
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BFA_MSIX_CPE_Q2 = 2,
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BFA_MSIX_CPE_Q3 = 3,
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BFA_MSIX_CPE_Q4 = 4,
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BFA_MSIX_CPE_Q5 = 5,
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BFA_MSIX_CPE_Q6 = 6,
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BFA_MSIX_CPE_Q7 = 7,
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BFA_MSIX_RME_Q0 = 8,
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BFA_MSIX_RME_Q1 = 9,
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BFA_MSIX_RME_Q2 = 10,
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BFA_MSIX_RME_Q3 = 11,
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BFA_MSIX_RME_Q4 = 12,
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BFA_MSIX_RME_Q5 = 13,
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BFA_MSIX_RME_Q6 = 14,
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BFA_MSIX_RME_Q7 = 15,
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BFA_MSIX_ERR_EMC = 16,
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BFA_MSIX_ERR_LPU0 = 17,
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BFA_MSIX_ERR_LPU1 = 18,
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BFA_MSIX_ERR_PSS = 19,
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BFA_MSIX_MBOX_LPU0 = 20,
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BFA_MSIX_MBOX_LPU1 = 21,
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BFA_MSIX_CB_MAX = 22,
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};
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/*
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* And corresponding host interrupt status bit field defines
|
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|
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*/
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#define __HFN_INT_CPE_Q0 0x00000001U
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#define __HFN_INT_CPE_Q1 0x00000002U
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#define __HFN_INT_CPE_Q2 0x00000004U
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#define __HFN_INT_CPE_Q3 0x00000008U
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|
#define __HFN_INT_CPE_Q4 0x00000010U
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#define __HFN_INT_CPE_Q5 0x00000020U
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#define __HFN_INT_CPE_Q6 0x00000040U
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|
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|
|
#define __HFN_INT_CPE_Q7 0x00000080U
|
|
|
|
|
#define __HFN_INT_RME_Q0 0x00000100U
|
|
|
|
|
#define __HFN_INT_RME_Q1 0x00000200U
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|
|
|
|
#define __HFN_INT_RME_Q2 0x00000400U
|
|
|
|
|
#define __HFN_INT_RME_Q3 0x00000800U
|
|
|
|
|
#define __HFN_INT_RME_Q4 0x00001000U
|
|
|
|
|
#define __HFN_INT_RME_Q5 0x00002000U
|
|
|
|
|
#define __HFN_INT_RME_Q6 0x00004000U
|
|
|
|
|
#define __HFN_INT_RME_Q7 0x00008000U
|
|
|
|
|
#define __HFN_INT_ERR_EMC 0x00010000U
|
|
|
|
|
#define __HFN_INT_ERR_LPU0 0x00020000U
|
|
|
|
|
#define __HFN_INT_ERR_LPU1 0x00040000U
|
|
|
|
|
#define __HFN_INT_ERR_PSS 0x00080000U
|
|
|
|
|
#define __HFN_INT_MBOX_LPU0 0x00100000U
|
|
|
|
|
#define __HFN_INT_MBOX_LPU1 0x00200000U
|
|
|
|
|
#define __HFN_INT_MBOX1_LPU0 0x00400000U
|
|
|
|
|
#define __HFN_INT_MBOX1_LPU1 0x00800000U
|
|
|
|
|
#define __HFN_INT_CPE_MASK 0x000000ffU
|
|
|
|
|
#define __HFN_INT_RME_MASK 0x0000ff00U
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* crossbow memory map.
|
|
|
|
|
*/
|
|
|
|
|
#define PSS_SMEM_PAGE_START 0x8000
|
|
|
|
|
#define PSS_SMEM_PGNUM(_pg0, _ma) ((_pg0) + ((_ma) >> 15))
|
|
|
|
|
#define PSS_SMEM_PGOFF(_ma) ((_ma) & 0x7fff)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* End of crossbow memory map
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
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|
|
|
|
#endif /* __BFI_CBREG_H__ */
|
|
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|
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|
