WSL2-Linux-Kernel/include/dt-bindings/clock/pxa-clock.h

/*
 * Inspired by original work from pxa2xx-regs.h by Nicolas Pitre
 * Copyright (C) 2014 Robert Jarzmik
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef __DT_BINDINGS_CLOCK_PXA2XX_H__
#define __DT_BINDINGS_CLOCK_PXA2XX_H__

#define CLK_NONE 0
#define CLK_1WIRE 1
#define CLK_AC97 2
#define CLK_AC97CONF 3
#define CLK_ASSP 4
#define CLK_BOOT 5
#define CLK_BTUART 6
#define CLK_CAMERA 7
#define CLK_CIR 8
#define CLK_CORE 9
#define CLK_DMC 10
#define CLK_FFUART 11
#define CLK_FICP 12
#define CLK_GPIO 13
#define CLK_HSIO2 14
#define CLK_HWUART 15
#define CLK_I2C 16
#define CLK_I2S 17
#define CLK_IM 18
#define CLK_INC 19
#define CLK_ISC 20
#define CLK_KEYPAD 21
#define CLK_LCD 22
#define CLK_MEMC 23
#define CLK_MEMSTK 24
#define CLK_MINI_IM 25
#define CLK_MINI_LCD 26
#define CLK_MMC 27
#define CLK_MMC1 28
#define CLK_MMC2 29
#define CLK_MMC3 30
#define CLK_MSL 31
#define CLK_MSL0 32
#define CLK_MVED 33
#define CLK_NAND 34
#define CLK_NSSP 35
#define CLK_OSTIMER 36
#define CLK_PWM0 37
#define CLK_PWM1 38
#define CLK_PWM2 39
#define CLK_PWM3 40
#define CLK_PWRI2C 41
#define CLK_PXA300_GCU 42
#define CLK_PXA320_GCU 43
#define CLK_SMC 44
#define CLK_SSP 45
#define CLK_SSP1 46
#define CLK_SSP2 47
#define CLK_SSP3 48
#define CLK_SSP4 49
#define CLK_STUART 50
#define CLK_TOUCH 51
#define CLK_TPM 52
#define CLK_UDC 53
#define CLK_USB 54
#define CLK_USB2 55
#define CLK_USBH 56
#define CLK_USBHOST 57
#define CLK_USIM 58
#define CLK_USIM1 59
#define CLK_USMI0 60
#define CLK_MAX 61

#endif
clk: add pxa clocks infrastructure Add a the common code used by all PXA variants. This is the first step in the transition from architecture defined clocks (in arch/arm/mach-pxa) towards clock framework. The goal is to have the same features (and not all the features) of the existing clocks, and enable the transition of PXA to device-tree. All PXA rely on a "CKEN" type clock, which : - has a gate (bit in CKEN register) - is generated from a PLL, generally divided - has an alternate low power clock Each variant will specialize the CKEN clock : - pxa25x have no low power clock - pxa27x in low power use always the 13 MHz ring oscillator - pxa3xx in low power have specific dividers for each clock The device-tree provides a list of CLK_* (ex: CLK_USB or CLK_I2C) to get a handle on the clock. While pxa-clock.h will describe all the clocks of all the variants, each variant will only use a subset of it. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Mike Turquette <mturquette@linaro.org> 2014-07-31 00:50:59 +04:00			`/*`
			`* Inspired by original work from pxa2xx-regs.h by Nicolas Pitre`
			`* Copyright (C) 2014 Robert Jarzmik`
			`*`
			`* This program is free software; you can redistribute it and/or modify`
			`* it under the terms of the GNU General Public License as published by`
			`* the Free Software Foundation; either version 2 of the License, or`
			`* (at your option) any later version.`
			`*/`

			`#ifndef __DT_BINDINGS_CLOCK_PXA2XX_H__`
			`#define __DT_BINDINGS_CLOCK_PXA2XX_H__`

			`#define CLK_NONE 0`
			`#define CLK_1WIRE 1`
			`#define CLK_AC97 2`
			`#define CLK_AC97CONF 3`
			`#define CLK_ASSP 4`
			`#define CLK_BOOT 5`
			`#define CLK_BTUART 6`
			`#define CLK_CAMERA 7`
			`#define CLK_CIR 8`
			`#define CLK_CORE 9`
			`#define CLK_DMC 10`
			`#define CLK_FFUART 11`
			`#define CLK_FICP 12`
			`#define CLK_GPIO 13`
			`#define CLK_HSIO2 14`
			`#define CLK_HWUART 15`
			`#define CLK_I2C 16`
			`#define CLK_I2S 17`
			`#define CLK_IM 18`
			`#define CLK_INC 19`
			`#define CLK_ISC 20`
			`#define CLK_KEYPAD 21`
			`#define CLK_LCD 22`
			`#define CLK_MEMC 23`
			`#define CLK_MEMSTK 24`
			`#define CLK_MINI_IM 25`
			`#define CLK_MINI_LCD 26`
			`#define CLK_MMC 27`
			`#define CLK_MMC1 28`
			`#define CLK_MMC2 29`
			`#define CLK_MMC3 30`
			`#define CLK_MSL 31`
			`#define CLK_MSL0 32`
			`#define CLK_MVED 33`
			`#define CLK_NAND 34`
			`#define CLK_NSSP 35`
			`#define CLK_OSTIMER 36`
			`#define CLK_PWM0 37`
			`#define CLK_PWM1 38`
			`#define CLK_PWM2 39`
			`#define CLK_PWM3 40`
			`#define CLK_PWRI2C 41`
			`#define CLK_PXA300_GCU 42`
			`#define CLK_PXA320_GCU 43`
			`#define CLK_SMC 44`
			`#define CLK_SSP 45`
			`#define CLK_SSP1 46`
			`#define CLK_SSP2 47`
			`#define CLK_SSP3 48`
			`#define CLK_SSP4 49`
			`#define CLK_STUART 50`
			`#define CLK_TOUCH 51`
			`#define CLK_TPM 52`
			`#define CLK_UDC 53`
			`#define CLK_USB 54`
			`#define CLK_USB2 55`
			`#define CLK_USBH 56`
			`#define CLK_USBHOST 57`
			`#define CLK_USIM 58`
			`#define CLK_USIM1 59`
			`#define CLK_USMI0 60`
			`#define CLK_MAX 61`

			`#endif`