2019-01-28 19:23:23 +03:00
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// SPDX-License-Identifier: GPL-2.0+
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// Copyright IBM Corp 2019
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2018-11-09 00:05:24 +03:00
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#include <linux/device.h>
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#include <linux/errno.h>
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2018-11-09 00:05:25 +03:00
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#include <linux/fsi-occ.h>
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2018-11-09 00:05:24 +03:00
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#include <linux/i2c.h>
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2018-11-09 00:05:25 +03:00
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#include <linux/jiffies.h>
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2018-11-09 00:05:24 +03:00
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#include <linux/module.h>
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2018-11-09 00:05:25 +03:00
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#include <linux/sched.h>
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#include <asm/unaligned.h>
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2018-11-09 00:05:24 +03:00
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#include "common.h"
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2018-11-09 00:05:25 +03:00
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#define OCC_TIMEOUT_MS 1000
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#define OCC_CMD_IN_PRG_WAIT_MS 50
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/* OCB (on-chip control bridge - interface to OCC) registers */
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#define OCB_DATA1 0x6B035
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#define OCB_ADDR 0x6B070
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#define OCB_DATA3 0x6B075
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/* OCC SRAM address space */
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#define OCC_SRAM_ADDR_CMD 0xFFFF6000
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#define OCC_SRAM_ADDR_RESP 0xFFFF7000
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#define OCC_DATA_ATTN 0x20010000
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2018-11-09 00:05:24 +03:00
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struct p8_i2c_occ {
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struct occ occ;
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struct i2c_client *client;
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};
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#define to_p8_i2c_occ(x) container_of((x), struct p8_i2c_occ, occ)
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2018-11-09 00:05:25 +03:00
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static int p8_i2c_occ_getscom(struct i2c_client *client, u32 address, u8 *data)
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{
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ssize_t rc;
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__be64 buf;
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struct i2c_msg msgs[2];
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/* p8 i2c slave requires shift */
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address <<= 1;
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msgs[0].addr = client->addr;
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msgs[0].flags = client->flags & I2C_M_TEN;
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msgs[0].len = sizeof(u32);
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/* address is a scom address; bus-endian */
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msgs[0].buf = (char *)&address;
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/* data from OCC is big-endian */
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msgs[1].addr = client->addr;
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msgs[1].flags = (client->flags & I2C_M_TEN) | I2C_M_RD;
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msgs[1].len = sizeof(u64);
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msgs[1].buf = (char *)&buf;
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rc = i2c_transfer(client->adapter, msgs, 2);
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if (rc < 0)
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return rc;
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*(u64 *)data = be64_to_cpu(buf);
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return 0;
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}
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static int p8_i2c_occ_putscom(struct i2c_client *client, u32 address, u8 *data)
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{
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u32 buf[3];
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ssize_t rc;
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/* p8 i2c slave requires shift */
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address <<= 1;
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/* address is bus-endian; data passed through from user as-is */
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buf[0] = address;
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memcpy(&buf[1], &data[4], sizeof(u32));
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memcpy(&buf[2], data, sizeof(u32));
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rc = i2c_master_send(client, (const char *)buf, sizeof(buf));
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if (rc < 0)
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return rc;
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else if (rc != sizeof(buf))
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return -EIO;
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return 0;
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}
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static int p8_i2c_occ_putscom_u32(struct i2c_client *client, u32 address,
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u32 data0, u32 data1)
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{
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u8 buf[8];
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memcpy(buf, &data0, 4);
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memcpy(buf + 4, &data1, 4);
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return p8_i2c_occ_putscom(client, address, buf);
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}
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static int p8_i2c_occ_putscom_be(struct i2c_client *client, u32 address,
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u8 *data)
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{
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__be32 data0, data1;
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memcpy(&data0, data, 4);
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memcpy(&data1, data + 4, 4);
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return p8_i2c_occ_putscom_u32(client, address, be32_to_cpu(data0),
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be32_to_cpu(data1));
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}
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2018-11-09 00:05:24 +03:00
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static int p8_i2c_occ_send_cmd(struct occ *occ, u8 *cmd)
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{
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2018-11-09 00:05:25 +03:00
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int i, rc;
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unsigned long start;
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u16 data_length;
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const unsigned long timeout = msecs_to_jiffies(OCC_TIMEOUT_MS);
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const long wait_time = msecs_to_jiffies(OCC_CMD_IN_PRG_WAIT_MS);
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struct p8_i2c_occ *ctx = to_p8_i2c_occ(occ);
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struct i2c_client *client = ctx->client;
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struct occ_response *resp = &occ->resp;
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start = jiffies;
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/* set sram address for command */
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rc = p8_i2c_occ_putscom_u32(client, OCB_ADDR, OCC_SRAM_ADDR_CMD, 0);
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if (rc)
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return rc;
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/* write command (expected to already be BE), we need bus-endian... */
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rc = p8_i2c_occ_putscom_be(client, OCB_DATA3, cmd);
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if (rc)
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return rc;
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/* trigger OCC attention */
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rc = p8_i2c_occ_putscom_u32(client, OCB_DATA1, OCC_DATA_ATTN, 0);
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if (rc)
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return rc;
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do {
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/* set sram address for response */
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rc = p8_i2c_occ_putscom_u32(client, OCB_ADDR,
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OCC_SRAM_ADDR_RESP, 0);
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if (rc)
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return rc;
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rc = p8_i2c_occ_getscom(client, OCB_DATA3, (u8 *)resp);
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if (rc)
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return rc;
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/* wait for OCC */
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if (resp->return_status == OCC_RESP_CMD_IN_PRG) {
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rc = -EALREADY;
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if (time_after(jiffies, start + timeout))
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break;
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set_current_state(TASK_INTERRUPTIBLE);
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schedule_timeout(wait_time);
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}
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} while (rc);
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/* check the OCC response */
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switch (resp->return_status) {
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case OCC_RESP_CMD_IN_PRG:
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rc = -ETIMEDOUT;
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break;
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case OCC_RESP_SUCCESS:
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rc = 0;
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break;
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case OCC_RESP_CMD_INVAL:
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case OCC_RESP_CMD_LEN_INVAL:
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case OCC_RESP_DATA_INVAL:
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case OCC_RESP_CHKSUM_ERR:
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rc = -EINVAL;
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break;
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case OCC_RESP_INT_ERR:
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case OCC_RESP_BAD_STATE:
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case OCC_RESP_CRIT_EXCEPT:
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case OCC_RESP_CRIT_INIT:
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case OCC_RESP_CRIT_WATCHDOG:
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case OCC_RESP_CRIT_OCB:
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case OCC_RESP_CRIT_HW:
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rc = -EREMOTEIO;
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break;
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default:
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rc = -EPROTO;
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}
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if (rc < 0)
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return rc;
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data_length = get_unaligned_be16(&resp->data_length);
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if (data_length > OCC_RESP_DATA_BYTES)
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return -EMSGSIZE;
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/* fetch the rest of the response data */
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for (i = 8; i < data_length + 7; i += 8) {
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rc = p8_i2c_occ_getscom(client, OCB_DATA3, ((u8 *)resp) + i);
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if (rc)
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return rc;
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}
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return 0;
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2018-11-09 00:05:24 +03:00
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}
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2020-08-13 19:02:22 +03:00
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static int p8_i2c_occ_probe(struct i2c_client *client)
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2018-11-09 00:05:24 +03:00
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{
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struct occ *occ;
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struct p8_i2c_occ *ctx = devm_kzalloc(&client->dev, sizeof(*ctx),
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GFP_KERNEL);
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if (!ctx)
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return -ENOMEM;
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ctx->client = client;
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occ = &ctx->occ;
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occ->bus_dev = &client->dev;
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dev_set_drvdata(&client->dev, occ);
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2018-11-09 00:05:27 +03:00
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occ->powr_sample_time_us = 250;
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2018-11-09 00:05:24 +03:00
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occ->poll_cmd_data = 0x10; /* P8 OCC poll data */
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occ->send_cmd = p8_i2c_occ_send_cmd;
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return occ_setup(occ, "p8_occ");
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}
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2018-11-09 00:05:29 +03:00
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static int p8_i2c_occ_remove(struct i2c_client *client)
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{
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struct occ *occ = dev_get_drvdata(&client->dev);
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occ_shutdown(occ);
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return 0;
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}
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2018-11-09 00:05:24 +03:00
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static const struct of_device_id p8_i2c_occ_of_match[] = {
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{ .compatible = "ibm,p8-occ-hwmon" },
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{}
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};
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MODULE_DEVICE_TABLE(of, p8_i2c_occ_of_match);
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static struct i2c_driver p8_i2c_occ_driver = {
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.class = I2C_CLASS_HWMON,
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.driver = {
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.name = "occ-hwmon",
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.of_match_table = p8_i2c_occ_of_match,
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},
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2020-08-13 19:02:22 +03:00
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.probe_new = p8_i2c_occ_probe,
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2018-11-09 00:05:29 +03:00
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.remove = p8_i2c_occ_remove,
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2018-11-09 00:05:24 +03:00
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};
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module_i2c_driver(p8_i2c_occ_driver);
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MODULE_AUTHOR("Eddie James <eajames@linux.ibm.com>");
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MODULE_DESCRIPTION("BMC P8 OCC hwmon driver");
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MODULE_LICENSE("GPL");
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