irqchip: add basic infrastructure
With the recent creation of the drivers/irqchip/ directory, it is
desirable to move irq controller drivers here. At the moment, the only
driver here is irq-bcm2835, the driver for the irq controller found in
the ARM BCM2835 SoC, present in Rasberry Pi systems. This irq
controller driver was exporting its initialization function and its
irq handling function through a header file in
<linux/irqchip/bcm2835.h>.
When proposing to also move another irq controller driver in
drivers/irqchip, Rob Herring raised the very valid point that moving
things to drivers/irqchip was good in order to remove more stuff from
arch/arm, but if it means adding gazillions of headers files in
include/linux/irqchip/, it would not be very nice.
So, upon the suggestion of Rob Herring and Arnd Bergmann, this commit
introduces a small infrastructure that defines a central
irqchip_init() function in drivers/irqchip/irqchip.c, which is meant
to be called as the ->init_irq() callback of ARM platforms. This
function calls of_irq_init() with an array of match strings and init
functions generated from a special linker section.
Note that the irq controller driver initialization function is
responsible for setting the global handle_arch_irq() variable, so that
ARM platforms no longer have to define the ->handle_irq field in their
DT_MACHINE structure.
A global header, <linux/irqchip.h> is also added to expose the single
irqchip_init() function to the reset of the kernel.
A further commit moves the BCM2835 irq controller driver to this new
small infrastructure, therefore removing the include/linux/irqchip/
directory.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
[rob.herring: reword commit message to reflect use of linker sections.]
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-11-21 02:00:52 +04:00
|
|
|
obj-$(CONFIG_IRQCHIP) += irqchip.o
|
|
|
|
|
|
2016-02-19 18:22:44 +03:00
|
|
|
obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
|
2016-01-23 15:57:47 +03:00
|
|
|
obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
|
2016-01-23 15:57:46 +03:00
|
|
|
obj-$(CONFIG_ATH79) += irq-ath79-misc.o
|
2012-11-12 21:26:03 +04:00
|
|
|
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
|
2015-08-07 02:00:33 +03:00
|
|
|
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
|
2013-02-13 02:04:52 +04:00
|
|
|
obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
|
2014-08-07 14:51:34 +04:00
|
|
|
obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
|
irqchip: Add LPC32xx interrupt controller driver
The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2
interrupt controllers.
This is a list of new features in comparison to the legacy driver:
* irq types are taken from device tree settings, no more need to
hardcode them,
* old driver is based on irq_domain_add_legacy, which causes problems
with handling MIC hardware interrupt 0 produced by SIC1,
* there is one driver for MIC, SIC1 and SIC2, no more need to handle
them separately, e.g. have two separate handlers for SIC1 and SIC2,
* the driver does not have any dependencies on hardcoded register
offsets,
* the driver is much simpler for maintenance,
* SPARSE_IRQS option is supported.
Legacy LPC32xx interrupt controller driver was broken since commit
76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"), which
requires a private interrupt handler, otherwise any SIC1 generated
interrupt (mapped to MIC hwirq 0) breaks the kernel with the message
"unexpected IRQ trap at vector 00".
The change disables compilation of a legacy driver found at
arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate
commit.
Fixes: 76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler")
Tested-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-04-25 04:00:38 +03:00
|
|
|
obj-$(CONFIG_ARCH_LPC32XX) += irq-lpc32xx.o
|
2013-04-21 09:21:48 +04:00
|
|
|
obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
|
2015-10-12 22:15:34 +03:00
|
|
|
obj-$(CONFIG_IRQ_MXS) += irq-mxs.o
|
2015-03-11 18:42:59 +03:00
|
|
|
obj-$(CONFIG_ARCH_TEGRA) += irq-tegra.o
|
2013-04-04 09:53:33 +04:00
|
|
|
obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
|
2013-09-09 16:01:20 +04:00
|
|
|
obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
|
2012-10-09 13:54:47 +04:00
|
|
|
obj-$(CONFIG_METAG) += irq-metag-ext.o
|
|
|
|
|
obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
|
2013-07-04 16:38:51 +04:00
|
|
|
obj-$(CONFIG_ARCH_MOXART) += irq-moxart.o
|
2014-02-02 12:07:46 +04:00
|
|
|
obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o
|
2014-05-27 00:31:42 +04:00
|
|
|
obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o
|
2013-06-06 20:27:09 +04:00
|
|
|
obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
|
2014-09-16 01:15:02 +04:00
|
|
|
obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o
|
2013-03-24 13:10:04 +04:00
|
|
|
obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
|
2014-03-19 23:21:17 +04:00
|
|
|
obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o
|
2012-11-12 21:26:03 +04:00
|
|
|
obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
|
2014-06-30 19:01:30 +04:00
|
|
|
obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o
|
2015-10-24 01:15:52 +03:00
|
|
|
obj-$(CONFIG_REALVIEW_DT) += irq-gic-realview.o
|
2014-11-25 21:47:22 +03:00
|
|
|
obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o
|
2014-06-30 19:01:31 +04:00
|
|
|
obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o
|
2015-07-28 16:46:22 +03:00
|
|
|
obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-pci-msi.o irq-gic-v3-its-platform-msi.o
|
irqchip: Add per-cpu interrupt partitioning library
We've unfortunately started seeing a situation where percpu interrupts
are partitioned in the system: one arbitrary set of CPUs has an
interrupt connected to a type of device, while another disjoint
set of CPUs has the same interrupt connected to another type of device.
This makes it impossible to have a device driver requesting this interrupt
using the current percpu-interrupt abstraction, as the same interrupt number
is now potentially claimed by at least two drivers, and we forbid interrupt
sharing on per-cpu interrupt.
A solution to this is to turn things upside down. Let's assume that our
system describes all the possible partitions for a given interrupt, and
give each of them a unique identifier. It is then possible to create
a namespace where the affinity identifier itself is a form of interrupt
number. At this point, it becomes easy to implement a set of partitions
as a cascaded irqchip, each affinity identifier being the HW irq.
This allows us to keep a number of nice properties:
- Each partition results in a separate percpu-interrupt (with a restrictied
affinity), which keeps drivers happy.
- Because the underlying interrupt is still per-cpu, the overhead of
the indirection can be kept pretty minimal.
- The core code can ignore most of that crap.
For that purpose, we implement a small library that deals with some of
the boilerplate code, relying on platform-specific drivers to provide
a description of the affinity sets and a set of callbacks.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Link: http://lkml.kernel.org/r/1460365075-7316-4-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-04-11 11:57:53 +03:00
|
|
|
obj-$(CONFIG_PARTITION_PERCPU) += irq-partition-percpu.o
|
irqchip/mgigen: Add platform device driver for mbigen device
Mbigen means Message Based Interrupt Generator(MBIGEN).
Its a kind of interrupt controller that collects
the interrupts from external devices and generate msi interrupt.
Mbigen is applied to reduce the number of wire connected interrupts.
As the peripherals increasing, the interrupts lines needed is
increasing much, especially on the Arm64 server SOC.
Therefore, the interrupt pin in GIC is not enough to cover so
many peripherals.
Mbigen is designed to fix this problem.
Mbigen chip locates in ITS or outside of ITS.
Mbigen chip hardware structure shows as below:
mbigen chip
|---------------------|-------------------|
mgn_node0 mgn_node1 mgn_node2
| |-------| |-------|------|
dev1 dev1 dev2 dev1 dev3 dev4
Each mbigen chip contains several mbigen nodes.
External devices can connect to mbigen node through wire connecting way.
Because a mbigen node only can support 128 interrupt maximum, depends
on the interrupt lines number of devices, a device can connects to one
more mbigen nodes.
Also, several different devices can connect to a same mbigen node.
When devices triggered interrupt,mbigen chip detects and collects
the interrupts and generates the MBI interrupts by writing the ITS
Translator register.
To simplify mbigen driver,I used a new conception--mbigen device.
Each mbigen device is initialized as a platform device.
Mbigen device presents the parts(register, pin definition etc.) in
mbigen chip corresponding to a peripheral device.
So from software view, the structure likes below
mbigen chip
|---------------------|-----------------|
mbigen device1 mbigen device2 mbigen device3
| | |
dev1 dev2 dev3
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ma Jun <majun258@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-12-17 14:56:35 +03:00
|
|
|
obj-$(CONFIG_HISILICON_IRQ_MBIGEN) += irq-mbigen.o
|
2013-06-26 11:18:48 +04:00
|
|
|
obj-$(CONFIG_ARM_NVIC) += irq-nvic.o
|
2012-10-28 02:25:26 +04:00
|
|
|
obj-$(CONFIG_ARM_VIC) += irq-vic.o
|
2016-02-10 17:46:56 +03:00
|
|
|
obj-$(CONFIG_ARMADA_370_XP_IRQ) += irq-armada-370-xp.o
|
2014-07-10 21:14:18 +04:00
|
|
|
obj-$(CONFIG_ATMEL_AIC_IRQ) += irq-atmel-aic-common.o irq-atmel-aic.o
|
|
|
|
|
obj-$(CONFIG_ATMEL_AIC5_IRQ) += irq-atmel-aic-common.o irq-atmel-aic5.o
|
2015-07-08 15:46:08 +03:00
|
|
|
obj-$(CONFIG_I8259) += irq-i8259.o
|
2013-04-22 18:43:50 +04:00
|
|
|
obj-$(CONFIG_IMGPDC_IRQ) += irq-imgpdc.o
|
2015-05-26 19:20:06 +03:00
|
|
|
obj-$(CONFIG_IRQ_MIPS_CPU) += irq-mips-cpu.o
|
2013-03-19 14:21:44 +04:00
|
|
|
obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o
|
2013-02-18 18:28:34 +04:00
|
|
|
obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
|
2013-02-27 12:15:01 +04:00
|
|
|
obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
|
2012-11-21 07:21:40 +04:00
|
|
|
obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
|
2013-12-05 10:12:17 +04:00
|
|
|
obj-$(CONFIG_ARCH_NSPIRE) += irq-zevio.o
|
2013-03-24 05:12:25 +04:00
|
|
|
obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o
|
2015-02-18 18:13:58 +03:00
|
|
|
obj-$(CONFIG_ST_IRQCHIP) += irq-st.o
|
2016-01-20 21:07:17 +03:00
|
|
|
obj-$(CONFIG_TANGO_IRQ) += irq-tango.o
|
2013-06-25 20:29:57 +04:00
|
|
|
obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o
|
2015-12-21 23:11:23 +03:00
|
|
|
obj-$(CONFIG_TS4800_IRQ) += irq-ts4800.o
|
2013-12-01 12:59:49 +04:00
|
|
|
obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o
|
2013-12-01 12:04:57 +04:00
|
|
|
obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o
|
2013-12-03 14:27:23 +04:00
|
|
|
obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
|
2015-03-02 01:41:27 +03:00
|
|
|
obj-$(CONFIG_SOC_VF610) += irq-vf610-mscm-ir.o
|
2015-11-22 17:30:14 +03:00
|
|
|
obj-$(CONFIG_BCM6345_L1_IRQ) += irq-bcm6345-l1.o
|
IRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllers
This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
it has the following characteristics:
- 64 to 160+ level IRQs
- Atomic set/clear registers
- Reasonably predictable register layout (N status words, then N
mask status words, then N mask set words, then N mask clear words)
- SMP affinity supported on most systems
- Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3
This driver registers one IRQ domain and one IRQ chip to cover all
instances of the block. Up to 4 instances of the block may appear, as
it supports 4-way IRQ affinity on BCM7435.
The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC
is used instead. So this driver is primarily intended for MIPS STB chips.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8844/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-12-25 20:49:06 +03:00
|
|
|
obj-$(CONFIG_BCM7038_L1_IRQ) += irq-bcm7038-l1.o
|
2014-11-07 09:44:27 +03:00
|
|
|
obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o
|
|
|
|
|
obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o
|
2014-07-23 18:40:30 +04:00
|
|
|
obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o
|
2014-09-19 01:47:19 +04:00
|
|
|
obj-$(CONFIG_MIPS_GIC) += irq-mips-gic.o
|
2014-11-25 11:04:20 +03:00
|
|
|
obj-$(CONFIG_ARCH_MEDIATEK) += irq-mtk-sysirq.o
|
2015-01-15 13:34:00 +03:00
|
|
|
obj-$(CONFIG_ARCH_DIGICOLOR) += irq-digicolor.o
|
2015-05-09 20:30:47 +03:00
|
|
|
obj-$(CONFIG_RENESAS_H8300H_INTC) += irq-renesas-h8300h.o
|
|
|
|
|
obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o
|
2015-05-19 18:17:09 +03:00
|
|
|
obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o
|
2015-05-24 18:11:31 +03:00
|
|
|
obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
|
2015-08-24 22:04:15 +03:00
|
|
|
obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
|
2016-01-14 04:15:35 +03:00
|
|
|
obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o
|
2016-02-19 16:34:43 +03:00
|
|
|
obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
|
2016-03-23 14:08:20 +03:00
|
|
|
obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
|
2015-10-29 01:26:22 +03:00
|
|
|
obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
|
