98 строки
2.5 KiB
C
98 строки
2.5 KiB
C
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/*
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* Atheros AR71xx/AR724x/AR913x specific interrupt handling
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*
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* Copyright (C) 2015 Alban Bedel <albeu@free.fr>
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/interrupt.h>
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#include <linux/irqchip.h>
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#include <linux/of.h>
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#include <asm/irq_cpu.h>
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#include <asm/mach-ath79/ath79.h>
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/*
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* The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
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* these devices typically allocate coherent DMA memory, however the
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* DMA controller may still have some unsynchronized data in the FIFO.
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* Issue a flush in the handlers to ensure that the driver sees
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* the update.
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*
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* This array map the interrupt lines to the DDR write buffer channels.
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*/
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static unsigned irq_wb_chan[8] = {
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-1, -1, -1, -1, -1, -1, -1, -1,
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};
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned long pending;
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int irq;
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pending = read_c0_status() & read_c0_cause() & ST0_IM;
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if (!pending) {
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spurious_interrupt();
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return;
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}
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pending >>= CAUSEB_IP;
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while (pending) {
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irq = fls(pending) - 1;
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if (irq < ARRAY_SIZE(irq_wb_chan) && irq_wb_chan[irq] != -1)
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ath79_ddr_wb_flush(irq_wb_chan[irq]);
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do_IRQ(MIPS_CPU_IRQ_BASE + irq);
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pending &= ~BIT(irq);
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}
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}
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static int __init ar79_cpu_intc_of_init(
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struct device_node *node, struct device_node *parent)
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{
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int err, i, count;
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/* Fill the irq_wb_chan table */
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count = of_count_phandle_with_args(
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node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells");
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for (i = 0; i < count; i++) {
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struct of_phandle_args args;
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u32 irq = i;
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of_property_read_u32_index(
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node, "qca,ddr-wb-channel-interrupts", i, &irq);
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if (irq >= ARRAY_SIZE(irq_wb_chan))
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continue;
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err = of_parse_phandle_with_args(
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node, "qca,ddr-wb-channels",
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"#qca,ddr-wb-channel-cells",
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i, &args);
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if (err)
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return err;
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irq_wb_chan[irq] = args.args[0];
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}
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return mips_cpu_irq_of_init(node, parent);
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}
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IRQCHIP_DECLARE(ar79_cpu_intc, "qca,ar7100-cpu-intc",
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ar79_cpu_intc_of_init);
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void __init ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3)
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{
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irq_wb_chan[2] = irq_wb_chan2;
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irq_wb_chan[3] = irq_wb_chan3;
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mips_cpu_irq_init();
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}
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