2020-10-13 17:45:52 +03:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Common LiteX header providing
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* helper functions for accessing CSRs.
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*
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* Copyright (C) 2019-2020 Antmicro <www.antmicro.com>
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*/
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#ifndef _LINUX_LITEX_H
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#define _LINUX_LITEX_H
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#include <linux/io.h>
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2021-01-12 20:31:41 +03:00
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static inline void _write_litex_subregister(u32 val, void __iomem *addr)
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{
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writel((u32 __force)cpu_to_le32(val), addr);
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}
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static inline u32 _read_litex_subregister(void __iomem *addr)
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{
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return le32_to_cpu((__le32 __force)readl(addr));
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}
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2021-01-12 20:31:40 +03:00
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/*
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* LiteX SoC Generator, depending on the configuration, can split a single
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* logical CSR (Control&Status Register) into a series of consecutive physical
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* registers.
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*
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drivers/soc/litex: support 32-bit subregisters, 64-bit CPUs
Upstream LiteX now defaults to using 32-bit CSR subregisters
(see https://github.com/enjoy-digital/litex/commit/a2b71fde).
This patch expands on commit 22447a99c97e ("drivers/soc/litex: add
LiteX SoC Controller driver"), adding support for handling both 8-
and 32-bit LiteX CSR (MMIO) subregisters, as determined by the
LITEX_SUBREG_SIZE Kconfig option.
NOTE that while LITEX_SUBREG_SIZE could theoretically be a device
tree property, defining it as a compile-time constant allows for
much better optimization of the resulting code. This is further
supported by the low expected usefulness of deploying the same
kernel across LiteX SoCs built with different CSR-Bus data widths.
Finally, the litex_[read|write][8|16|32|64]() accessors are
redefined in terms of litex_[get|set]_reg(), which, after compiler
optimization, will result in code as efficient as hardcoded shifts,
but with the added benefit of automatically matching the appropriate
LITEX_SUBREG_SIZE.
NOTE that litex_[get|set]_reg() nominally operate on 64-bit data,
but that will also be optimized by the compiler in situations where
narrower data is used from a call site.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
2021-01-12 20:31:43 +03:00
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* For example, in the configuration with 8-bit CSR Bus, a 32-bit aligned,
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* 32-bit wide logical CSR will be laid out as four 32-bit physical
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* subregisters, each one containing one byte of meaningful data.
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2021-01-12 20:31:40 +03:00
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*
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2021-05-26 13:51:26 +03:00
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* For Linux support, upstream LiteX enforces a 32-bit wide CSR bus, which
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* means that only larger-than-32-bit CSRs will be split across multiple
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* subregisters (e.g., a 64-bit CSR will be spread across two consecutive
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* 32-bit subregisters).
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2021-01-12 20:31:40 +03:00
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*
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2021-05-26 13:51:26 +03:00
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* For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus
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2021-01-12 20:31:40 +03:00
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*/
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2020-10-13 17:45:52 +03:00
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static inline void litex_write8(void __iomem *reg, u8 val)
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{
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2021-05-26 13:51:26 +03:00
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_write_litex_subregister(val, reg);
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2020-10-13 17:45:52 +03:00
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}
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static inline void litex_write16(void __iomem *reg, u16 val)
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{
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2021-05-26 13:51:26 +03:00
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_write_litex_subregister(val, reg);
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2020-10-13 17:45:52 +03:00
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}
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static inline void litex_write32(void __iomem *reg, u32 val)
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{
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2021-05-26 13:51:26 +03:00
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_write_litex_subregister(val, reg);
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2020-10-13 17:45:52 +03:00
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}
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static inline void litex_write64(void __iomem *reg, u64 val)
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{
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2021-05-26 13:51:26 +03:00
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_write_litex_subregister(val >> 32, reg);
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_write_litex_subregister(val, reg + 4);
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2020-10-13 17:45:52 +03:00
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}
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static inline u8 litex_read8(void __iomem *reg)
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{
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2021-05-26 13:51:26 +03:00
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return _read_litex_subregister(reg);
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2020-10-13 17:45:52 +03:00
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}
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static inline u16 litex_read16(void __iomem *reg)
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{
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2021-05-26 13:51:26 +03:00
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return _read_litex_subregister(reg);
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2020-10-13 17:45:52 +03:00
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}
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static inline u32 litex_read32(void __iomem *reg)
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{
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2021-05-26 13:51:26 +03:00
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return _read_litex_subregister(reg);
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2020-10-13 17:45:52 +03:00
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}
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static inline u64 litex_read64(void __iomem *reg)
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{
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2021-05-26 13:51:26 +03:00
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return ((u64)_read_litex_subregister(reg) << 32) |
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_read_litex_subregister(reg + 4);
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2020-10-13 17:45:52 +03:00
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}
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#endif /* _LINUX_LITEX_H */
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