2011-10-04 14:19:01 +04:00
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/* exynos_drm.h
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* Authors:
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* Inki Dae <inki.dae@samsung.com>
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* Joonyoung Shim <jy0922.shim@samsung.com>
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* Seung-Woo Kim <sw0312.kim@samsung.com>
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*
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2012-12-17 21:30:17 +04:00
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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2011-10-04 14:19:01 +04:00
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*/
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#ifndef _EXYNOS_DRM_H_
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#define _EXYNOS_DRM_H_
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2012-10-04 21:21:50 +04:00
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#include <uapi/drm/exynos_drm.h>
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2013-08-21 18:22:01 +04:00
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#include <video/videomode.h>
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2012-05-17 15:06:32 +04:00
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2011-10-04 14:19:01 +04:00
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/**
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2012-02-14 10:59:46 +04:00
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* A structure for lcd panel information.
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2011-10-04 14:19:01 +04:00
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*
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* @timing: default video mode for initializing
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2012-02-14 10:59:46 +04:00
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* @width_mm: physical size of lcd width.
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* @height_mm: physical size of lcd height.
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*/
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struct exynos_drm_panel_info {
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2013-08-21 18:22:01 +04:00
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struct videomode vm;
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2012-02-14 10:59:46 +04:00
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u32 width_mm;
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u32 height_mm;
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};
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/**
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* Platform Specific Structure for DRM based FIMD.
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*
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* @panel: default panel info for initializing
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2011-10-04 14:19:01 +04:00
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* @default_win: default window layer number to be used for UI.
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* @bpp: default bit per pixel.
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*/
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struct exynos_drm_fimd_pdata {
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2012-02-14 10:59:46 +04:00
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struct exynos_drm_panel_info panel;
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2011-10-04 14:19:01 +04:00
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u32 vidcon0;
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u32 vidcon1;
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unsigned int default_win;
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unsigned int bpp;
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};
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drm/exynos: added hdmi display support
This patch is hdmi display support for exynos drm driver.
There is already v4l2 based exynos hdmi driver in drivers/media/video/s5p-tv
and some low level code is already in s5p-tv and even headers for register
define are almost same. but in this patch, we decide not to consider separated
common code with s5p-tv.
Exynos HDMI is composed of 5 blocks, mixer, vp, hdmi, hdmiphy and ddc.
1. mixer. The piece of hardware responsible for mixing and blending multiple
data inputs before passing it to an output device. The mixer is capable of
handling up to three image layers. One is the output of VP. Other two are
images in RGB format. The blending factor, and layers' priority are controlled
by mixer's registers. The output is passed to HDMI.
2. vp (video processor). It is used for processing of NV12/NV21 data. An image
stored in RAM is accessed by DMA. The output in YCbCr444 format is send to
mixer.
3. hdmi. The piece of HW responsible for generation of HDMI packets. It takes
pixel data from mixer and transforms it into data frames. The output is send
to HDMIPHY interface.
4. hdmiphy. Physical interface for HDMI. Its duties are sending HDMI packets to
HDMI connector. Basically, it contains a PLL that produces source clock for
mixer, vp and hdmi.
5. ddc (display data channel). It is dedicated i2c channel to exchange display
information as edid with display monitor.
With plane support, exynos hdmi driver fully supports two mixer layes and vp
layer. Also vp layer supports multi buffer plane pixel formats having non
contigus memory spaces.
In exynos drm driver, common drm_hdmi driver to interface with drm framework
has opertion pointers for mixer and hdmi. this drm_hdmi driver is registered as
sub driver of exynos_drm. hdmi has hdmiphy and ddc i2c clients and controls
them. mixer controls all overlay layers in both mixer and vp.
Vblank interrupts for hdmi are handled by mixer internally because drm
framework cannot support multiple irq id. And pipe number is used to check
which display device irq happens.
History
v2: this version
- drm plane feature support to handle overlay layers.
- multi buffer plane pixel format support for vp layer.
- vp layer support
RFCv1: original
- at https://lkml.org/lkml/2011/11/4/164
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2011-12-21 12:39:39 +04:00
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/**
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* Platform Specific Structure for DRM based HDMI.
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*
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* @hdmi_dev: device point to specific hdmi driver.
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* @mixer_dev: device point to specific mixer driver.
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*
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* this structure is used for common hdmi driver and each device object
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* would be used to access specific device driver(hdmi or mixer driver)
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*/
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struct exynos_drm_common_hdmi_pd {
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struct device *hdmi_dev;
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struct device *mixer_dev;
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};
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/**
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* Platform Specific Structure for DRM based HDMI core.
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*
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2012-03-16 13:47:03 +04:00
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* @is_v13: set if hdmi version 13 is.
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2012-04-23 14:35:47 +04:00
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* @cfg_hpd: function pointer to configure hdmi hotplug detection pin
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* @get_hpd: function pointer to get value of hdmi hotplug detection pin
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drm/exynos: added hdmi display support
This patch is hdmi display support for exynos drm driver.
There is already v4l2 based exynos hdmi driver in drivers/media/video/s5p-tv
and some low level code is already in s5p-tv and even headers for register
define are almost same. but in this patch, we decide not to consider separated
common code with s5p-tv.
Exynos HDMI is composed of 5 blocks, mixer, vp, hdmi, hdmiphy and ddc.
1. mixer. The piece of hardware responsible for mixing and blending multiple
data inputs before passing it to an output device. The mixer is capable of
handling up to three image layers. One is the output of VP. Other two are
images in RGB format. The blending factor, and layers' priority are controlled
by mixer's registers. The output is passed to HDMI.
2. vp (video processor). It is used for processing of NV12/NV21 data. An image
stored in RAM is accessed by DMA. The output in YCbCr444 format is send to
mixer.
3. hdmi. The piece of HW responsible for generation of HDMI packets. It takes
pixel data from mixer and transforms it into data frames. The output is send
to HDMIPHY interface.
4. hdmiphy. Physical interface for HDMI. Its duties are sending HDMI packets to
HDMI connector. Basically, it contains a PLL that produces source clock for
mixer, vp and hdmi.
5. ddc (display data channel). It is dedicated i2c channel to exchange display
information as edid with display monitor.
With plane support, exynos hdmi driver fully supports two mixer layes and vp
layer. Also vp layer supports multi buffer plane pixel formats having non
contigus memory spaces.
In exynos drm driver, common drm_hdmi driver to interface with drm framework
has opertion pointers for mixer and hdmi. this drm_hdmi driver is registered as
sub driver of exynos_drm. hdmi has hdmiphy and ddc i2c clients and controls
them. mixer controls all overlay layers in both mixer and vp.
Vblank interrupts for hdmi are handled by mixer internally because drm
framework cannot support multiple irq id. And pipe number is used to check
which display device irq happens.
History
v2: this version
- drm plane feature support to handle overlay layers.
- multi buffer plane pixel format support for vp layer.
- vp layer support
RFCv1: original
- at https://lkml.org/lkml/2011/11/4/164
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2011-12-21 12:39:39 +04:00
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*/
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struct exynos_drm_hdmi_pdata {
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2012-04-23 14:35:47 +04:00
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bool is_v13;
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void (*cfg_hpd)(bool external);
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int (*get_hpd)(void);
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drm/exynos: added hdmi display support
This patch is hdmi display support for exynos drm driver.
There is already v4l2 based exynos hdmi driver in drivers/media/video/s5p-tv
and some low level code is already in s5p-tv and even headers for register
define are almost same. but in this patch, we decide not to consider separated
common code with s5p-tv.
Exynos HDMI is composed of 5 blocks, mixer, vp, hdmi, hdmiphy and ddc.
1. mixer. The piece of hardware responsible for mixing and blending multiple
data inputs before passing it to an output device. The mixer is capable of
handling up to three image layers. One is the output of VP. Other two are
images in RGB format. The blending factor, and layers' priority are controlled
by mixer's registers. The output is passed to HDMI.
2. vp (video processor). It is used for processing of NV12/NV21 data. An image
stored in RAM is accessed by DMA. The output in YCbCr444 format is send to
mixer.
3. hdmi. The piece of HW responsible for generation of HDMI packets. It takes
pixel data from mixer and transforms it into data frames. The output is send
to HDMIPHY interface.
4. hdmiphy. Physical interface for HDMI. Its duties are sending HDMI packets to
HDMI connector. Basically, it contains a PLL that produces source clock for
mixer, vp and hdmi.
5. ddc (display data channel). It is dedicated i2c channel to exchange display
information as edid with display monitor.
With plane support, exynos hdmi driver fully supports two mixer layes and vp
layer. Also vp layer supports multi buffer plane pixel formats having non
contigus memory spaces.
In exynos drm driver, common drm_hdmi driver to interface with drm framework
has opertion pointers for mixer and hdmi. this drm_hdmi driver is registered as
sub driver of exynos_drm. hdmi has hdmiphy and ddc i2c clients and controls
them. mixer controls all overlay layers in both mixer and vp.
Vblank interrupts for hdmi are handled by mixer internally because drm
framework cannot support multiple irq id. And pipe number is used to check
which display device irq happens.
History
v2: this version
- drm plane feature support to handle overlay layers.
- multi buffer plane pixel format support for vp layer.
- vp layer support
RFCv1: original
- at https://lkml.org/lkml/2011/11/4/164
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2011-12-21 12:39:39 +04:00
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};
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2012-12-14 12:58:55 +04:00
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/**
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* Platform Specific Structure for DRM based IPP.
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*
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* @inv_pclk: if set 1. invert pixel clock
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* @inv_vsync: if set 1. invert vsync signal for wb
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* @inv_href: if set 1. invert href signal
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* @inv_hsync: if set 1. invert hsync signal for wb
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*/
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struct exynos_drm_ipp_pol {
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unsigned int inv_pclk;
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unsigned int inv_vsync;
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unsigned int inv_href;
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unsigned int inv_hsync;
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};
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/**
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* Platform Specific Structure for DRM based FIMC.
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*
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* @pol: current hardware block polarity settings.
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* @clk_rate: current hardware clock rate.
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*/
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struct exynos_drm_fimc_pdata {
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struct exynos_drm_ipp_pol pol;
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int clk_rate;
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};
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2012-02-15 05:23:33 +04:00
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#endif /* _EXYNOS_DRM_H_ */
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