2012-06-01 20:21:46 +04:00
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/*
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2014-02-17 18:23:22 +04:00
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* System controller support for Armada 370, 375 and XP platforms.
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2012-06-01 20:21:46 +04:00
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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2014-02-17 18:23:22 +04:00
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* The Armada 370, 375 and Armada XP SoCs have a range of
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2012-06-01 20:21:46 +04:00
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* miscellaneous registers, that do not belong to a particular device,
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* but rather provide system-level features. This basic
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* system-controller driver provides a device tree binding for those
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* registers, and implements utility functions offering various
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* features related to those registers.
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*
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* For now, the feature set is limited to restarting the platform by a
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* soft-reset, but it might be extended in the future.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of_address.h>
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#include <linux/io.h>
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2013-07-09 03:01:40 +04:00
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#include <linux/reboot.h>
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2013-11-07 13:02:38 +04:00
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#include "common.h"
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2014-07-23 17:00:41 +04:00
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#include "mvebu-soc-id.h"
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#include "pmsu.h"
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#define ARMADA_375_CRYPT0_ENG_TARGET 41
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#define ARMADA_375_CRYPT0_ENG_ATTR 1
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2012-06-01 20:21:46 +04:00
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static void __iomem *system_controller_base;
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2014-07-23 17:00:41 +04:00
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static phys_addr_t system_controller_phys_base;
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2012-06-01 20:21:46 +04:00
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struct mvebu_system_controller {
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u32 rstoutn_mask_offset;
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u32 system_soft_reset_offset;
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u32 rstoutn_mask_reset_out_en;
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u32 system_soft_reset;
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2014-04-14 17:54:03 +04:00
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u32 resume_boot_addr;
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2014-06-23 19:42:08 +04:00
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u32 dev_id;
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u32 rev_id;
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2012-06-01 20:21:46 +04:00
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};
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static struct mvebu_system_controller *mvebu_sc;
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2013-11-07 13:02:38 +04:00
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static const struct mvebu_system_controller armada_370_xp_system_controller = {
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2012-06-01 20:21:46 +04:00
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.rstoutn_mask_offset = 0x60,
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.system_soft_reset_offset = 0x64,
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.rstoutn_mask_reset_out_en = 0x1,
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.system_soft_reset = 0x1,
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2014-06-23 19:42:08 +04:00
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.dev_id = 0x38,
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.rev_id = 0x3c,
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2012-06-01 20:21:46 +04:00
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};
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2014-02-17 18:23:22 +04:00
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static const struct mvebu_system_controller armada_375_system_controller = {
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.rstoutn_mask_offset = 0x54,
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.system_soft_reset_offset = 0x58,
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.rstoutn_mask_reset_out_en = 0x1,
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.system_soft_reset = 0x1,
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2014-04-14 17:54:03 +04:00
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.resume_boot_addr = 0xd4,
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2014-06-23 19:42:08 +04:00
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.dev_id = 0x38,
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.rev_id = 0x3c,
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2014-02-17 18:23:22 +04:00
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};
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2013-11-07 13:02:38 +04:00
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static const struct mvebu_system_controller orion_system_controller = {
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2012-06-01 20:21:46 +04:00
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.rstoutn_mask_offset = 0x108,
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.system_soft_reset_offset = 0x10c,
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.rstoutn_mask_reset_out_en = 0x4,
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.system_soft_reset = 0x1,
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};
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2014-02-11 20:24:02 +04:00
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static const struct of_device_id of_system_controller_table[] = {
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2012-06-01 20:21:46 +04:00
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{
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.compatible = "marvell,orion-system-controller",
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.data = (void *) &orion_system_controller,
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}, {
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.compatible = "marvell,armada-370-xp-system-controller",
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.data = (void *) &armada_370_xp_system_controller,
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2014-02-17 18:23:22 +04:00
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}, {
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.compatible = "marvell,armada-375-system-controller",
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.data = (void *) &armada_375_system_controller,
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2012-06-01 20:21:46 +04:00
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},
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{ /* end of list */ },
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};
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2013-07-09 03:01:40 +04:00
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void mvebu_restart(enum reboot_mode mode, const char *cmd)
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2012-06-01 20:21:46 +04:00
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{
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if (!system_controller_base) {
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pr_err("Cannot restart, system-controller not available: check the device tree\n");
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} else {
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/*
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* Enable soft reset to assert RSTOUTn.
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*/
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writel(mvebu_sc->rstoutn_mask_reset_out_en,
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system_controller_base +
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mvebu_sc->rstoutn_mask_offset);
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/*
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* Assert soft reset.
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*/
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writel(mvebu_sc->system_soft_reset,
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system_controller_base +
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mvebu_sc->system_soft_reset_offset);
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}
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while (1)
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;
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}
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2014-06-23 19:42:08 +04:00
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int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev)
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{
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if (of_machine_is_compatible("marvell,armada380") &&
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system_controller_base) {
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*dev = readl(system_controller_base + mvebu_sc->dev_id) >> 16;
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*rev = (readl(system_controller_base + mvebu_sc->rev_id) >> 8)
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& 0xF;
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return 0;
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} else
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return -ENODEV;
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}
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2015-02-02 17:27:16 +03:00
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#if defined(CONFIG_SMP) && defined(CONFIG_MACH_MVEBU_V7)
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2016-06-07 22:03:48 +03:00
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static void mvebu_armada375_smp_wa_init(void)
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2014-07-23 17:00:41 +04:00
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{
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u32 dev, rev;
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phys_addr_t resume_addr_reg;
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if (mvebu_get_soc_id(&dev, &rev) != 0)
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return;
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if (rev != ARMADA_375_Z1_REV)
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return;
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resume_addr_reg = system_controller_phys_base +
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mvebu_sc->resume_boot_addr;
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mvebu_setup_boot_addr_wa(ARMADA_375_CRYPT0_ENG_TARGET,
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ARMADA_375_CRYPT0_ENG_ATTR,
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resume_addr_reg);
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}
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2014-04-14 17:54:03 +04:00
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void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr)
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{
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BUG_ON(system_controller_base == NULL);
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BUG_ON(mvebu_sc->resume_boot_addr == 0);
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2014-07-23 17:00:41 +04:00
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if (of_machine_is_compatible("marvell,armada375"))
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mvebu_armada375_smp_wa_init();
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2017-01-15 05:59:29 +03:00
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writel(__pa_symbol(boot_addr), system_controller_base +
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2014-04-14 17:54:03 +04:00
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mvebu_sc->resume_boot_addr);
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}
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#endif
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2012-06-01 20:21:46 +04:00
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static int __init mvebu_system_controller_init(void)
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{
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2014-02-11 20:24:02 +04:00
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const struct of_device_id *match;
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2012-06-01 20:21:46 +04:00
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struct device_node *np;
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2014-02-11 20:24:02 +04:00
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np = of_find_matching_node_and_match(NULL, of_system_controller_table,
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&match);
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2012-06-01 20:21:46 +04:00
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if (np) {
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2014-07-23 17:00:41 +04:00
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struct resource res;
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2012-06-01 20:21:46 +04:00
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system_controller_base = of_iomap(np, 0);
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2014-07-23 17:00:41 +04:00
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of_address_to_resource(np, 0, &res);
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system_controller_phys_base = res.start;
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2012-06-01 20:21:46 +04:00
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mvebu_sc = (struct mvebu_system_controller *)match->data;
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2013-08-27 08:41:14 +04:00
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of_node_put(np);
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2012-06-01 20:21:46 +04:00
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}
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return 0;
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}
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2014-04-14 17:54:03 +04:00
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early_initcall(mvebu_system_controller_init);
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