2019-06-04 11:11:32 +03:00
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// SPDX-License-Identifier: GPL-2.0-only
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2011-11-23 18:30:32 +04:00
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/*
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* Kernel-based Virtual Machine driver for Linux
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* cpuid support routines
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*
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* derived from arch/x86/kvm/x86.c
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*
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* Copyright 2011 Red Hat, Inc. and/or its affiliates.
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* Copyright IBM Corporation, 2008
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*/
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#include <linux/kvm_host.h>
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2016-07-14 03:19:00 +03:00
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#include <linux/export.h>
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2011-12-14 20:58:18 +04:00
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#include <linux/vmalloc.h>
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#include <linux/uaccess.h>
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2017-02-05 14:07:04 +03:00
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#include <linux/sched/stat.h>
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2016-11-07 09:03:20 +03:00
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#include <asm/processor.h>
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2011-11-23 18:30:32 +04:00
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#include <asm/user.h>
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2015-04-28 09:41:33 +03:00
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#include <asm/fpu/xstate.h>
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2011-11-23 18:30:32 +04:00
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#include "cpuid.h"
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#include "lapic.h"
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#include "mmu.h"
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#include "trace.h"
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2015-06-19 14:54:23 +03:00
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#include "pmu.h"
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2011-11-23 18:30:32 +04:00
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KVM: x86: Introduce kvm_cpu_caps to replace runtime CPUID masking
Calculate the CPUID masks for KVM_GET_SUPPORTED_CPUID at load time using
what is effectively a KVM-adjusted copy of boot_cpu_data, or more
precisely, the x86_capability array in boot_cpu_data.
In terms of KVM support, the vast majority of CPUID feature bits are
constant, and *all* feature support is known at KVM load time. Rather
than apply boot_cpu_data, which is effectively read-only after init,
at runtime, copy it into a KVM-specific array and use *that* to mask
CPUID registers.
In additional to consolidating the masking, kvm_cpu_caps can be adjusted
by SVM/VMX at load time and thus eliminate all feature bit manipulation
in ->set_supported_cpuid().
Opportunistically clean up a few warts:
- Replace bare "unsigned" with "unsigned int" when a feature flag is
captured in a local variable, e.g. f_nx.
- Sort the CPUID masks by function, index and register (alphabetically
for registers, i.e. EBX comes before ECX/EDX).
- Remove the superfluous /* cpuid 7.0.ecx */ comments.
No functional change intended.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
[Call kvm_set_cpu_caps from kvm_x86_ops->hardware_setup due to fixed
GBPAGES patch. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-03 02:56:41 +03:00
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/*
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* Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be
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* aligned to sizeof(unsigned long) because it's not accessed via bitops.
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*/
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u32 kvm_cpu_caps[NCAPINTS] __read_mostly;
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EXPORT_SYMBOL_GPL(kvm_cpu_caps);
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2014-12-03 16:38:01 +03:00
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static u32 xstate_required_size(u64 xstate_bv, bool compacted)
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2013-10-02 18:06:16 +04:00
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{
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int feature_bit = 0;
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u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
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2015-09-03 02:31:26 +03:00
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xstate_bv &= XFEATURE_MASK_EXTEND;
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2013-10-02 18:06:16 +04:00
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while (xstate_bv) {
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if (xstate_bv & 0x1) {
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2014-12-03 16:38:01 +03:00
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u32 eax, ebx, ecx, edx, offset;
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2013-10-02 18:06:16 +04:00
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cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx);
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2014-12-03 16:38:01 +03:00
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offset = compacted ? ret : ebx;
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ret = max(ret, offset + eax);
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2013-10-02 18:06:16 +04:00
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}
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xstate_bv >>= 1;
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feature_bit++;
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}
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return ret;
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}
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2019-12-18 00:32:42 +03:00
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#define F feature_bit
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2014-12-03 16:34:47 +03:00
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2020-10-01 16:05:39 +03:00
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static inline struct kvm_cpuid_entry2 *cpuid_entry2_find(
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struct kvm_cpuid_entry2 *entries, int nent, u32 function, u32 index)
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{
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struct kvm_cpuid_entry2 *e;
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int i;
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for (i = 0; i < nent; i++) {
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e = &entries[i];
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if (e->function == function && (e->index == index ||
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!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX)))
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return e;
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}
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return NULL;
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}
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static int kvm_check_cpuid(struct kvm_cpuid_entry2 *entries, int nent)
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2020-07-09 07:34:22 +03:00
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{
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struct kvm_cpuid_entry2 *best;
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/*
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* The existing code assumes virtual address is 48-bit or 57-bit in the
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* canonical address checks; exit if it is ever changed.
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*/
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2020-10-01 16:05:39 +03:00
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best = cpuid_entry2_find(entries, nent, 0x80000008, 0);
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2020-07-09 07:34:22 +03:00
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if (best) {
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int vaddr_bits = (best->eax & 0xff00) >> 8;
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if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0)
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return -EINVAL;
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}
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return 0;
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}
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2020-10-28 02:10:42 +03:00
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void kvm_update_pv_runtime(struct kvm_vcpu *vcpu)
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{
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struct kvm_cpuid_entry2 *best;
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best = kvm_find_cpuid_entry(vcpu, KVM_CPUID_FEATURES, 0);
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/*
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* save the feature bitmap to avoid cpuid lookup for every PV
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* operation
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*/
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if (best)
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vcpu->arch.pv_cpuid.features = best->eax;
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}
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2020-07-09 07:34:23 +03:00
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void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu)
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2011-11-23 18:30:32 +04:00
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{
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struct kvm_cpuid_entry2 *best;
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best = kvm_find_cpuid_entry(vcpu, 1, 0);
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2020-07-08 09:50:48 +03:00
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if (best) {
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/* Update OSXSAVE bit */
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if (boot_cpu_has(X86_FEATURE_XSAVE))
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cpuid_entry_change(best, X86_FEATURE_OSXSAVE,
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2020-03-03 02:56:31 +03:00
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kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE));
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2011-11-23 18:30:32 +04:00
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2020-07-08 09:50:48 +03:00
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cpuid_entry_change(best, X86_FEATURE_APIC,
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2020-03-03 02:56:31 +03:00
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vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE);
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2020-07-08 09:50:48 +03:00
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}
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2016-11-09 20:50:11 +03:00
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2016-03-22 11:51:21 +03:00
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best = kvm_find_cpuid_entry(vcpu, 7, 0);
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2020-03-03 02:56:31 +03:00
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if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7)
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cpuid_entry_change(best, X86_FEATURE_OSPKE,
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kvm_read_cr4_bits(vcpu, X86_CR4_PKE));
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2016-03-22 11:51:21 +03:00
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2013-10-02 18:06:15 +04:00
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best = kvm_find_cpuid_entry(vcpu, 0xD, 0);
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2020-07-09 07:34:23 +03:00
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if (best)
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2020-04-29 18:43:12 +03:00
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best->ebx = xstate_required_size(vcpu->arch.xcr0, false);
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2013-10-02 18:06:15 +04:00
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2014-12-03 16:38:01 +03:00
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best = kvm_find_cpuid_entry(vcpu, 0xD, 1);
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2020-03-03 02:56:30 +03:00
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if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) ||
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cpuid_entry_has(best, X86_FEATURE_XSAVEC)))
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2014-12-03 16:38:01 +03:00
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best->ebx = xstate_required_size(vcpu->arch.xcr0, true);
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2018-03-12 14:53:03 +03:00
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best = kvm_find_cpuid_entry(vcpu, KVM_CPUID_FEATURES, 0);
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if (kvm_hlt_in_guest(vcpu->kvm) && best &&
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(best->eax & (1 << KVM_FEATURE_PV_UNHALT)))
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best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT);
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2019-05-21 09:06:54 +03:00
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if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) {
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best = kvm_find_cpuid_entry(vcpu, 0x1, 0);
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2020-03-03 02:56:31 +03:00
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if (best)
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cpuid_entry_change(best, X86_FEATURE_MWAIT,
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vcpu->arch.ia32_misc_enable_msr &
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MSR_IA32_MISC_ENABLE_MWAIT);
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2019-05-21 09:06:54 +03:00
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}
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2020-07-09 07:34:23 +03:00
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}
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2020-07-09 07:34:24 +03:00
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static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
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2020-07-09 07:34:23 +03:00
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{
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struct kvm_lapic *apic = vcpu->arch.apic;
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struct kvm_cpuid_entry2 *best;
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best = kvm_find_cpuid_entry(vcpu, 1, 0);
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if (best && apic) {
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if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER))
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apic->lapic_timer.timer_mode_mask = 3 << 17;
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else
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apic->lapic_timer.timer_mode_mask = 1 << 17;
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kvm_apic_set_version(vcpu);
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}
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best = kvm_find_cpuid_entry(vcpu, 0xD, 0);
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if (!best)
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vcpu->arch.guest_supported_xcr0 = 0;
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else
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vcpu->arch.guest_supported_xcr0 =
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(best->eax | ((u64)best->edx << 32)) & supported_xcr0;
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2019-05-21 09:06:54 +03:00
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2020-10-28 02:10:42 +03:00
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kvm_update_pv_runtime(vcpu);
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2015-03-29 23:56:12 +03:00
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vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
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2017-08-24 15:27:55 +03:00
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kvm_mmu_reset_context(vcpu);
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2015-03-29 23:56:12 +03:00
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2015-06-19 14:44:45 +03:00
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kvm_pmu_refresh(vcpu);
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2020-07-08 03:39:55 +03:00
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vcpu->arch.cr4_guest_rsvd_bits =
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__cr4_reserved_bits(guest_cpuid_has, vcpu);
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2020-09-30 07:16:56 +03:00
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/* Invoke the vendor callback only after the above state is updated. */
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kvm_x86_ops.vcpu_after_set_cpuid(vcpu);
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2011-11-23 18:30:32 +04:00
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}
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static int is_efer_nx(void)
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{
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2020-03-03 02:57:06 +03:00
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return host_efer & EFER_NX;
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2011-11-23 18:30:32 +04:00
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}
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static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
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{
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int i;
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struct kvm_cpuid_entry2 *e, *entry;
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entry = NULL;
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for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
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e = &vcpu->arch.cpuid_entries[i];
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if (e->function == 0x80000001) {
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entry = e;
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break;
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}
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}
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2020-03-03 02:56:30 +03:00
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if (entry && cpuid_entry_has(entry, X86_FEATURE_NX) && !is_efer_nx()) {
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2020-03-03 02:56:31 +03:00
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cpuid_entry_clear(entry, X86_FEATURE_NX);
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2011-11-23 18:30:32 +04:00
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printk(KERN_INFO "kvm: guest NX capability removed\n");
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}
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}
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2015-03-29 23:56:12 +03:00
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int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu)
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{
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struct kvm_cpuid_entry2 *best;
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best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
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if (!best || best->eax < 0x80000008)
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goto not_found;
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best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
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if (best)
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return best->eax & 0xff;
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not_found:
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return 36;
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}
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2011-11-23 18:30:32 +04:00
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/* when an old userspace process fills a new kernel module */
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int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
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struct kvm_cpuid *cpuid,
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struct kvm_cpuid_entry __user *entries)
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{
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int r, i;
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2020-10-01 16:05:40 +03:00
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struct kvm_cpuid_entry *e = NULL;
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struct kvm_cpuid_entry2 *e2 = NULL;
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2011-11-23 18:30:32 +04:00
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if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
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2020-10-01 16:05:40 +03:00
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return -E2BIG;
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2016-06-01 15:09:19 +03:00
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if (cpuid->nent) {
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2020-10-01 16:05:40 +03:00
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e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent));
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if (IS_ERR(e))
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return PTR_ERR(e);
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e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT);
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if (!e2) {
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r = -ENOMEM;
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goto out_free_cpuid;
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2020-06-03 13:11:31 +03:00
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}
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2016-06-01 15:09:19 +03:00
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}
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2011-11-23 18:30:32 +04:00
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for (i = 0; i < cpuid->nent; i++) {
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2020-10-01 16:05:40 +03:00
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e2[i].function = e[i].function;
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e2[i].eax = e[i].eax;
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e2[i].ebx = e[i].ebx;
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e2[i].ecx = e[i].ecx;
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e2[i].edx = e[i].edx;
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e2[i].index = 0;
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e2[i].flags = 0;
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e2[i].padding[0] = 0;
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e2[i].padding[1] = 0;
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e2[i].padding[2] = 0;
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2011-11-23 18:30:32 +04:00
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}
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2020-10-01 16:05:40 +03:00
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r = kvm_check_cpuid(e2, cpuid->nent);
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2020-07-09 07:34:22 +03:00
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if (r) {
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2020-10-01 16:05:40 +03:00
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kvfree(e2);
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goto out_free_cpuid;
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2020-07-09 07:34:22 +03:00
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}
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2020-10-01 16:05:40 +03:00
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kvfree(vcpu->arch.cpuid_entries);
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vcpu->arch.cpuid_entries = e2;
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vcpu->arch.cpuid_nent = cpuid->nent;
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2011-11-23 18:30:32 +04:00
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cpuid_fix_nx_cap(vcpu);
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2020-07-09 07:34:23 +03:00
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kvm_update_cpuid_runtime(vcpu);
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2020-07-09 07:34:24 +03:00
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kvm_vcpu_after_set_cpuid(vcpu);
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2011-11-23 18:30:32 +04:00
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2020-10-01 16:05:40 +03:00
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out_free_cpuid:
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kvfree(e);
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|
|
2011-11-23 18:30:32 +04:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
|
|
|
|
struct kvm_cpuid2 *cpuid,
|
|
|
|
struct kvm_cpuid_entry2 __user *entries)
|
|
|
|
{
|
2020-10-01 16:05:40 +03:00
|
|
|
struct kvm_cpuid_entry2 *e2 = NULL;
|
2011-11-23 18:30:32 +04:00
|
|
|
int r;
|
|
|
|
|
|
|
|
if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
|
2020-10-01 16:05:40 +03:00
|
|
|
return -E2BIG;
|
|
|
|
|
|
|
|
if (cpuid->nent) {
|
|
|
|
e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent));
|
|
|
|
if (IS_ERR(e2))
|
|
|
|
return PTR_ERR(e2);
|
|
|
|
}
|
|
|
|
|
|
|
|
r = kvm_check_cpuid(e2, cpuid->nent);
|
2020-07-09 07:34:22 +03:00
|
|
|
if (r) {
|
2020-10-01 16:05:40 +03:00
|
|
|
kvfree(e2);
|
|
|
|
return r;
|
2020-07-09 07:34:22 +03:00
|
|
|
}
|
|
|
|
|
2020-10-01 16:05:40 +03:00
|
|
|
kvfree(vcpu->arch.cpuid_entries);
|
|
|
|
vcpu->arch.cpuid_entries = e2;
|
|
|
|
vcpu->arch.cpuid_nent = cpuid->nent;
|
|
|
|
|
2020-07-09 07:34:23 +03:00
|
|
|
kvm_update_cpuid_runtime(vcpu);
|
2020-07-09 07:34:24 +03:00
|
|
|
kvm_vcpu_after_set_cpuid(vcpu);
|
2020-10-01 16:05:40 +03:00
|
|
|
|
|
|
|
return 0;
|
2011-11-23 18:30:32 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
|
|
|
|
struct kvm_cpuid2 *cpuid,
|
|
|
|
struct kvm_cpuid_entry2 __user *entries)
|
|
|
|
{
|
|
|
|
int r;
|
|
|
|
|
|
|
|
r = -E2BIG;
|
|
|
|
if (cpuid->nent < vcpu->arch.cpuid_nent)
|
|
|
|
goto out;
|
|
|
|
r = -EFAULT;
|
|
|
|
if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
|
|
|
|
vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
|
|
|
|
goto out;
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
out:
|
|
|
|
cpuid->nent = vcpu->arch.cpuid_nent;
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
KVM: x86: Introduce kvm_cpu_caps to replace runtime CPUID masking
Calculate the CPUID masks for KVM_GET_SUPPORTED_CPUID at load time using
what is effectively a KVM-adjusted copy of boot_cpu_data, or more
precisely, the x86_capability array in boot_cpu_data.
In terms of KVM support, the vast majority of CPUID feature bits are
constant, and *all* feature support is known at KVM load time. Rather
than apply boot_cpu_data, which is effectively read-only after init,
at runtime, copy it into a KVM-specific array and use *that* to mask
CPUID registers.
In additional to consolidating the masking, kvm_cpu_caps can be adjusted
by SVM/VMX at load time and thus eliminate all feature bit manipulation
in ->set_supported_cpuid().
Opportunistically clean up a few warts:
- Replace bare "unsigned" with "unsigned int" when a feature flag is
captured in a local variable, e.g. f_nx.
- Sort the CPUID masks by function, index and register (alphabetically
for registers, i.e. EBX comes before ECX/EDX).
- Remove the superfluous /* cpuid 7.0.ecx */ comments.
No functional change intended.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
[Call kvm_set_cpu_caps from kvm_x86_ops->hardware_setup due to fixed
GBPAGES patch. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-03 02:56:41 +03:00
|
|
|
static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask)
|
|
|
|
{
|
2020-03-03 02:56:52 +03:00
|
|
|
const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32);
|
|
|
|
struct kvm_cpuid_entry2 entry;
|
|
|
|
|
KVM: x86: Introduce kvm_cpu_caps to replace runtime CPUID masking
Calculate the CPUID masks for KVM_GET_SUPPORTED_CPUID at load time using
what is effectively a KVM-adjusted copy of boot_cpu_data, or more
precisely, the x86_capability array in boot_cpu_data.
In terms of KVM support, the vast majority of CPUID feature bits are
constant, and *all* feature support is known at KVM load time. Rather
than apply boot_cpu_data, which is effectively read-only after init,
at runtime, copy it into a KVM-specific array and use *that* to mask
CPUID registers.
In additional to consolidating the masking, kvm_cpu_caps can be adjusted
by SVM/VMX at load time and thus eliminate all feature bit manipulation
in ->set_supported_cpuid().
Opportunistically clean up a few warts:
- Replace bare "unsigned" with "unsigned int" when a feature flag is
captured in a local variable, e.g. f_nx.
- Sort the CPUID masks by function, index and register (alphabetically
for registers, i.e. EBX comes before ECX/EDX).
- Remove the superfluous /* cpuid 7.0.ecx */ comments.
No functional change intended.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
[Call kvm_set_cpu_caps from kvm_x86_ops->hardware_setup due to fixed
GBPAGES patch. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-03 02:56:41 +03:00
|
|
|
reverse_cpuid_check(leaf);
|
|
|
|
kvm_cpu_caps[leaf] &= mask;
|
2020-03-03 02:56:52 +03:00
|
|
|
|
|
|
|
cpuid_count(cpuid.function, cpuid.index,
|
|
|
|
&entry.eax, &entry.ebx, &entry.ecx, &entry.edx);
|
|
|
|
|
2020-03-25 22:12:59 +03:00
|
|
|
kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg);
|
KVM: x86: Introduce kvm_cpu_caps to replace runtime CPUID masking
Calculate the CPUID masks for KVM_GET_SUPPORTED_CPUID at load time using
what is effectively a KVM-adjusted copy of boot_cpu_data, or more
precisely, the x86_capability array in boot_cpu_data.
In terms of KVM support, the vast majority of CPUID feature bits are
constant, and *all* feature support is known at KVM load time. Rather
than apply boot_cpu_data, which is effectively read-only after init,
at runtime, copy it into a KVM-specific array and use *that* to mask
CPUID registers.
In additional to consolidating the masking, kvm_cpu_caps can be adjusted
by SVM/VMX at load time and thus eliminate all feature bit manipulation
in ->set_supported_cpuid().
Opportunistically clean up a few warts:
- Replace bare "unsigned" with "unsigned int" when a feature flag is
captured in a local variable, e.g. f_nx.
- Sort the CPUID masks by function, index and register (alphabetically
for registers, i.e. EBX comes before ECX/EDX).
- Remove the superfluous /* cpuid 7.0.ecx */ comments.
No functional change intended.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
[Call kvm_set_cpu_caps from kvm_x86_ops->hardware_setup due to fixed
GBPAGES patch. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-03 02:56:41 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void kvm_set_cpu_caps(void)
|
|
|
|
{
|
|
|
|
unsigned int f_nx = is_efer_nx() ? F(NX) : 0;
|
|
|
|
#ifdef CONFIG_X86_64
|
|
|
|
unsigned int f_gbpages = F(GBPAGES);
|
|
|
|
unsigned int f_lm = F(LM);
|
|
|
|
#else
|
|
|
|
unsigned int f_gbpages = 0;
|
|
|
|
unsigned int f_lm = 0;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
BUILD_BUG_ON(sizeof(kvm_cpu_caps) >
|
|
|
|
sizeof(boot_cpu_data.x86_capability));
|
|
|
|
|
|
|
|
memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability,
|
|
|
|
sizeof(kvm_cpu_caps));
|
|
|
|
|
|
|
|
kvm_cpu_cap_mask(CPUID_1_ECX,
|
|
|
|
/*
|
|
|
|
* NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not*
|
|
|
|
* advertised to guests via CPUID!
|
|
|
|
*/
|
|
|
|
F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
|
|
|
|
0 /* DS-CPL, VMX, SMX, EST */ |
|
|
|
|
0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
|
2020-05-29 10:43:45 +03:00
|
|
|
F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) |
|
KVM: x86: Introduce kvm_cpu_caps to replace runtime CPUID masking
Calculate the CPUID masks for KVM_GET_SUPPORTED_CPUID at load time using
what is effectively a KVM-adjusted copy of boot_cpu_data, or more
precisely, the x86_capability array in boot_cpu_data.
In terms of KVM support, the vast majority of CPUID feature bits are
constant, and *all* feature support is known at KVM load time. Rather
than apply boot_cpu_data, which is effectively read-only after init,
at runtime, copy it into a KVM-specific array and use *that* to mask
CPUID registers.
In additional to consolidating the masking, kvm_cpu_caps can be adjusted
by SVM/VMX at load time and thus eliminate all feature bit manipulation
in ->set_supported_cpuid().
Opportunistically clean up a few warts:
- Replace bare "unsigned" with "unsigned int" when a feature flag is
captured in a local variable, e.g. f_nx.
- Sort the CPUID masks by function, index and register (alphabetically
for registers, i.e. EBX comes before ECX/EDX).
- Remove the superfluous /* cpuid 7.0.ecx */ comments.
No functional change intended.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
[Call kvm_set_cpu_caps from kvm_x86_ops->hardware_setup due to fixed
GBPAGES patch. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-03 02:56:41 +03:00
|
|
|
F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) |
|
|
|
|
F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
|
|
|
|
0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
|
|
|
|
F(F16C) | F(RDRAND)
|
|
|
|
);
|
2020-03-03 02:56:54 +03:00
|
|
|
/* KVM emulates x2apic in software irrespective of host support. */
|
|
|
|
kvm_cpu_cap_set(X86_FEATURE_X2APIC);
|
KVM: x86: Introduce kvm_cpu_caps to replace runtime CPUID masking
Calculate the CPUID masks for KVM_GET_SUPPORTED_CPUID at load time using
what is effectively a KVM-adjusted copy of boot_cpu_data, or more
precisely, the x86_capability array in boot_cpu_data.
In terms of KVM support, the vast majority of CPUID feature bits are
constant, and *all* feature support is known at KVM load time. Rather
than apply boot_cpu_data, which is effectively read-only after init,
at runtime, copy it into a KVM-specific array and use *that* to mask
CPUID registers.
In additional to consolidating the masking, kvm_cpu_caps can be adjusted
by SVM/VMX at load time and thus eliminate all feature bit manipulation
in ->set_supported_cpuid().
Opportunistically clean up a few warts:
- Replace bare "unsigned" with "unsigned int" when a feature flag is
captured in a local variable, e.g. f_nx.
- Sort the CPUID masks by function, index and register (alphabetically
for registers, i.e. EBX comes before ECX/EDX).
- Remove the superfluous /* cpuid 7.0.ecx */ comments.
No functional change intended.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
[Call kvm_set_cpu_caps from kvm_x86_ops->hardware_setup due to fixed
GBPAGES patch. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-03 02:56:41 +03:00
|
|
|
|
|
|
|
kvm_cpu_cap_mask(CPUID_1_EDX,
|
|
|
|
F(FPU) | F(VME) | F(DE) | F(PSE) |
|
|
|
|
F(TSC) | F(MSR) | F(PAE) | F(MCE) |
|
|
|
|
F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
|
|
|
|
F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
|
|
|
|
F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) |
|
|
|
|
0 /* Reserved, DS, ACPI */ | F(MMX) |
|
|
|
|
F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
|
|
|
|
0 /* HTT, TM, Reserved, PBE */
|
|
|
|
);
|
|
|
|
|
|
|
|
kvm_cpu_cap_mask(CPUID_7_0_EBX,
|
|
|
|
F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) |
|
|
|
|
F(BMI2) | F(ERMS) | 0 /*INVPCID*/ | F(RTM) | 0 /*MPX*/ | F(RDSEED) |
|
|
|
|
F(ADX) | F(SMAP) | F(AVX512IFMA) | F(AVX512F) | F(AVX512PF) |
|
|
|
|
F(AVX512ER) | F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(AVX512DQ) |
|
|
|
|
F(SHA_NI) | F(AVX512BW) | F(AVX512VL) | 0 /*INTEL_PT*/
|
|
|
|
);
|
|
|
|
|
|
|
|
kvm_cpu_cap_mask(CPUID_7_ECX,
|
2020-05-13 02:59:16 +03:00
|
|
|
F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) |
|
KVM: x86: Introduce kvm_cpu_caps to replace runtime CPUID masking
Calculate the CPUID masks for KVM_GET_SUPPORTED_CPUID at load time using
what is effectively a KVM-adjusted copy of boot_cpu_data, or more
precisely, the x86_capability array in boot_cpu_data.
In terms of KVM support, the vast majority of CPUID feature bits are
constant, and *all* feature support is known at KVM load time. Rather
than apply boot_cpu_data, which is effectively read-only after init,
at runtime, copy it into a KVM-specific array and use *that* to mask
CPUID registers.
In additional to consolidating the masking, kvm_cpu_caps can be adjusted
by SVM/VMX at load time and thus eliminate all feature bit manipulation
in ->set_supported_cpuid().
Opportunistically clean up a few warts:
- Replace bare "unsigned" with "unsigned int" when a feature flag is
captured in a local variable, e.g. f_nx.
- Sort the CPUID masks by function, index and register (alphabetically
for registers, i.e. EBX comes before ECX/EDX).
- Remove the superfluous /* cpuid 7.0.ecx */ comments.
No functional change intended.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
[Call kvm_set_cpu_caps from kvm_x86_ops->hardware_setup due to fixed
GBPAGES patch. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-03 02:56:41 +03:00
|
|
|
F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) |
|
|
|
|
F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) |
|
|
|
|
F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/
|
|
|
|
);
|
|
|
|
/* Set LA57 based on hardware capability. */
|
|
|
|
if (cpuid_ecx(7) & F(LA57))
|
|
|
|
kvm_cpu_cap_set(X86_FEATURE_LA57);
|
|
|
|
|
2020-05-13 02:59:16 +03:00
|
|
|
/*
|
|
|
|
* PKU not yet implemented for shadow paging and requires OSPKE
|
|
|
|
* to be set on the host. Clear it if that is not the case
|
|
|
|
*/
|
|
|
|
if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE))
|
|
|
|
kvm_cpu_cap_clear(X86_FEATURE_PKU);
|
|
|
|
|
KVM: x86: Introduce kvm_cpu_caps to replace runtime CPUID masking
Calculate the CPUID masks for KVM_GET_SUPPORTED_CPUID at load time using
what is effectively a KVM-adjusted copy of boot_cpu_data, or more
precisely, the x86_capability array in boot_cpu_data.
In terms of KVM support, the vast majority of CPUID feature bits are
constant, and *all* feature support is known at KVM load time. Rather
than apply boot_cpu_data, which is effectively read-only after init,
at runtime, copy it into a KVM-specific array and use *that* to mask
CPUID registers.
In additional to consolidating the masking, kvm_cpu_caps can be adjusted
by SVM/VMX at load time and thus eliminate all feature bit manipulation
in ->set_supported_cpuid().
Opportunistically clean up a few warts:
- Replace bare "unsigned" with "unsigned int" when a feature flag is
captured in a local variable, e.g. f_nx.
- Sort the CPUID masks by function, index and register (alphabetically
for registers, i.e. EBX comes before ECX/EDX).
- Remove the superfluous /* cpuid 7.0.ecx */ comments.
No functional change intended.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
[Call kvm_set_cpu_caps from kvm_x86_ops->hardware_setup due to fixed
GBPAGES patch. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-03 02:56:41 +03:00
|
|
|
kvm_cpu_cap_mask(CPUID_7_EDX,
|
|
|
|
F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
|
|
|
|
F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
|
2020-08-09 20:04:56 +03:00
|
|
|
F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
|
2020-08-25 03:47:58 +03:00
|
|
|
F(SERIALIZE) | F(TSXLDTRK)
|
KVM: x86: Introduce kvm_cpu_caps to replace runtime CPUID masking
Calculate the CPUID masks for KVM_GET_SUPPORTED_CPUID at load time using
what is effectively a KVM-adjusted copy of boot_cpu_data, or more
precisely, the x86_capability array in boot_cpu_data.
In terms of KVM support, the vast majority of CPUID feature bits are
constant, and *all* feature support is known at KVM load time. Rather
than apply boot_cpu_data, which is effectively read-only after init,
at runtime, copy it into a KVM-specific array and use *that* to mask
CPUID registers.
In additional to consolidating the masking, kvm_cpu_caps can be adjusted
by SVM/VMX at load time and thus eliminate all feature bit manipulation
in ->set_supported_cpuid().
Opportunistically clean up a few warts:
- Replace bare "unsigned" with "unsigned int" when a feature flag is
captured in a local variable, e.g. f_nx.
- Sort the CPUID masks by function, index and register (alphabetically
for registers, i.e. EBX comes before ECX/EDX).
- Remove the superfluous /* cpuid 7.0.ecx */ comments.
No functional change intended.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
[Call kvm_set_cpu_caps from kvm_x86_ops->hardware_setup due to fixed
GBPAGES patch. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-03 02:56:41 +03:00
|
|
|
);
|
|
|
|
|
2020-03-03 02:56:54 +03:00
|
|
|
/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
|
|
|
|
kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST);
|
|
|
|
kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES);
|
|
|
|
|
|
|
|
if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS))
|
|
|
|
kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL);
|
|
|
|
if (boot_cpu_has(X86_FEATURE_STIBP))
|
|
|
|
kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP);
|
|
|
|
if (boot_cpu_has(X86_FEATURE_AMD_SSBD))
|
|
|
|
kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
|
|
|
|
|
KVM: x86: Introduce kvm_cpu_caps to replace runtime CPUID masking
Calculate the CPUID masks for KVM_GET_SUPPORTED_CPUID at load time using
what is effectively a KVM-adjusted copy of boot_cpu_data, or more
precisely, the x86_capability array in boot_cpu_data.
In terms of KVM support, the vast majority of CPUID feature bits are
constant, and *all* feature support is known at KVM load time. Rather
than apply boot_cpu_data, which is effectively read-only after init,
at runtime, copy it into a KVM-specific array and use *that* to mask
CPUID registers.
In additional to consolidating the masking, kvm_cpu_caps can be adjusted
by SVM/VMX at load time and thus eliminate all feature bit manipulation
in ->set_supported_cpuid().
Opportunistically clean up a few warts:
- Replace bare "unsigned" with "unsigned int" when a feature flag is
captured in a local variable, e.g. f_nx.
- Sort the CPUID masks by function, index and register (alphabetically
for registers, i.e. EBX comes before ECX/EDX).
- Remove the superfluous /* cpuid 7.0.ecx */ comments.
No functional change intended.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
[Call kvm_set_cpu_caps from kvm_x86_ops->hardware_setup due to fixed
GBPAGES patch. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-03 02:56:41 +03:00
|
|
|
kvm_cpu_cap_mask(CPUID_7_1_EAX,
|
|
|
|
F(AVX512_BF16)
|
|
|
|
);
|
|
|
|
|
|
|
|
kvm_cpu_cap_mask(CPUID_D_1_EAX,
|
|
|
|
F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES)
|
|
|
|
);
|
|
|
|
|
|
|
|
kvm_cpu_cap_mask(CPUID_8000_0001_ECX,
|
|
|
|
F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
|
|
|
|
F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
|
|
|
|
F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) |
|
|
|
|
0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) |
|
|
|
|
F(TOPOEXT) | F(PERFCTR_CORE)
|
|
|
|
);
|
|
|
|
|
|
|
|
kvm_cpu_cap_mask(CPUID_8000_0001_EDX,
|
|
|
|
F(FPU) | F(VME) | F(DE) | F(PSE) |
|
|
|
|
F(TSC) | F(MSR) | F(PAE) | F(MCE) |
|
|
|
|
F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
|
|
|
|
F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
|
|
|
|
F(PAT) | F(PSE36) | 0 /* Reserved */ |
|
|
|
|
f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
|
|
|
|
F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) |
|
|
|
|
0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW)
|
|
|
|
);
|
|
|
|
|
|
|
|
if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64))
|
|
|
|
kvm_cpu_cap_set(X86_FEATURE_GBPAGES);
|
|
|
|
|
|
|
|
kvm_cpu_cap_mask(CPUID_8000_0008_EBX,
|
|
|
|
F(CLZERO) | F(XSAVEERPTR) |
|
|
|
|
F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
|
|
|
|
F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON)
|
|
|
|
);
|
|
|
|
|
2020-03-03 02:56:54 +03:00
|
|
|
/*
|
|
|
|
* AMD has separate bits for each SPEC_CTRL bit.
|
|
|
|
* arch/x86/kernel/cpu/bugs.c is kind enough to
|
|
|
|
* record that in cpufeatures so use them.
|
|
|
|
*/
|
|
|
|
if (boot_cpu_has(X86_FEATURE_IBPB))
|
|
|
|
kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB);
|
|
|
|
if (boot_cpu_has(X86_FEATURE_IBRS))
|
|
|
|
kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS);
|
|
|
|
if (boot_cpu_has(X86_FEATURE_STIBP))
|
|
|
|
kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP);
|
|
|
|
if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
|
|
|
|
kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD);
|
|
|
|
if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
|
|
|
|
kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO);
|
|
|
|
/*
|
|
|
|
* The preference is to use SPEC CTRL MSR instead of the
|
|
|
|
* VIRT_SPEC MSR.
|
|
|
|
*/
|
|
|
|
if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
|
|
|
|
!boot_cpu_has(X86_FEATURE_AMD_SSBD))
|
|
|
|
kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
|
|
|
|
|
2020-03-03 02:56:42 +03:00
|
|
|
/*
|
|
|
|
* Hide all SVM features by default, SVM will set the cap bits for
|
|
|
|
* features it emulates and/or exposes for L1.
|
|
|
|
*/
|
|
|
|
kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0);
|
|
|
|
|
KVM: x86: Introduce kvm_cpu_caps to replace runtime CPUID masking
Calculate the CPUID masks for KVM_GET_SUPPORTED_CPUID at load time using
what is effectively a KVM-adjusted copy of boot_cpu_data, or more
precisely, the x86_capability array in boot_cpu_data.
In terms of KVM support, the vast majority of CPUID feature bits are
constant, and *all* feature support is known at KVM load time. Rather
than apply boot_cpu_data, which is effectively read-only after init,
at runtime, copy it into a KVM-specific array and use *that* to mask
CPUID registers.
In additional to consolidating the masking, kvm_cpu_caps can be adjusted
by SVM/VMX at load time and thus eliminate all feature bit manipulation
in ->set_supported_cpuid().
Opportunistically clean up a few warts:
- Replace bare "unsigned" with "unsigned int" when a feature flag is
captured in a local variable, e.g. f_nx.
- Sort the CPUID masks by function, index and register (alphabetically
for registers, i.e. EBX comes before ECX/EDX).
- Remove the superfluous /* cpuid 7.0.ecx */ comments.
No functional change intended.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
[Call kvm_set_cpu_caps from kvm_x86_ops->hardware_setup due to fixed
GBPAGES patch. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-03 02:56:41 +03:00
|
|
|
kvm_cpu_cap_mask(CPUID_C000_0001_EDX,
|
|
|
|
F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
|
|
|
|
F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
|
|
|
|
F(PMM) | F(PMM_EN)
|
|
|
|
);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(kvm_set_cpu_caps);
|
|
|
|
|
2020-03-03 02:56:19 +03:00
|
|
|
struct kvm_cpuid_array {
|
|
|
|
struct kvm_cpuid_entry2 *entries;
|
2020-06-04 07:16:36 +03:00
|
|
|
int maxnent;
|
2020-03-03 02:56:19 +03:00
|
|
|
int nent;
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array,
|
2020-03-03 02:56:16 +03:00
|
|
|
u32 function, u32 index)
|
2011-11-23 18:30:32 +04:00
|
|
|
{
|
2020-03-03 02:56:19 +03:00
|
|
|
struct kvm_cpuid_entry2 *entry;
|
|
|
|
|
|
|
|
if (array->nent >= array->maxnent)
|
2020-03-03 02:56:16 +03:00
|
|
|
return NULL;
|
2020-03-03 02:56:19 +03:00
|
|
|
|
|
|
|
entry = &array->entries[array->nent++];
|
2020-03-03 02:56:16 +03:00
|
|
|
|
2011-11-23 18:30:32 +04:00
|
|
|
entry->function = function;
|
|
|
|
entry->index = index;
|
2019-06-24 11:23:33 +03:00
|
|
|
entry->flags = 0;
|
|
|
|
|
2011-11-23 18:30:32 +04:00
|
|
|
cpuid_count(entry->function, entry->index,
|
|
|
|
&entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
|
2019-07-04 13:20:48 +03:00
|
|
|
|
|
|
|
switch (function) {
|
|
|
|
case 4:
|
|
|
|
case 7:
|
|
|
|
case 0xb:
|
|
|
|
case 0xd:
|
2019-09-12 19:55:03 +03:00
|
|
|
case 0xf:
|
|
|
|
case 0x10:
|
|
|
|
case 0x12:
|
2019-07-04 13:20:48 +03:00
|
|
|
case 0x14:
|
2019-09-12 19:55:03 +03:00
|
|
|
case 0x17:
|
|
|
|
case 0x18:
|
|
|
|
case 0x1f:
|
2019-07-04 13:20:48 +03:00
|
|
|
case 0x8000001d:
|
|
|
|
entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
|
|
|
|
break;
|
|
|
|
}
|
2020-03-03 02:56:16 +03:00
|
|
|
|
|
|
|
return entry;
|
2011-11-23 18:30:32 +04:00
|
|
|
}
|
|
|
|
|
2020-03-03 02:56:19 +03:00
|
|
|
static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func)
|
2013-09-22 18:44:50 +04:00
|
|
|
{
|
2020-03-03 02:56:56 +03:00
|
|
|
struct kvm_cpuid_entry2 *entry;
|
|
|
|
|
|
|
|
if (array->nent >= array->maxnent)
|
|
|
|
return -E2BIG;
|
2020-03-03 02:56:19 +03:00
|
|
|
|
2020-03-03 02:56:56 +03:00
|
|
|
entry = &array->entries[array->nent];
|
2019-06-24 11:23:33 +03:00
|
|
|
entry->function = func;
|
|
|
|
entry->index = 0;
|
|
|
|
entry->flags = 0;
|
|
|
|
|
2013-10-29 15:54:56 +04:00
|
|
|
switch (func) {
|
|
|
|
case 0:
|
2016-07-12 12:04:26 +03:00
|
|
|
entry->eax = 7;
|
2020-03-03 02:56:19 +03:00
|
|
|
++array->nent;
|
2013-10-29 15:54:56 +04:00
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
entry->ecx = F(MOVBE);
|
2020-03-03 02:56:19 +03:00
|
|
|
++array->nent;
|
2013-10-29 15:54:56 +04:00
|
|
|
break;
|
2016-07-12 12:04:26 +03:00
|
|
|
case 7:
|
|
|
|
entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
|
2019-06-24 11:23:33 +03:00
|
|
|
entry->eax = 0;
|
|
|
|
entry->ecx = F(RDPID);
|
2020-03-03 02:56:19 +03:00
|
|
|
++array->nent;
|
2013-10-29 15:54:56 +04:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2013-09-22 18:44:50 +04:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-03-03 02:56:19 +03:00
|
|
|
static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
|
2011-11-23 18:30:32 +04:00
|
|
|
{
|
2020-03-03 02:56:19 +03:00
|
|
|
struct kvm_cpuid_entry2 *entry;
|
2020-03-03 02:56:17 +03:00
|
|
|
int r, i, max_idx;
|
2011-11-23 18:30:32 +04:00
|
|
|
|
|
|
|
/* all calls to cpuid_count() should be made on the same cpu */
|
|
|
|
get_cpu();
|
2011-11-28 13:20:29 +04:00
|
|
|
|
|
|
|
r = -E2BIG;
|
|
|
|
|
2020-03-03 02:56:19 +03:00
|
|
|
entry = do_host_cpuid(array, function, 0);
|
2020-03-03 02:56:56 +03:00
|
|
|
if (!entry)
|
2011-11-28 13:20:29 +04:00
|
|
|
goto out;
|
|
|
|
|
2011-11-23 18:30:32 +04:00
|
|
|
switch (function) {
|
|
|
|
case 0:
|
2019-06-06 04:18:45 +03:00
|
|
|
/* Limited to the highest leaf implemented in KVM. */
|
|
|
|
entry->eax = min(entry->eax, 0x1fU);
|
2011-11-23 18:30:32 +04:00
|
|
|
break;
|
|
|
|
case 1:
|
2020-03-03 02:56:53 +03:00
|
|
|
cpuid_entry_override(entry, CPUID_1_EDX);
|
|
|
|
cpuid_entry_override(entry, CPUID_1_ECX);
|
2011-11-23 18:30:32 +04:00
|
|
|
break;
|
2020-03-03 02:56:17 +03:00
|
|
|
case 2:
|
KVM: x86: Squash CPUID 0x2.0 insanity for modern CPUs
Rework CPUID 0x2.0 to be a normal CPUID leaf if it returns "01" in AL,
i.e. EAX & 0xff, as a step towards removing KVM's stateful CPUID code
altogether.
Long ago, Intel documented CPUID 0x2.0 as being a stateful leaf, e.g. a
version of the SDM circa 1995 states:
The least-significant byte in register EAX (register AL) indicates the
number of times the CPUID instruction must be executed with an input
value of 2 to get a complete description of the processors's caches
and TLBs. The Pentium Pro family of processors will return a 1.
A 2000 version of the SDM only updated the paragraph to reference
Intel's new processory family:
The first member of the family of Pentium 4 processors will return a 1.
Fast forward to the present, and Intel's SDM now states:
The least-significant byte in register EAX (register AL) will always
return 01H. Software should ignore this value and not interpret it as
an information descriptor.
AMD's APM simply states that CPUID 0x2 is reserved.
Given that CPUID itself was introduced in the Pentium, odds are good
that the only Intel CPU family that *maybe* implemented a stateful CPUID
was the P5. Which obviously did not support VMX, or KVM.
In other words, KVM's emulation of a stateful CPUID 0x2.0 has likely
been dead code from the day it was introduced. This is backed up by
commit 0fdf8e59faa5c ("KVM: Fix cpuid iteration on multiple leaves per
eac"), which shows that the stateful iteration code was completely
broken when it was introduced by commit 0771671749b59 ("KVM: Enhance
guest cpuid management"), i.e. not actually tested.
Annotate all stateful code paths as "unlikely", but defer its removal to
a future patch to simplify reinstating the code if by some miracle there
is someone running KVM on a CPU with a stateful CPUID 0x2.
Reviewed-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-03 02:56:50 +03:00
|
|
|
/*
|
|
|
|
* On ancient CPUs, function 2 entries are STATEFUL. That is,
|
|
|
|
* CPUID(function=2, index=0) may return different results each
|
|
|
|
* time, with the least-significant byte in EAX enumerating the
|
|
|
|
* number of times software should do CPUID(2, 0).
|
|
|
|
*
|
2020-03-03 02:56:51 +03:00
|
|
|
* Modern CPUs, i.e. every CPU KVM has *ever* run on are less
|
|
|
|
* idiotic. Intel's SDM states that EAX & 0xff "will always
|
|
|
|
* return 01H. Software should ignore this value and not
|
KVM: x86: Squash CPUID 0x2.0 insanity for modern CPUs
Rework CPUID 0x2.0 to be a normal CPUID leaf if it returns "01" in AL,
i.e. EAX & 0xff, as a step towards removing KVM's stateful CPUID code
altogether.
Long ago, Intel documented CPUID 0x2.0 as being a stateful leaf, e.g. a
version of the SDM circa 1995 states:
The least-significant byte in register EAX (register AL) indicates the
number of times the CPUID instruction must be executed with an input
value of 2 to get a complete description of the processors's caches
and TLBs. The Pentium Pro family of processors will return a 1.
A 2000 version of the SDM only updated the paragraph to reference
Intel's new processory family:
The first member of the family of Pentium 4 processors will return a 1.
Fast forward to the present, and Intel's SDM now states:
The least-significant byte in register EAX (register AL) will always
return 01H. Software should ignore this value and not interpret it as
an information descriptor.
AMD's APM simply states that CPUID 0x2 is reserved.
Given that CPUID itself was introduced in the Pentium, odds are good
that the only Intel CPU family that *maybe* implemented a stateful CPUID
was the P5. Which obviously did not support VMX, or KVM.
In other words, KVM's emulation of a stateful CPUID 0x2.0 has likely
been dead code from the day it was introduced. This is backed up by
commit 0fdf8e59faa5c ("KVM: Fix cpuid iteration on multiple leaves per
eac"), which shows that the stateful iteration code was completely
broken when it was introduced by commit 0771671749b59 ("KVM: Enhance
guest cpuid management"), i.e. not actually tested.
Annotate all stateful code paths as "unlikely", but defer its removal to
a future patch to simplify reinstating the code if by some miracle there
is someone running KVM on a CPU with a stateful CPUID 0x2.
Reviewed-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-03 02:56:50 +03:00
|
|
|
* interpret it as an informational descriptor", while AMD's
|
|
|
|
* APM states that CPUID(2) is reserved.
|
2020-03-03 02:56:51 +03:00
|
|
|
*
|
|
|
|
* WARN if a frankenstein CPU that supports virtualization and
|
|
|
|
* a stateful CPUID.0x2 is encountered.
|
KVM: x86: Squash CPUID 0x2.0 insanity for modern CPUs
Rework CPUID 0x2.0 to be a normal CPUID leaf if it returns "01" in AL,
i.e. EAX & 0xff, as a step towards removing KVM's stateful CPUID code
altogether.
Long ago, Intel documented CPUID 0x2.0 as being a stateful leaf, e.g. a
version of the SDM circa 1995 states:
The least-significant byte in register EAX (register AL) indicates the
number of times the CPUID instruction must be executed with an input
value of 2 to get a complete description of the processors's caches
and TLBs. The Pentium Pro family of processors will return a 1.
A 2000 version of the SDM only updated the paragraph to reference
Intel's new processory family:
The first member of the family of Pentium 4 processors will return a 1.
Fast forward to the present, and Intel's SDM now states:
The least-significant byte in register EAX (register AL) will always
return 01H. Software should ignore this value and not interpret it as
an information descriptor.
AMD's APM simply states that CPUID 0x2 is reserved.
Given that CPUID itself was introduced in the Pentium, odds are good
that the only Intel CPU family that *maybe* implemented a stateful CPUID
was the P5. Which obviously did not support VMX, or KVM.
In other words, KVM's emulation of a stateful CPUID 0x2.0 has likely
been dead code from the day it was introduced. This is backed up by
commit 0fdf8e59faa5c ("KVM: Fix cpuid iteration on multiple leaves per
eac"), which shows that the stateful iteration code was completely
broken when it was introduced by commit 0771671749b59 ("KVM: Enhance
guest cpuid management"), i.e. not actually tested.
Annotate all stateful code paths as "unlikely", but defer its removal to
a future patch to simplify reinstating the code if by some miracle there
is someone running KVM on a CPU with a stateful CPUID 0x2.
Reviewed-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-03 02:56:50 +03:00
|
|
|
*/
|
2020-03-03 02:56:51 +03:00
|
|
|
WARN_ON_ONCE((entry->eax & 0xff) > 1);
|
2011-11-23 18:30:32 +04:00
|
|
|
break;
|
2019-03-27 23:15:36 +03:00
|
|
|
/* functions 4 and 0x8000001d have additional index. */
|
|
|
|
case 4:
|
2020-03-03 02:56:18 +03:00
|
|
|
case 0x8000001d:
|
|
|
|
/*
|
|
|
|
* Read entries until the cache type in the previous entry is
|
|
|
|
* zero, i.e. indicates an invalid entry.
|
|
|
|
*/
|
2020-03-03 02:56:19 +03:00
|
|
|
for (i = 1; entry->eax & 0x1f; ++i) {
|
|
|
|
entry = do_host_cpuid(array, function, i);
|
|
|
|
if (!entry)
|
2020-03-03 02:56:08 +03:00
|
|
|
goto out;
|
2011-11-23 18:30:32 +04:00
|
|
|
}
|
|
|
|
break;
|
2015-05-24 18:22:38 +03:00
|
|
|
case 6: /* Thermal management */
|
|
|
|
entry->eax = 0x4; /* allow ARAT */
|
|
|
|
entry->ebx = 0;
|
|
|
|
entry->ecx = 0;
|
|
|
|
entry->edx = 0;
|
|
|
|
break;
|
2019-07-04 13:18:13 +03:00
|
|
|
/* function 7 has additional index. */
|
2020-03-03 02:56:17 +03:00
|
|
|
case 7:
|
2020-03-03 02:56:48 +03:00
|
|
|
entry->eax = min(entry->eax, 1u);
|
2020-03-03 02:56:53 +03:00
|
|
|
cpuid_entry_override(entry, CPUID_7_0_EBX);
|
|
|
|
cpuid_entry_override(entry, CPUID_7_ECX);
|
|
|
|
cpuid_entry_override(entry, CPUID_7_EDX);
|
2020-03-03 02:56:48 +03:00
|
|
|
|
2020-03-03 02:56:49 +03:00
|
|
|
/* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */
|
|
|
|
if (entry->eax == 1) {
|
|
|
|
entry = do_host_cpuid(array, function, 1);
|
2020-03-03 02:56:19 +03:00
|
|
|
if (!entry)
|
2019-07-04 13:18:13 +03:00
|
|
|
goto out;
|
|
|
|
|
2020-03-03 02:56:53 +03:00
|
|
|
cpuid_entry_override(entry, CPUID_7_1_EAX);
|
2020-03-03 02:56:48 +03:00
|
|
|
entry->ebx = 0;
|
|
|
|
entry->ecx = 0;
|
|
|
|
entry->edx = 0;
|
2019-07-04 13:18:13 +03:00
|
|
|
}
|
2011-11-23 18:30:32 +04:00
|
|
|
break;
|
|
|
|
case 9:
|
|
|
|
break;
|
2011-11-10 16:57:28 +04:00
|
|
|
case 0xa: { /* Architectural Performance Monitoring */
|
|
|
|
struct x86_pmu_capability cap;
|
|
|
|
union cpuid10_eax eax;
|
|
|
|
union cpuid10_edx edx;
|
|
|
|
|
|
|
|
perf_get_x86_pmu_capability(&cap);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Only support guest architectural pmu on a host
|
|
|
|
* with architectural pmu.
|
|
|
|
*/
|
|
|
|
if (!cap.version)
|
|
|
|
memset(&cap, 0, sizeof(cap));
|
|
|
|
|
|
|
|
eax.split.version_id = min(cap.version, 2);
|
|
|
|
eax.split.num_counters = cap.num_counters_gp;
|
|
|
|
eax.split.bit_width = cap.bit_width_gp;
|
|
|
|
eax.split.mask_length = cap.events_mask_len;
|
|
|
|
|
2020-06-24 04:59:28 +03:00
|
|
|
edx.split.num_counters_fixed = min(cap.num_counters_fixed, MAX_FIXED_COUNTERS);
|
2011-11-10 16:57:28 +04:00
|
|
|
edx.split.bit_width_fixed = cap.bit_width_fixed;
|
|
|
|
edx.split.reserved = 0;
|
|
|
|
|
|
|
|
entry->eax = eax.full;
|
|
|
|
entry->ebx = cap.events_mask;
|
|
|
|
entry->ecx = 0;
|
|
|
|
entry->edx = edx.full;
|
|
|
|
break;
|
|
|
|
}
|
2019-06-06 04:18:45 +03:00
|
|
|
/*
|
|
|
|
* Per Intel's SDM, the 0x1f is a superset of 0xb,
|
|
|
|
* thus they can be handled by common code.
|
|
|
|
*/
|
|
|
|
case 0x1f:
|
2020-03-03 02:56:17 +03:00
|
|
|
case 0xb:
|
2019-09-25 21:17:14 +03:00
|
|
|
/*
|
2020-03-03 02:56:19 +03:00
|
|
|
* Populate entries until the level type (ECX[15:8]) of the
|
|
|
|
* previous entry is zero. Note, CPUID EAX.{0x1f,0xb}.0 is
|
|
|
|
* the starting entry, filled by the primary do_host_cpuid().
|
2019-09-25 21:17:14 +03:00
|
|
|
*/
|
2020-03-03 02:56:19 +03:00
|
|
|
for (i = 1; entry->ecx & 0xff00; ++i) {
|
|
|
|
entry = do_host_cpuid(array, function, i);
|
|
|
|
if (!entry)
|
2011-11-28 13:20:29 +04:00
|
|
|
goto out;
|
2011-11-23 18:30:32 +04:00
|
|
|
}
|
|
|
|
break;
|
2020-03-03 02:56:23 +03:00
|
|
|
case 0xd:
|
|
|
|
entry->eax &= supported_xcr0;
|
|
|
|
entry->ebx = xstate_required_size(supported_xcr0, false);
|
2014-12-04 20:30:41 +03:00
|
|
|
entry->ecx = entry->ebx;
|
2020-03-03 02:56:23 +03:00
|
|
|
entry->edx &= supported_xcr0 >> 32;
|
|
|
|
if (!supported_xcr0)
|
2014-11-21 20:13:26 +03:00
|
|
|
break;
|
|
|
|
|
2020-03-03 02:56:19 +03:00
|
|
|
entry = do_host_cpuid(array, function, 1);
|
|
|
|
if (!entry)
|
2020-03-03 02:56:09 +03:00
|
|
|
goto out;
|
|
|
|
|
2020-03-03 02:56:53 +03:00
|
|
|
cpuid_entry_override(entry, CPUID_D_1_EAX);
|
2020-03-03 02:56:19 +03:00
|
|
|
if (entry->eax & (F(XSAVES)|F(XSAVEC)))
|
2020-03-05 18:11:56 +03:00
|
|
|
entry->ebx = xstate_required_size(supported_xcr0 | supported_xss,
|
|
|
|
true);
|
|
|
|
else {
|
|
|
|
WARN_ON_ONCE(supported_xss != 0);
|
2020-03-03 02:56:19 +03:00
|
|
|
entry->ebx = 0;
|
2020-03-05 18:11:56 +03:00
|
|
|
}
|
|
|
|
entry->ecx &= supported_xss;
|
|
|
|
entry->edx &= supported_xss >> 32;
|
2020-03-03 02:56:09 +03:00
|
|
|
|
2020-03-03 02:56:21 +03:00
|
|
|
for (i = 2; i < 64; ++i) {
|
2020-03-05 18:11:56 +03:00
|
|
|
bool s_state;
|
|
|
|
if (supported_xcr0 & BIT_ULL(i))
|
|
|
|
s_state = false;
|
|
|
|
else if (supported_xss & BIT_ULL(i))
|
|
|
|
s_state = true;
|
|
|
|
else
|
2020-03-03 02:56:10 +03:00
|
|
|
continue;
|
2020-03-03 02:56:09 +03:00
|
|
|
|
2020-03-03 02:56:21 +03:00
|
|
|
entry = do_host_cpuid(array, function, i);
|
2020-03-03 02:56:19 +03:00
|
|
|
if (!entry)
|
2011-11-28 13:20:29 +04:00
|
|
|
goto out;
|
|
|
|
|
2020-03-03 02:56:11 +03:00
|
|
|
/*
|
2020-03-03 02:56:23 +03:00
|
|
|
* The supported check above should have filtered out
|
2020-03-05 18:11:56 +03:00
|
|
|
* invalid sub-leafs. Only valid sub-leafs should
|
2020-03-03 02:56:11 +03:00
|
|
|
* reach this point, and they should have a non-zero
|
2020-03-05 18:11:56 +03:00
|
|
|
* save state size. Furthermore, check whether the
|
|
|
|
* processor agrees with supported_xcr0/supported_xss
|
|
|
|
* on whether this is an XCR0- or IA32_XSS-managed area.
|
2020-03-03 02:56:11 +03:00
|
|
|
*/
|
2020-03-05 18:11:56 +03:00
|
|
|
if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) {
|
2020-03-03 02:56:19 +03:00
|
|
|
--array->nent;
|
2020-03-03 02:56:09 +03:00
|
|
|
continue;
|
2020-03-03 02:56:12 +03:00
|
|
|
}
|
2020-03-03 02:56:19 +03:00
|
|
|
entry->edx = 0;
|
2011-11-23 18:30:32 +04:00
|
|
|
}
|
|
|
|
break;
|
2018-10-24 11:05:11 +03:00
|
|
|
/* Intel PT */
|
2020-03-03 02:56:17 +03:00
|
|
|
case 0x14:
|
2020-03-03 02:56:55 +03:00
|
|
|
if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) {
|
2020-03-03 02:56:26 +03:00
|
|
|
entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
|
2018-10-24 11:05:11 +03:00
|
|
|
break;
|
2020-03-03 02:56:26 +03:00
|
|
|
}
|
2018-10-24 11:05:11 +03:00
|
|
|
|
2020-03-03 02:56:17 +03:00
|
|
|
for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) {
|
2020-03-03 02:56:19 +03:00
|
|
|
if (!do_host_cpuid(array, function, i))
|
2018-10-24 11:05:11 +03:00
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
break;
|
2011-11-23 18:30:32 +04:00
|
|
|
case KVM_CPUID_SIGNATURE: {
|
2012-08-30 03:30:13 +04:00
|
|
|
static const char signature[12] = "KVMKVMKVM\0\0";
|
|
|
|
const u32 *sigptr = (const u32 *)signature;
|
2012-05-02 18:55:56 +04:00
|
|
|
entry->eax = KVM_CPUID_FEATURES;
|
2011-11-23 18:30:32 +04:00
|
|
|
entry->ebx = sigptr[0];
|
|
|
|
entry->ecx = sigptr[1];
|
|
|
|
entry->edx = sigptr[2];
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case KVM_CPUID_FEATURES:
|
|
|
|
entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
|
|
|
|
(1 << KVM_FEATURE_NOP_IO_DELAY) |
|
|
|
|
(1 << KVM_FEATURE_CLOCKSOURCE2) |
|
|
|
|
(1 << KVM_FEATURE_ASYNC_PF) |
|
2012-06-24 20:25:07 +04:00
|
|
|
(1 << KVM_FEATURE_PV_EOI) |
|
2013-08-26 12:48:34 +04:00
|
|
|
(1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) |
|
2017-12-13 04:33:04 +03:00
|
|
|
(1 << KVM_FEATURE_PV_UNHALT) |
|
2018-02-02 00:16:21 +03:00
|
|
|
(1 << KVM_FEATURE_PV_TLB_FLUSH) |
|
KVM: X86: Implement "send IPI" hypercall
Using hypercall to send IPIs by one vmexit instead of one by one for
xAPIC/x2APIC physical mode and one vmexit per-cluster for x2APIC cluster
mode. Intel guest can enter x2apic cluster mode when interrupt remmaping
is enabled in qemu, however, latest AMD EPYC still just supports xapic
mode which can get great improvement by Exit-less IPIs. This patchset
lets a guest send multicast IPIs, with at most 128 destinations per
hypercall in 64-bit mode and 64 vCPUs per hypercall in 32-bit mode.
Hardware: Xeon Skylake 2.5GHz, 2 sockets, 40 cores, 80 threads, the VM
is 80 vCPUs, IPI microbenchmark(https://lkml.org/lkml/2017/12/19/141):
x2apic cluster mode, vanilla
Dry-run: 0, 2392199 ns
Self-IPI: 6907514, 15027589 ns
Normal IPI: 223910476, 251301666 ns
Broadcast IPI: 0, 9282161150 ns
Broadcast lock: 0, 8812934104 ns
x2apic cluster mode, pv-ipi
Dry-run: 0, 2449341 ns
Self-IPI: 6720360, 15028732 ns
Normal IPI: 228643307, 255708477 ns
Broadcast IPI: 0, 7572293590 ns => 22% performance boost
Broadcast lock: 0, 8316124651 ns
x2apic physical mode, vanilla
Dry-run: 0, 3135933 ns
Self-IPI: 8572670, 17901757 ns
Normal IPI: 226444334, 255421709 ns
Broadcast IPI: 0, 19845070887 ns
Broadcast lock: 0, 19827383656 ns
x2apic physical mode, pv-ipi
Dry-run: 0, 2446381 ns
Self-IPI: 6788217, 15021056 ns
Normal IPI: 219454441, 249583458 ns
Broadcast IPI: 0, 7806540019 ns => 154% performance boost
Broadcast lock: 0, 9143618799 ns
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: Vitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: Wanpeng Li <wanpengli@tencent.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-07-23 09:39:54 +03:00
|
|
|
(1 << KVM_FEATURE_ASYNC_PF_VMEXIT) |
|
2019-06-04 01:52:44 +03:00
|
|
|
(1 << KVM_FEATURE_PV_SEND_IPI) |
|
2019-06-11 15:23:50 +03:00
|
|
|
(1 << KVM_FEATURE_POLL_CONTROL) |
|
2020-05-25 17:41:22 +03:00
|
|
|
(1 << KVM_FEATURE_PV_SCHED_YIELD) |
|
|
|
|
(1 << KVM_FEATURE_ASYNC_PF_INT);
|
2011-11-23 18:30:32 +04:00
|
|
|
|
|
|
|
if (sched_info_on())
|
|
|
|
entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
|
|
|
|
|
|
|
|
entry->ebx = 0;
|
|
|
|
entry->ecx = 0;
|
|
|
|
entry->edx = 0;
|
|
|
|
break;
|
|
|
|
case 0x80000000:
|
2017-12-04 19:57:25 +03:00
|
|
|
entry->eax = min(entry->eax, 0x8000001f);
|
2011-11-23 18:30:32 +04:00
|
|
|
break;
|
|
|
|
case 0x80000001:
|
2020-03-03 02:56:53 +03:00
|
|
|
cpuid_entry_override(entry, CPUID_8000_0001_EDX);
|
|
|
|
cpuid_entry_override(entry, CPUID_8000_0001_ECX);
|
2011-11-23 18:30:32 +04:00
|
|
|
break;
|
2020-04-15 04:23:20 +03:00
|
|
|
case 0x80000006:
|
|
|
|
/* L2 cache and TLB: pass through host info. */
|
|
|
|
break;
|
2014-04-27 05:30:23 +04:00
|
|
|
case 0x80000007: /* Advanced power management */
|
|
|
|
/* invariant TSC is CPUID.80000007H:EDX[8] */
|
|
|
|
entry->edx &= (1 << 8);
|
|
|
|
/* mask against host */
|
|
|
|
entry->edx &= boot_cpu_data.x86_power;
|
|
|
|
entry->eax = entry->ebx = entry->ecx = 0;
|
|
|
|
break;
|
2011-11-23 18:30:32 +04:00
|
|
|
case 0x80000008: {
|
|
|
|
unsigned g_phys_as = (entry->eax >> 16) & 0xff;
|
|
|
|
unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
|
|
|
|
unsigned phys_as = entry->eax & 0xff;
|
|
|
|
|
|
|
|
if (!g_phys_as)
|
|
|
|
g_phys_as = phys_as;
|
|
|
|
entry->eax = g_phys_as | (virt_as << 8);
|
2018-02-02 00:59:43 +03:00
|
|
|
entry->edx = 0;
|
2020-03-03 02:56:53 +03:00
|
|
|
cpuid_entry_override(entry, CPUID_8000_0008_EBX);
|
2011-11-23 18:30:32 +04:00
|
|
|
break;
|
|
|
|
}
|
2020-03-03 02:57:09 +03:00
|
|
|
case 0x8000000A:
|
|
|
|
if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) {
|
|
|
|
entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
entry->eax = 1; /* SVM revision 1 */
|
|
|
|
entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
|
|
|
|
ASID emulation to nested SVM */
|
|
|
|
entry->ecx = 0; /* Reserved */
|
|
|
|
cpuid_entry_override(entry, CPUID_8000_000A_EDX);
|
|
|
|
break;
|
2011-11-23 18:30:32 +04:00
|
|
|
case 0x80000019:
|
|
|
|
entry->ecx = entry->edx = 0;
|
|
|
|
break;
|
|
|
|
case 0x8000001a:
|
2019-03-27 23:15:37 +03:00
|
|
|
case 0x8000001e:
|
2011-11-23 18:30:32 +04:00
|
|
|
break;
|
2019-11-21 23:33:43 +03:00
|
|
|
/* Support memory encryption cpuid if host supports it */
|
|
|
|
case 0x8000001F:
|
|
|
|
if (!boot_cpu_has(X86_FEATURE_SEV))
|
|
|
|
entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
|
|
|
|
break;
|
2011-11-23 18:30:32 +04:00
|
|
|
/*Add support for Centaur's CPUID instruction*/
|
|
|
|
case 0xC0000000:
|
|
|
|
/*Just support up to 0xC0000004 now*/
|
|
|
|
entry->eax = min(entry->eax, 0xC0000004);
|
|
|
|
break;
|
|
|
|
case 0xC0000001:
|
2020-03-03 02:56:53 +03:00
|
|
|
cpuid_entry_override(entry, CPUID_C000_0001_EDX);
|
2011-11-23 18:30:32 +04:00
|
|
|
break;
|
|
|
|
case 3: /* Processor serial number */
|
|
|
|
case 5: /* MONITOR/MWAIT */
|
|
|
|
case 0xC0000002:
|
|
|
|
case 0xC0000003:
|
|
|
|
case 0xC0000004:
|
|
|
|
default:
|
|
|
|
entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2011-11-28 13:20:29 +04:00
|
|
|
r = 0;
|
|
|
|
|
|
|
|
out:
|
2011-11-23 18:30:32 +04:00
|
|
|
put_cpu();
|
2011-11-28 13:20:29 +04:00
|
|
|
|
|
|
|
return r;
|
2011-11-23 18:30:32 +04:00
|
|
|
}
|
|
|
|
|
2020-03-03 02:56:19 +03:00
|
|
|
static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func,
|
|
|
|
unsigned int type)
|
2013-09-22 18:44:50 +04:00
|
|
|
{
|
|
|
|
if (type == KVM_GET_EMULATED_CPUID)
|
2020-03-03 02:56:19 +03:00
|
|
|
return __do_cpuid_func_emulated(array, func);
|
2013-09-22 18:44:50 +04:00
|
|
|
|
2020-03-03 02:56:19 +03:00
|
|
|
return __do_cpuid_func(array, func);
|
2013-09-22 18:44:50 +04:00
|
|
|
}
|
|
|
|
|
2020-03-03 02:56:06 +03:00
|
|
|
#define CENTAUR_CPUID_SIGNATURE 0xC0000000
|
2011-11-28 13:20:29 +04:00
|
|
|
|
2020-03-03 02:56:19 +03:00
|
|
|
static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func,
|
|
|
|
unsigned int type)
|
2020-03-03 02:56:05 +03:00
|
|
|
{
|
|
|
|
u32 limit;
|
|
|
|
int r;
|
|
|
|
|
2020-03-03 02:56:06 +03:00
|
|
|
if (func == CENTAUR_CPUID_SIGNATURE &&
|
|
|
|
boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR)
|
|
|
|
return 0;
|
|
|
|
|
2020-03-03 02:56:19 +03:00
|
|
|
r = do_cpuid_func(array, func, type);
|
2020-03-03 02:56:05 +03:00
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
2020-03-03 02:56:19 +03:00
|
|
|
limit = array->entries[array->nent - 1].eax;
|
2020-03-03 02:56:05 +03:00
|
|
|
for (func = func + 1; func <= limit; ++func) {
|
2020-03-03 02:56:19 +03:00
|
|
|
r = do_cpuid_func(array, func, type);
|
2020-03-03 02:56:05 +03:00
|
|
|
if (r)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2013-09-22 18:44:50 +04:00
|
|
|
static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries,
|
|
|
|
__u32 num_entries, unsigned int ioctl_type)
|
|
|
|
{
|
|
|
|
int i;
|
2013-11-06 18:46:02 +04:00
|
|
|
__u32 pad[3];
|
2013-09-22 18:44:50 +04:00
|
|
|
|
|
|
|
if (ioctl_type != KVM_GET_EMULATED_CPUID)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We want to make sure that ->padding is being passed clean from
|
|
|
|
* userspace in case we want to use it for something in the future.
|
|
|
|
*
|
|
|
|
* Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we
|
|
|
|
* have to give ourselves satisfied only with the emulated side. /me
|
|
|
|
* sheds a tear.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < num_entries; i++) {
|
2013-11-06 18:46:02 +04:00
|
|
|
if (copy_from_user(pad, entries[i].padding, sizeof(pad)))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
if (pad[0] || pad[1] || pad[2])
|
2013-09-22 18:44:50 +04:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid,
|
|
|
|
struct kvm_cpuid_entry2 __user *entries,
|
|
|
|
unsigned int type)
|
2011-11-23 18:30:32 +04:00
|
|
|
{
|
2020-03-03 02:56:06 +03:00
|
|
|
static const u32 funcs[] = {
|
|
|
|
0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE,
|
2011-11-28 13:20:29 +04:00
|
|
|
};
|
2011-11-23 18:30:32 +04:00
|
|
|
|
2020-03-03 02:56:19 +03:00
|
|
|
struct kvm_cpuid_array array = {
|
|
|
|
.nent = 0,
|
|
|
|
};
|
|
|
|
int r, i;
|
2020-03-03 02:56:07 +03:00
|
|
|
|
2011-11-23 18:30:32 +04:00
|
|
|
if (cpuid->nent < 1)
|
2020-03-03 02:56:07 +03:00
|
|
|
return -E2BIG;
|
2011-11-23 18:30:32 +04:00
|
|
|
if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
|
|
|
|
cpuid->nent = KVM_MAX_CPUID_ENTRIES;
|
2013-09-22 18:44:50 +04:00
|
|
|
|
|
|
|
if (sanity_check_entries(entries, cpuid->nent, type))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2020-03-03 02:56:19 +03:00
|
|
|
array.entries = vzalloc(array_size(sizeof(struct kvm_cpuid_entry2),
|
treewide: Use array_size() in vzalloc()
The vzalloc() function has no 2-factor argument form, so multiplication
factors need to be wrapped in array_size(). This patch replaces cases of:
vzalloc(a * b)
with:
vzalloc(array_size(a, b))
as well as handling cases of:
vzalloc(a * b * c)
with:
vzalloc(array3_size(a, b, c))
This does, however, attempt to ignore constant size factors like:
vzalloc(4 * 1024)
though any constants defined via macros get caught up in the conversion.
Any factors with a sizeof() of "unsigned char", "char", and "u8" were
dropped, since they're redundant.
The Coccinelle script used for this was:
// Fix redundant parens around sizeof().
@@
type TYPE;
expression THING, E;
@@
(
vzalloc(
- (sizeof(TYPE)) * E
+ sizeof(TYPE) * E
, ...)
|
vzalloc(
- (sizeof(THING)) * E
+ sizeof(THING) * E
, ...)
)
// Drop single-byte sizes and redundant parens.
@@
expression COUNT;
typedef u8;
typedef __u8;
@@
(
vzalloc(
- sizeof(u8) * (COUNT)
+ COUNT
, ...)
|
vzalloc(
- sizeof(__u8) * (COUNT)
+ COUNT
, ...)
|
vzalloc(
- sizeof(char) * (COUNT)
+ COUNT
, ...)
|
vzalloc(
- sizeof(unsigned char) * (COUNT)
+ COUNT
, ...)
|
vzalloc(
- sizeof(u8) * COUNT
+ COUNT
, ...)
|
vzalloc(
- sizeof(__u8) * COUNT
+ COUNT
, ...)
|
vzalloc(
- sizeof(char) * COUNT
+ COUNT
, ...)
|
vzalloc(
- sizeof(unsigned char) * COUNT
+ COUNT
, ...)
)
// 2-factor product with sizeof(type/expression) and identifier or constant.
@@
type TYPE;
expression THING;
identifier COUNT_ID;
constant COUNT_CONST;
@@
(
vzalloc(
- sizeof(TYPE) * (COUNT_ID)
+ array_size(COUNT_ID, sizeof(TYPE))
, ...)
|
vzalloc(
- sizeof(TYPE) * COUNT_ID
+ array_size(COUNT_ID, sizeof(TYPE))
, ...)
|
vzalloc(
- sizeof(TYPE) * (COUNT_CONST)
+ array_size(COUNT_CONST, sizeof(TYPE))
, ...)
|
vzalloc(
- sizeof(TYPE) * COUNT_CONST
+ array_size(COUNT_CONST, sizeof(TYPE))
, ...)
|
vzalloc(
- sizeof(THING) * (COUNT_ID)
+ array_size(COUNT_ID, sizeof(THING))
, ...)
|
vzalloc(
- sizeof(THING) * COUNT_ID
+ array_size(COUNT_ID, sizeof(THING))
, ...)
|
vzalloc(
- sizeof(THING) * (COUNT_CONST)
+ array_size(COUNT_CONST, sizeof(THING))
, ...)
|
vzalloc(
- sizeof(THING) * COUNT_CONST
+ array_size(COUNT_CONST, sizeof(THING))
, ...)
)
// 2-factor product, only identifiers.
@@
identifier SIZE, COUNT;
@@
vzalloc(
- SIZE * COUNT
+ array_size(COUNT, SIZE)
, ...)
// 3-factor product with 1 sizeof(type) or sizeof(expression), with
// redundant parens removed.
@@
expression THING;
identifier STRIDE, COUNT;
type TYPE;
@@
(
vzalloc(
- sizeof(TYPE) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
vzalloc(
- sizeof(TYPE) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
vzalloc(
- sizeof(TYPE) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
vzalloc(
- sizeof(TYPE) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(TYPE))
, ...)
|
vzalloc(
- sizeof(THING) * (COUNT) * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
vzalloc(
- sizeof(THING) * (COUNT) * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
vzalloc(
- sizeof(THING) * COUNT * (STRIDE)
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
|
vzalloc(
- sizeof(THING) * COUNT * STRIDE
+ array3_size(COUNT, STRIDE, sizeof(THING))
, ...)
)
// 3-factor product with 2 sizeof(variable), with redundant parens removed.
@@
expression THING1, THING2;
identifier COUNT;
type TYPE1, TYPE2;
@@
(
vzalloc(
- sizeof(TYPE1) * sizeof(TYPE2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
vzalloc(
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(TYPE2))
, ...)
|
vzalloc(
- sizeof(THING1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
vzalloc(
- sizeof(THING1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(THING1), sizeof(THING2))
, ...)
|
vzalloc(
- sizeof(TYPE1) * sizeof(THING2) * COUNT
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
|
vzalloc(
- sizeof(TYPE1) * sizeof(THING2) * (COUNT)
+ array3_size(COUNT, sizeof(TYPE1), sizeof(THING2))
, ...)
)
// 3-factor product, only identifiers, with redundant parens removed.
@@
identifier STRIDE, SIZE, COUNT;
@@
(
vzalloc(
- (COUNT) * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
vzalloc(
- COUNT * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
vzalloc(
- COUNT * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
vzalloc(
- (COUNT) * (STRIDE) * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
vzalloc(
- COUNT * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
vzalloc(
- (COUNT) * STRIDE * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
vzalloc(
- (COUNT) * (STRIDE) * (SIZE)
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
|
vzalloc(
- COUNT * STRIDE * SIZE
+ array3_size(COUNT, STRIDE, SIZE)
, ...)
)
// Any remaining multi-factor products, first at least 3-factor products
// when they're not all constants...
@@
expression E1, E2, E3;
constant C1, C2, C3;
@@
(
vzalloc(C1 * C2 * C3, ...)
|
vzalloc(
- E1 * E2 * E3
+ array3_size(E1, E2, E3)
, ...)
)
// And then all remaining 2 factors products when they're not all constants.
@@
expression E1, E2;
constant C1, C2;
@@
(
vzalloc(C1 * C2, ...)
|
vzalloc(
- E1 * E2
+ array_size(E1, E2)
, ...)
)
Signed-off-by: Kees Cook <keescook@chromium.org>
2018-06-13 00:27:37 +03:00
|
|
|
cpuid->nent));
|
2020-03-03 02:56:19 +03:00
|
|
|
if (!array.entries)
|
2020-03-03 02:56:07 +03:00
|
|
|
return -ENOMEM;
|
2011-11-23 18:30:32 +04:00
|
|
|
|
2020-06-04 07:16:36 +03:00
|
|
|
array.maxnent = cpuid->nent;
|
|
|
|
|
2020-03-03 02:56:06 +03:00
|
|
|
for (i = 0; i < ARRAY_SIZE(funcs); i++) {
|
2020-03-03 02:56:19 +03:00
|
|
|
r = get_cpuid_func(&array, funcs[i], type);
|
2011-11-28 13:20:29 +04:00
|
|
|
if (r)
|
2011-11-23 18:30:32 +04:00
|
|
|
goto out_free;
|
|
|
|
}
|
2020-03-03 02:56:19 +03:00
|
|
|
cpuid->nent = array.nent;
|
2011-11-23 18:30:32 +04:00
|
|
|
|
2020-03-03 02:56:19 +03:00
|
|
|
if (copy_to_user(entries, array.entries,
|
|
|
|
array.nent * sizeof(struct kvm_cpuid_entry2)))
|
2020-03-03 02:56:07 +03:00
|
|
|
r = -EFAULT;
|
2011-11-23 18:30:32 +04:00
|
|
|
|
|
|
|
out_free:
|
2020-03-03 02:56:19 +03:00
|
|
|
vfree(array.entries);
|
2011-11-23 18:30:32 +04:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
|
|
|
|
u32 function, u32 index)
|
|
|
|
{
|
2020-10-01 16:05:39 +03:00
|
|
|
return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent,
|
|
|
|
function, index);
|
2011-11-23 18:30:32 +04:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
|
|
|
|
|
|
|
|
/*
|
KVM: x86: Fix CPUID range checks for Hypervisor and Centaur classes
Rework the masking in the out-of-range CPUID logic to handle the
Hypervisor sub-classes, as well as the Centaur class if the guest
virtual CPU vendor is Centaur.
Masking against 0x80000000 only handles basic and extended leafs, which
results in Hypervisor range checks being performed against the basic
CPUID class, and Centuar range checks being performed against the
Extended class. E.g. if CPUID.0x40000000.EAX returns 0x4000000A and
there is no entry for CPUID.0x40000006, then function 0x40000006 would
be incorrectly reported as out of bounds.
While there is no official definition of what constitutes a class, the
convention established for Hypervisor classes effectively uses bits 31:8
as the mask by virtue of checking for different bases in increments of
0x100, e.g. KVM advertises its CPUID functions starting at 0x40000100
when HyperV features are advertised at the default base of 0x40000000.
The bad range check doesn't cause functional problems for any known VMM
because out-of-range semantics only come into play if the exact entry
isn't found, and VMMs either support a very limited Hypervisor range,
e.g. the official KVM range is 0x40000000-0x40000001 (effectively no
room for undefined leafs) or explicitly defines gaps to be zero, e.g.
Qemu explicitly creates zeroed entries up to the Centaur and Hypervisor
limits (the latter comes into play when providing HyperV features).
The bad behavior can be visually confirmed by dumping CPUID output in
the guest when running Qemu with a stable TSC, as Qemu extends the limit
of range 0x40000000 to 0x40000010 to advertise VMware's cpuid_freq,
without defining zeroed entries for 0x40000002 - 0x4000000f.
Note, documentation of Centaur/VIA CPUs is hard to come by. Designating
0xc0000000 - 0xcfffffff as the Centaur class is a best guess as to the
behavior of a real Centaur/VIA CPU.
Fixes: 43561123ab37 ("kvm: x86: Improve emulation of CPUID leaves 0BH and 1FH")
Cc: Jim Mattson <jmattson@google.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-05 04:34:34 +03:00
|
|
|
* Intel CPUID semantics treats any query for an out-of-range leaf as if the
|
|
|
|
* highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics
|
|
|
|
* returns all zeroes for any undefined leaf, whether or not the leaf is in
|
|
|
|
* range. Centaur/VIA follows Intel semantics.
|
|
|
|
*
|
|
|
|
* A leaf is considered out-of-range if its function is higher than the maximum
|
|
|
|
* supported leaf of its associated class or if its associated class does not
|
|
|
|
* exist.
|
|
|
|
*
|
|
|
|
* There are three primary classes to be considered, with their respective
|
|
|
|
* ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary
|
|
|
|
* class exists if a guest CPUID entry for its <base> leaf exists. For a given
|
|
|
|
* class, CPUID.<base>.EAX contains the max supported leaf for the class.
|
|
|
|
*
|
|
|
|
* - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff
|
|
|
|
* - Hypervisor: 0x40000000 - 0x4fffffff
|
|
|
|
* - Extended: 0x80000000 - 0xbfffffff
|
|
|
|
* - Centaur: 0xc0000000 - 0xcfffffff
|
|
|
|
*
|
|
|
|
* The Hypervisor class is further subdivided into sub-classes that each act as
|
|
|
|
* their own indepdent class associated with a 0x100 byte range. E.g. if Qemu
|
|
|
|
* is advertising support for both HyperV and KVM, the resulting Hypervisor
|
|
|
|
* CPUID sub-classes are:
|
|
|
|
*
|
|
|
|
* - HyperV: 0x40000000 - 0x400000ff
|
|
|
|
* - KVM: 0x40000100 - 0x400001ff
|
2011-11-23 18:30:32 +04:00
|
|
|
*/
|
2020-03-05 04:34:36 +03:00
|
|
|
static struct kvm_cpuid_entry2 *
|
|
|
|
get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index)
|
2011-11-23 18:30:32 +04:00
|
|
|
{
|
KVM: x86: Fix CPUID range checks for Hypervisor and Centaur classes
Rework the masking in the out-of-range CPUID logic to handle the
Hypervisor sub-classes, as well as the Centaur class if the guest
virtual CPU vendor is Centaur.
Masking against 0x80000000 only handles basic and extended leafs, which
results in Hypervisor range checks being performed against the basic
CPUID class, and Centuar range checks being performed against the
Extended class. E.g. if CPUID.0x40000000.EAX returns 0x4000000A and
there is no entry for CPUID.0x40000006, then function 0x40000006 would
be incorrectly reported as out of bounds.
While there is no official definition of what constitutes a class, the
convention established for Hypervisor classes effectively uses bits 31:8
as the mask by virtue of checking for different bases in increments of
0x100, e.g. KVM advertises its CPUID functions starting at 0x40000100
when HyperV features are advertised at the default base of 0x40000000.
The bad range check doesn't cause functional problems for any known VMM
because out-of-range semantics only come into play if the exact entry
isn't found, and VMMs either support a very limited Hypervisor range,
e.g. the official KVM range is 0x40000000-0x40000001 (effectively no
room for undefined leafs) or explicitly defines gaps to be zero, e.g.
Qemu explicitly creates zeroed entries up to the Centaur and Hypervisor
limits (the latter comes into play when providing HyperV features).
The bad behavior can be visually confirmed by dumping CPUID output in
the guest when running Qemu with a stable TSC, as Qemu extends the limit
of range 0x40000000 to 0x40000010 to advertise VMware's cpuid_freq,
without defining zeroed entries for 0x40000002 - 0x4000000f.
Note, documentation of Centaur/VIA CPUs is hard to come by. Designating
0xc0000000 - 0xcfffffff as the Centaur class is a best guess as to the
behavior of a real Centaur/VIA CPU.
Fixes: 43561123ab37 ("kvm: x86: Improve emulation of CPUID leaves 0BH and 1FH")
Cc: Jim Mattson <jmattson@google.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-05 04:34:34 +03:00
|
|
|
struct kvm_cpuid_entry2 *basic, *class;
|
2020-03-05 04:34:36 +03:00
|
|
|
u32 function = *fn_ptr;
|
KVM: x86: Fix CPUID range checks for Hypervisor and Centaur classes
Rework the masking in the out-of-range CPUID logic to handle the
Hypervisor sub-classes, as well as the Centaur class if the guest
virtual CPU vendor is Centaur.
Masking against 0x80000000 only handles basic and extended leafs, which
results in Hypervisor range checks being performed against the basic
CPUID class, and Centuar range checks being performed against the
Extended class. E.g. if CPUID.0x40000000.EAX returns 0x4000000A and
there is no entry for CPUID.0x40000006, then function 0x40000006 would
be incorrectly reported as out of bounds.
While there is no official definition of what constitutes a class, the
convention established for Hypervisor classes effectively uses bits 31:8
as the mask by virtue of checking for different bases in increments of
0x100, e.g. KVM advertises its CPUID functions starting at 0x40000100
when HyperV features are advertised at the default base of 0x40000000.
The bad range check doesn't cause functional problems for any known VMM
because out-of-range semantics only come into play if the exact entry
isn't found, and VMMs either support a very limited Hypervisor range,
e.g. the official KVM range is 0x40000000-0x40000001 (effectively no
room for undefined leafs) or explicitly defines gaps to be zero, e.g.
Qemu explicitly creates zeroed entries up to the Centaur and Hypervisor
limits (the latter comes into play when providing HyperV features).
The bad behavior can be visually confirmed by dumping CPUID output in
the guest when running Qemu with a stable TSC, as Qemu extends the limit
of range 0x40000000 to 0x40000010 to advertise VMware's cpuid_freq,
without defining zeroed entries for 0x40000002 - 0x4000000f.
Note, documentation of Centaur/VIA CPUs is hard to come by. Designating
0xc0000000 - 0xcfffffff as the Centaur class is a best guess as to the
behavior of a real Centaur/VIA CPU.
Fixes: 43561123ab37 ("kvm: x86: Improve emulation of CPUID leaves 0BH and 1FH")
Cc: Jim Mattson <jmattson@google.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-05 04:34:34 +03:00
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basic = kvm_find_cpuid_entry(vcpu, 0, 0);
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if (!basic)
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2020-03-05 04:34:36 +03:00
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return NULL;
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if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) ||
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is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx))
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return NULL;
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KVM: x86: Fix CPUID range checks for Hypervisor and Centaur classes
Rework the masking in the out-of-range CPUID logic to handle the
Hypervisor sub-classes, as well as the Centaur class if the guest
virtual CPU vendor is Centaur.
Masking against 0x80000000 only handles basic and extended leafs, which
results in Hypervisor range checks being performed against the basic
CPUID class, and Centuar range checks being performed against the
Extended class. E.g. if CPUID.0x40000000.EAX returns 0x4000000A and
there is no entry for CPUID.0x40000006, then function 0x40000006 would
be incorrectly reported as out of bounds.
While there is no official definition of what constitutes a class, the
convention established for Hypervisor classes effectively uses bits 31:8
as the mask by virtue of checking for different bases in increments of
0x100, e.g. KVM advertises its CPUID functions starting at 0x40000100
when HyperV features are advertised at the default base of 0x40000000.
The bad range check doesn't cause functional problems for any known VMM
because out-of-range semantics only come into play if the exact entry
isn't found, and VMMs either support a very limited Hypervisor range,
e.g. the official KVM range is 0x40000000-0x40000001 (effectively no
room for undefined leafs) or explicitly defines gaps to be zero, e.g.
Qemu explicitly creates zeroed entries up to the Centaur and Hypervisor
limits (the latter comes into play when providing HyperV features).
The bad behavior can be visually confirmed by dumping CPUID output in
the guest when running Qemu with a stable TSC, as Qemu extends the limit
of range 0x40000000 to 0x40000010 to advertise VMware's cpuid_freq,
without defining zeroed entries for 0x40000002 - 0x4000000f.
Note, documentation of Centaur/VIA CPUs is hard to come by. Designating
0xc0000000 - 0xcfffffff as the Centaur class is a best guess as to the
behavior of a real Centaur/VIA CPU.
Fixes: 43561123ab37 ("kvm: x86: Improve emulation of CPUID leaves 0BH and 1FH")
Cc: Jim Mattson <jmattson@google.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-05 04:34:34 +03:00
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if (function >= 0x40000000 && function <= 0x4fffffff)
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class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00, 0);
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else if (function >= 0xc0000000)
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class = kvm_find_cpuid_entry(vcpu, 0xc0000000, 0);
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else
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class = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
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2019-09-26 03:04:17 +03:00
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|
2020-03-05 04:34:36 +03:00
|
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if (class && function <= class->eax)
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return NULL;
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/*
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* Leaf specific adjustments are also applied when redirecting to the
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* max basic entry, e.g. if the max basic leaf is 0xb but there is no
|
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* entry for CPUID.0xb.index (see below), then the output value for EDX
|
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* needs to be pulled from CPUID.0xb.1.
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*/
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*fn_ptr = basic->eax;
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|
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/*
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* The class does not exist or the requested function is out of range;
|
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|
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* the effective CPUID entry is the max basic leaf. Note, the index of
|
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* the original requested leaf is observed!
|
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*/
|
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return kvm_find_cpuid_entry(vcpu, basic->eax, index);
|
2011-11-23 18:30:32 +04:00
|
|
|
}
|
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|
|
2017-08-24 15:27:52 +03:00
|
|
|
bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx,
|
2020-03-05 04:34:37 +03:00
|
|
|
u32 *ecx, u32 *edx, bool exact_only)
|
2011-11-23 18:30:32 +04:00
|
|
|
{
|
2020-03-05 04:34:31 +03:00
|
|
|
u32 orig_function = *eax, function = *eax, index = *ecx;
|
2019-09-26 03:04:17 +03:00
|
|
|
struct kvm_cpuid_entry2 *entry;
|
2020-03-17 22:53:54 +03:00
|
|
|
bool exact, used_max_basic = false;
|
2017-08-24 15:27:52 +03:00
|
|
|
|
2019-09-26 03:04:17 +03:00
|
|
|
entry = kvm_find_cpuid_entry(vcpu, function, index);
|
2020-03-05 04:34:37 +03:00
|
|
|
exact = !!entry;
|
2020-03-05 04:34:36 +03:00
|
|
|
|
2020-03-17 22:53:54 +03:00
|
|
|
if (!entry && !exact_only) {
|
2020-03-05 04:34:36 +03:00
|
|
|
entry = get_out_of_range_cpuid_entry(vcpu, &function, index);
|
2020-03-17 22:53:54 +03:00
|
|
|
used_max_basic = !!entry;
|
|
|
|
}
|
2020-03-05 04:34:36 +03:00
|
|
|
|
2019-09-26 03:04:17 +03:00
|
|
|
if (entry) {
|
|
|
|
*eax = entry->eax;
|
|
|
|
*ebx = entry->ebx;
|
|
|
|
*ecx = entry->ecx;
|
|
|
|
*edx = entry->edx;
|
2019-11-18 20:23:00 +03:00
|
|
|
if (function == 7 && index == 0) {
|
|
|
|
u64 data;
|
|
|
|
if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) &&
|
|
|
|
(data & TSX_CTRL_CPUID_CLEAR))
|
|
|
|
*ebx &= ~(F(RTM) | F(HLE));
|
|
|
|
}
|
2019-09-26 03:04:17 +03:00
|
|
|
} else {
|
2012-06-07 15:07:48 +04:00
|
|
|
*eax = *ebx = *ecx = *edx = 0;
|
2019-09-26 03:04:17 +03:00
|
|
|
/*
|
|
|
|
* When leaf 0BH or 1FH is defined, CL is pass-through
|
|
|
|
* and EDX is always the x2APIC ID, even for undefined
|
|
|
|
* subleaves. Index 1 will exist iff the leaf is
|
|
|
|
* implemented, so we pass through CL iff leaf 1
|
|
|
|
* exists. EDX can be copied from any existing index.
|
|
|
|
*/
|
|
|
|
if (function == 0xb || function == 0x1f) {
|
|
|
|
entry = kvm_find_cpuid_entry(vcpu, function, 1);
|
|
|
|
if (entry) {
|
|
|
|
*ecx = index & 0xff;
|
|
|
|
*edx = entry->edx;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2020-03-17 22:53:54 +03:00
|
|
|
trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact,
|
|
|
|
used_max_basic);
|
2020-03-05 04:34:37 +03:00
|
|
|
return exact;
|
2012-06-07 15:07:48 +04:00
|
|
|
}
|
2012-12-05 18:26:19 +04:00
|
|
|
EXPORT_SYMBOL_GPL(kvm_cpuid);
|
2012-06-07 15:07:48 +04:00
|
|
|
|
2016-11-29 23:40:37 +03:00
|
|
|
int kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
|
2012-06-07 15:07:48 +04:00
|
|
|
{
|
2016-11-07 03:55:49 +03:00
|
|
|
u32 eax, ebx, ecx, edx;
|
2012-06-07 15:07:48 +04:00
|
|
|
|
2017-03-20 11:16:28 +03:00
|
|
|
if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0))
|
|
|
|
return 1;
|
|
|
|
|
2019-04-30 20:36:17 +03:00
|
|
|
eax = kvm_rax_read(vcpu);
|
|
|
|
ecx = kvm_rcx_read(vcpu);
|
2020-03-05 04:34:37 +03:00
|
|
|
kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false);
|
2019-04-30 20:36:17 +03:00
|
|
|
kvm_rax_write(vcpu, eax);
|
|
|
|
kvm_rbx_write(vcpu, ebx);
|
|
|
|
kvm_rcx_write(vcpu, ecx);
|
|
|
|
kvm_rdx_write(vcpu, edx);
|
KVM: x86: Add kvm_skip_emulated_instruction and use it.
kvm_skip_emulated_instruction calls both
kvm_x86_ops->skip_emulated_instruction and kvm_vcpu_check_singlestep,
skipping the emulated instruction and generating a trap if necessary.
Replacing skip_emulated_instruction calls with
kvm_skip_emulated_instruction is straightforward, except for:
- ICEBP, which is already inside a trap, so avoid triggering another trap.
- Instructions that can trigger exits to userspace, such as the IO insns,
MOVs to CR8, and HALT. If kvm_skip_emulated_instruction does trigger a
KVM_GUESTDBG_SINGLESTEP exit, and the handling code for
IN/OUT/MOV CR8/HALT also triggers an exit to userspace, the latter will
take precedence. The singlestep will be triggered again on the next
instruction, which is the current behavior.
- Task switch instructions which would require additional handling (e.g.
the task switch bit) and are instead left alone.
- Cases where VMLAUNCH/VMRESUME do not proceed to the next instruction,
which do not trigger singlestep traps as mentioned previously.
Signed-off-by: Kyle Huey <khuey@kylehuey.com>
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
2016-11-29 23:40:40 +03:00
|
|
|
return kvm_skip_emulated_instruction(vcpu);
|
2011-11-23 18:30:32 +04:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
|