2019-05-19 15:07:45 +03:00
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# SPDX-License-Identifier: GPL-2.0-only
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2005-07-31 03:31:23 +04:00
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#
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# PHY Layer Configuration
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#
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phylink: add phylink infrastructure
The link between the ethernet MAC and its PHY has become more complex
as the interface evolves. This is especially true with serdes links,
where the part of the PHY is effectively integrated into the MAC.
Serdes links can be connected to a variety of devices, including SFF
modules soldered down onto the board with the MAC, a SFP cage with
a hotpluggable SFP module which may contain a PHY or directly modulate
the serdes signals onto optical media with or without a PHY, or even
a classical PHY connection.
Moreover, the negotiation information on serdes links comes in two
varieties - SGMII mode, where the PHY provides its speed/duplex/flow
control information to the MAC, and 1000base-X mode where both ends
exchange their abilities and each resolve the link capabilities.
This means we need a more flexible means to support these arrangements,
particularly with the hotpluggable nature of SFP, where the PHY can
be attached or detached after the network device has been brought up.
Ethtool information can come from multiple sources:
- we may have a PHY operating in either SGMII or 1000base-X mode, in
which case we take ethtool/mii data directly from the PHY.
- we may have a optical SFP module without a PHY, with the MAC
operating in 1000base-X mode - the ethtool/mii data needs to come
from the MAC.
- we may have a copper SFP module with a PHY whic can't be accessed,
which means we need to take ethtool/mii data from the MAC.
Phylink aims to solve this by providing an intermediary between the
MAC and PHY, providing a safe way for PHYs to be hotplugged, and
allowing a SFP driver to reconfigure the serdes connection.
Phylink also takes over support of fixed link connections, where the
speed/duplex/flow control are fixed, but link status may be controlled
by a GPIO signal. By avoiding the fixed-phy implementation, phylink
can provide a faster response to link events: fixed-phy has to wait for
phylib to operate its state machine, which can take several seconds.
In comparison, phylink takes milliseconds.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
- remove sync status
- rework supported and advertisment handling
- add 1000base-x speed for fixed links
- use functionality exported from phy-core, reworking
__phylink_ethtool_ksettings_set for it
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-07-25 17:03:13 +03:00
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config PHYLINK
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tristate
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depends on NETDEVICES
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select PHYLIB
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select SWPHY
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help
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PHYlink models the link between the PHY and MAC, allowing fixed
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configuration links, PHYs, and Serdes links with MAC level
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autonegotiation modes.
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2017-09-18 15:59:20 +03:00
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menuconfig PHYLIB
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2018-04-27 22:41:49 +03:00
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tristate "PHY Device support and infrastructure"
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2017-09-18 15:59:20 +03:00
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depends on NETDEVICES
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select MDIO_DEVICE
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2020-07-05 12:55:47 +03:00
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select MDIO_DEVRES
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2017-09-18 15:59:20 +03:00
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help
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Ethernet controllers are usually attached to PHY
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devices. This option provides infrastructure for
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managing PHY devices.
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2017-03-23 20:01:19 +03:00
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if PHYLIB
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config SWPHY
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bool
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config LED_TRIGGER_PHY
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bool "Support LED triggers for tracking link state"
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depends on LEDS_TRIGGERS
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2020-06-13 19:50:22 +03:00
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help
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2017-03-23 20:01:19 +03:00
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Adds support for a set of LED trigger events per-PHY. Link
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state change will trigger the events, for consumption by an
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LED class driver. There are triggers for each link speed currently
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2017-11-02 02:49:18 +03:00
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supported by the PHY and also a one common "link" trigger as a
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logical-or of all the link speed ones.
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All these triggers are named according to the following pattern:
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2017-08-14 16:43:00 +03:00
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<mii bus id>:<phy>:<speed>
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2017-03-23 20:01:19 +03:00
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Where speed is in the form:
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2017-11-02 02:49:18 +03:00
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<Speed in megabits>Mbps OR <Speed in gigabits>Gbps OR link
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for any speed known to the PHY.
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2017-03-23 20:01:19 +03:00
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2020-08-27 05:00:32 +03:00
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config FIXED_PHY
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tristate "MDIO Bus/PHY emulation with fixed speed/link PHYs"
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depends on PHYLIB
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select SWPHY
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help
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Adds the platform "fixed" MDIO Bus to cover the boards that use
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PHYs that are not connected to the real MDIO bus.
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Currently tested with mpc866ads and mpc8349e-mitx.
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2016-08-19 00:56:05 +03:00
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2017-07-25 17:03:39 +03:00
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config SFP
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tristate "SFP cage support"
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depends on I2C && PHYLINK
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2018-07-19 19:41:39 +03:00
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depends on HWMON || HWMON=n
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2017-07-25 17:03:39 +03:00
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select MDIO_I2C
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2020-08-27 05:00:32 +03:00
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comment "MII PHY device drivers"
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config AMD_PHY
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tristate "AMD PHYs"
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help
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Currently supports the am79c874
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config MESON_GXL_PHY
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tristate "Amlogic Meson GXL Internal PHY"
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depends on ARCH_MESON || COMPILE_TEST
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help
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Currently has a driver for the Amlogic Meson GXL Internal PHY
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2019-08-16 16:09:59 +03:00
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config ADIN_PHY
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tristate "Analog Devices Industrial Ethernet PHYs"
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help
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Adds support for the Analog Devices Industrial Ethernet PHYs.
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Currently supports the:
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- ADIN1200 - Robust,Industrial, Low Power 10/100 Ethernet PHY
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- ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
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Ethernet PHY
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2016-08-19 00:56:05 +03:00
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config AQUANTIA_PHY
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2017-08-14 16:43:00 +03:00
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tristate "Aquantia PHYs"
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2020-06-13 19:50:22 +03:00
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help
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2017-08-14 16:43:00 +03:00
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Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405
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2016-08-19 00:56:05 +03:00
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2019-06-07 08:37:34 +03:00
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config AX88796B_PHY
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2018-04-19 05:05:18 +03:00
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tristate "Asix PHYs"
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help
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Currently supports the Asix Electronics PHY found in the X-Surf 100
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AX88796B package.
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2020-08-27 05:00:32 +03:00
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config BROADCOM_PHY
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tristate "Broadcom 54XX PHYs"
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select BCM_NET_PHYLIB
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help
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Currently supports the BCM5411, BCM5421, BCM5461, BCM54616S, BCM5464,
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BCM5481, BCM54810 and BCM5482 PHYs.
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config BCM54140_PHY
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tristate "Broadcom BCM54140 PHY"
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depends on PHYLIB
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depends on HWMON || HWMON=n
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select BCM_NET_PHYLIB
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help
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Support the Broadcom BCM54140 Quad SGMII/QSGMII PHY.
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This driver also supports the hardware monitoring of this PHY and
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exposes voltage and temperature sensors.
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2009-07-01 05:29:36 +04:00
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config BCM63XX_PHY
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2016-08-19 00:56:06 +03:00
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tristate "Broadcom 63xx SOCs internal PHY"
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2018-09-12 02:53:10 +03:00
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depends on BCM63XX || COMPILE_TEST
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2015-10-06 22:25:48 +03:00
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select BCM_NET_PHYLIB
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2020-06-13 19:50:22 +03:00
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help
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2009-07-01 05:29:36 +04:00
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Currently supports the 6348 and 6358 PHYs.
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2014-02-14 04:08:45 +04:00
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config BCM7XXX_PHY
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2016-08-19 00:56:06 +03:00
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tristate "Broadcom 7xxx SOCs internal PHYs"
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2015-10-06 22:25:48 +03:00
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select BCM_NET_PHYLIB
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2020-06-13 19:50:22 +03:00
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help
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2014-02-14 04:08:45 +04:00
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Currently supports the BCM7366, BCM7439, BCM7445, and
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40nm and 65nm generation of BCM7xxx Set Top Box SoCs.
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2020-08-27 05:00:32 +03:00
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config BCM84881_PHY
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tristate "Broadcom BCM84881 PHY"
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depends on PHYLIB
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help
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Support the Broadcom BCM84881 PHY.
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2012-06-27 11:33:38 +04:00
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config BCM87XX_PHY
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2016-08-19 00:56:06 +03:00
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tristate "Broadcom BCM8706 and BCM8727 PHYs"
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2012-06-27 11:33:38 +04:00
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help
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Currently supports the BCM8706 and BCM8727 10G Ethernet PHYs.
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2016-08-19 00:56:05 +03:00
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config BCM_CYGNUS_PHY
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2019-03-22 02:23:30 +03:00
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tristate "Broadcom Cygnus/Omega SoC internal PHY"
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2019-03-20 22:53:13 +03:00
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depends on ARCH_BCM_IPROC || COMPILE_TEST
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2016-08-19 00:56:05 +03:00
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depends on MDIO_BCM_IPROC
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select BCM_NET_PHYLIB
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2020-06-13 19:50:22 +03:00
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help
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2016-08-19 00:56:05 +03:00
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This PHY driver is for the 1G internal PHYs of the Broadcom
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2019-03-20 22:53:13 +03:00
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Cygnus and Omega Family SoC.
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2007-05-12 03:24:51 +04:00
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2016-08-19 00:56:05 +03:00
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Currently supports internal PHY's used in the BCM11300,
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BCM11320, BCM11350, BCM11360, BCM58300, BCM58302,
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BCM58303 & BCM58305 Broadcom Cygnus SoCs.
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2008-02-03 14:50:54 +03:00
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2016-08-19 00:56:05 +03:00
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config BCM_NET_PHYLIB
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tristate
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2008-11-29 03:14:12 +03:00
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2016-08-19 00:56:05 +03:00
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config CICADA_PHY
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2016-08-19 00:56:06 +03:00
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tristate "Cicada PHYs"
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2020-06-13 19:50:22 +03:00
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help
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2016-08-19 00:56:05 +03:00
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Currently supports the cis8204
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2008-12-10 09:21:25 +03:00
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2017-05-29 12:11:30 +03:00
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config CORTINA_PHY
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tristate "Cortina EDC CDR 10G Ethernet PHY"
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2020-06-13 19:50:22 +03:00
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help
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2017-05-29 12:11:30 +03:00
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Currently supports the CS4340 phy.
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2016-08-19 00:56:05 +03:00
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config DAVICOM_PHY
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2016-08-19 00:56:06 +03:00
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tristate "Davicom PHYs"
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2020-06-13 19:50:22 +03:00
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help
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2016-08-19 00:56:05 +03:00
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Currently supports dm9161e and dm9131
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2010-04-29 10:12:41 +04:00
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2016-08-19 00:56:05 +03:00
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config ICPLUS_PHY
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2016-08-19 00:56:06 +03:00
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tristate "ICPlus PHYs"
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2020-06-13 19:50:22 +03:00
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help
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2016-08-19 00:56:05 +03:00
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Currently supports the IP175C and IP1001 PHYs.
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2015-10-06 22:25:47 +03:00
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2020-08-27 05:00:32 +03:00
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config LXT_PHY
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tristate "Intel LXT PHYs"
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help
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Currently supports the lxt970, lxt971
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2016-06-06 00:41:11 +03:00
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config INTEL_XWAY_PHY
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2016-08-19 00:56:06 +03:00
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tristate "Intel XWAY PHYs"
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2020-06-13 19:50:22 +03:00
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help
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2016-06-06 00:41:11 +03:00
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Supports the Intel XWAY (former Lantiq) 11G and 22E PHYs.
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These PHYs are marked as standalone chips under the names
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PEF 7061, PEF 7071 and PEF 7072 or integrated into the Intel
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SoCs xRX200, xRX300, xRX330, xRX350 and xRX550.
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2016-08-19 00:56:05 +03:00
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config LSI_ET1011C_PHY
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2016-08-19 00:56:06 +03:00
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tristate "LSI ET1011C PHY"
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2020-06-13 19:50:22 +03:00
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help
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2016-08-19 00:56:05 +03:00
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Supports the LSI ET1011C PHY.
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2016-07-15 11:26:33 +03:00
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2016-08-19 00:56:05 +03:00
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config MARVELL_PHY
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2020-08-27 05:00:32 +03:00
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tristate "Marvell Alaska PHYs"
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2020-06-13 19:50:22 +03:00
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help
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2020-08-27 05:00:32 +03:00
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Currently has a driver for the 88E1XXX
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2016-08-19 00:56:05 +03:00
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2017-06-05 14:23:16 +03:00
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config MARVELL_10G_PHY
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tristate "Marvell Alaska 10Gbit PHYs"
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2020-06-13 19:50:22 +03:00
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help
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2017-06-05 14:23:16 +03:00
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Support for the Marvell Alaska MV88X3310 and compatible PHYs.
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2016-08-19 00:56:05 +03:00
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config MICREL_PHY
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2016-08-19 00:56:06 +03:00
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tristate "Micrel PHYs"
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2020-06-13 19:50:22 +03:00
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help
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2016-08-19 00:56:05 +03:00
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Supports the KSZ9021, VSC8201, KS8001 PHYs.
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config MICROCHIP_PHY
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2016-08-19 00:56:06 +03:00
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tristate "Microchip PHYs"
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2016-07-26 03:12:40 +03:00
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help
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2016-08-19 00:56:05 +03:00
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Supports the LAN88XX PHYs.
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2016-07-26 03:12:40 +03:00
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2018-05-02 18:39:17 +03:00
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config MICROCHIP_T1_PHY
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tristate "Microchip T1 PHYs"
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2020-06-13 19:50:22 +03:00
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help
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2018-05-02 18:39:17 +03:00
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Supports the LAN87XX PHYs.
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2016-08-05 15:24:21 +03:00
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config MICROSEMI_PHY
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2016-09-08 11:39:31 +03:00
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tristate "Microsemi PHYs"
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2020-01-14 01:31:46 +03:00
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depends on MACSEC || MACSEC=n
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2020-06-25 10:18:16 +03:00
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select CRYPTO_LIB_AES if MACSEC
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2020-06-13 19:50:22 +03:00
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help
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net: phy: mscc: add support for VSC8514 PHY.
The VSC8514 PHY is a 4-ports PHY that is 10/100/1000BASE-T, 100BASE-FX,
1000BASE-X, can communicate with the MAC via QSGMII.
The MAC interface protocol for each port within QSGMII can
be either 1000BASE-X or SGMII, if the QSGMII MAC that the VSC8514 is
connecting to supports this functionality.
VSC8514 also supports SGMII MAC-side autonegotiation on each individual
port, downshifting, can set the blinking pattern of each of its 4 LEDs,
SyncE, 1000BASE-T Ring Resiliency as well as HP Auto-MDIX detection.
This adds support for 10BASE-T, 100BASE-TX, and 1000BASE-T,
QSGMII link with the MAC, downshifting, HP Auto-MDIX detection
and blinking pattern for its 4 LEDs.
The GPIO register bank is a set of registers that are common to all PHYs
in the package. So any modification in any register of this bank affects
all PHYs of the package.
If the PHYs haven't been reset before booting the Linux kernel and were
configured to use interrupts for e.g. link status updates, it is
required to clear the interrupts mask register of all PHYs before being
able to use interrupts with any PHY. The first PHY of the package that
will be init will take care of clearing all PHYs interrupts mask
registers. Thus, we need to keep track of the init sequence in the
package, if it's already been done or if it's to be done.
Most of the init sequence of a PHY of the package is common to all PHYs
in the package, thus we use the SMI broadcast feature which enables us
to propagate a write in one register of one PHY to all PHYs in the same
package.
Signed-off-by: Kavya Sree Kotagiri <kavyasree.kotagiri@microchip.com>
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Co-developed-by: Quentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-22 14:51:35 +03:00
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Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs
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2016-08-05 15:24:21 +03:00
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2016-08-19 00:56:05 +03:00
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config NATIONAL_PHY
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2016-08-19 00:56:06 +03:00
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tristate "National Semiconductor PHYs"
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2020-06-13 19:50:22 +03:00
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help
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2016-08-19 00:56:05 +03:00
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Currently supports the DP83865 PHY.
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2019-05-24 17:22:28 +03:00
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config NXP_TJA11XX_PHY
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tristate "NXP TJA11xx PHYs support"
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depends on HWMON
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2020-06-13 19:50:22 +03:00
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help
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2019-05-24 17:22:28 +03:00
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Currently supports the NXP TJA1100 and TJA1101 PHY.
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2019-11-07 01:36:12 +03:00
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config AT803X_PHY
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tristate "Qualcomm Atheros AR803X PHYs"
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2019-11-07 16:03:44 +03:00
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depends on REGULATOR
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2019-11-07 01:36:12 +03:00
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help
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2019-11-07 01:36:15 +03:00
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Currently supports the AR8030, AR8031, AR8033 and AR8035 model
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2019-11-07 01:36:12 +03:00
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2016-08-19 00:56:05 +03:00
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config QSEMI_PHY
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2016-08-19 00:56:06 +03:00
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tristate "Quality Semiconductor PHYs"
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2020-06-13 19:50:22 +03:00
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help
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2016-08-19 00:56:05 +03:00
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Currently supports the qs6612
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config REALTEK_PHY
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2016-08-19 00:56:06 +03:00
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tristate "Realtek PHYs"
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2020-06-13 19:50:22 +03:00
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help
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2016-08-19 00:56:05 +03:00
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Supports the Realtek 821x PHY.
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2017-10-08 16:40:08 +03:00
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config RENESAS_PHY
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2020-08-27 05:00:32 +03:00
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tristate "Renesas PHYs"
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2020-06-13 19:50:22 +03:00
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help
|
2017-10-08 16:40:08 +03:00
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Supports the Renesas PHYs uPD60620 and uPD60620A.
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2017-08-10 16:56:40 +03:00
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config ROCKCHIP_PHY
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2020-08-27 05:00:32 +03:00
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tristate "Rockchip Ethernet PHYs"
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2020-06-13 19:50:22 +03:00
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help
|
2019-09-23 18:52:43 +03:00
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|
Currently supports the integrated Ethernet PHY.
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2017-08-10 16:56:40 +03:00
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|
2016-08-19 00:56:05 +03:00
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config SMSC_PHY
|
2016-08-19 00:56:06 +03:00
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|
tristate "SMSC PHYs"
|
2020-06-13 19:50:22 +03:00
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|
help
|
2016-08-19 00:56:05 +03:00
|
|
|
Currently supports the LAN83C185, LAN8187 and LAN8700 PHYs
|
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config STE10XP
|
2016-08-19 00:56:06 +03:00
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|
tristate "STMicroelectronics STe10Xp PHYs"
|
2020-06-13 19:50:22 +03:00
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|
help
|
2016-08-19 00:56:05 +03:00
|
|
|
This is the driver for the STe100p and STe101p PHYs.
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|
|
config TERANETICS_PHY
|
2017-08-14 16:43:00 +03:00
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|
|
tristate "Teranetics PHYs"
|
2020-06-13 19:50:22 +03:00
|
|
|
help
|
2017-08-14 16:43:00 +03:00
|
|
|
Currently supports the Teranetics TN2020
|
2016-08-19 00:56:05 +03:00
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|
|
|
2020-08-27 05:00:32 +03:00
|
|
|
config DP83822_PHY
|
|
|
|
tristate "Texas Instruments DP83822/825/826 PHYs"
|
|
|
|
help
|
|
|
|
Supports the DP83822, DP83825I, DP83825CM, DP83825CS, DP83825S,
|
|
|
|
DP83826C and DP83826NC PHYs.
|
|
|
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|
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|
|
config DP83TC811_PHY
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|
|
|
tristate "Texas Instruments DP83TC811 PHY"
|
|
|
|
help
|
|
|
|
Supports the DP83TC811 PHY.
|
|
|
|
|
|
|
|
config DP83848_PHY
|
|
|
|
tristate "Texas Instruments DP83848 PHY"
|
|
|
|
help
|
|
|
|
Supports the DP83848 PHY.
|
|
|
|
|
|
|
|
config DP83867_PHY
|
|
|
|
tristate "Texas Instruments DP83867 Gigabit PHY"
|
|
|
|
help
|
|
|
|
Currently supports the DP83867 PHY.
|
|
|
|
|
|
|
|
config DP83869_PHY
|
|
|
|
tristate "Texas Instruments DP83869 Gigabit PHY"
|
|
|
|
help
|
|
|
|
Currently supports the DP83869 PHY. This PHY supports copper and
|
|
|
|
fiber connections.
|
|
|
|
|
2016-08-19 00:56:05 +03:00
|
|
|
config VITESSE_PHY
|
2017-08-14 16:43:00 +03:00
|
|
|
tristate "Vitesse PHYs"
|
2020-06-13 19:50:22 +03:00
|
|
|
help
|
2017-08-14 16:43:00 +03:00
|
|
|
Currently supports the vsc8244
|
2016-08-19 00:56:05 +03:00
|
|
|
|
2016-08-10 08:50:08 +03:00
|
|
|
config XILINX_GMII2RGMII
|
2017-08-14 16:43:00 +03:00
|
|
|
tristate "Xilinx GMII2RGMII converter driver"
|
2020-06-13 19:50:22 +03:00
|
|
|
help
|
2017-08-14 16:43:00 +03:00
|
|
|
This driver support xilinx GMII to RGMII IP core it provides
|
|
|
|
the Reduced Gigabit Media Independent Interface(RGMII) between
|
|
|
|
Ethernet physical media devices and the Gigabit Ethernet controller.
|
2016-08-10 08:50:08 +03:00
|
|
|
|
2007-05-11 09:52:55 +04:00
|
|
|
endif # PHYLIB
|
2011-12-18 11:33:41 +04:00
|
|
|
|
|
|
|
config MICREL_KS8995MA
|
|
|
|
tristate "Micrel KS8995MA 5-ports 10/100 managed Ethernet switch"
|
|
|
|
depends on SPI
|