2019-01-21 21:05:50 +03:00
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// SPDX-License-Identifier: GPL-2.0+
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2006-10-03 19:18:13 +04:00
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/*
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* drivers/net/phy/broadcom.c
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*
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* Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
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* transceivers.
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*
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* Copyright (c) 2006 Maciej W. Rozycki
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*
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* Inspired by code written by Amy Fong.
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*/
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2015-10-06 22:25:48 +03:00
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#include "bcm-phy-lib.h"
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2006-10-03 19:18:13 +04:00
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#include <linux/module.h>
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#include <linux/phy.h>
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2009-11-02 17:30:00 +03:00
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#include <linux/brcmphy.h>
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2016-11-04 08:10:58 +03:00
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#include <linux/of.h>
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2009-08-25 14:11:26 +04:00
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#define BRCM_PHY_MODEL(phydev) \
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((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
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2009-11-02 17:31:39 +03:00
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#define BRCM_PHY_REV(phydev) \
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((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
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2006-10-03 19:18:13 +04:00
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MODULE_DESCRIPTION("Broadcom PHY driver");
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MODULE_AUTHOR("Maciej W. Rozycki");
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MODULE_LICENSE("GPL");
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2019-10-03 21:43:51 +03:00
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static int bcm54xx_config_clock_delay(struct phy_device *phydev);
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2017-01-27 16:07:01 +03:00
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static int bcm54210e_config_init(struct phy_device *phydev)
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{
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int val;
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2019-10-03 21:43:51 +03:00
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bcm54xx_config_clock_delay(phydev);
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2017-01-27 16:07:01 +03:00
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2017-10-12 11:21:25 +03:00
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if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) {
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val = phy_read(phydev, MII_CTRL1000);
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val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
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phy_write(phydev, MII_CTRL1000, val);
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}
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2017-01-27 16:07:01 +03:00
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return 0;
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}
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2017-02-01 00:54:54 +03:00
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static int bcm54612e_config_init(struct phy_device *phydev)
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{
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2018-06-04 23:17:04 +03:00
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int reg;
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2019-10-03 21:43:52 +03:00
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bcm54xx_config_clock_delay(phydev);
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2017-02-01 00:54:54 +03:00
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2018-06-04 23:17:04 +03:00
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/* Enable CLK125 MUX on LED4 if ref clock is enabled. */
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if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
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int err;
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reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
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err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
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BCM54612E_LED4_CLK125OUT_EN | reg);
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if (err < 0)
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return err;
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}
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2017-02-01 00:54:54 +03:00
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return 0;
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}
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2018-11-06 01:35:40 +03:00
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static int bcm54xx_config_clock_delay(struct phy_device *phydev)
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2016-11-04 08:10:58 +03:00
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{
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int rc, val;
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2017-04-30 08:34:21 +03:00
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/* handling PHY's internal RX clock delay */
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2016-11-04 08:10:58 +03:00
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val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
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val |= MII_BCM54XX_AUXCTL_MISC_WREN;
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2017-04-30 08:34:21 +03:00
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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/* Disable RGMII RXC-RXD skew */
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val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
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}
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
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/* Enable RGMII RXC-RXD skew */
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val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
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}
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2016-11-04 08:10:58 +03:00
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rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
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val);
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if (rc < 0)
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return rc;
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2017-04-30 08:34:21 +03:00
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/* handling PHY's internal TX clock delay */
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2016-11-04 08:10:58 +03:00
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val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
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2017-04-30 08:34:21 +03:00
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
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/* Disable internal TX clock delay */
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val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
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}
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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/* Enable internal TX clock delay */
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val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN;
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}
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2016-11-04 08:10:58 +03:00
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rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
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if (rc < 0)
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return rc;
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return 0;
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}
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2009-11-02 17:28:04 +03:00
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/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
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2008-11-04 03:56:51 +03:00
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static int bcm50610_a0_workaround(struct phy_device *phydev)
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{
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int err;
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2015-10-06 22:25:48 +03:00
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err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,
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2008-11-04 03:56:51 +03:00
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MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
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MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
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if (err < 0)
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2009-11-02 17:28:04 +03:00
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return err;
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2008-11-04 03:56:51 +03:00
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2015-10-06 22:25:48 +03:00
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err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,
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MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
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2008-11-04 03:56:51 +03:00
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if (err < 0)
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2009-11-02 17:28:04 +03:00
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return err;
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2008-11-04 03:56:51 +03:00
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2015-10-06 22:25:48 +03:00
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err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,
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2008-11-04 03:56:51 +03:00
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MII_BCM54XX_EXP_EXP75_VDACCTRL);
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if (err < 0)
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2009-11-02 17:28:04 +03:00
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return err;
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2008-11-04 03:56:51 +03:00
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2015-10-06 22:25:48 +03:00
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err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,
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2008-11-04 03:56:51 +03:00
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MII_BCM54XX_EXP_EXP96_MYST);
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if (err < 0)
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2009-11-02 17:28:04 +03:00
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return err;
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2008-11-04 03:56:51 +03:00
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2015-10-06 22:25:48 +03:00
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err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,
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2008-11-04 03:56:51 +03:00
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MII_BCM54XX_EXP_EXP97_MYST);
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2009-11-02 17:28:04 +03:00
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return err;
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}
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static int bcm54xx_phydsp_config(struct phy_device *phydev)
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{
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int err, err2;
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/* Enable the SMDSP clock */
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err = bcm54xx_auxctl_write(phydev,
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MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
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MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
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MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
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if (err < 0)
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return err;
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2009-11-02 17:28:33 +03:00
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if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
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BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
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/* Clear bit 9 to fix a phy interop issue. */
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2015-10-06 22:25:48 +03:00
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err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,
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2009-11-02 17:28:33 +03:00
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MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
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if (err < 0)
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goto error;
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if (phydev->drv->phy_id == PHY_ID_BCM50610) {
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err = bcm50610_a0_workaround(phydev);
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if (err < 0)
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goto error;
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}
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}
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2009-11-02 17:28:04 +03:00
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if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
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int val;
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2015-10-06 22:25:48 +03:00
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val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);
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2009-11-02 17:28:04 +03:00
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if (val < 0)
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goto error;
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val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
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2015-10-06 22:25:48 +03:00
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err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);
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2009-11-02 17:28:04 +03:00
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}
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2008-11-04 03:56:51 +03:00
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error:
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2009-11-02 17:28:04 +03:00
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/* Disable the SMDSP clock */
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err2 = bcm54xx_auxctl_write(phydev,
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MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
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MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
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2008-11-04 03:56:51 +03:00
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2009-11-02 17:28:04 +03:00
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/* Return the first error reported. */
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return err ? err : err2;
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2008-11-04 03:56:51 +03:00
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}
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2009-11-02 17:31:39 +03:00
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static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
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{
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2009-12-19 07:16:10 +03:00
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u32 orig;
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int val;
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2009-11-02 17:32:12 +03:00
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bool clk125en = true;
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2009-11-02 17:31:39 +03:00
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/* Abort if we are using an untested phy. */
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2009-12-30 09:43:06 +03:00
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if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
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BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
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2020-02-19 23:00:47 +03:00
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BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M &&
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2020-05-15 20:24:47 +03:00
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BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54810 &&
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BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811)
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2009-11-02 17:31:39 +03:00
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return;
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2015-10-06 22:25:48 +03:00
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val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
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2009-11-02 17:31:39 +03:00
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if (val < 0)
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return;
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orig = val;
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2009-11-02 17:32:12 +03:00
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if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
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BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
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BRCM_PHY_REV(phydev) >= 0x3) {
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/*
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* Here, bit 0 _disables_ CLK125 when set.
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* This bit is set by default.
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*/
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clk125en = false;
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} else {
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if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
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2020-05-15 20:24:47 +03:00
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if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811) {
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/* Here, bit 0 _enables_ CLK125 when set */
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val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
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}
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2009-11-02 17:32:12 +03:00
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clk125en = false;
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2009-11-02 17:31:39 +03:00
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}
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}
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2012-02-09 15:17:23 +04:00
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if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
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2009-11-02 17:32:12 +03:00
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val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
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else
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val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
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2020-05-15 20:24:47 +03:00
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if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) {
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if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 ||
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BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54811)
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val |= BCM54810_SHD_SCR3_TRDDAPD;
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else
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val |= BCM54XX_SHD_SCR3_TRDDAPD;
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}
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2009-11-02 17:32:38 +03:00
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2009-11-02 17:31:39 +03:00
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if (orig != val)
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2015-10-06 22:25:48 +03:00
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bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
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2009-11-02 17:32:12 +03:00
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2015-10-06 22:25:48 +03:00
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val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
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2009-11-02 17:32:12 +03:00
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if (val < 0)
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return;
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orig = val;
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2012-02-09 15:17:23 +04:00
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if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
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2009-11-02 17:32:12 +03:00
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val |= BCM54XX_SHD_APD_EN;
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else
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val &= ~BCM54XX_SHD_APD_EN;
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if (orig != val)
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2015-10-06 22:25:48 +03:00
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bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
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2009-11-02 17:31:39 +03:00
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}
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2006-10-03 19:18:13 +04:00
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static int bcm54xx_config_init(struct phy_device *phydev)
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{
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2017-04-30 08:34:21 +03:00
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int reg, err, val;
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2006-10-03 19:18:13 +04:00
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reg = phy_read(phydev, MII_BCM54XX_ECR);
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if (reg < 0)
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return reg;
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/* Mask interrupts globally. */
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reg |= MII_BCM54XX_ECR_IM;
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err = phy_write(phydev, MII_BCM54XX_ECR, reg);
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if (err < 0)
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return err;
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/* Unmask events we are interested in. */
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reg = ~(MII_BCM54XX_INT_DUPLEX |
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MII_BCM54XX_INT_SPEED |
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MII_BCM54XX_INT_LINK);
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err = phy_write(phydev, MII_BCM54XX_IMR, reg);
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if (err < 0)
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return err;
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2008-11-04 03:56:51 +03:00
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2009-11-02 17:30:40 +03:00
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|
|
if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
|
|
|
|
BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
|
|
|
|
(phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
|
2015-10-06 22:25:48 +03:00
|
|
|
bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);
|
2009-11-02 17:30:40 +03:00
|
|
|
|
2020-02-19 23:00:48 +03:00
|
|
|
bcm54xx_adjust_rxrefclk(phydev);
|
2009-11-02 17:31:39 +03:00
|
|
|
|
2017-01-27 16:07:01 +03:00
|
|
|
if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E) {
|
|
|
|
err = bcm54210e_config_init(phydev);
|
|
|
|
if (err)
|
|
|
|
return err;
|
2017-02-01 00:54:54 +03:00
|
|
|
} else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54612E) {
|
|
|
|
err = bcm54612e_config_init(phydev);
|
|
|
|
if (err)
|
|
|
|
return err;
|
2017-01-27 16:07:01 +03:00
|
|
|
} else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
|
2017-04-30 08:34:21 +03:00
|
|
|
/* For BCM54810, we need to disable BroadR-Reach function */
|
|
|
|
val = bcm_phy_read_exp(phydev,
|
|
|
|
BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
|
|
|
|
val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
|
|
|
|
err = bcm_phy_write_exp(phydev,
|
|
|
|
BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
|
|
|
|
val);
|
|
|
|
if (err < 0)
|
2016-11-04 08:10:58 +03:00
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2009-11-02 17:28:04 +03:00
|
|
|
bcm54xx_phydsp_config(phydev);
|
2009-08-25 14:11:26 +04:00
|
|
|
|
2019-03-24 01:18:46 +03:00
|
|
|
/* Encode link speed into LED1 and LED3 pair (green/amber).
|
|
|
|
* Also flash these two LEDs on activity. This means configuring
|
|
|
|
* them for MULTICOLOR and encoding link/activity into them.
|
|
|
|
*/
|
|
|
|
val = BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_MULTICOLOR1) |
|
|
|
|
BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_MULTICOLOR1);
|
|
|
|
bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1, val);
|
|
|
|
|
|
|
|
val = BCM_LED_MULTICOLOR_IN_PHASE |
|
|
|
|
BCM5482_SHD_LEDS1_LED1(BCM_LED_MULTICOLOR_LINK_ACT) |
|
|
|
|
BCM5482_SHD_LEDS1_LED3(BCM_LED_MULTICOLOR_LINK_ACT);
|
|
|
|
bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val);
|
|
|
|
|
2006-10-03 19:18:13 +04:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-02-19 23:00:49 +03:00
|
|
|
static int bcm54xx_resume(struct phy_device *phydev)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Writes to register other than BMCR would be ignored
|
|
|
|
* unless we clear the PDOWN bit first
|
|
|
|
*/
|
|
|
|
ret = genphy_resume(phydev);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return bcm54xx_config_init(phydev);
|
|
|
|
}
|
|
|
|
|
2020-05-15 20:24:47 +03:00
|
|
|
static int bcm54811_config_init(struct phy_device *phydev)
|
|
|
|
{
|
|
|
|
int err, reg;
|
|
|
|
|
|
|
|
/* Disable BroadR-Reach function. */
|
|
|
|
reg = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
|
|
|
|
reg &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
|
|
|
|
err = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
|
|
|
|
reg);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
err = bcm54xx_config_init(phydev);
|
|
|
|
|
|
|
|
/* Enable CLK125 MUX on LED4 if ref clock is enabled. */
|
|
|
|
if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
|
|
|
|
reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
|
|
|
|
err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
|
|
|
|
BCM54612E_LED4_CLK125OUT_EN | reg);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
2020-05-16 05:09:26 +03:00
|
|
|
}
|
2020-05-15 20:24:47 +03:00
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2008-05-17 09:40:39 +04:00
|
|
|
static int bcm5482_config_init(struct phy_device *phydev)
|
|
|
|
{
|
|
|
|
int err, reg;
|
|
|
|
|
|
|
|
err = bcm54xx_config_init(phydev);
|
|
|
|
|
|
|
|
if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
|
|
|
|
/*
|
|
|
|
* Enable secondary SerDes and its use as an LED source
|
|
|
|
*/
|
2015-10-06 22:25:48 +03:00
|
|
|
reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_SSD);
|
|
|
|
bcm_phy_write_shadow(phydev, BCM5482_SHD_SSD,
|
2008-05-17 09:40:39 +04:00
|
|
|
reg |
|
|
|
|
BCM5482_SHD_SSD_LEDM |
|
|
|
|
BCM5482_SHD_SSD_EN);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable SGMII slave mode and auto-detection
|
|
|
|
*/
|
2008-11-04 03:56:29 +03:00
|
|
|
reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD;
|
2015-10-06 22:25:48 +03:00
|
|
|
err = bcm_phy_read_exp(phydev, reg);
|
2008-11-04 03:56:29 +03:00
|
|
|
if (err < 0)
|
|
|
|
return err;
|
2015-10-06 22:25:48 +03:00
|
|
|
err = bcm_phy_write_exp(phydev, reg, err |
|
2008-11-04 03:56:29 +03:00
|
|
|
BCM5482_SSD_SGMII_SLAVE_EN |
|
|
|
|
BCM5482_SSD_SGMII_SLAVE_AD);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
2008-05-17 09:40:39 +04:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable secondary SerDes powerdown
|
|
|
|
*/
|
2008-11-04 03:56:29 +03:00
|
|
|
reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD;
|
2015-10-06 22:25:48 +03:00
|
|
|
err = bcm_phy_read_exp(phydev, reg);
|
2008-11-04 03:56:29 +03:00
|
|
|
if (err < 0)
|
|
|
|
return err;
|
2015-10-06 22:25:48 +03:00
|
|
|
err = bcm_phy_write_exp(phydev, reg,
|
2008-11-04 03:56:29 +03:00
|
|
|
err & ~BCM5482_SSD_1000BX_CTL_PWRDOWN);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
2008-05-17 09:40:39 +04:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Select 1000BASE-X register set (primary SerDes)
|
|
|
|
*/
|
2019-10-22 21:31:08 +03:00
|
|
|
reg = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
|
|
|
|
bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE,
|
|
|
|
reg | BCM54XX_SHD_MODE_1000BX);
|
2008-05-17 09:40:39 +04:00
|
|
|
|
|
|
|
/*
|
|
|
|
* LED1=ACTIVITYLED, LED3=LINKSPD[2]
|
|
|
|
* (Use LED1 as secondary SerDes ACTIVITY LED)
|
|
|
|
*/
|
2015-10-06 22:25:48 +03:00
|
|
|
bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1,
|
2008-05-17 09:40:39 +04:00
|
|
|
BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) |
|
|
|
|
BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Auto-negotiation doesn't seem to work quite right
|
|
|
|
* in this mode, so we disable it and force it to the
|
|
|
|
* right speed/duplex setting. Only 'link status'
|
|
|
|
* is important.
|
|
|
|
*/
|
|
|
|
phydev->autoneg = AUTONEG_DISABLE;
|
|
|
|
phydev->speed = SPEED_1000;
|
|
|
|
phydev->duplex = DUPLEX_FULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bcm5482_read_status(struct phy_device *phydev)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
|
|
|
err = genphy_read_status(phydev);
|
|
|
|
|
|
|
|
if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
|
|
|
|
/*
|
|
|
|
* Only link status matters for 1000Base-X mode, so force
|
|
|
|
* 1000 Mbit/s full-duplex status
|
|
|
|
*/
|
|
|
|
if (phydev->link) {
|
|
|
|
phydev->speed = SPEED_1000;
|
|
|
|
phydev->duplex = DUPLEX_FULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2008-03-04 19:41:32 +03:00
|
|
|
static int bcm5481_config_aneg(struct phy_device *phydev)
|
|
|
|
{
|
2016-11-04 08:10:58 +03:00
|
|
|
struct device_node *np = phydev->mdio.dev.of_node;
|
2008-03-04 19:41:32 +03:00
|
|
|
int ret;
|
|
|
|
|
2020-02-18 18:47:01 +03:00
|
|
|
/* Aneg firstly. */
|
2008-03-04 19:41:32 +03:00
|
|
|
ret = genphy_config_aneg(phydev);
|
|
|
|
|
|
|
|
/* Then we can set up the delay. */
|
2018-11-06 01:35:40 +03:00
|
|
|
bcm54xx_config_clock_delay(phydev);
|
2008-03-04 19:41:32 +03:00
|
|
|
|
2016-11-04 08:10:58 +03:00
|
|
|
if (of_property_read_bool(np, "enet-phy-lane-swap")) {
|
|
|
|
/* Lane Swap - Undocumented register...magic! */
|
|
|
|
ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
|
|
|
|
0x11B);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2008-03-04 19:41:32 +03:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2019-10-22 21:31:08 +03:00
|
|
|
static int bcm54616s_probe(struct phy_device *phydev)
|
|
|
|
{
|
|
|
|
int val, intf_sel;
|
|
|
|
|
|
|
|
val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
|
|
|
|
if (val < 0)
|
|
|
|
return val;
|
|
|
|
|
|
|
|
/* The PHY is strapped in RGMII-fiber mode when INTERF_SEL[1:0]
|
|
|
|
* is 01b, and the link between PHY and its link partner can be
|
|
|
|
* either 1000Base-X or 100Base-FX.
|
|
|
|
* RGMII-1000Base-X is properly supported, but RGMII-100Base-FX
|
|
|
|
* support is still missing as of now.
|
|
|
|
*/
|
|
|
|
intf_sel = (val & BCM54XX_SHD_INTF_SEL_MASK) >> 1;
|
|
|
|
if (intf_sel == 1) {
|
|
|
|
val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL);
|
|
|
|
if (val < 0)
|
|
|
|
return val;
|
|
|
|
|
|
|
|
/* Bit 0 of the SerDes 100-FX Control register, when set
|
|
|
|
* to 1, sets the MII/RGMII -> 100BASE-FX configuration.
|
|
|
|
* When this bit is set to 0, it sets the GMII/RGMII ->
|
|
|
|
* 1000BASE-X configuration.
|
|
|
|
*/
|
|
|
|
if (!(val & BCM54616S_100FX_MODE))
|
|
|
|
phydev->dev_flags |= PHY_BCM_FLAGS_MODE_1000BX;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-11-06 01:35:40 +03:00
|
|
|
static int bcm54616s_config_aneg(struct phy_device *phydev)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2020-02-18 18:47:01 +03:00
|
|
|
/* Aneg firstly. */
|
2019-10-22 21:31:08 +03:00
|
|
|
if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX)
|
|
|
|
ret = genphy_c37_config_aneg(phydev);
|
|
|
|
else
|
|
|
|
ret = genphy_config_aneg(phydev);
|
2018-11-06 01:35:40 +03:00
|
|
|
|
|
|
|
/* Then we can set up the delay. */
|
|
|
|
bcm54xx_config_clock_delay(phydev);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2019-10-22 21:31:08 +03:00
|
|
|
static int bcm54616s_read_status(struct phy_device *phydev)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
|
|
|
if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX)
|
|
|
|
err = genphy_c37_read_status(phydev);
|
|
|
|
else
|
|
|
|
err = genphy_read_status(phydev);
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2009-08-25 14:10:58 +04:00
|
|
|
static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
|
|
|
|
{
|
|
|
|
int val;
|
|
|
|
|
|
|
|
val = phy_read(phydev, reg);
|
|
|
|
if (val < 0)
|
|
|
|
return val;
|
|
|
|
|
|
|
|
return phy_write(phydev, reg, val | set);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int brcm_fet_config_init(struct phy_device *phydev)
|
|
|
|
{
|
|
|
|
int reg, err, err2, brcmtest;
|
|
|
|
|
|
|
|
/* Reset the PHY to bring it to a known state. */
|
|
|
|
err = phy_write(phydev, MII_BMCR, BMCR_RESET);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
reg = phy_read(phydev, MII_BRCM_FET_INTREG);
|
|
|
|
if (reg < 0)
|
|
|
|
return reg;
|
|
|
|
|
|
|
|
/* Unmask events we are interested in and mask interrupts globally. */
|
|
|
|
reg = MII_BRCM_FET_IR_DUPLEX_EN |
|
|
|
|
MII_BRCM_FET_IR_SPEED_EN |
|
|
|
|
MII_BRCM_FET_IR_LINK_EN |
|
|
|
|
MII_BRCM_FET_IR_ENABLE |
|
|
|
|
MII_BRCM_FET_IR_MASK;
|
|
|
|
|
|
|
|
err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
/* Enable shadow register access */
|
|
|
|
brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
|
|
|
|
if (brcmtest < 0)
|
|
|
|
return brcmtest;
|
|
|
|
|
|
|
|
reg = brcmtest | MII_BRCM_FET_BT_SRE;
|
|
|
|
|
|
|
|
err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
/* Set the LED mode */
|
|
|
|
reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
|
|
|
|
if (reg < 0) {
|
|
|
|
err = reg;
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
|
|
|
|
reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
|
|
|
|
|
|
|
|
err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
|
|
|
|
if (err < 0)
|
|
|
|
goto done;
|
|
|
|
|
|
|
|
/* Enable auto MDIX */
|
|
|
|
err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
|
|
|
|
MII_BRCM_FET_SHDW_MC_FAME);
|
|
|
|
if (err < 0)
|
|
|
|
goto done;
|
|
|
|
|
2009-11-02 17:31:11 +03:00
|
|
|
if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
|
|
|
|
/* Enable auto power down */
|
|
|
|
err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
|
|
|
|
MII_BRCM_FET_SHDW_AS2_APDE);
|
|
|
|
}
|
2009-08-25 14:10:58 +04:00
|
|
|
|
|
|
|
done:
|
|
|
|
/* Disable shadow register access */
|
|
|
|
err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
|
|
|
|
if (!err)
|
|
|
|
err = err2;
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int brcm_fet_ack_interrupt(struct phy_device *phydev)
|
|
|
|
{
|
|
|
|
int reg;
|
|
|
|
|
|
|
|
/* Clear pending interrupts. */
|
|
|
|
reg = phy_read(phydev, MII_BRCM_FET_INTREG);
|
|
|
|
if (reg < 0)
|
|
|
|
return reg;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int brcm_fet_config_intr(struct phy_device *phydev)
|
|
|
|
{
|
|
|
|
int reg, err;
|
|
|
|
|
|
|
|
reg = phy_read(phydev, MII_BRCM_FET_INTREG);
|
|
|
|
if (reg < 0)
|
|
|
|
return reg;
|
|
|
|
|
|
|
|
if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
|
|
|
|
reg &= ~MII_BRCM_FET_IR_MASK;
|
|
|
|
else
|
|
|
|
reg |= MII_BRCM_FET_IR_MASK;
|
|
|
|
|
|
|
|
err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2017-12-15 04:48:16 +03:00
|
|
|
struct bcm53xx_phy_priv {
|
|
|
|
u64 *stats;
|
|
|
|
};
|
|
|
|
|
|
|
|
static int bcm53xx_phy_probe(struct phy_device *phydev)
|
|
|
|
{
|
|
|
|
struct bcm53xx_phy_priv *priv;
|
|
|
|
|
|
|
|
priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
|
|
|
|
if (!priv)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
phydev->priv = priv;
|
|
|
|
|
|
|
|
priv->stats = devm_kcalloc(&phydev->mdio.dev,
|
|
|
|
bcm_phy_get_sset_count(phydev), sizeof(u64),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!priv->stats)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void bcm53xx_phy_get_stats(struct phy_device *phydev,
|
|
|
|
struct ethtool_stats *stats, u64 *data)
|
|
|
|
{
|
|
|
|
struct bcm53xx_phy_priv *priv = phydev->priv;
|
|
|
|
|
|
|
|
bcm_phy_get_stats(phydev, priv->stats, stats, data);
|
|
|
|
}
|
|
|
|
|
2012-07-04 09:44:34 +04:00
|
|
|
static struct phy_driver broadcom_drivers[] = {
|
|
|
|
{
|
2010-06-17 03:02:23 +04:00
|
|
|
.phy_id = PHY_ID_BCM5411,
|
2006-10-03 19:18:13 +04:00
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
.name = "Broadcom BCM5411",
|
2019-04-12 21:47:03 +03:00
|
|
|
/* PHY_GBIT_FEATURES */
|
2006-10-03 19:18:13 +04:00
|
|
|
.config_init = bcm54xx_config_init,
|
2015-10-06 22:25:48 +03:00
|
|
|
.ack_interrupt = bcm_phy_ack_intr,
|
|
|
|
.config_intr = bcm_phy_config_intr,
|
2012-07-04 09:44:34 +04:00
|
|
|
}, {
|
2010-06-17 03:02:23 +04:00
|
|
|
.phy_id = PHY_ID_BCM5421,
|
2006-10-03 19:18:13 +04:00
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
.name = "Broadcom BCM5421",
|
2019-04-12 21:47:03 +03:00
|
|
|
/* PHY_GBIT_FEATURES */
|
2006-10-03 19:18:13 +04:00
|
|
|
.config_init = bcm54xx_config_init,
|
2015-10-06 22:25:48 +03:00
|
|
|
.ack_interrupt = bcm_phy_ack_intr,
|
|
|
|
.config_intr = bcm_phy_config_intr,
|
2017-01-27 16:07:01 +03:00
|
|
|
}, {
|
|
|
|
.phy_id = PHY_ID_BCM54210E,
|
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
.name = "Broadcom BCM54210E",
|
2019-04-12 21:47:03 +03:00
|
|
|
/* PHY_GBIT_FEATURES */
|
2017-01-27 16:07:01 +03:00
|
|
|
.config_init = bcm54xx_config_init,
|
|
|
|
.ack_interrupt = bcm_phy_ack_intr,
|
|
|
|
.config_intr = bcm_phy_config_intr,
|
2012-07-04 09:44:34 +04:00
|
|
|
}, {
|
2010-06-17 03:02:23 +04:00
|
|
|
.phy_id = PHY_ID_BCM5461,
|
2006-10-03 19:18:13 +04:00
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
.name = "Broadcom BCM5461",
|
2019-04-12 21:47:03 +03:00
|
|
|
/* PHY_GBIT_FEATURES */
|
2006-10-03 19:18:13 +04:00
|
|
|
.config_init = bcm54xx_config_init,
|
2015-10-06 22:25:48 +03:00
|
|
|
.ack_interrupt = bcm_phy_ack_intr,
|
|
|
|
.config_intr = bcm_phy_config_intr,
|
2016-10-21 20:20:13 +03:00
|
|
|
}, {
|
|
|
|
.phy_id = PHY_ID_BCM54612E,
|
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
.name = "Broadcom BCM54612E",
|
2019-04-12 21:47:03 +03:00
|
|
|
/* PHY_GBIT_FEATURES */
|
2016-10-21 20:20:13 +03:00
|
|
|
.config_init = bcm54xx_config_init,
|
|
|
|
.ack_interrupt = bcm_phy_ack_intr,
|
|
|
|
.config_intr = bcm_phy_config_intr,
|
2015-04-08 13:15:18 +03:00
|
|
|
}, {
|
|
|
|
.phy_id = PHY_ID_BCM54616S,
|
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
.name = "Broadcom BCM54616S",
|
2019-04-12 21:47:03 +03:00
|
|
|
/* PHY_GBIT_FEATURES */
|
2015-04-08 13:15:18 +03:00
|
|
|
.config_init = bcm54xx_config_init,
|
2018-11-06 01:35:40 +03:00
|
|
|
.config_aneg = bcm54616s_config_aneg,
|
2015-10-06 22:25:48 +03:00
|
|
|
.ack_interrupt = bcm_phy_ack_intr,
|
|
|
|
.config_intr = bcm_phy_config_intr,
|
2019-10-22 21:31:08 +03:00
|
|
|
.read_status = bcm54616s_read_status,
|
|
|
|
.probe = bcm54616s_probe,
|
2012-07-04 09:44:34 +04:00
|
|
|
}, {
|
2010-06-17 03:02:23 +04:00
|
|
|
.phy_id = PHY_ID_BCM5464,
|
2008-04-15 07:35:41 +04:00
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
.name = "Broadcom BCM5464",
|
2019-04-12 21:47:03 +03:00
|
|
|
/* PHY_GBIT_FEATURES */
|
2008-04-15 07:35:41 +04:00
|
|
|
.config_init = bcm54xx_config_init,
|
2015-10-06 22:25:48 +03:00
|
|
|
.ack_interrupt = bcm_phy_ack_intr,
|
|
|
|
.config_intr = bcm_phy_config_intr,
|
2019-06-08 16:53:56 +03:00
|
|
|
.suspend = genphy_suspend,
|
|
|
|
.resume = genphy_resume,
|
2012-07-04 09:44:34 +04:00
|
|
|
}, {
|
2010-06-17 03:02:23 +04:00
|
|
|
.phy_id = PHY_ID_BCM5481,
|
2008-03-04 19:41:32 +03:00
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
.name = "Broadcom BCM5481",
|
2019-04-12 21:47:03 +03:00
|
|
|
/* PHY_GBIT_FEATURES */
|
2008-03-04 19:41:32 +03:00
|
|
|
.config_init = bcm54xx_config_init,
|
2017-12-02 12:50:37 +03:00
|
|
|
.config_aneg = bcm5481_config_aneg,
|
2015-10-06 22:25:48 +03:00
|
|
|
.ack_interrupt = bcm_phy_ack_intr,
|
|
|
|
.config_intr = bcm_phy_config_intr,
|
2016-11-04 08:10:58 +03:00
|
|
|
}, {
|
|
|
|
.phy_id = PHY_ID_BCM54810,
|
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
.name = "Broadcom BCM54810",
|
2019-04-12 21:47:03 +03:00
|
|
|
/* PHY_GBIT_FEATURES */
|
2016-11-04 08:10:58 +03:00
|
|
|
.config_init = bcm54xx_config_init,
|
2017-12-02 12:50:37 +03:00
|
|
|
.config_aneg = bcm5481_config_aneg,
|
2016-11-04 08:10:58 +03:00
|
|
|
.ack_interrupt = bcm_phy_ack_intr,
|
|
|
|
.config_intr = bcm_phy_config_intr,
|
2020-02-19 23:00:49 +03:00
|
|
|
.suspend = genphy_suspend,
|
|
|
|
.resume = bcm54xx_resume,
|
2020-05-15 20:24:47 +03:00
|
|
|
}, {
|
|
|
|
.phy_id = PHY_ID_BCM54811,
|
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
.name = "Broadcom BCM54811",
|
|
|
|
/* PHY_GBIT_FEATURES */
|
|
|
|
.config_init = bcm54811_config_init,
|
|
|
|
.config_aneg = bcm5481_config_aneg,
|
|
|
|
.ack_interrupt = bcm_phy_ack_intr,
|
|
|
|
.config_intr = bcm_phy_config_intr,
|
|
|
|
.suspend = genphy_suspend,
|
|
|
|
.resume = bcm54xx_resume,
|
2012-07-04 09:44:34 +04:00
|
|
|
}, {
|
2010-06-17 03:02:23 +04:00
|
|
|
.phy_id = PHY_ID_BCM5482,
|
2008-01-29 19:19:00 +03:00
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
.name = "Broadcom BCM5482",
|
2019-04-12 21:47:03 +03:00
|
|
|
/* PHY_GBIT_FEATURES */
|
2008-05-17 09:40:39 +04:00
|
|
|
.config_init = bcm5482_config_init,
|
2017-12-02 12:50:37 +03:00
|
|
|
.read_status = bcm5482_read_status,
|
2015-10-06 22:25:48 +03:00
|
|
|
.ack_interrupt = bcm_phy_ack_intr,
|
|
|
|
.config_intr = bcm_phy_config_intr,
|
2012-07-04 09:44:34 +04:00
|
|
|
}, {
|
2008-11-04 03:56:51 +03:00
|
|
|
.phy_id = PHY_ID_BCM50610,
|
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
.name = "Broadcom BCM50610",
|
2019-04-12 21:47:03 +03:00
|
|
|
/* PHY_GBIT_FEATURES */
|
2008-11-04 03:56:51 +03:00
|
|
|
.config_init = bcm54xx_config_init,
|
2015-10-06 22:25:48 +03:00
|
|
|
.ack_interrupt = bcm_phy_ack_intr,
|
|
|
|
.config_intr = bcm_phy_config_intr,
|
2012-07-04 09:44:34 +04:00
|
|
|
}, {
|
2009-08-25 14:10:30 +04:00
|
|
|
.phy_id = PHY_ID_BCM50610M,
|
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
.name = "Broadcom BCM50610M",
|
2019-04-12 21:47:03 +03:00
|
|
|
/* PHY_GBIT_FEATURES */
|
2009-08-25 14:10:30 +04:00
|
|
|
.config_init = bcm54xx_config_init,
|
2015-10-06 22:25:48 +03:00
|
|
|
.ack_interrupt = bcm_phy_ack_intr,
|
|
|
|
.config_intr = bcm_phy_config_intr,
|
2012-07-04 09:44:34 +04:00
|
|
|
}, {
|
2009-08-25 14:11:26 +04:00
|
|
|
.phy_id = PHY_ID_BCM57780,
|
2008-11-22 04:22:53 +03:00
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
.name = "Broadcom BCM57780",
|
2019-04-12 21:47:03 +03:00
|
|
|
/* PHY_GBIT_FEATURES */
|
2008-11-22 04:22:53 +03:00
|
|
|
.config_init = bcm54xx_config_init,
|
2015-10-06 22:25:48 +03:00
|
|
|
.ack_interrupt = bcm_phy_ack_intr,
|
|
|
|
.config_intr = bcm_phy_config_intr,
|
2012-07-04 09:44:34 +04:00
|
|
|
}, {
|
2010-02-17 18:17:04 +03:00
|
|
|
.phy_id = PHY_ID_BCMAC131,
|
2009-08-25 14:10:58 +04:00
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
.name = "Broadcom BCMAC131",
|
2019-04-12 21:47:03 +03:00
|
|
|
/* PHY_BASIC_FEATURES */
|
2009-08-25 14:10:58 +04:00
|
|
|
.config_init = brcm_fet_config_init,
|
|
|
|
.ack_interrupt = brcm_fet_ack_interrupt,
|
|
|
|
.config_intr = brcm_fet_config_intr,
|
2012-07-04 09:44:34 +04:00
|
|
|
}, {
|
2010-06-17 03:02:24 +04:00
|
|
|
.phy_id = PHY_ID_BCM5241,
|
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
.name = "Broadcom BCM5241",
|
2019-04-12 21:47:03 +03:00
|
|
|
/* PHY_BASIC_FEATURES */
|
2010-06-17 03:02:24 +04:00
|
|
|
.config_init = brcm_fet_config_init,
|
|
|
|
.ack_interrupt = brcm_fet_ack_interrupt,
|
|
|
|
.config_intr = brcm_fet_config_intr,
|
2017-12-15 04:48:16 +03:00
|
|
|
}, {
|
|
|
|
.phy_id = PHY_ID_BCM5395,
|
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
.name = "Broadcom BCM5395",
|
|
|
|
.flags = PHY_IS_INTERNAL,
|
2019-04-12 21:47:03 +03:00
|
|
|
/* PHY_GBIT_FEATURES */
|
2017-12-15 04:48:16 +03:00
|
|
|
.get_sset_count = bcm_phy_get_sset_count,
|
|
|
|
.get_strings = bcm_phy_get_strings,
|
|
|
|
.get_stats = bcm53xx_phy_get_stats,
|
|
|
|
.probe = bcm53xx_phy_probe,
|
2020-04-17 21:38:02 +03:00
|
|
|
}, {
|
|
|
|
.phy_id = PHY_ID_BCM53125,
|
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
.name = "Broadcom BCM53125",
|
|
|
|
.flags = PHY_IS_INTERNAL,
|
|
|
|
/* PHY_GBIT_FEATURES */
|
|
|
|
.get_sset_count = bcm_phy_get_sset_count,
|
|
|
|
.get_strings = bcm_phy_get_strings,
|
|
|
|
.get_stats = bcm53xx_phy_get_stats,
|
|
|
|
.probe = bcm53xx_phy_probe,
|
|
|
|
.config_init = bcm54xx_config_init,
|
|
|
|
.ack_interrupt = bcm_phy_ack_intr,
|
|
|
|
.config_intr = bcm_phy_config_intr,
|
2018-05-02 18:13:58 +03:00
|
|
|
}, {
|
|
|
|
.phy_id = PHY_ID_BCM89610,
|
|
|
|
.phy_id_mask = 0xfffffff0,
|
|
|
|
.name = "Broadcom BCM89610",
|
2019-04-12 21:47:03 +03:00
|
|
|
/* PHY_GBIT_FEATURES */
|
2018-05-02 18:13:58 +03:00
|
|
|
.config_init = bcm54xx_config_init,
|
|
|
|
.ack_interrupt = bcm_phy_ack_intr,
|
|
|
|
.config_intr = bcm_phy_config_intr,
|
2012-07-04 09:44:34 +04:00
|
|
|
} };
|
2010-06-17 03:02:24 +04:00
|
|
|
|
2014-11-11 21:45:59 +03:00
|
|
|
module_phy_driver(broadcom_drivers);
|
2010-04-02 05:05:56 +04:00
|
|
|
|
2010-10-04 03:43:32 +04:00
|
|
|
static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
|
2010-06-17 03:02:23 +04:00
|
|
|
{ PHY_ID_BCM5411, 0xfffffff0 },
|
|
|
|
{ PHY_ID_BCM5421, 0xfffffff0 },
|
2017-01-27 16:07:01 +03:00
|
|
|
{ PHY_ID_BCM54210E, 0xfffffff0 },
|
2010-06-17 03:02:23 +04:00
|
|
|
{ PHY_ID_BCM5461, 0xfffffff0 },
|
2016-10-21 20:20:13 +03:00
|
|
|
{ PHY_ID_BCM54612E, 0xfffffff0 },
|
2015-04-08 13:15:18 +03:00
|
|
|
{ PHY_ID_BCM54616S, 0xfffffff0 },
|
2010-06-17 03:02:23 +04:00
|
|
|
{ PHY_ID_BCM5464, 0xfffffff0 },
|
2015-11-22 02:08:54 +03:00
|
|
|
{ PHY_ID_BCM5481, 0xfffffff0 },
|
2016-11-04 08:10:58 +03:00
|
|
|
{ PHY_ID_BCM54810, 0xfffffff0 },
|
2020-05-15 20:24:47 +03:00
|
|
|
{ PHY_ID_BCM54811, 0xfffffff0 },
|
2010-06-17 03:02:23 +04:00
|
|
|
{ PHY_ID_BCM5482, 0xfffffff0 },
|
2010-04-02 05:05:56 +04:00
|
|
|
{ PHY_ID_BCM50610, 0xfffffff0 },
|
|
|
|
{ PHY_ID_BCM50610M, 0xfffffff0 },
|
|
|
|
{ PHY_ID_BCM57780, 0xfffffff0 },
|
|
|
|
{ PHY_ID_BCMAC131, 0xfffffff0 },
|
2010-06-17 03:02:24 +04:00
|
|
|
{ PHY_ID_BCM5241, 0xfffffff0 },
|
2017-12-15 04:48:16 +03:00
|
|
|
{ PHY_ID_BCM5395, 0xfffffff0 },
|
2020-04-17 21:38:02 +03:00
|
|
|
{ PHY_ID_BCM53125, 0xfffffff0 },
|
2018-05-02 18:13:58 +03:00
|
|
|
{ PHY_ID_BCM89610, 0xfffffff0 },
|
2010-04-02 05:05:56 +04:00
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
MODULE_DEVICE_TABLE(mdio, broadcom_tbl);
|