2018-09-08 14:07:17 +03:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 MediaTek Inc.
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*
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* Author: Sean Wang <sean.wang@mediatek.com>
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*
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*/
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#ifndef __PINCTRL_MTK_COMMON_V2_H
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#define __PINCTRL_MTK_COMMON_V2_H
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2018-09-19 01:03:13 +03:00
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#include <linux/gpio/driver.h>
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2018-09-08 14:07:17 +03:00
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#define MTK_INPUT 0
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#define MTK_OUTPUT 1
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#define MTK_DISABLE 0
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#define MTK_ENABLE 1
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2018-09-08 14:07:27 +03:00
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#define MTK_PULLDOWN 0
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#define MTK_PULLUP 1
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2018-09-08 14:07:17 +03:00
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2018-09-21 07:07:35 +03:00
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#define EINT_NA U16_MAX
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2018-09-21 07:07:36 +03:00
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#define NO_EINT_SUPPORT EINT_NA
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2018-09-08 14:07:20 +03:00
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2018-09-08 14:07:30 +03:00
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#define PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \
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_s_bit, _x_bits, _sz_reg, _fixed) { \
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2018-09-08 14:07:19 +03:00
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.s_pin = _s_pin, \
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.e_pin = _e_pin, \
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2018-09-08 14:07:30 +03:00
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.i_base = _i_base, \
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2018-09-08 14:07:19 +03:00
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.s_addr = _s_addr, \
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.x_addrs = _x_addrs, \
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.s_bit = _s_bit, \
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.x_bits = _x_bits, \
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.sz_reg = _sz_reg, \
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.fixed = _fixed, \
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}
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#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
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2018-09-08 14:07:30 +03:00
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PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
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2018-09-08 14:07:19 +03:00
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_x_bits, 32, 0)
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#define PINS_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
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2018-09-08 14:07:30 +03:00
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PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
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2018-09-08 14:07:19 +03:00
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_x_bits, 32, 1)
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2018-09-08 14:07:17 +03:00
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/* List these attributes which could be modified for the pin */
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enum {
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PINCTRL_PIN_REG_MODE,
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PINCTRL_PIN_REG_DIR,
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PINCTRL_PIN_REG_DI,
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PINCTRL_PIN_REG_DO,
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PINCTRL_PIN_REG_SR,
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PINCTRL_PIN_REG_SMT,
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PINCTRL_PIN_REG_PD,
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PINCTRL_PIN_REG_PU,
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PINCTRL_PIN_REG_E4,
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PINCTRL_PIN_REG_E8,
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PINCTRL_PIN_REG_TDSEL,
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PINCTRL_PIN_REG_RDSEL,
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2018-09-08 14:07:22 +03:00
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PINCTRL_PIN_REG_DRV,
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2018-09-08 14:07:25 +03:00
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PINCTRL_PIN_REG_PUPD,
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PINCTRL_PIN_REG_R0,
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PINCTRL_PIN_REG_R1,
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2018-09-08 14:07:26 +03:00
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PINCTRL_PIN_REG_IES,
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2018-09-08 14:07:27 +03:00
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PINCTRL_PIN_REG_PULLEN,
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PINCTRL_PIN_REG_PULLSEL,
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pinctrl: add drive for I2C related pins on MT8183
This patch provides the advanced drive for I2C used pins on MT8183.
The detail strength specification description of the I2C pin:
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
For I2C pins, there are existing generic driving setup and the above
specific driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA
driving adjustment in generic driving setup. But in specific driving
setup, they can support 0.125/0.25/0.5/1mA adjustment.
If we enable specific driving setup for I2C pins,
the existing generic driving setup will be disabled.
For some special features, we need the I2C pins specific driving setup.
The specific driving setup is controlled by E1E0EN.
So we need add extra vendor driving preperty instead of the generic
driving property. We can add "mediatek,drive-strength-adv = <XXX>;"
to describe the specific driving setup property.
"XXX" means the value of E1E0EN. So the valid arguments of
"mediatek,drive-strength-adv" are from 0 to 7.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-01 06:35:35 +03:00
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PINCTRL_PIN_REG_DRV_EN,
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PINCTRL_PIN_REG_DRV_E0,
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PINCTRL_PIN_REG_DRV_E1,
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2018-09-08 14:07:17 +03:00
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PINCTRL_PIN_REG_MAX,
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};
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2018-09-08 14:07:20 +03:00
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/* Group the pins by the driving current */
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enum {
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DRV_FIXED,
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DRV_GRP0,
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DRV_GRP1,
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DRV_GRP2,
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DRV_GRP3,
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DRV_GRP4,
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DRV_GRP_MAX,
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};
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2018-09-08 14:07:30 +03:00
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static const char * const mtk_default_register_base_names[] = {
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"base",
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};
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2018-09-08 14:07:17 +03:00
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/* struct mtk_pin_field - the structure that holds the information of the field
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* used to describe the attribute for the pin
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2018-09-08 14:07:30 +03:00
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* @base: the index pointing to the entry in base address list
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2018-09-08 14:07:17 +03:00
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* @offset: the register offset relative to the base address
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* @mask: the mask used to filter out the field from the register
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* @bitpos: the start bit relative to the register
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* @next: the indication that the field would be extended to the
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next register
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*/
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struct mtk_pin_field {
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2018-09-08 14:07:30 +03:00
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u8 index;
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2018-09-08 14:07:17 +03:00
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u32 offset;
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u32 mask;
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u8 bitpos;
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u8 next;
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};
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/* struct mtk_pin_field_calc - the structure that holds the range providing
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* the guide used to look up the relevant field
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* @s_pin: the start pin within the range
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* @e_pin: the end pin within the range
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2018-09-08 14:07:30 +03:00
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* @i_base: the index pointing to the entry in base address list
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2018-09-08 14:07:17 +03:00
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* @s_addr: the start address for the range
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* @x_addrs: the address distance between two consecutive registers
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* within the range
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* @s_bit: the start bit for the first register within the range
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* @x_bits: the bit distance between two consecutive pins within
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* the range
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2018-09-08 14:07:19 +03:00
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* @sz_reg: the size of bits in a register
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* @fixed: the consecutive pins share the same bits with the 1st
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* pin
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2018-09-08 14:07:17 +03:00
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*/
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struct mtk_pin_field_calc {
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u16 s_pin;
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u16 e_pin;
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2018-09-08 14:07:30 +03:00
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u8 i_base;
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2018-09-08 14:07:17 +03:00
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u32 s_addr;
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u8 x_addrs;
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u8 s_bit;
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u8 x_bits;
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2018-09-08 14:07:19 +03:00
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u8 sz_reg;
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u8 fixed;
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2018-09-08 14:07:17 +03:00
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};
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/* struct mtk_pin_reg_calc - the structure that holds all ranges used to
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* determine which register the pin would make use of
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* for certain pin attribute.
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* @range: the start address for the range
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* @nranges: the number of items in the range
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*/
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struct mtk_pin_reg_calc {
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const struct mtk_pin_field_calc *range;
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unsigned int nranges;
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};
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2018-09-08 14:07:32 +03:00
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/**
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* struct mtk_func_desc - the structure that providing information
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* all the funcs for this pin
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* @name: the name of function
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* @muxval: the mux to the function
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*/
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struct mtk_func_desc {
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const char *name;
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u8 muxval;
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};
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/**
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* struct mtk_eint_desc - the structure that providing information
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* for eint data per pin
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* @eint_m: the eint mux for this pin
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* @eitn_n: the eint number for this pin
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*/
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struct mtk_eint_desc {
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2018-10-08 22:14:10 +03:00
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u16 eint_m;
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2018-09-08 14:07:32 +03:00
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u16 eint_n;
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};
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2018-09-08 14:07:20 +03:00
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/**
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* struct mtk_pin_desc - the structure that providing information
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* for each pin of chips
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* @number: unique pin number from the global pin number space
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* @name: name for this pin
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* @eint: the eint data for this pin
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2018-09-08 14:07:20 +03:00
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* @drv_n: the index with the driving group
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2018-09-08 14:07:32 +03:00
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* @funcs: all available functions for this pins (only used in
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* those drivers compatible to pinctrl-mtk-common.c-like
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* ones)
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2018-09-08 14:07:20 +03:00
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*/
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struct mtk_pin_desc {
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unsigned int number;
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const char *name;
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2018-09-08 14:07:32 +03:00
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struct mtk_eint_desc eint;
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2018-09-08 14:07:20 +03:00
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u8 drv_n;
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2018-09-08 14:07:32 +03:00
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struct mtk_func_desc *funcs;
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2018-09-08 14:07:20 +03:00
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};
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2018-09-08 14:07:33 +03:00
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struct mtk_pinctrl_group {
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const char *name;
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unsigned long config;
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unsigned pin;
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};
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2018-09-08 14:07:22 +03:00
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struct mtk_pinctrl;
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2018-09-08 14:07:17 +03:00
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/* struct mtk_pin_soc - the structure that holds SoC-specific data */
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struct mtk_pin_soc {
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const struct mtk_pin_reg_calc *reg_cal;
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2018-09-08 14:07:32 +03:00
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const struct mtk_pin_desc *pins;
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2018-09-08 14:07:17 +03:00
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unsigned int npins;
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const struct group_desc *grps;
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unsigned int ngrps;
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const struct function_desc *funcs;
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unsigned int nfuncs;
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const struct mtk_eint_regs *eint_regs;
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const struct mtk_eint_hw *eint_hw;
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2018-09-08 14:07:21 +03:00
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/* Specific parameters per SoC */
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u8 gpio_m;
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2018-09-08 14:07:26 +03:00
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bool ies_present;
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2018-09-08 14:07:30 +03:00
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const char * const *base_names;
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unsigned int nbase_names;
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2018-09-08 14:07:22 +03:00
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/* Specific pinconfig operations */
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2018-09-08 14:07:24 +03:00
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int (*bias_disable_set)(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc);
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int (*bias_disable_get)(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, int *res);
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int (*bias_set)(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, bool pullup);
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int (*bias_get)(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, bool pullup, int *res);
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2020-01-22 09:53:13 +03:00
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int (*bias_set_combo)(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, u32 pullup, u32 arg);
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int (*bias_get_combo)(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, u32 *pullup, u32 *arg);
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2018-09-08 14:07:22 +03:00
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int (*drive_set)(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, u32 arg);
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int (*drive_get)(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, int *val);
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2018-09-08 14:07:25 +03:00
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int (*adv_pull_set)(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, bool pullup,
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u32 arg);
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int (*adv_pull_get)(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, bool pullup,
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u32 *val);
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pinctrl: add drive for I2C related pins on MT8183
This patch provides the advanced drive for I2C used pins on MT8183.
The detail strength specification description of the I2C pin:
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
For I2C pins, there are existing generic driving setup and the above
specific driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA
driving adjustment in generic driving setup. But in specific driving
setup, they can support 0.125/0.25/0.5/1mA adjustment.
If we enable specific driving setup for I2C pins,
the existing generic driving setup will be disabled.
For some special features, we need the I2C pins specific driving setup.
The specific driving setup is controlled by E1E0EN.
So we need add extra vendor driving preperty instead of the generic
driving property. We can add "mediatek,drive-strength-adv = <XXX>;"
to describe the specific driving setup property.
"XXX" means the value of E1E0EN. So the valid arguments of
"mediatek,drive-strength-adv" are from 0 to 7.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-01 06:35:35 +03:00
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int (*adv_drive_set)(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, u32 arg);
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int (*adv_drive_get)(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, u32 *val);
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2018-09-08 14:07:32 +03:00
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/* Specific driver data */
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void *driver_data;
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2018-09-08 14:07:17 +03:00
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};
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struct mtk_pinctrl {
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struct pinctrl_dev *pctrl;
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2018-09-08 14:07:30 +03:00
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void __iomem **base;
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u8 nbase;
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2018-09-08 14:07:17 +03:00
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struct device *dev;
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struct gpio_chip chip;
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const struct mtk_pin_soc *soc;
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struct mtk_eint *eint;
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2018-09-08 14:07:33 +03:00
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struct mtk_pinctrl_group *groups;
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const char **grp_names;
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2018-09-08 14:07:17 +03:00
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};
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2018-09-08 14:07:30 +03:00
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void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set);
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2018-09-08 14:07:17 +03:00
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2018-09-08 14:07:29 +03:00
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int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
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int field, int value);
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int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc,
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int field, int *value);
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2018-09-08 14:07:17 +03:00
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2018-09-08 14:07:37 +03:00
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int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev);
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2018-09-08 14:07:24 +03:00
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int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc);
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int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, int *res);
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int mtk_pinconf_bias_set(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, bool pullup);
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int mtk_pinconf_bias_get(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, bool pullup,
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int *res);
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2018-09-08 14:07:27 +03:00
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int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc);
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int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc,
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int *res);
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int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, bool pullup);
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int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, bool pullup,
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int *res);
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2020-01-22 09:53:13 +03:00
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int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc,
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u32 pullup, u32 enable);
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int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc,
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u32 *pullup, u32 *enable);
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2018-09-08 14:07:27 +03:00
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2018-09-08 14:07:22 +03:00
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int mtk_pinconf_drive_set(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, u32 arg);
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int mtk_pinconf_drive_get(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, int *val);
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2018-09-08 14:07:23 +03:00
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int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, u32 arg);
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int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, int *val);
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pinctrl: mediatek: Supporting driving setting without mapping current to register value
MediaTek's smartphone project actual usage does need to know current value
(in mA) in procedure of finding the best driving setting.
The steps in the procedure is like as follow:
1. set driving setting field in setting register as 0, measure waveform,
perform test, and etc.
2. set driving setting field in setting register as 1, measure waveform,
perform test, and etc.
...
n. set driving setting field in setting register as n-1, measure
waveform, perform test, and etc.
Check the results of steps 1~n and adopt the setting that get best result.
This procedure does need to know the mapping between current to register
value.
Therefore, setting driving without mapping current is more practical for
MediaTek's smartphone usage.
Signed-off-by: Light Hsieh <light.hsieh@mediatek.com>
Link: https://lore.kernel.org/r/1579675994-7001-2-git-send-email-light.hsieh@mediatek.com
Acked-by: Sean Wang <sean.wang@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-22 09:53:10 +03:00
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int mtk_pinconf_drive_set_raw(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, u32 arg);
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int mtk_pinconf_drive_get_raw(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, int *val);
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2018-09-08 14:07:25 +03:00
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int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, bool pullup,
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u32 arg);
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int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, bool pullup,
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u32 *val);
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pinctrl: add drive for I2C related pins on MT8183
This patch provides the advanced drive for I2C used pins on MT8183.
The detail strength specification description of the I2C pin:
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
For I2C pins, there are existing generic driving setup and the above
specific driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA
driving adjustment in generic driving setup. But in specific driving
setup, they can support 0.125/0.25/0.5/1mA adjustment.
If we enable specific driving setup for I2C pins,
the existing generic driving setup will be disabled.
For some special features, we need the I2C pins specific driving setup.
The specific driving setup is controlled by E1E0EN.
So we need add extra vendor driving preperty instead of the generic
driving property. We can add "mediatek,drive-strength-adv = <XXX>;"
to describe the specific driving setup property.
"XXX" means the value of E1E0EN. So the valid arguments of
"mediatek,drive-strength-adv" are from 0 to 7.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-01 06:35:35 +03:00
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int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, u32 arg);
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int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
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const struct mtk_pin_desc *desc, u32 *val);
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2018-09-08 14:07:25 +03:00
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2018-09-08 14:07:17 +03:00
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#endif /* __PINCTRL_MTK_COMMON_V2_H */
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