2009-03-04 23:01:37 +03:00
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/*
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* davinci_nand.c - NAND Flash Driver for DaVinci family chips
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*
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* Copyright © 2006 Texas Instruments.
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*
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* Port to 2.6.23 Copyright © 2008 by:
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* Sander Huijsen <Shuijsen@optelecom-nkf.com>
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* Troy Kisky <troy.kisky@boundarydevices.com>
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* Dirk Behme <Dirk.Behme@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 11:04:11 +03:00
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#include <linux/slab.h>
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2009-03-04 23:01:37 +03:00
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#include <mach/nand.h>
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2010-08-09 14:16:35 +04:00
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#include <mach/aemif.h>
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2009-03-04 23:01:37 +03:00
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#include <asm/mach-types.h>
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/*
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* This is a device driver for the NAND flash controller found on the
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* various DaVinci family chips. It handles up to four SoC chipselects,
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* and some flavors of secondary chipselect (e.g. based on A12) as used
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* with multichip packages.
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*
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2009-04-22 06:58:13 +04:00
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* The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
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2009-03-04 23:01:37 +03:00
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* available on chips like the DM355 and OMAP-L137 and needed with the
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* more error-prone MLC NAND chips.
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*
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* This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
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* outputs in a "wire-AND" configuration, with no per-chip signals.
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*/
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struct davinci_nand_info {
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struct mtd_info mtd;
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struct nand_chip chip;
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2009-04-22 06:58:13 +04:00
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struct nand_ecclayout ecclayout;
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2009-03-04 23:01:37 +03:00
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struct device *dev;
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struct clk *clk;
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bool partitioned;
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2009-04-22 06:58:13 +04:00
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bool is_readmode;
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2009-03-04 23:01:37 +03:00
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void __iomem *base;
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void __iomem *vaddr;
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uint32_t ioaddr;
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uint32_t current_cs;
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uint32_t mask_chipsel;
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uint32_t mask_ale;
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uint32_t mask_cle;
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uint32_t core_chipsel;
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2010-08-09 14:16:36 +04:00
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struct davinci_aemif_timing *timing;
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2009-03-04 23:01:37 +03:00
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};
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static DEFINE_SPINLOCK(davinci_nand_lock);
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2009-04-22 06:58:13 +04:00
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static bool ecc4_busy;
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2009-03-04 23:01:37 +03:00
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#define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd)
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static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
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int offset)
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{
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return __raw_readl(info->base + offset);
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}
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static inline void davinci_nand_writel(struct davinci_nand_info *info,
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int offset, unsigned long value)
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{
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__raw_writel(value, info->base + offset);
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}
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/*----------------------------------------------------------------------*/
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/*
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* Access to hardware control lines: ALE, CLE, secondary chipselect.
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*/
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static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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uint32_t addr = info->current_cs;
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struct nand_chip *nand = mtd->priv;
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/* Did the control lines change? */
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if (ctrl & NAND_CTRL_CHANGE) {
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if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
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addr |= info->mask_cle;
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else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
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addr |= info->mask_ale;
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nand->IO_ADDR_W = (void __iomem __force *)addr;
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}
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if (cmd != NAND_CMD_NONE)
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iowrite8(cmd, nand->IO_ADDR_W);
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}
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static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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uint32_t addr = info->ioaddr;
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/* maybe kick in a second chipselect */
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if (chip > 0)
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addr |= info->mask_chipsel;
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info->current_cs = addr;
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info->chip.IO_ADDR_W = (void __iomem __force *)addr;
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info->chip.IO_ADDR_R = info->chip.IO_ADDR_W;
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}
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/*----------------------------------------------------------------------*/
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/*
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* 1-bit hardware ECC ... context maintained for each core chipselect
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*/
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static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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return davinci_nand_readl(info, NANDF1ECC_OFFSET
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+ 4 * info->core_chipsel);
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}
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static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
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{
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struct davinci_nand_info *info;
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uint32_t nandcfr;
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unsigned long flags;
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info = to_davinci_nand(mtd);
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/* Reset ECC hardware */
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nand_davinci_readecc_1bit(mtd);
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spin_lock_irqsave(&davinci_nand_lock, flags);
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/* Restart ECC hardware */
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nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
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nandcfr |= BIT(8 + info->core_chipsel);
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davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);
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spin_unlock_irqrestore(&davinci_nand_lock, flags);
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}
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/*
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* Read hardware ECC value and pack into three bytes
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*/
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static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
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const u_char *dat, u_char *ecc_code)
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{
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unsigned int ecc_val = nand_davinci_readecc_1bit(mtd);
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unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);
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/* invert so that erased block ecc is correct */
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ecc24 = ~ecc24;
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ecc_code[0] = (u_char)(ecc24);
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ecc_code[1] = (u_char)(ecc24 >> 8);
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ecc_code[2] = (u_char)(ecc24 >> 16);
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return 0;
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}
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static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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struct nand_chip *chip = mtd->priv;
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uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
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(read_ecc[2] << 16);
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uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
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(calc_ecc[2] << 16);
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uint32_t diff = eccCalc ^ eccNand;
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if (diff) {
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if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
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/* Correctable error */
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if ((diff >> (12 + 3)) < chip->ecc.size) {
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dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
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return 1;
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} else {
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return -1;
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}
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} else if (!(diff & (diff - 1))) {
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/* Single bit ECC error in the ECC itself,
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* nothing to fix */
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return 1;
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} else {
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/* Uncorrectable error */
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return -1;
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}
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}
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return 0;
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}
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/*----------------------------------------------------------------------*/
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2009-04-22 06:58:13 +04:00
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/*
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* 4-bit hardware ECC ... context maintained over entire AEMIF
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*
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* This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME
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* since that forces use of a problematic "infix OOB" layout.
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* Among other things, it trashes manufacturer bad block markers.
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* Also, and specific to this hardware, it ECC-protects the "prepad"
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* in the OOB ... while having ECC protection for parts of OOB would
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* seem useful, the current MTD stack sometimes wants to update the
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* OOB without recomputing ECC.
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*/
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static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&davinci_nand_lock, flags);
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/* Start 4-bit ECC calculation for read/write */
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val = davinci_nand_readl(info, NANDFCR_OFFSET);
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val &= ~(0x03 << 4);
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val |= (info->core_chipsel << 4) | BIT(12);
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davinci_nand_writel(info, NANDFCR_OFFSET, val);
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info->is_readmode = (mode == NAND_ECC_READ);
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spin_unlock_irqrestore(&davinci_nand_lock, flags);
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}
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/* Read raw ECC code after writing to NAND. */
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static void
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nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4])
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{
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const u32 mask = 0x03ff03ff;
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code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;
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code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;
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code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;
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code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;
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}
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/* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
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static int nand_davinci_calculate_4bit(struct mtd_info *mtd,
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const u_char *dat, u_char *ecc_code)
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{
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struct davinci_nand_info *info = to_davinci_nand(mtd);
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u32 raw_ecc[4], *p;
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unsigned i;
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/* After a read, terminate ECC calculation by a dummy read
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* of some 4-bit ECC register. ECC covers everything that
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* was read; correct() just uses the hardware state, so
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* ecc_code is not needed.
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*/
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if (info->is_readmode) {
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davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
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return 0;
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}
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/* Pack eight raw 10-bit ecc values into ten bytes, making
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* two passes which each convert four values (in upper and
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* lower halves of two 32-bit words) into five bytes. The
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* ROM boot loader uses this same packing scheme.
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*/
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nand_davinci_readecc_4bit(info, raw_ecc);
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for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
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*ecc_code++ = p[0] & 0xff;
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|
|
*ecc_code++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
|
|
|
|
*ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
|
|
|
|
*ecc_code++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
|
|
|
|
*ecc_code++ = (p[1] >> 18) & 0xff;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Correct up to 4 bits in data we just read, using state left in the
|
|
|
|
* hardware plus the ecc_code computed when it was first written.
|
|
|
|
*/
|
|
|
|
static int nand_davinci_correct_4bit(struct mtd_info *mtd,
|
|
|
|
u_char *data, u_char *ecc_code, u_char *null)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
struct davinci_nand_info *info = to_davinci_nand(mtd);
|
|
|
|
unsigned short ecc10[8];
|
|
|
|
unsigned short *ecc16;
|
|
|
|
u32 syndrome[4];
|
2010-07-21 02:24:01 +04:00
|
|
|
u32 ecc_state;
|
2009-04-22 06:58:13 +04:00
|
|
|
unsigned num_errors, corrected;
|
2010-09-03 14:35:37 +04:00
|
|
|
unsigned long timeo;
|
2009-04-22 06:58:13 +04:00
|
|
|
|
|
|
|
/* All bytes 0xff? It's an erased page; ignore its ECC. */
|
|
|
|
for (i = 0; i < 10; i++) {
|
|
|
|
if (ecc_code[i] != 0xff)
|
|
|
|
goto compare;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
compare:
|
|
|
|
/* Unpack ten bytes into eight 10 bit values. We know we're
|
|
|
|
* little-endian, and use type punning for less shifting/masking.
|
|
|
|
*/
|
|
|
|
if (WARN_ON(0x01 & (unsigned) ecc_code))
|
|
|
|
return -EINVAL;
|
|
|
|
ecc16 = (unsigned short *)ecc_code;
|
|
|
|
|
|
|
|
ecc10[0] = (ecc16[0] >> 0) & 0x3ff;
|
|
|
|
ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0);
|
|
|
|
ecc10[2] = (ecc16[1] >> 4) & 0x3ff;
|
|
|
|
ecc10[3] = ((ecc16[1] >> 14) & 0x3) | ((ecc16[2] << 2) & 0x3fc);
|
|
|
|
ecc10[4] = (ecc16[2] >> 8) | ((ecc16[3] << 8) & 0x300);
|
|
|
|
ecc10[5] = (ecc16[3] >> 2) & 0x3ff;
|
|
|
|
ecc10[6] = ((ecc16[3] >> 12) & 0xf) | ((ecc16[4] << 4) & 0x3f0);
|
|
|
|
ecc10[7] = (ecc16[4] >> 6) & 0x3ff;
|
|
|
|
|
|
|
|
/* Tell ECC controller about the expected ECC codes. */
|
|
|
|
for (i = 7; i >= 0; i--)
|
|
|
|
davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]);
|
|
|
|
|
|
|
|
/* Allow time for syndrome calculation ... then read it.
|
|
|
|
* A syndrome of all zeroes 0 means no detected errors.
|
|
|
|
*/
|
|
|
|
davinci_nand_readl(info, NANDFSR_OFFSET);
|
|
|
|
nand_davinci_readecc_4bit(info, syndrome);
|
|
|
|
if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3]))
|
|
|
|
return 0;
|
|
|
|
|
2009-09-18 23:51:48 +04:00
|
|
|
/*
|
|
|
|
* Clear any previous address calculation by doing a dummy read of an
|
|
|
|
* error address register.
|
|
|
|
*/
|
|
|
|
davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);
|
|
|
|
|
2009-04-22 06:58:13 +04:00
|
|
|
/* Start address calculation, and wait for it to complete.
|
|
|
|
* We _could_ start reading more data while this is working,
|
|
|
|
* to speed up the overall page read.
|
|
|
|
*/
|
|
|
|
davinci_nand_writel(info, NANDFCR_OFFSET,
|
|
|
|
davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));
|
2010-07-21 02:24:01 +04:00
|
|
|
|
|
|
|
/*
|
|
|
|
* ECC_STATE field reads 0x3 (Error correction complete) immediately
|
|
|
|
* after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
|
|
|
|
* begin trying to poll for the state, you may fall right out of your
|
|
|
|
* loop without any of the correction calculations having taken place.
|
2010-08-25 16:18:20 +04:00
|
|
|
* The recommendation from the hardware team is to initially delay as
|
|
|
|
* long as ECC_STATE reads less than 4. After that, ECC HW has entered
|
|
|
|
* correction state.
|
2010-07-21 02:24:01 +04:00
|
|
|
*/
|
2010-09-03 14:35:37 +04:00
|
|
|
timeo = jiffies + usecs_to_jiffies(100);
|
2010-07-21 02:24:01 +04:00
|
|
|
do {
|
|
|
|
ecc_state = (davinci_nand_readl(info,
|
|
|
|
NANDFSR_OFFSET) >> 8) & 0x0f;
|
|
|
|
cpu_relax();
|
|
|
|
} while ((ecc_state < 4) && time_before(jiffies, timeo));
|
|
|
|
|
2009-04-22 06:58:13 +04:00
|
|
|
for (;;) {
|
|
|
|
u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET);
|
|
|
|
|
|
|
|
switch ((fsr >> 8) & 0x0f) {
|
|
|
|
case 0: /* no error, should not happen */
|
2009-09-18 23:51:48 +04:00
|
|
|
davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
|
2009-04-22 06:58:13 +04:00
|
|
|
return 0;
|
|
|
|
case 1: /* five or more errors detected */
|
2009-09-18 23:51:48 +04:00
|
|
|
davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
|
2009-04-22 06:58:13 +04:00
|
|
|
return -EIO;
|
|
|
|
case 2: /* error addresses computed */
|
|
|
|
case 3:
|
|
|
|
num_errors = 1 + ((fsr >> 16) & 0x03);
|
|
|
|
goto correct;
|
|
|
|
default: /* still working on it */
|
|
|
|
cpu_relax();
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
correct:
|
|
|
|
/* correct each error */
|
|
|
|
for (i = 0, corrected = 0; i < num_errors; i++) {
|
|
|
|
int error_address, error_value;
|
|
|
|
|
|
|
|
if (i > 1) {
|
|
|
|
error_address = davinci_nand_readl(info,
|
|
|
|
NAND_ERR_ADD2_OFFSET);
|
|
|
|
error_value = davinci_nand_readl(info,
|
|
|
|
NAND_ERR_ERRVAL2_OFFSET);
|
|
|
|
} else {
|
|
|
|
error_address = davinci_nand_readl(info,
|
|
|
|
NAND_ERR_ADD1_OFFSET);
|
|
|
|
error_value = davinci_nand_readl(info,
|
|
|
|
NAND_ERR_ERRVAL1_OFFSET);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i & 1) {
|
|
|
|
error_address >>= 16;
|
|
|
|
error_value >>= 16;
|
|
|
|
}
|
|
|
|
error_address &= 0x3ff;
|
|
|
|
error_address = (512 + 7) - error_address;
|
|
|
|
|
|
|
|
if (error_address < 512) {
|
|
|
|
data[error_address] ^= error_value;
|
|
|
|
corrected++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return corrected;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
|
2009-03-04 23:01:37 +03:00
|
|
|
/*
|
|
|
|
* NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
|
|
|
|
* how these chips are normally wired. This translates to both 8 and 16
|
|
|
|
* bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
|
|
|
|
*
|
|
|
|
* For now we assume that configuration, or any other one which ignores
|
|
|
|
* the two LSBs for NAND access ... so we can issue 32-bit reads/writes
|
|
|
|
* and have that transparently morphed into multiple NAND operations.
|
|
|
|
*/
|
|
|
|
static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
|
|
|
|
{
|
|
|
|
struct nand_chip *chip = mtd->priv;
|
|
|
|
|
|
|
|
if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
|
|
|
|
ioread32_rep(chip->IO_ADDR_R, buf, len >> 2);
|
|
|
|
else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
|
|
|
|
ioread16_rep(chip->IO_ADDR_R, buf, len >> 1);
|
|
|
|
else
|
|
|
|
ioread8_rep(chip->IO_ADDR_R, buf, len);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void nand_davinci_write_buf(struct mtd_info *mtd,
|
|
|
|
const uint8_t *buf, int len)
|
|
|
|
{
|
|
|
|
struct nand_chip *chip = mtd->priv;
|
|
|
|
|
|
|
|
if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
|
|
|
|
iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2);
|
|
|
|
else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
|
|
|
|
iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1);
|
|
|
|
else
|
|
|
|
iowrite8_rep(chip->IO_ADDR_R, buf, len);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check hardware register for wait status. Returns 1 if device is ready,
|
|
|
|
* 0 if it is still busy.
|
|
|
|
*/
|
|
|
|
static int nand_davinci_dev_ready(struct mtd_info *mtd)
|
|
|
|
{
|
|
|
|
struct davinci_nand_info *info = to_davinci_nand(mtd);
|
|
|
|
|
|
|
|
return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*----------------------------------------------------------------------*/
|
|
|
|
|
2009-04-22 06:58:13 +04:00
|
|
|
/* An ECC layout for using 4-bit ECC with small-page flash, storing
|
|
|
|
* ten ECC bytes plus the manufacturer's bad block marker byte, and
|
|
|
|
* and not overlapping the default BBT markers.
|
|
|
|
*/
|
|
|
|
static struct nand_ecclayout hwecc4_small __initconst = {
|
|
|
|
.eccbytes = 10,
|
|
|
|
.eccpos = { 0, 1, 2, 3, 4,
|
|
|
|
/* offset 5 holds the badblock marker */
|
|
|
|
6, 7,
|
|
|
|
13, 14, 15, },
|
|
|
|
.oobfree = {
|
|
|
|
{.offset = 8, .length = 5, },
|
|
|
|
{.offset = 16, },
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2009-09-18 23:51:48 +04:00
|
|
|
/* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash,
|
|
|
|
* storing ten ECC bytes plus the manufacturer's bad block marker byte,
|
|
|
|
* and not overlapping the default BBT markers.
|
|
|
|
*/
|
|
|
|
static struct nand_ecclayout hwecc4_2048 __initconst = {
|
|
|
|
.eccbytes = 40,
|
|
|
|
.eccpos = {
|
|
|
|
/* at the end of spare sector */
|
|
|
|
24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
|
|
|
|
34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
|
|
|
|
44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
|
|
|
|
54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
|
|
|
|
},
|
|
|
|
.oobfree = {
|
|
|
|
/* 2 bytes at offset 0 hold manufacturer badblock markers */
|
|
|
|
{.offset = 2, .length = 22, },
|
|
|
|
/* 5 bytes at offset 8 hold BBT markers */
|
|
|
|
/* 8 bytes at offset 16 hold JFFS2 clean markers */
|
|
|
|
},
|
|
|
|
};
|
2009-04-22 06:58:13 +04:00
|
|
|
|
2009-03-04 23:01:37 +03:00
|
|
|
static int __init nand_davinci_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct davinci_nand_pdata *pdata = pdev->dev.platform_data;
|
|
|
|
struct davinci_nand_info *info;
|
|
|
|
struct resource *res1;
|
|
|
|
struct resource *res2;
|
|
|
|
void __iomem *vaddr;
|
|
|
|
void __iomem *base;
|
|
|
|
int ret;
|
|
|
|
uint32_t val;
|
|
|
|
nand_ecc_modes_t ecc_mode;
|
|
|
|
|
2009-04-22 06:51:31 +04:00
|
|
|
/* insist on board-specific configuration */
|
|
|
|
if (!pdata)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2009-03-04 23:01:37 +03:00
|
|
|
/* which external chipselect will we be managing? */
|
|
|
|
if (pdev->id < 0 || pdev->id > 3)
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
info = kzalloc(sizeof(*info), GFP_KERNEL);
|
|
|
|
if (!info) {
|
|
|
|
dev_err(&pdev->dev, "unable to allocate memory\n");
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err_nomem;
|
|
|
|
}
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, info);
|
|
|
|
|
|
|
|
res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
|
|
if (!res1 || !res2) {
|
|
|
|
dev_err(&pdev->dev, "resource missing\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto err_nomem;
|
|
|
|
}
|
|
|
|
|
2009-12-15 00:13:13 +03:00
|
|
|
vaddr = ioremap(res1->start, resource_size(res1));
|
|
|
|
base = ioremap(res2->start, resource_size(res2));
|
2009-03-04 23:01:37 +03:00
|
|
|
if (!vaddr || !base) {
|
|
|
|
dev_err(&pdev->dev, "ioremap failed\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto err_ioremap;
|
|
|
|
}
|
|
|
|
|
|
|
|
info->dev = &pdev->dev;
|
|
|
|
info->base = base;
|
|
|
|
info->vaddr = vaddr;
|
|
|
|
|
|
|
|
info->mtd.priv = &info->chip;
|
|
|
|
info->mtd.name = dev_name(&pdev->dev);
|
|
|
|
info->mtd.owner = THIS_MODULE;
|
|
|
|
|
2009-03-26 10:42:50 +03:00
|
|
|
info->mtd.dev.parent = &pdev->dev;
|
|
|
|
|
2009-03-04 23:01:37 +03:00
|
|
|
info->chip.IO_ADDR_R = vaddr;
|
|
|
|
info->chip.IO_ADDR_W = vaddr;
|
|
|
|
info->chip.chip_delay = 0;
|
|
|
|
info->chip.select_chip = nand_davinci_select_chip;
|
|
|
|
|
|
|
|
/* options such as NAND_USE_FLASH_BBT or 16-bit widths */
|
2009-04-22 06:51:31 +04:00
|
|
|
info->chip.options = pdata->options;
|
2009-10-13 03:16:37 +04:00
|
|
|
info->chip.bbt_td = pdata->bbt_td;
|
|
|
|
info->chip.bbt_md = pdata->bbt_md;
|
2010-08-09 14:16:36 +04:00
|
|
|
info->timing = pdata->timing;
|
2009-03-04 23:01:37 +03:00
|
|
|
|
|
|
|
info->ioaddr = (uint32_t __force) vaddr;
|
|
|
|
|
|
|
|
info->current_cs = info->ioaddr;
|
|
|
|
info->core_chipsel = pdev->id;
|
|
|
|
info->mask_chipsel = pdata->mask_chipsel;
|
|
|
|
|
|
|
|
/* use nandboot-capable ALE/CLE masks by default */
|
2009-10-01 18:25:06 +04:00
|
|
|
info->mask_ale = pdata->mask_ale ? : MASK_ALE;
|
2009-04-22 06:51:31 +04:00
|
|
|
info->mask_cle = pdata->mask_cle ? : MASK_CLE;
|
2009-03-04 23:01:37 +03:00
|
|
|
|
|
|
|
/* Set address of hardware control function */
|
|
|
|
info->chip.cmd_ctrl = nand_davinci_hwcontrol;
|
|
|
|
info->chip.dev_ready = nand_davinci_dev_ready;
|
|
|
|
|
|
|
|
/* Speed up buffer I/O */
|
|
|
|
info->chip.read_buf = nand_davinci_read_buf;
|
|
|
|
info->chip.write_buf = nand_davinci_write_buf;
|
|
|
|
|
2009-04-22 06:51:31 +04:00
|
|
|
/* Use board-specific ECC config */
|
|
|
|
ecc_mode = pdata->ecc_mode;
|
2009-03-04 23:01:37 +03:00
|
|
|
|
2009-04-22 06:58:13 +04:00
|
|
|
ret = -EINVAL;
|
2009-03-04 23:01:37 +03:00
|
|
|
switch (ecc_mode) {
|
|
|
|
case NAND_ECC_NONE:
|
|
|
|
case NAND_ECC_SOFT:
|
2009-04-22 06:58:13 +04:00
|
|
|
pdata->ecc_bits = 0;
|
2009-03-04 23:01:37 +03:00
|
|
|
break;
|
|
|
|
case NAND_ECC_HW:
|
2009-04-22 06:58:13 +04:00
|
|
|
if (pdata->ecc_bits == 4) {
|
|
|
|
/* No sanity checks: CPUs must support this,
|
|
|
|
* and the chips may not use NAND_BUSWIDTH_16.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* No sharing 4-bit hardware between chipselects yet */
|
|
|
|
spin_lock_irq(&davinci_nand_lock);
|
|
|
|
if (ecc4_busy)
|
|
|
|
ret = -EBUSY;
|
|
|
|
else
|
|
|
|
ecc4_busy = true;
|
|
|
|
spin_unlock_irq(&davinci_nand_lock);
|
|
|
|
|
|
|
|
if (ret == -EBUSY)
|
|
|
|
goto err_ecc;
|
|
|
|
|
|
|
|
info->chip.ecc.calculate = nand_davinci_calculate_4bit;
|
|
|
|
info->chip.ecc.correct = nand_davinci_correct_4bit;
|
|
|
|
info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
|
|
|
|
info->chip.ecc.bytes = 10;
|
|
|
|
} else {
|
|
|
|
info->chip.ecc.calculate = nand_davinci_calculate_1bit;
|
|
|
|
info->chip.ecc.correct = nand_davinci_correct_1bit;
|
|
|
|
info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
|
|
|
|
info->chip.ecc.bytes = 3;
|
|
|
|
}
|
2009-03-04 23:01:37 +03:00
|
|
|
info->chip.ecc.size = 512;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto err_ecc;
|
|
|
|
}
|
|
|
|
info->chip.ecc.mode = ecc_mode;
|
|
|
|
|
2009-06-05 21:48:08 +04:00
|
|
|
info->clk = clk_get(&pdev->dev, "aemif");
|
2009-03-04 23:01:37 +03:00
|
|
|
if (IS_ERR(info->clk)) {
|
|
|
|
ret = PTR_ERR(info->clk);
|
2009-06-05 21:48:08 +04:00
|
|
|
dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret);
|
2009-03-04 23:01:37 +03:00
|
|
|
goto err_clk;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = clk_enable(info->clk);
|
|
|
|
if (ret < 0) {
|
2009-06-05 21:48:08 +04:00
|
|
|
dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
|
|
|
|
ret);
|
2009-03-04 23:01:37 +03:00
|
|
|
goto err_clk_enable;
|
|
|
|
}
|
|
|
|
|
2010-08-09 14:16:36 +04:00
|
|
|
/*
|
|
|
|
* Setup Async configuration register in case we did not boot from
|
|
|
|
* NAND and so bootloader did not bother to set it up.
|
2009-03-04 23:01:37 +03:00
|
|
|
*/
|
2010-08-09 14:16:36 +04:00
|
|
|
val = davinci_nand_readl(info, A1CR_OFFSET + info->core_chipsel * 4);
|
|
|
|
|
|
|
|
/* Extended Wait is not valid and Select Strobe mode is not used */
|
|
|
|
val &= ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK);
|
|
|
|
if (info->chip.options & NAND_BUSWIDTH_16)
|
|
|
|
val |= 0x1;
|
|
|
|
|
|
|
|
davinci_nand_writel(info, A1CR_OFFSET + info->core_chipsel * 4, val);
|
|
|
|
|
|
|
|
ret = davinci_aemif_setup_timing(info->timing, info->base,
|
|
|
|
info->core_chipsel);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_dbg(&pdev->dev, "NAND timing values setup fail\n");
|
|
|
|
goto err_timing;
|
|
|
|
}
|
2009-03-04 23:01:37 +03:00
|
|
|
|
|
|
|
spin_lock_irq(&davinci_nand_lock);
|
|
|
|
|
|
|
|
/* put CSxNAND into NAND mode */
|
|
|
|
val = davinci_nand_readl(info, NANDFCR_OFFSET);
|
|
|
|
val |= BIT(info->core_chipsel);
|
|
|
|
davinci_nand_writel(info, NANDFCR_OFFSET, val);
|
|
|
|
|
|
|
|
spin_unlock_irq(&davinci_nand_lock);
|
|
|
|
|
|
|
|
/* Scan to find existence of the device(s) */
|
2010-02-26 21:32:56 +03:00
|
|
|
ret = nand_scan_ident(&info->mtd, pdata->mask_chipsel ? 2 : 1, NULL);
|
2009-03-04 23:01:37 +03:00
|
|
|
if (ret < 0) {
|
|
|
|
dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
|
|
|
|
goto err_scan;
|
|
|
|
}
|
|
|
|
|
2009-04-22 06:58:13 +04:00
|
|
|
/* Update ECC layout if needed ... for 1-bit HW ECC, the default
|
|
|
|
* is OK, but it allocates 6 bytes when only 3 are needed (for
|
|
|
|
* each 512 bytes). For the 4-bit HW ECC, that default is not
|
|
|
|
* usable: 10 bytes are needed, not 6.
|
|
|
|
*/
|
|
|
|
if (pdata->ecc_bits == 4) {
|
|
|
|
int chunks = info->mtd.writesize / 512;
|
|
|
|
|
|
|
|
if (!chunks || info->mtd.oobsize < 16) {
|
|
|
|
dev_dbg(&pdev->dev, "too small\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto err_scan;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* For small page chips, preserve the manufacturer's
|
|
|
|
* badblock marking data ... and make sure a flash BBT
|
|
|
|
* table marker fits in the free bytes.
|
|
|
|
*/
|
|
|
|
if (chunks == 1) {
|
|
|
|
info->ecclayout = hwecc4_small;
|
|
|
|
info->ecclayout.oobfree[1].length =
|
|
|
|
info->mtd.oobsize - 16;
|
|
|
|
goto syndrome_done;
|
|
|
|
}
|
2009-09-18 23:51:48 +04:00
|
|
|
if (chunks == 4) {
|
|
|
|
info->ecclayout = hwecc4_2048;
|
|
|
|
info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
|
|
|
|
goto syndrome_done;
|
|
|
|
}
|
2009-04-22 06:58:13 +04:00
|
|
|
|
2009-09-18 23:51:48 +04:00
|
|
|
/* 4KiB page chips are not yet supported. The eccpos from
|
|
|
|
* nand_ecclayout cannot hold 80 bytes and change to eccpos[]
|
|
|
|
* breaks userspace ioctl interface with mtd-utils. Once we
|
|
|
|
* resolve this issue, NAND_ECC_HW_OOB_FIRST mode can be used
|
|
|
|
* for the 4KiB page chips.
|
2010-08-25 05:12:00 +04:00
|
|
|
*
|
|
|
|
* TODO: Note that nand_ecclayout has now been expanded and can
|
|
|
|
* hold plenty of OOB entries.
|
2009-04-22 06:58:13 +04:00
|
|
|
*/
|
|
|
|
dev_warn(&pdev->dev, "no 4-bit ECC support yet "
|
2009-09-18 23:51:48 +04:00
|
|
|
"for 4KiB-page NAND\n");
|
2009-04-22 06:58:13 +04:00
|
|
|
ret = -EIO;
|
|
|
|
goto err_scan;
|
|
|
|
|
|
|
|
syndrome_done:
|
|
|
|
info->chip.ecc.layout = &info->ecclayout;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = nand_scan_tail(&info->mtd);
|
|
|
|
if (ret < 0)
|
|
|
|
goto err_scan;
|
|
|
|
|
2009-03-04 23:01:37 +03:00
|
|
|
if (mtd_has_partitions()) {
|
|
|
|
struct mtd_partition *mtd_parts = NULL;
|
|
|
|
int mtd_parts_nb = 0;
|
|
|
|
|
|
|
|
if (mtd_has_cmdlinepart()) {
|
|
|
|
static const char *probes[] __initconst =
|
|
|
|
{ "cmdlinepart", NULL };
|
|
|
|
|
|
|
|
mtd_parts_nb = parse_mtd_partitions(&info->mtd, probes,
|
|
|
|
&mtd_parts, 0);
|
|
|
|
}
|
|
|
|
|
2009-04-22 06:51:31 +04:00
|
|
|
if (mtd_parts_nb <= 0) {
|
2009-03-04 23:01:37 +03:00
|
|
|
mtd_parts = pdata->parts;
|
|
|
|
mtd_parts_nb = pdata->nr_parts;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Register any partitions */
|
|
|
|
if (mtd_parts_nb > 0) {
|
|
|
|
ret = add_mtd_partitions(&info->mtd,
|
|
|
|
mtd_parts, mtd_parts_nb);
|
|
|
|
if (ret == 0)
|
|
|
|
info->partitioned = true;
|
|
|
|
}
|
|
|
|
|
2009-04-22 06:51:31 +04:00
|
|
|
} else if (pdata->nr_parts) {
|
2009-03-04 23:01:37 +03:00
|
|
|
dev_warn(&pdev->dev, "ignoring %d default partitions on %s\n",
|
|
|
|
pdata->nr_parts, info->mtd.name);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If there's no partition info, just package the whole chip
|
|
|
|
* as a single MTD device.
|
|
|
|
*/
|
|
|
|
if (!info->partitioned)
|
|
|
|
ret = add_mtd_device(&info->mtd) ? -ENODEV : 0;
|
|
|
|
|
|
|
|
if (ret < 0)
|
|
|
|
goto err_scan;
|
|
|
|
|
|
|
|
val = davinci_nand_readl(info, NRCSR_OFFSET);
|
|
|
|
dev_info(&pdev->dev, "controller rev. %d.%d\n",
|
|
|
|
(val >> 8) & 0xff, val & 0xff);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_scan:
|
2010-08-09 14:16:36 +04:00
|
|
|
err_timing:
|
2009-03-04 23:01:37 +03:00
|
|
|
clk_disable(info->clk);
|
|
|
|
|
|
|
|
err_clk_enable:
|
|
|
|
clk_put(info->clk);
|
|
|
|
|
2009-04-22 06:58:13 +04:00
|
|
|
spin_lock_irq(&davinci_nand_lock);
|
|
|
|
if (ecc_mode == NAND_ECC_HW_SYNDROME)
|
|
|
|
ecc4_busy = false;
|
|
|
|
spin_unlock_irq(&davinci_nand_lock);
|
|
|
|
|
2009-03-04 23:01:37 +03:00
|
|
|
err_ecc:
|
|
|
|
err_clk:
|
|
|
|
err_ioremap:
|
|
|
|
if (base)
|
|
|
|
iounmap(base);
|
|
|
|
if (vaddr)
|
|
|
|
iounmap(vaddr);
|
|
|
|
|
|
|
|
err_nomem:
|
|
|
|
kfree(info);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int __exit nand_davinci_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct davinci_nand_info *info = platform_get_drvdata(pdev);
|
|
|
|
int status;
|
|
|
|
|
|
|
|
if (mtd_has_partitions() && info->partitioned)
|
|
|
|
status = del_mtd_partitions(&info->mtd);
|
|
|
|
else
|
|
|
|
status = del_mtd_device(&info->mtd);
|
|
|
|
|
2009-04-22 06:58:13 +04:00
|
|
|
spin_lock_irq(&davinci_nand_lock);
|
|
|
|
if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
|
|
|
|
ecc4_busy = false;
|
|
|
|
spin_unlock_irq(&davinci_nand_lock);
|
|
|
|
|
2009-03-04 23:01:37 +03:00
|
|
|
iounmap(info->base);
|
|
|
|
iounmap(info->vaddr);
|
|
|
|
|
|
|
|
nand_release(&info->mtd);
|
|
|
|
|
|
|
|
clk_disable(info->clk);
|
|
|
|
clk_put(info->clk);
|
|
|
|
|
|
|
|
kfree(info);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver nand_davinci_driver = {
|
|
|
|
.remove = __exit_p(nand_davinci_remove),
|
|
|
|
.driver = {
|
|
|
|
.name = "davinci_nand",
|
|
|
|
},
|
|
|
|
};
|
|
|
|
MODULE_ALIAS("platform:davinci_nand");
|
|
|
|
|
|
|
|
static int __init nand_davinci_init(void)
|
|
|
|
{
|
|
|
|
return platform_driver_probe(&nand_davinci_driver, nand_davinci_probe);
|
|
|
|
}
|
|
|
|
module_init(nand_davinci_init);
|
|
|
|
|
|
|
|
static void __exit nand_davinci_exit(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&nand_davinci_driver);
|
|
|
|
}
|
|
|
|
module_exit(nand_davinci_exit);
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_AUTHOR("Texas Instruments");
|
|
|
|
MODULE_DESCRIPTION("Davinci NAND flash driver");
|
|
|
|
|