2019-05-27 09:55:06 +03:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2014-10-08 11:31:10 +04:00
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/*
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* SMI PCIe driver for DVBSky cards.
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*
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* Copyright (C) 2014 Max nibble <nibble.max@gmail.com>
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*/
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#ifndef _SMI_PCIE_H_
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#define _SMI_PCIE_H_
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <media/rc-core.h>
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2017-12-28 21:03:51 +03:00
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#include <media/demux.h>
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#include <media/dmxdev.h>
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#include <media/dvb_demux.h>
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#include <media/dvb_frontend.h>
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#include <media/dvb_net.h>
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#include <media/dvbdev.h>
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2014-10-08 11:31:10 +04:00
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/* -------- Register Base -------- */
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#define MSI_CONTROL_REG_BASE 0x0800
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#define SYSTEM_CONTROL_REG_BASE 0x0880
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#define PCIE_EP_DEBUG_REG_BASE 0x08C0
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#define IR_CONTROL_REG_BASE 0x0900
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#define I2C_A_CONTROL_REG_BASE 0x0940
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#define I2C_B_CONTROL_REG_BASE 0x0980
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#define ATV_PORTA_CONTROL_REG_BASE 0x09C0
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#define DTV_PORTA_CONTROL_REG_BASE 0x0A00
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#define AES_PORTA_CONTROL_REG_BASE 0x0A80
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#define DMA_PORTA_CONTROL_REG_BASE 0x0AC0
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#define ATV_PORTB_CONTROL_REG_BASE 0x0B00
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#define DTV_PORTB_CONTROL_REG_BASE 0x0B40
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#define AES_PORTB_CONTROL_REG_BASE 0x0BC0
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#define DMA_PORTB_CONTROL_REG_BASE 0x0C00
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#define UART_A_REGISTER_BASE 0x0C40
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#define UART_B_REGISTER_BASE 0x0C80
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#define GPS_CONTROL_REG_BASE 0x0CC0
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#define DMA_PORTC_CONTROL_REG_BASE 0x0D00
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#define DMA_PORTD_CONTROL_REG_BASE 0x0D00
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#define AES_RANDOM_DATA_BASE 0x0D80
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#define AES_KEY_IN_BASE 0x0D90
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#define RANDOM_DATA_LIB_BASE 0x0E00
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#define IR_DATA_BUFFER_BASE 0x0F00
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#define PORTA_TS_BUFFER_BASE 0x1000
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#define PORTA_I2S_BUFFER_BASE 0x1400
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#define PORTB_TS_BUFFER_BASE 0x1800
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#define PORTB_I2S_BUFFER_BASE 0x1C00
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/* -------- MSI control and state register -------- */
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#define MSI_DELAY_TIMER (MSI_CONTROL_REG_BASE + 0x00)
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#define MSI_INT_STATUS (MSI_CONTROL_REG_BASE + 0x08)
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#define MSI_INT_STATUS_CLR (MSI_CONTROL_REG_BASE + 0x0C)
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#define MSI_INT_STATUS_SET (MSI_CONTROL_REG_BASE + 0x10)
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#define MSI_INT_ENA (MSI_CONTROL_REG_BASE + 0x14)
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#define MSI_INT_ENA_CLR (MSI_CONTROL_REG_BASE + 0x18)
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#define MSI_INT_ENA_SET (MSI_CONTROL_REG_BASE + 0x1C)
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#define MSI_SOFT_RESET (MSI_CONTROL_REG_BASE + 0x20)
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#define MSI_CFG_SRC0 (MSI_CONTROL_REG_BASE + 0x24)
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/* -------- Hybird Controller System Control register -------- */
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#define MUX_MODE_CTRL (SYSTEM_CONTROL_REG_BASE + 0x00)
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#define rbPaMSMask 0x07
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#define rbPaMSDtvNoGpio 0x00 /*[2:0], DTV Simple mode */
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#define rbPaMSDtv4bitGpio 0x01 /*[2:0], DTV TS2 Serial mode)*/
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#define rbPaMSDtv7bitGpio 0x02 /*[2:0], DTV TS0 Serial mode*/
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#define rbPaMS8bitGpio 0x03 /*[2:0], GPIO mode selected;(8bit GPIO)*/
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#define rbPaMSAtv 0x04 /*[2:0], 3'b1xx: ATV mode select*/
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#define rbPbMSMask 0x38
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#define rbPbMSDtvNoGpio 0x00 /*[5:3], DTV Simple mode */
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#define rbPbMSDtv4bitGpio 0x08 /*[5:3], DTV TS2 Serial mode*/
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#define rbPbMSDtv7bitGpio 0x10 /*[5:3], DTV TS0 Serial mode*/
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#define rbPbMS8bitGpio 0x18 /*[5:3], GPIO mode selected;(8bit GPIO)*/
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#define rbPbMSAtv 0x20 /*[5:3], 3'b1xx: ATV mode select*/
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#define rbPaAESEN 0x40 /*[6], port A AES enable bit*/
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#define rbPbAESEN 0x80 /*[7], port B AES enable bit*/
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#define INTERNAL_RST (SYSTEM_CONTROL_REG_BASE + 0x04)
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#define PERIPHERAL_CTRL (SYSTEM_CONTROL_REG_BASE + 0x08)
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#define GPIO_0to7_CTRL (SYSTEM_CONTROL_REG_BASE + 0x0C)
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#define GPIO_8to15_CTRL (SYSTEM_CONTROL_REG_BASE + 0x10)
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#define GPIO_16to24_CTRL (SYSTEM_CONTROL_REG_BASE + 0x14)
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#define GPIO_INT_SRC_CFG (SYSTEM_CONTROL_REG_BASE + 0x18)
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#define SYS_BUF_STATUS (SYSTEM_CONTROL_REG_BASE + 0x1C)
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#define PCIE_IP_REG_ACS (SYSTEM_CONTROL_REG_BASE + 0x20)
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#define PCIE_IP_REG_ACS_ADDR (SYSTEM_CONTROL_REG_BASE + 0x24)
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#define PCIE_IP_REG_ACS_DATA (SYSTEM_CONTROL_REG_BASE + 0x28)
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/* -------- IR Control register -------- */
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#define IR_Init_Reg (IR_CONTROL_REG_BASE + 0x00)
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#define IR_Idle_Cnt_Low (IR_CONTROL_REG_BASE + 0x04)
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#define IR_Idle_Cnt_High (IR_CONTROL_REG_BASE + 0x05)
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#define IR_Unit_Cnt_Low (IR_CONTROL_REG_BASE + 0x06)
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#define IR_Unit_Cnt_High (IR_CONTROL_REG_BASE + 0x07)
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#define IR_Data_Cnt (IR_CONTROL_REG_BASE + 0x08)
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#define rbIRen 0x80
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#define rbIRhighidle 0x10
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#define rbIRlowidle 0x00
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#define rbIRVld 0x04
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/* -------- I2C A control and state register -------- */
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#define I2C_A_CTL_STATUS (I2C_A_CONTROL_REG_BASE + 0x00)
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#define I2C_A_ADDR (I2C_A_CONTROL_REG_BASE + 0x04)
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#define I2C_A_SW_CTL (I2C_A_CONTROL_REG_BASE + 0x08)
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#define I2C_A_TIME_OUT_CNT (I2C_A_CONTROL_REG_BASE + 0x0C)
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#define I2C_A_FIFO_STATUS (I2C_A_CONTROL_REG_BASE + 0x10)
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#define I2C_A_FS_EN (I2C_A_CONTROL_REG_BASE + 0x14)
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#define I2C_A_FIFO_DATA (I2C_A_CONTROL_REG_BASE + 0x20)
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/* -------- I2C B control and state register -------- */
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#define I2C_B_CTL_STATUS (I2C_B_CONTROL_REG_BASE + 0x00)
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#define I2C_B_ADDR (I2C_B_CONTROL_REG_BASE + 0x04)
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#define I2C_B_SW_CTL (I2C_B_CONTROL_REG_BASE + 0x08)
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#define I2C_B_TIME_OUT_CNT (I2C_B_CONTROL_REG_BASE + 0x0C)
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#define I2C_B_FIFO_STATUS (I2C_B_CONTROL_REG_BASE + 0x10)
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#define I2C_B_FS_EN (I2C_B_CONTROL_REG_BASE + 0x14)
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#define I2C_B_FIFO_DATA (I2C_B_CONTROL_REG_BASE + 0x20)
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#define VIDEO_CTRL_STATUS_A (ATV_PORTA_CONTROL_REG_BASE + 0x04)
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/* -------- Digital TV control register, Port A -------- */
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#define MPEG2_CTRL_A (DTV_PORTA_CONTROL_REG_BASE + 0x00)
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#define SERIAL_IN_ADDR_A (DTV_PORTA_CONTROL_REG_BASE + 0x4C)
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#define VLD_CNT_ADDR_A (DTV_PORTA_CONTROL_REG_BASE + 0x60)
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#define ERR_CNT_ADDR_A (DTV_PORTA_CONTROL_REG_BASE + 0x64)
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#define BRD_CNT_ADDR_A (DTV_PORTA_CONTROL_REG_BASE + 0x68)
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/* -------- DMA Control Register, Port A -------- */
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#define DMA_PORTA_CHAN0_ADDR_LOW (DMA_PORTA_CONTROL_REG_BASE + 0x00)
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#define DMA_PORTA_CHAN0_ADDR_HI (DMA_PORTA_CONTROL_REG_BASE + 0x04)
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#define DMA_PORTA_CHAN0_TRANS_STATE (DMA_PORTA_CONTROL_REG_BASE + 0x08)
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#define DMA_PORTA_CHAN0_CONTROL (DMA_PORTA_CONTROL_REG_BASE + 0x0C)
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#define DMA_PORTA_CHAN1_ADDR_LOW (DMA_PORTA_CONTROL_REG_BASE + 0x10)
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#define DMA_PORTA_CHAN1_ADDR_HI (DMA_PORTA_CONTROL_REG_BASE + 0x14)
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#define DMA_PORTA_CHAN1_TRANS_STATE (DMA_PORTA_CONTROL_REG_BASE + 0x18)
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#define DMA_PORTA_CHAN1_CONTROL (DMA_PORTA_CONTROL_REG_BASE + 0x1C)
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#define DMA_PORTA_MANAGEMENT (DMA_PORTA_CONTROL_REG_BASE + 0x20)
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#define VIDEO_CTRL_STATUS_B (ATV_PORTB_CONTROL_REG_BASE + 0x04)
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/* -------- Digital TV control register, Port B -------- */
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#define MPEG2_CTRL_B (DTV_PORTB_CONTROL_REG_BASE + 0x00)
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#define SERIAL_IN_ADDR_B (DTV_PORTB_CONTROL_REG_BASE + 0x4C)
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#define VLD_CNT_ADDR_B (DTV_PORTB_CONTROL_REG_BASE + 0x60)
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#define ERR_CNT_ADDR_B (DTV_PORTB_CONTROL_REG_BASE + 0x64)
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#define BRD_CNT_ADDR_B (DTV_PORTB_CONTROL_REG_BASE + 0x68)
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/* -------- AES control register, Port B -------- */
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#define AES_CTRL_B (AES_PORTB_CONTROL_REG_BASE + 0x00)
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#define AES_KEY_BASE_B (AES_PORTB_CONTROL_REG_BASE + 0x04)
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/* -------- DMA Control Register, Port B -------- */
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#define DMA_PORTB_CHAN0_ADDR_LOW (DMA_PORTB_CONTROL_REG_BASE + 0x00)
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#define DMA_PORTB_CHAN0_ADDR_HI (DMA_PORTB_CONTROL_REG_BASE + 0x04)
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#define DMA_PORTB_CHAN0_TRANS_STATE (DMA_PORTB_CONTROL_REG_BASE + 0x08)
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#define DMA_PORTB_CHAN0_CONTROL (DMA_PORTB_CONTROL_REG_BASE + 0x0C)
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#define DMA_PORTB_CHAN1_ADDR_LOW (DMA_PORTB_CONTROL_REG_BASE + 0x10)
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#define DMA_PORTB_CHAN1_ADDR_HI (DMA_PORTB_CONTROL_REG_BASE + 0x14)
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#define DMA_PORTB_CHAN1_TRANS_STATE (DMA_PORTB_CONTROL_REG_BASE + 0x18)
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#define DMA_PORTB_CHAN1_CONTROL (DMA_PORTB_CONTROL_REG_BASE + 0x1C)
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#define DMA_PORTB_MANAGEMENT (DMA_PORTB_CONTROL_REG_BASE + 0x20)
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#define DMA_TRANS_UNIT_188 (0x00000007)
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/* -------- Macro define of 24 interrupt resource --------*/
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#define DMA_A_CHAN0_DONE_INT (0x00000001)
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#define DMA_A_CHAN1_DONE_INT (0x00000002)
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#define DMA_B_CHAN0_DONE_INT (0x00000004)
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#define DMA_B_CHAN1_DONE_INT (0x00000008)
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#define DMA_C_CHAN0_DONE_INT (0x00000010)
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#define DMA_C_CHAN1_DONE_INT (0x00000020)
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#define DMA_D_CHAN0_DONE_INT (0x00000040)
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#define DMA_D_CHAN1_DONE_INT (0x00000080)
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#define DATA_BUF_OVERFLOW_INT (0x00000100)
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#define UART_0_X_INT (0x00000200)
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#define UART_1_X_INT (0x00000400)
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#define IR_X_INT (0x00000800)
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#define GPIO_0_INT (0x00001000)
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#define GPIO_1_INT (0x00002000)
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#define GPIO_2_INT (0x00004000)
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#define GPIO_3_INT (0x00008000)
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#define ALL_INT (0x0000FFFF)
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/* software I2C bit mask */
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#define SW_I2C_MSK_MODE 0x01
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#define SW_I2C_MSK_CLK_OUT 0x02
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#define SW_I2C_MSK_DAT_OUT 0x04
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#define SW_I2C_MSK_CLK_EN 0x08
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#define SW_I2C_MSK_DAT_EN 0x10
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#define SW_I2C_MSK_DAT_IN 0x40
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#define SW_I2C_MSK_CLK_IN 0x80
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#define SMI_VID 0x1ADE
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#define SMI_PID 0x3038
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#define SMI_TS_DMA_BUF_SIZE (1024 * 188)
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struct smi_cfg_info {
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#define SMI_DVBSKY_S952 0
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#define SMI_DVBSKY_S950 1
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#define SMI_DVBSKY_T9580 2
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#define SMI_DVBSKY_T982 3
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2016-03-10 01:38:27 +03:00
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#define SMI_TECHNOTREND_S2_4200 4
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2014-10-08 11:31:10 +04:00
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int type;
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char *name;
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#define SMI_TS_NULL 0
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#define SMI_TS_DMA_SINGLE 1
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#define SMI_TS_DMA_BOTH 3
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/* SMI_TS_NULL: not use;
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* SMI_TS_DMA_SINGLE: use DMA 0 only;
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* SMI_TS_DMA_BOTH:use DMA 0 and 1.*/
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int ts_0;
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int ts_1;
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#define DVBSKY_FE_NULL 0
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#define DVBSKY_FE_M88RS6000 1
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#define DVBSKY_FE_M88DS3103 2
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#define DVBSKY_FE_SIT2 3
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int fe_0;
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int fe_1;
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2016-03-11 09:48:03 +03:00
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char *rc_map;
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2014-10-08 11:31:10 +04:00
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};
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2015-06-29 17:09:42 +03:00
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struct smi_rc {
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struct smi_dev *dev;
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struct rc_dev *rc_dev;
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char input_phys[64];
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2017-07-01 19:13:19 +03:00
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char device_name[64];
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2015-06-29 17:09:42 +03:00
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u8 irData[256];
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int users;
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};
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2014-10-08 11:31:10 +04:00
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struct smi_port {
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struct smi_dev *dev;
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int idx;
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int enable;
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int fe_type;
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/* regs */
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u32 DMA_CHAN0_ADDR_LOW;
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u32 DMA_CHAN0_ADDR_HI;
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u32 DMA_CHAN0_TRANS_STATE;
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u32 DMA_CHAN0_CONTROL;
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u32 DMA_CHAN1_ADDR_LOW;
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u32 DMA_CHAN1_ADDR_HI;
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u32 DMA_CHAN1_TRANS_STATE;
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u32 DMA_CHAN1_CONTROL;
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u32 DMA_MANAGEMENT;
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/* dma */
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dma_addr_t dma_addr[2];
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u8 *cpu_addr[2];
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u32 _dmaInterruptCH0;
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u32 _dmaInterruptCH1;
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u32 _int_status;
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struct tasklet_struct tasklet;
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/* dvb */
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struct dmx_frontend hw_frontend;
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struct dmx_frontend mem_frontend;
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struct dmxdev dmxdev;
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struct dvb_adapter dvb_adapter;
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struct dvb_demux demux;
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struct dvb_net dvbnet;
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|
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int users;
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struct dvb_frontend *fe;
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|
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|
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/* frontend i2c module */
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|
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struct i2c_client *i2c_client_demod;
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struct i2c_client *i2c_client_tuner;
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|
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};
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struct smi_dev {
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int nr;
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|
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struct smi_cfg_info *info;
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|
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/* pcie */
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struct pci_dev *pci_dev;
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|
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u32 __iomem *lmmio;
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|
|
/* ts port */
|
|
|
|
|
struct smi_port ts_port[2];
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|
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/* i2c */
|
|
|
|
|
struct i2c_adapter i2c_bus[2];
|
|
|
|
|
struct i2c_algo_bit_data i2c_bit[2];
|
2015-06-29 17:09:42 +03:00
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|
|
|
|
|
|
/* ir */
|
|
|
|
|
struct smi_rc ir;
|
2014-10-08 11:31:10 +04:00
|
|
|
};
|
|
|
|
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|
|
|
|
#define smi_read(reg) readl(dev->lmmio + ((reg)>>2))
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|
|
#define smi_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
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|
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|
|
#define smi_andor(reg, mask, value) \
|
|
|
|
|
writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
|
|
|
|
|
((value) & (mask)), dev->lmmio+((reg)>>2))
|
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|
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|
|
#define smi_set(reg, bit) smi_andor((reg), (bit), (bit))
|
|
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|
|
#define smi_clear(reg, bit) smi_andor((reg), (bit), 0)
|
|
|
|
|
|
2015-06-29 17:09:42 +03:00
|
|
|
int smi_ir_irq(struct smi_rc *ir, u32 int_status);
|
|
|
|
|
void smi_ir_start(struct smi_rc *ir);
|
|
|
|
|
void smi_ir_exit(struct smi_dev *dev);
|
|
|
|
|
int smi_ir_init(struct smi_dev *dev);
|
|
|
|
|
|
2014-10-08 11:31:10 +04:00
|
|
|
#endif /* #ifndef _SMI_PCIE_H_ */
|
