496 строки
12 KiB
C
496 строки
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Actions Semiconductor Owl SoC's I2C driver
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*
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* Copyright (c) 2014 Actions Semi Inc.
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* Author: David Liu <liuwei@actions-semi.com>
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*
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* Copyright (c) 2018 Linaro Ltd.
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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/* I2C registers */
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#define OWL_I2C_REG_CTL 0x0000
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#define OWL_I2C_REG_CLKDIV 0x0004
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#define OWL_I2C_REG_STAT 0x0008
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#define OWL_I2C_REG_ADDR 0x000C
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#define OWL_I2C_REG_TXDAT 0x0010
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#define OWL_I2C_REG_RXDAT 0x0014
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#define OWL_I2C_REG_CMD 0x0018
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#define OWL_I2C_REG_FIFOCTL 0x001C
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#define OWL_I2C_REG_FIFOSTAT 0x0020
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#define OWL_I2C_REG_DATCNT 0x0024
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#define OWL_I2C_REG_RCNT 0x0028
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/* I2Cx_CTL Bit Mask */
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#define OWL_I2C_CTL_RB BIT(1)
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#define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2)
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#define OWL_I2C_CTL_GBCC_NONE OWL_I2C_CTL_GBCC(0)
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#define OWL_I2C_CTL_GBCC_START OWL_I2C_CTL_GBCC(1)
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#define OWL_I2C_CTL_GBCC_STOP OWL_I2C_CTL_GBCC(2)
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#define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3)
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#define OWL_I2C_CTL_IRQE BIT(5)
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#define OWL_I2C_CTL_EN BIT(7)
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#define OWL_I2C_CTL_AE BIT(8)
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#define OWL_I2C_CTL_SHSM BIT(10)
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#define OWL_I2C_DIV_FACTOR(x) ((x) & 0xff)
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/* I2Cx_STAT Bit Mask */
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#define OWL_I2C_STAT_RACK BIT(0)
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#define OWL_I2C_STAT_BEB BIT(1)
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#define OWL_I2C_STAT_IRQP BIT(2)
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#define OWL_I2C_STAT_LAB BIT(3)
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#define OWL_I2C_STAT_STPD BIT(4)
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#define OWL_I2C_STAT_STAD BIT(5)
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#define OWL_I2C_STAT_BBB BIT(6)
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#define OWL_I2C_STAT_TCB BIT(7)
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#define OWL_I2C_STAT_LBST BIT(8)
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#define OWL_I2C_STAT_SAMB BIT(9)
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#define OWL_I2C_STAT_SRGC BIT(10)
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/* I2Cx_CMD Bit Mask */
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#define OWL_I2C_CMD_SBE BIT(0)
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#define OWL_I2C_CMD_RBE BIT(4)
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#define OWL_I2C_CMD_DE BIT(8)
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#define OWL_I2C_CMD_NS BIT(9)
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#define OWL_I2C_CMD_SE BIT(10)
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#define OWL_I2C_CMD_MSS BIT(11)
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#define OWL_I2C_CMD_WRS BIT(12)
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#define OWL_I2C_CMD_SECL BIT(15)
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#define OWL_I2C_CMD_AS(x) (((x) & 0x7) << 1)
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#define OWL_I2C_CMD_SAS(x) (((x) & 0x7) << 5)
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/* I2Cx_FIFOCTL Bit Mask */
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#define OWL_I2C_FIFOCTL_NIB BIT(0)
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#define OWL_I2C_FIFOCTL_RFR BIT(1)
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#define OWL_I2C_FIFOCTL_TFR BIT(2)
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/* I2Cc_FIFOSTAT Bit Mask */
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#define OWL_I2C_FIFOSTAT_RNB BIT(1)
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#define OWL_I2C_FIFOSTAT_RFE BIT(2)
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#define OWL_I2C_FIFOSTAT_TFF BIT(5)
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#define OWL_I2C_FIFOSTAT_TFD GENMASK(23, 16)
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#define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8)
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/* I2C bus timeout */
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#define OWL_I2C_TIMEOUT msecs_to_jiffies(4 * 1000)
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#define OWL_I2C_MAX_RETRIES 50
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#define OWL_I2C_DEF_SPEED_HZ 100000
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#define OWL_I2C_MAX_SPEED_HZ 400000
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struct owl_i2c_dev {
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struct i2c_adapter adap;
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struct i2c_msg *msg;
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struct completion msg_complete;
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struct clk *clk;
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spinlock_t lock;
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void __iomem *base;
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unsigned long clk_rate;
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u32 bus_freq;
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u32 msg_ptr;
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int err;
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};
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static void owl_i2c_update_reg(void __iomem *reg, unsigned int val, bool state)
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{
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unsigned int regval;
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regval = readl(reg);
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if (state)
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regval |= val;
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else
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regval &= ~val;
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writel(regval, reg);
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}
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static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev)
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{
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owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
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OWL_I2C_CTL_EN, false);
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mdelay(1);
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owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
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OWL_I2C_CTL_EN, true);
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/* Clear status registers */
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writel(0, i2c_dev->base + OWL_I2C_REG_STAT);
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}
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static int owl_i2c_reset_fifo(struct owl_i2c_dev *i2c_dev)
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{
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unsigned int val, timeout = 0;
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/* Reset FIFO */
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owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
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OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR,
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true);
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/* Wait 50ms for FIFO reset complete */
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do {
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val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL);
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if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR)))
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break;
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usleep_range(500, 1000);
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} while (timeout++ < OWL_I2C_MAX_RETRIES);
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if (timeout > OWL_I2C_MAX_RETRIES) {
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dev_err(&i2c_dev->adap.dev, "FIFO reset timeout\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev)
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{
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unsigned int val;
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val = DIV_ROUND_UP(i2c_dev->clk_rate, i2c_dev->bus_freq * 16);
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/* Set clock divider factor */
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writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV);
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}
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static irqreturn_t owl_i2c_interrupt(int irq, void *_dev)
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{
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struct owl_i2c_dev *i2c_dev = _dev;
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struct i2c_msg *msg = i2c_dev->msg;
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unsigned long flags;
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unsigned int stat, fifostat;
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spin_lock_irqsave(&i2c_dev->lock, flags);
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i2c_dev->err = 0;
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/* Handle NACK from slave */
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fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT);
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if (fifostat & OWL_I2C_FIFOSTAT_RNB) {
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i2c_dev->err = -ENXIO;
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goto stop;
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}
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/* Handle bus error */
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stat = readl(i2c_dev->base + OWL_I2C_REG_STAT);
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if (stat & OWL_I2C_STAT_BEB) {
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i2c_dev->err = -EIO;
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goto stop;
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}
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/* Handle FIFO read */
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if (msg->flags & I2C_M_RD) {
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while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
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OWL_I2C_FIFOSTAT_RFE) && i2c_dev->msg_ptr < msg->len) {
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msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base +
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OWL_I2C_REG_RXDAT);
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}
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} else {
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/* Handle the remaining bytes which were not sent */
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while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
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OWL_I2C_FIFOSTAT_TFF) && i2c_dev->msg_ptr < msg->len) {
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writel(msg->buf[i2c_dev->msg_ptr++],
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i2c_dev->base + OWL_I2C_REG_TXDAT);
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}
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}
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stop:
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/* Clear pending interrupts */
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owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT,
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OWL_I2C_STAT_IRQP, true);
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complete_all(&i2c_dev->msg_complete);
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spin_unlock_irqrestore(&i2c_dev->lock, flags);
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return IRQ_HANDLED;
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}
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static u32 owl_i2c_func(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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}
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static int owl_i2c_check_bus_busy(struct i2c_adapter *adap)
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{
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struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
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unsigned long timeout;
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/* Check for Bus busy */
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timeout = jiffies + OWL_I2C_TIMEOUT;
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while (readl(i2c_dev->base + OWL_I2C_REG_STAT) & OWL_I2C_STAT_BBB) {
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if (time_after(jiffies, timeout)) {
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dev_err(&adap->dev, "Bus busy timeout\n");
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return -ETIMEDOUT;
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}
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}
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return 0;
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}
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static int owl_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
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int num)
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{
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struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
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struct i2c_msg *msg;
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unsigned long time_left, flags;
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unsigned int i2c_cmd, val;
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unsigned int addr;
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int ret, idx;
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spin_lock_irqsave(&i2c_dev->lock, flags);
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/* Reset I2C controller */
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owl_i2c_reset(i2c_dev);
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/* Set bus frequency */
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owl_i2c_set_freq(i2c_dev);
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/*
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* Spinlock should be released before calling reset FIFO and
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* bus busy check since those functions may sleep
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*/
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spin_unlock_irqrestore(&i2c_dev->lock, flags);
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/* Reset FIFO */
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ret = owl_i2c_reset_fifo(i2c_dev);
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if (ret)
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goto unlocked_err_exit;
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/* Check for bus busy */
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ret = owl_i2c_check_bus_busy(adap);
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if (ret)
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goto unlocked_err_exit;
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spin_lock_irqsave(&i2c_dev->lock, flags);
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/* Check for Arbitration lost */
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val = readl(i2c_dev->base + OWL_I2C_REG_STAT);
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if (val & OWL_I2C_STAT_LAB) {
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val &= ~OWL_I2C_STAT_LAB;
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writel(val, i2c_dev->base + OWL_I2C_REG_STAT);
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ret = -EAGAIN;
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goto err_exit;
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}
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reinit_completion(&i2c_dev->msg_complete);
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/* Enable I2C controller interrupt */
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owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
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OWL_I2C_CTL_IRQE, true);
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/*
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* Select: FIFO enable, Master mode, Stop enable, Data count enable,
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* Send start bit
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*/
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i2c_cmd = OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE |
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OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE;
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/* Handle repeated start condition */
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if (num > 1) {
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/* Set internal address length and enable repeated start */
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i2c_cmd |= OWL_I2C_CMD_AS(msgs[0].len + 1) |
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OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE;
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/* Write slave address */
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addr = i2c_8bit_addr_from_msg(&msgs[0]);
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writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
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/* Write internal register address */
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for (idx = 0; idx < msgs[0].len; idx++)
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writel(msgs[0].buf[idx],
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i2c_dev->base + OWL_I2C_REG_TXDAT);
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msg = &msgs[1];
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} else {
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/* Set address length */
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i2c_cmd |= OWL_I2C_CMD_AS(1);
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msg = &msgs[0];
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}
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i2c_dev->msg = msg;
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i2c_dev->msg_ptr = 0;
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/* Set data count for the message */
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writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT);
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addr = i2c_8bit_addr_from_msg(msg);
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writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
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if (!(msg->flags & I2C_M_RD)) {
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/* Write data to FIFO */
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for (idx = 0; idx < msg->len; idx++) {
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/* Check for FIFO full */
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if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
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OWL_I2C_FIFOSTAT_TFF)
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break;
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writel(msg->buf[idx],
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i2c_dev->base + OWL_I2C_REG_TXDAT);
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}
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i2c_dev->msg_ptr = idx;
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}
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/* Ignore the NACK if needed */
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if (msg->flags & I2C_M_IGNORE_NAK)
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owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
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OWL_I2C_FIFOCTL_NIB, true);
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else
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owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
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OWL_I2C_FIFOCTL_NIB, false);
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/* Start the transfer */
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writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD);
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spin_unlock_irqrestore(&i2c_dev->lock, flags);
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time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
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adap->timeout);
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spin_lock_irqsave(&i2c_dev->lock, flags);
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if (time_left == 0) {
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dev_err(&adap->dev, "Transaction timed out\n");
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/* Send stop condition and release the bus */
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owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
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OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB,
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true);
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ret = -ETIMEDOUT;
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goto err_exit;
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}
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ret = i2c_dev->err < 0 ? i2c_dev->err : num;
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err_exit:
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spin_unlock_irqrestore(&i2c_dev->lock, flags);
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unlocked_err_exit:
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/* Disable I2C controller */
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owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
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OWL_I2C_CTL_EN, false);
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|
return ret;
|
||
|
}
|
||
|
|
||
|
static const struct i2c_algorithm owl_i2c_algorithm = {
|
||
|
.master_xfer = owl_i2c_master_xfer,
|
||
|
.functionality = owl_i2c_func,
|
||
|
};
|
||
|
|
||
|
static const struct i2c_adapter_quirks owl_i2c_quirks = {
|
||
|
.flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST,
|
||
|
.max_read_len = 240,
|
||
|
.max_write_len = 240,
|
||
|
.max_comb_1st_msg_len = 6,
|
||
|
.max_comb_2nd_msg_len = 240,
|
||
|
};
|
||
|
|
||
|
static int owl_i2c_probe(struct platform_device *pdev)
|
||
|
{
|
||
|
struct device *dev = &pdev->dev;
|
||
|
struct owl_i2c_dev *i2c_dev;
|
||
|
struct resource *res;
|
||
|
int ret, irq;
|
||
|
|
||
|
i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL);
|
||
|
if (!i2c_dev)
|
||
|
return -ENOMEM;
|
||
|
|
||
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||
|
i2c_dev->base = devm_ioremap_resource(dev, res);
|
||
|
if (IS_ERR(i2c_dev->base))
|
||
|
return PTR_ERR(i2c_dev->base);
|
||
|
|
||
|
irq = platform_get_irq(pdev, 0);
|
||
|
if (irq < 0) {
|
||
|
dev_err(dev, "failed to get IRQ number\n");
|
||
|
return irq;
|
||
|
}
|
||
|
|
||
|
if (of_property_read_u32(dev->of_node, "clock-frequency",
|
||
|
&i2c_dev->bus_freq))
|
||
|
i2c_dev->bus_freq = OWL_I2C_DEF_SPEED_HZ;
|
||
|
|
||
|
/* We support only frequencies of 100k and 400k for now */
|
||
|
if (i2c_dev->bus_freq != OWL_I2C_DEF_SPEED_HZ &&
|
||
|
i2c_dev->bus_freq != OWL_I2C_MAX_SPEED_HZ) {
|
||
|
dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq);
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
|
||
|
i2c_dev->clk = devm_clk_get(dev, NULL);
|
||
|
if (IS_ERR(i2c_dev->clk)) {
|
||
|
dev_err(dev, "failed to get clock\n");
|
||
|
return PTR_ERR(i2c_dev->clk);
|
||
|
}
|
||
|
|
||
|
ret = clk_prepare_enable(i2c_dev->clk);
|
||
|
if (ret)
|
||
|
return ret;
|
||
|
|
||
|
i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk);
|
||
|
if (!i2c_dev->clk_rate) {
|
||
|
dev_err(dev, "input clock rate should not be zero\n");
|
||
|
ret = -EINVAL;
|
||
|
goto disable_clk;
|
||
|
}
|
||
|
|
||
|
init_completion(&i2c_dev->msg_complete);
|
||
|
spin_lock_init(&i2c_dev->lock);
|
||
|
i2c_dev->adap.owner = THIS_MODULE;
|
||
|
i2c_dev->adap.algo = &owl_i2c_algorithm;
|
||
|
i2c_dev->adap.timeout = OWL_I2C_TIMEOUT;
|
||
|
i2c_dev->adap.quirks = &owl_i2c_quirks;
|
||
|
i2c_dev->adap.dev.parent = dev;
|
||
|
i2c_dev->adap.dev.of_node = dev->of_node;
|
||
|
snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
|
||
|
"%s", "OWL I2C adapter");
|
||
|
i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
|
||
|
|
||
|
platform_set_drvdata(pdev, i2c_dev);
|
||
|
|
||
|
ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name,
|
||
|
i2c_dev);
|
||
|
if (ret) {
|
||
|
dev_err(dev, "failed to request irq %d\n", irq);
|
||
|
goto disable_clk;
|
||
|
}
|
||
|
|
||
|
return i2c_add_adapter(&i2c_dev->adap);
|
||
|
|
||
|
disable_clk:
|
||
|
clk_disable_unprepare(i2c_dev->clk);
|
||
|
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
static const struct of_device_id owl_i2c_of_match[] = {
|
||
|
{ .compatible = "actions,s900-i2c" },
|
||
|
{ /* sentinel */ }
|
||
|
};
|
||
|
MODULE_DEVICE_TABLE(of, owl_i2c_of_match);
|
||
|
|
||
|
static struct platform_driver owl_i2c_driver = {
|
||
|
.probe = owl_i2c_probe,
|
||
|
.driver = {
|
||
|
.name = "owl-i2c",
|
||
|
.of_match_table = of_match_ptr(owl_i2c_of_match),
|
||
|
},
|
||
|
};
|
||
|
module_platform_driver(owl_i2c_driver);
|
||
|
|
||
|
MODULE_AUTHOR("David Liu <liuwei@actions-semi.com>");
|
||
|
MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
|
||
|
MODULE_DESCRIPTION("Actions Semiconductor Owl SoC's I2C driver");
|
||
|
MODULE_LICENSE("GPL");
|