2019-06-04 11:11:33 +03:00
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// SPDX-License-Identifier: GPL-2.0-only
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2007-09-12 06:13:17 +04:00
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/*
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* linux/arch/arm/mach-pxa/pxa3xx.c
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*
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* code specific to pxa3xx aka Monahans
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*
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* Copyright (C) 2006 Marvell International Ltd.
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*
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2007-10-30 10:01:38 +03:00
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* 2007-09-02: eric miao <eric.miao@marvell.com>
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2007-09-12 06:13:17 +04:00
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* initial version
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*/
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2018-06-17 20:02:05 +03:00
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#include <linux/dmaengine.h>
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#include <linux/dma/pxa-dma.h>
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2007-09-12 06:13:17 +04:00
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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2013-04-09 14:12:04 +04:00
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#include <linux/gpio-pxa.h>
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2007-09-12 06:13:17 +04:00
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#include <linux/pm.h>
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#include <linux/platform_device.h>
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#include <linux/irq.h>
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2016-08-15 01:24:55 +03:00
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#include <linux/irqchip.h>
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2008-01-08 01:18:30 +03:00
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#include <linux/io.h>
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2012-07-25 19:52:52 +04:00
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#include <linux/of.h>
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2011-04-23 00:03:11 +04:00
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#include <linux/syscore_ops.h>
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2017-11-13 20:27:39 +03:00
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#include <linux/platform_data/i2c-pxa.h>
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2018-06-17 20:02:05 +03:00
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#include <linux/platform_data/mmp_dma.h>
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2007-09-12 06:13:17 +04:00
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2010-10-11 04:20:19 +04:00
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#include <asm/mach/map.h>
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2011-06-22 20:41:48 +04:00
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#include <asm/suspend.h>
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2008-08-05 19:14:15 +04:00
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#include <mach/hardware.h>
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#include <mach/pxa3xx-regs.h>
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2008-08-07 14:05:25 +04:00
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#include <mach/reset.h>
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2012-08-24 17:16:48 +04:00
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#include <linux/platform_data/usb-ohci-pxa27x.h>
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2015-01-30 12:45:33 +03:00
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#include "pm.h"
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2008-08-05 19:14:15 +04:00
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#include <mach/dma.h>
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2010-11-03 18:29:35 +03:00
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#include <mach/smemc.h>
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2012-01-04 02:53:48 +04:00
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#include <mach/irqs.h>
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2007-09-12 06:13:17 +04:00
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#include "generic.h"
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#include "devices.h"
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2009-11-11 12:36:59 +03:00
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#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
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#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
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2012-07-22 21:50:22 +04:00
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extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
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2008-01-08 01:18:30 +03:00
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2015-08-23 22:13:57 +03:00
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/*
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* NAND NFC: DFI bus arbitration subset
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*/
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#define NDCR (*(volatile u32 __iomem*)(NAND_VIRT + 0))
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#define NDCR_ND_ARB_EN (1 << 12)
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#define NDCR_ND_ARB_CNTL (1 << 19)
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2015-10-12 16:44:49 +03:00
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#ifdef CONFIG_PM
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#define ISRAM_START 0x5c000000
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#define ISRAM_SIZE SZ_256K
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2008-01-08 01:18:30 +03:00
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static void __iomem *sram;
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static unsigned long wakeup_src;
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/*
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* Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
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* memory controller has to be reinitialised, so we place some code
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* in the SRAM to perform this function.
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*
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* We disable FIQs across the standby - otherwise, we might receive a
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* FIQ while the SDRAM is unavailable.
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*/
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static void pxa3xx_cpu_standby(unsigned int pwrmode)
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{
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void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
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memcpy_toio(sram + 0x8000, pm_enter_standby_start,
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pm_enter_standby_end - pm_enter_standby_start);
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AD2D0SR = ~0;
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AD2D1SR = ~0;
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AD2D0ER = wakeup_src;
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AD2D1ER = 0;
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ASCR = ASCR;
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ARSR = ARSR;
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local_fiq_disable();
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fn(pwrmode);
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local_fiq_enable();
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AD2D0ER = 0;
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AD2D1ER = 0;
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}
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2008-01-29 02:00:02 +03:00
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/*
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* NOTE: currently, the OBM (OEM Boot Module) binary comes along with
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* PXA3xx development kits assumes that the resuming process continues
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* with the address stored within the first 4 bytes of SDRAM. The PSPR
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* register is used privately by BootROM and OBM, and _must_ be set to
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* 0x5c014000 for the moment.
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*/
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static void pxa3xx_cpu_pm_suspend(void)
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{
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volatile unsigned long *p = (volatile void *)0xc0000000;
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unsigned long saved_data = *p;
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2011-06-21 19:29:30 +04:00
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#ifndef CONFIG_IWMMXT
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u64 acc0;
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2008-01-29 02:00:02 +03:00
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ARM: pxa: fix building without IWMMXT
When CONFIG_IWMMXT, the pxa3xx and pxa27x suspend/resume code
emits some xscale specific instructions, which are rejected
by the assembler, because gcc is built with -march=armv5
-mtune=xscale and passes that option to the assembler:
/tmp/cciHumzr.s:553: Error: selected processor does not support ARM mode `mra r2,r3,acc0'
/tmp/cciHumzr.s:605: Error: selected processor does not support ARM mode `mar acc0,r2,r3'
make[3]: *** [arch/arm/mach-pxa/pxa3xx.o] Error 1
/tmp/cci5MUNu.s:326: Error: selected processor does not support ARM mode `mra r2,r3,acc0'
/tmp/cci5MUNu.s:367: Error: selected processor does not support ARM mode `mar acc0,r2,r3'
make[3]: *** [arch/arm/mach-pxa/pxa27x.o] Error 1
Overriding with -Wa,-march=xscale no longer works, so instead
I'm adding an explict ".arch_extension" directive in all four inline
assembly statements, which should work even if they end up in a different
order in the assembly output.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2016-01-29 17:06:31 +03:00
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asm volatile(".arch_extension xscale\n\t"
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"mra %Q0, %R0, acc0" : "=r" (acc0));
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2011-06-21 19:29:30 +04:00
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#endif
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2008-01-29 02:00:02 +03:00
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/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
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CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
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CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
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/* clear and setup wakeup source */
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AD3SR = ~0;
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AD3ER = wakeup_src;
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ASCR = ASCR;
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ARSR = ARSR;
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PCFR |= (1u << 13); /* L1_DIS */
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PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
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PSPR = 0x5c014000;
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/* overwrite with the resume address */
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2017-01-15 05:59:29 +03:00
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*p = __pa_symbol(cpu_resume);
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2008-01-29 02:00:02 +03:00
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2011-06-22 20:41:48 +04:00
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cpu_suspend(0, pxa3xx_finish_suspend);
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2008-01-29 02:00:02 +03:00
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*p = saved_data;
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AD3ER = 0;
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2011-06-21 19:29:30 +04:00
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#ifndef CONFIG_IWMMXT
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ARM: pxa: fix building without IWMMXT
When CONFIG_IWMMXT, the pxa3xx and pxa27x suspend/resume code
emits some xscale specific instructions, which are rejected
by the assembler, because gcc is built with -march=armv5
-mtune=xscale and passes that option to the assembler:
/tmp/cciHumzr.s:553: Error: selected processor does not support ARM mode `mra r2,r3,acc0'
/tmp/cciHumzr.s:605: Error: selected processor does not support ARM mode `mar acc0,r2,r3'
make[3]: *** [arch/arm/mach-pxa/pxa3xx.o] Error 1
/tmp/cci5MUNu.s:326: Error: selected processor does not support ARM mode `mra r2,r3,acc0'
/tmp/cci5MUNu.s:367: Error: selected processor does not support ARM mode `mar acc0,r2,r3'
make[3]: *** [arch/arm/mach-pxa/pxa27x.o] Error 1
Overriding with -Wa,-march=xscale no longer works, so instead
I'm adding an explict ".arch_extension" directive in all four inline
assembly statements, which should work even if they end up in a different
order in the assembly output.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
2016-01-29 17:06:31 +03:00
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asm volatile(".arch_extension xscale\n\t"
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"mar acc0, %Q0, %R0" : "=r" (acc0));
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2011-06-21 19:29:30 +04:00
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#endif
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2008-01-29 02:00:02 +03:00
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}
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2008-01-08 01:18:30 +03:00
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static void pxa3xx_cpu_pm_enter(suspend_state_t state)
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{
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/*
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* Don't sleep if no wakeup sources are defined
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*/
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2008-04-09 14:32:21 +04:00
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if (wakeup_src == 0) {
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printk(KERN_ERR "Not suspending: no wakeup sources\n");
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2008-01-08 01:18:30 +03:00
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return;
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2008-04-09 14:32:21 +04:00
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}
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2008-01-08 01:18:30 +03:00
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switch (state) {
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case PM_SUSPEND_STANDBY:
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pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
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break;
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case PM_SUSPEND_MEM:
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2008-01-29 02:00:02 +03:00
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pxa3xx_cpu_pm_suspend();
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2008-01-08 01:18:30 +03:00
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break;
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}
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}
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static int pxa3xx_cpu_pm_valid(suspend_state_t state)
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{
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return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
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}
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static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
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.valid = pxa3xx_cpu_pm_valid,
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.enter = pxa3xx_cpu_pm_enter,
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2007-09-12 06:13:17 +04:00
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};
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2008-01-08 01:18:30 +03:00
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static void __init pxa3xx_init_pm(void)
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{
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sram = ioremap(ISRAM_START, ISRAM_SIZE);
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if (!sram) {
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printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
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return;
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}
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/*
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* Since we copy wakeup code into the SRAM, we need to ensure
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* that it is preserved over the low power modes. Note: bit 8
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* is undocumented in the developer manual, but must be set.
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*/
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AD1R |= ADXR_L2 | ADXR_R0;
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AD2R |= ADXR_L2 | ADXR_R0;
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AD3R |= ADXR_L2 | ADXR_R0;
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/*
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* Clear the resume enable registers.
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*/
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AD1D0ER = 0;
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AD2D0ER = 0;
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AD2D1ER = 0;
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AD3ER = 0;
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pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
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}
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2010-11-29 13:18:26 +03:00
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static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
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2008-01-08 01:18:30 +03:00
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{
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unsigned long flags, mask = 0;
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2010-11-29 13:18:26 +03:00
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switch (d->irq) {
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2008-01-08 01:18:30 +03:00
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case IRQ_SSP3:
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mask = ADXER_MFP_WSSP3;
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break;
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case IRQ_MSL:
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mask = ADXER_WMSL0;
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break;
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case IRQ_USBH2:
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case IRQ_USBH1:
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mask = ADXER_WUSBH;
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break;
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case IRQ_KEYPAD:
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mask = ADXER_WKP;
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break;
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case IRQ_AC97:
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mask = ADXER_MFP_WAC97;
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break;
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case IRQ_USIM:
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mask = ADXER_WUSIM0;
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break;
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case IRQ_SSP2:
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mask = ADXER_MFP_WSSP2;
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break;
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case IRQ_I2C:
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mask = ADXER_MFP_WI2C;
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break;
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case IRQ_STUART:
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mask = ADXER_MFP_WUART3;
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break;
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case IRQ_BTUART:
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mask = ADXER_MFP_WUART2;
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break;
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case IRQ_FFUART:
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mask = ADXER_MFP_WUART1;
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break;
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case IRQ_MMC:
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mask = ADXER_MFP_WMMC1;
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break;
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case IRQ_SSP:
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mask = ADXER_MFP_WSSP1;
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break;
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case IRQ_RTCAlrm:
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mask = ADXER_WRTC;
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break;
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case IRQ_SSP4:
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mask = ADXER_MFP_WSSP4;
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break;
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case IRQ_TSI:
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mask = ADXER_WTSI;
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break;
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case IRQ_USIM2:
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mask = ADXER_WUSIM1;
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break;
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case IRQ_MMC2:
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mask = ADXER_MFP_WMMC2;
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break;
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case IRQ_NAND:
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mask = ADXER_MFP_WFLASH;
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break;
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case IRQ_USB2:
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mask = ADXER_WUSB2;
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break;
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case IRQ_WAKEUP0:
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mask = ADXER_WEXTWAKE0;
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break;
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case IRQ_WAKEUP1:
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mask = ADXER_WEXTWAKE1;
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break;
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case IRQ_MMC3:
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mask = ADXER_MFP_GEN12;
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break;
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2008-04-23 13:28:18 +04:00
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default:
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return -EINVAL;
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2008-01-08 01:18:30 +03:00
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}
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local_irq_save(flags);
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if (on)
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wakeup_src |= mask;
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else
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wakeup_src &= ~mask;
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local_irq_restore(flags);
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return 0;
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}
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#else
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static inline void pxa3xx_init_pm(void) {}
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2008-03-04 09:19:58 +03:00
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#define pxa3xx_set_wake NULL
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2008-01-08 01:18:30 +03:00
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#endif
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2010-11-29 13:18:26 +03:00
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static void pxa_ack_ext_wakeup(struct irq_data *d)
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2009-11-11 12:36:59 +03:00
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{
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2010-11-29 13:18:26 +03:00
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|
|
PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
|
2009-11-11 12:36:59 +03:00
|
|
|
}
|
|
|
|
|
2010-11-29 13:18:26 +03:00
|
|
|
static void pxa_mask_ext_wakeup(struct irq_data *d)
|
2009-11-11 12:36:59 +03:00
|
|
|
{
|
2011-04-27 18:48:04 +04:00
|
|
|
pxa_mask_irq(d);
|
2010-11-29 13:18:26 +03:00
|
|
|
PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
|
2009-11-11 12:36:59 +03:00
|
|
|
}
|
|
|
|
|
2010-11-29 13:18:26 +03:00
|
|
|
static void pxa_unmask_ext_wakeup(struct irq_data *d)
|
2009-11-11 12:36:59 +03:00
|
|
|
{
|
2011-04-27 18:48:04 +04:00
|
|
|
pxa_unmask_irq(d);
|
2010-11-29 13:18:26 +03:00
|
|
|
PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
|
2009-11-11 12:36:59 +03:00
|
|
|
}
|
|
|
|
|
2010-11-29 13:18:26 +03:00
|
|
|
static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
|
2010-06-13 12:31:48 +04:00
|
|
|
{
|
|
|
|
if (flow_type & IRQ_TYPE_EDGE_RISING)
|
2010-11-29 13:18:26 +03:00
|
|
|
PWER |= 1 << (d->irq - IRQ_WAKEUP0);
|
2010-06-13 12:31:48 +04:00
|
|
|
|
|
|
|
if (flow_type & IRQ_TYPE_EDGE_FALLING)
|
2010-11-29 13:18:26 +03:00
|
|
|
PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);
|
2010-06-13 12:31:48 +04:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-11-11 12:36:59 +03:00
|
|
|
static struct irq_chip pxa_ext_wakeup_chip = {
|
|
|
|
.name = "WAKEUP",
|
2010-11-29 13:18:26 +03:00
|
|
|
.irq_ack = pxa_ack_ext_wakeup,
|
|
|
|
.irq_mask = pxa_mask_ext_wakeup,
|
|
|
|
.irq_unmask = pxa_unmask_ext_wakeup,
|
|
|
|
.irq_set_type = pxa_set_ext_wakeup_type,
|
2009-11-11 12:36:59 +03:00
|
|
|
};
|
|
|
|
|
2011-10-17 16:37:52 +04:00
|
|
|
static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
|
|
|
|
unsigned int))
|
2009-11-11 12:36:59 +03:00
|
|
|
{
|
|
|
|
int irq;
|
|
|
|
|
|
|
|
for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
|
2011-03-24 15:35:09 +03:00
|
|
|
irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
|
|
|
|
handle_edge_irq);
|
2015-07-27 23:55:13 +03:00
|
|
|
irq_clear_status_flags(irq, IRQ_NOREQUEST);
|
2009-11-11 12:36:59 +03:00
|
|
|
}
|
|
|
|
|
2010-11-29 13:18:26 +03:00
|
|
|
pxa_ext_wakeup_chip.irq_set_wake = fn;
|
2009-11-11 12:36:59 +03:00
|
|
|
}
|
|
|
|
|
2012-07-22 21:50:22 +04:00
|
|
|
static void __init __pxa3xx_init_irq(void)
|
2007-09-12 06:13:17 +04:00
|
|
|
{
|
|
|
|
/* enable CP6 access */
|
|
|
|
u32 value;
|
|
|
|
__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
|
|
|
|
value |= (1 << 6);
|
|
|
|
__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
|
|
|
|
|
2009-11-11 12:36:59 +03:00
|
|
|
pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
|
2007-09-12 06:13:17 +04:00
|
|
|
}
|
|
|
|
|
2012-07-22 21:50:22 +04:00
|
|
|
void __init pxa3xx_init_irq(void)
|
|
|
|
{
|
|
|
|
__pxa3xx_init_irq();
|
|
|
|
pxa_init_irq(56, pxa3xx_set_wake);
|
|
|
|
}
|
|
|
|
|
2012-08-20 09:46:51 +04:00
|
|
|
#ifdef CONFIG_OF
|
2016-08-15 01:24:55 +03:00
|
|
|
static int __init __init
|
|
|
|
pxa3xx_dt_init_irq(struct device_node *node, struct device_node *parent)
|
2012-07-22 21:50:22 +04:00
|
|
|
{
|
|
|
|
__pxa3xx_init_irq();
|
|
|
|
pxa_dt_irq_init(pxa3xx_set_wake);
|
2016-08-15 01:24:55 +03:00
|
|
|
set_handle_irq(ichp_handle_irq);
|
|
|
|
|
|
|
|
return 0;
|
2012-07-22 21:50:22 +04:00
|
|
|
}
|
2016-08-15 01:24:55 +03:00
|
|
|
IRQCHIP_DECLARE(pxa3xx_intc, "marvell,pxa-intc", pxa3xx_dt_init_irq);
|
2012-08-20 09:46:51 +04:00
|
|
|
#endif /* CONFIG_OF */
|
2012-07-22 21:50:22 +04:00
|
|
|
|
2010-10-11 04:20:19 +04:00
|
|
|
static struct map_desc pxa3xx_io_desc[] __initdata = {
|
|
|
|
{ /* Mem Ctl */
|
2011-10-02 00:03:45 +04:00
|
|
|
.virtual = (unsigned long)SMEMC_VIRT,
|
2010-11-03 18:29:35 +03:00
|
|
|
.pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
|
2014-07-11 15:00:36 +04:00
|
|
|
.length = SMEMC_SIZE,
|
2010-10-11 04:20:19 +04:00
|
|
|
.type = MT_DEVICE
|
2015-08-23 22:13:57 +03:00
|
|
|
}, {
|
|
|
|
.virtual = (unsigned long)NAND_VIRT,
|
|
|
|
.pfn = __phys_to_pfn(NAND_PHYS),
|
|
|
|
.length = NAND_SIZE,
|
|
|
|
.type = MT_DEVICE
|
|
|
|
},
|
2010-10-11 04:20:19 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
void __init pxa3xx_map_io(void)
|
|
|
|
{
|
|
|
|
pxa_map_io();
|
|
|
|
iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
|
|
|
|
pxa3xx_get_clk_frequency_khz(1);
|
|
|
|
}
|
|
|
|
|
2007-09-12 06:13:17 +04:00
|
|
|
/*
|
|
|
|
* device registration specific to PXA3xx.
|
|
|
|
*/
|
|
|
|
|
2008-08-17 09:23:05 +04:00
|
|
|
void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
|
|
|
|
{
|
2008-11-28 10:24:12 +03:00
|
|
|
pxa_register_device(&pxa3xx_device_i2c_power, info);
|
2008-08-17 09:23:05 +04:00
|
|
|
}
|
|
|
|
|
2013-04-09 14:12:04 +04:00
|
|
|
static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = {
|
|
|
|
.irq_base = PXA_GPIO_TO_IRQ(0),
|
|
|
|
};
|
|
|
|
|
2007-09-12 06:13:17 +04:00
|
|
|
static struct platform_device *devices[] __initdata = {
|
2009-04-21 21:19:36 +04:00
|
|
|
&pxa27x_device_udc,
|
2010-06-13 20:43:00 +04:00
|
|
|
&pxa_device_pmu,
|
2007-09-12 06:13:17 +04:00
|
|
|
&pxa_device_i2s,
|
2010-03-17 23:15:21 +03:00
|
|
|
&pxa_device_asoc_ssp1,
|
|
|
|
&pxa_device_asoc_ssp2,
|
|
|
|
&pxa_device_asoc_ssp3,
|
|
|
|
&pxa_device_asoc_ssp4,
|
|
|
|
&pxa_device_asoc_platform,
|
2007-09-12 06:13:17 +04:00
|
|
|
&pxa_device_rtc,
|
2014-08-13 23:59:19 +04:00
|
|
|
&pxa3xx_device_ssp1,
|
|
|
|
&pxa3xx_device_ssp2,
|
|
|
|
&pxa3xx_device_ssp3,
|
2007-12-10 12:54:36 +03:00
|
|
|
&pxa3xx_device_ssp4,
|
2008-04-14 00:44:04 +04:00
|
|
|
&pxa27x_device_pwm0,
|
|
|
|
&pxa27x_device_pwm1,
|
2007-09-12 06:13:17 +04:00
|
|
|
};
|
|
|
|
|
2018-06-17 20:02:05 +03:00
|
|
|
static const struct dma_slave_map pxa3xx_slave_map[] = {
|
|
|
|
/* PXA25x, PXA27x and PXA3xx common entries */
|
|
|
|
{ "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) },
|
|
|
|
{ "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) },
|
|
|
|
{ "pxa2xx-ac97", "pcm_pcm_aux_mono_out",
|
|
|
|
PDMA_FILTER_PARAM(LOWEST, 10) },
|
|
|
|
{ "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) },
|
|
|
|
{ "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) },
|
|
|
|
{ "pxa-ssp-dai.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
|
|
|
|
{ "pxa-ssp-dai.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
|
|
|
|
{ "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
|
|
|
|
{ "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
|
|
|
|
{ "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) },
|
|
|
|
{ "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) },
|
|
|
|
{ "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) },
|
|
|
|
{ "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) },
|
|
|
|
{ "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 66) },
|
|
|
|
{ "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 67) },
|
|
|
|
|
|
|
|
/* PXA3xx specific map */
|
|
|
|
{ "pxa-ssp-dai.3", "rx", PDMA_FILTER_PARAM(LOWEST, 2) },
|
|
|
|
{ "pxa-ssp-dai.3", "tx", PDMA_FILTER_PARAM(LOWEST, 3) },
|
|
|
|
{ "pxa2xx-mci.1", "rx", PDMA_FILTER_PARAM(LOWEST, 93) },
|
|
|
|
{ "pxa2xx-mci.1", "tx", PDMA_FILTER_PARAM(LOWEST, 94) },
|
|
|
|
{ "pxa3xx-nand", "data", PDMA_FILTER_PARAM(LOWEST, 97) },
|
|
|
|
{ "pxa2xx-mci.2", "rx", PDMA_FILTER_PARAM(LOWEST, 100) },
|
|
|
|
{ "pxa2xx-mci.2", "tx", PDMA_FILTER_PARAM(LOWEST, 101) },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct mmp_dma_platdata pxa3xx_dma_pdata = {
|
|
|
|
.dma_channels = 32,
|
|
|
|
.nb_requestors = 100,
|
|
|
|
.slave_map = pxa3xx_slave_map,
|
|
|
|
.slave_map_cnt = ARRAY_SIZE(pxa3xx_slave_map),
|
|
|
|
};
|
|
|
|
|
2007-09-12 06:13:17 +04:00
|
|
|
static int __init pxa3xx_init(void)
|
|
|
|
{
|
2011-04-23 00:03:11 +04:00
|
|
|
int ret = 0;
|
2007-09-12 06:13:17 +04:00
|
|
|
|
|
|
|
if (cpu_is_pxa3xx()) {
|
2008-07-29 10:26:00 +04:00
|
|
|
|
|
|
|
reset_status = ARSR;
|
|
|
|
|
2008-02-08 17:02:03 +03:00
|
|
|
/*
|
|
|
|
* clear RDH bit every time after reset
|
|
|
|
*
|
|
|
|
* Note: the last 3 bits DxS are write-1-to-clear so carefully
|
|
|
|
* preserve them here in case they will be referenced later
|
|
|
|
*/
|
|
|
|
ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
|
|
|
|
|
2015-08-23 22:13:57 +03:00
|
|
|
/*
|
|
|
|
* Disable DFI bus arbitration, to prevent a system bus lock if
|
|
|
|
* somebody disables the NAND clock (unused clock) while this
|
|
|
|
* bit remains set.
|
|
|
|
*/
|
|
|
|
NDCR = (NDCR & ~NDCR_ND_ARB_EN) | NDCR_ND_ARB_CNTL;
|
|
|
|
|
2008-01-08 01:18:30 +03:00
|
|
|
pxa3xx_init_pm();
|
|
|
|
|
2018-05-24 23:40:46 +03:00
|
|
|
enable_irq_wake(IRQ_WAKEUP0);
|
|
|
|
if (cpu_is_pxa320())
|
|
|
|
enable_irq_wake(IRQ_WAKEUP1);
|
|
|
|
|
2011-04-23 00:03:11 +04:00
|
|
|
register_syscore_ops(&pxa_irq_syscore_ops);
|
|
|
|
register_syscore_ops(&pxa3xx_mfp_syscore_ops);
|
2008-01-29 02:00:02 +03:00
|
|
|
|
2013-04-07 12:44:33 +04:00
|
|
|
if (of_have_populated_dt())
|
|
|
|
return 0;
|
|
|
|
|
2018-06-17 20:02:05 +03:00
|
|
|
pxa2xx_set_dmac_info(&pxa3xx_dma_pdata);
|
2013-04-07 12:44:33 +04:00
|
|
|
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2013-04-09 14:12:04 +04:00
|
|
|
if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) {
|
|
|
|
platform_device_add_data(&pxa3xx_device_gpio,
|
|
|
|
&pxa3xx_gpio_pdata,
|
|
|
|
sizeof(pxa3xx_gpio_pdata));
|
2013-04-07 12:44:33 +04:00
|
|
|
ret = platform_device_register(&pxa3xx_device_gpio);
|
2013-04-09 14:12:04 +04:00
|
|
|
}
|
2007-09-12 06:13:17 +04:00
|
|
|
}
|
2008-01-29 02:00:02 +03:00
|
|
|
|
|
|
|
return ret;
|
2007-09-12 06:13:17 +04:00
|
|
|
}
|
|
|
|
|
2008-04-19 13:59:24 +04:00
|
|
|
postcore_initcall(pxa3xx_init);
|