2020-10-29 04:55:33 +03:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel Platform Monitoring Technology PMT driver
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*
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* Copyright (c) 2020, Intel Corporation.
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* All Rights Reserved.
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*
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* Author: David E. Box <david.e.box@linux.intel.com>
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*/
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#include <linux/bits.h>
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#include <linux/kernel.h>
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#include <linux/mfd/core.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/types.h>
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/* Intel DVSEC capability vendor space offsets */
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#define INTEL_DVSEC_ENTRIES 0xA
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#define INTEL_DVSEC_SIZE 0xB
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#define INTEL_DVSEC_TABLE 0xC
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#define INTEL_DVSEC_TABLE_BAR(x) ((x) & GENMASK(2, 0))
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#define INTEL_DVSEC_TABLE_OFFSET(x) ((x) & GENMASK(31, 3))
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#define INTEL_DVSEC_ENTRY_SIZE 4
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/* PMT capabilities */
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#define DVSEC_INTEL_ID_TELEMETRY 2
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#define DVSEC_INTEL_ID_WATCHER 3
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#define DVSEC_INTEL_ID_CRASHLOG 4
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struct intel_dvsec_header {
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u16 length;
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u16 id;
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u8 num_entries;
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u8 entry_size;
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u8 tbir;
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u32 offset;
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};
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enum pmt_quirks {
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/* Watcher capability not supported */
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PMT_QUIRK_NO_WATCHER = BIT(0),
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/* Crashlog capability not supported */
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PMT_QUIRK_NO_CRASHLOG = BIT(1),
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/* Use shift instead of mask to read discovery table offset */
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PMT_QUIRK_TABLE_SHIFT = BIT(2),
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2021-02-24 23:10:05 +03:00
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/* DVSEC not present (provided in driver data) */
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PMT_QUIRK_NO_DVSEC = BIT(3),
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2020-10-29 04:55:33 +03:00
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};
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struct pmt_platform_info {
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unsigned long quirks;
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2021-02-24 23:10:05 +03:00
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struct intel_dvsec_header **capabilities;
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2020-10-29 04:55:33 +03:00
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};
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static const struct pmt_platform_info tgl_info = {
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.quirks = PMT_QUIRK_NO_WATCHER | PMT_QUIRK_NO_CRASHLOG |
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PMT_QUIRK_TABLE_SHIFT,
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};
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2021-02-24 23:10:05 +03:00
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/* DG1 Platform with DVSEC quirk*/
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static struct intel_dvsec_header dg1_telemetry = {
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.length = 0x10,
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.id = 2,
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.num_entries = 1,
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.entry_size = 3,
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.tbir = 0,
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.offset = 0x466000,
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};
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static struct intel_dvsec_header *dg1_capabilities[] = {
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&dg1_telemetry,
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NULL
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};
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static const struct pmt_platform_info dg1_info = {
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.quirks = PMT_QUIRK_NO_DVSEC,
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.capabilities = dg1_capabilities,
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};
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2020-10-29 04:55:33 +03:00
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static int pmt_add_dev(struct pci_dev *pdev, struct intel_dvsec_header *header,
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unsigned long quirks)
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{
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struct device *dev = &pdev->dev;
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struct resource *res, *tmp;
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struct mfd_cell *cell;
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const char *name;
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int count = header->num_entries;
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int size = header->entry_size;
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int id = header->id;
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int i;
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switch (id) {
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case DVSEC_INTEL_ID_TELEMETRY:
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name = "pmt_telemetry";
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break;
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case DVSEC_INTEL_ID_WATCHER:
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if (quirks & PMT_QUIRK_NO_WATCHER) {
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dev_info(dev, "Watcher not supported\n");
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return -EINVAL;
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2020-10-29 04:55:33 +03:00
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}
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name = "pmt_watcher";
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break;
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case DVSEC_INTEL_ID_CRASHLOG:
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if (quirks & PMT_QUIRK_NO_CRASHLOG) {
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dev_info(dev, "Crashlog not supported\n");
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return -EINVAL;
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}
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name = "pmt_crashlog";
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break;
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default:
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return -EINVAL;
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}
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if (!header->num_entries || !header->entry_size) {
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dev_err(dev, "Invalid count or size for %s header\n", name);
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return -EINVAL;
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}
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cell = devm_kzalloc(dev, sizeof(*cell), GFP_KERNEL);
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if (!cell)
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return -ENOMEM;
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res = devm_kcalloc(dev, count, sizeof(*res), GFP_KERNEL);
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if (!res)
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return -ENOMEM;
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if (quirks & PMT_QUIRK_TABLE_SHIFT)
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header->offset >>= 3;
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/*
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* The PMT DVSEC contains the starting offset and count for a block of
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* discovery tables, each providing access to monitoring facilities for
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* a section of the device. Create a resource list of these tables to
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* provide to the driver.
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*/
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for (i = 0, tmp = res; i < count; i++, tmp++) {
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tmp->start = pdev->resource[header->tbir].start +
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header->offset + i * (size << 2);
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tmp->end = tmp->start + (size << 2) - 1;
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tmp->flags = IORESOURCE_MEM;
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}
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cell->resources = res;
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cell->num_resources = count;
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cell->name = name;
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return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, cell, 1, NULL, 0,
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NULL);
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}
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static int pmt_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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struct pmt_platform_info *info;
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unsigned long quirks = 0;
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bool found_devices = false;
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int ret, pos = 0;
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ret = pcim_enable_device(pdev);
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if (ret)
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return ret;
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info = (struct pmt_platform_info *)id->driver_data;
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if (info)
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quirks = info->quirks;
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2021-02-24 23:10:05 +03:00
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if (info && (info->quirks & PMT_QUIRK_NO_DVSEC)) {
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struct intel_dvsec_header **header;
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2021-02-24 23:10:05 +03:00
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header = info->capabilities;
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while (*header) {
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ret = pmt_add_dev(pdev, *header, quirks);
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if (ret)
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dev_warn(&pdev->dev,
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"Failed to add device for DVSEC id %d\n",
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(*header)->id);
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else
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found_devices = true;
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2021-02-24 23:10:05 +03:00
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++header;
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}
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} else {
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do {
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struct intel_dvsec_header header;
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u32 table;
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u16 vid;
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pos = pci_find_next_ext_capability(pdev, pos, PCI_EXT_CAP_ID_DVSEC);
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if (!pos)
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break;
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pci_read_config_word(pdev, pos + PCI_DVSEC_HEADER1, &vid);
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if (vid != PCI_VENDOR_ID_INTEL)
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continue;
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pci_read_config_word(pdev, pos + PCI_DVSEC_HEADER2,
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&header.id);
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pci_read_config_byte(pdev, pos + INTEL_DVSEC_ENTRIES,
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&header.num_entries);
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pci_read_config_byte(pdev, pos + INTEL_DVSEC_SIZE,
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&header.entry_size);
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pci_read_config_dword(pdev, pos + INTEL_DVSEC_TABLE,
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&table);
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header.tbir = INTEL_DVSEC_TABLE_BAR(table);
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header.offset = INTEL_DVSEC_TABLE_OFFSET(table);
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ret = pmt_add_dev(pdev, &header, quirks);
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if (ret)
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continue;
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found_devices = true;
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} while (true);
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}
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2020-10-29 04:55:33 +03:00
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if (!found_devices)
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return -ENODEV;
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pm_runtime_put(&pdev->dev);
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pm_runtime_allow(&pdev->dev);
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return 0;
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}
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static void pmt_pci_remove(struct pci_dev *pdev)
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{
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pm_runtime_forbid(&pdev->dev);
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pm_runtime_get_sync(&pdev->dev);
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}
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#define PCI_DEVICE_ID_INTEL_PMT_ADL 0x467d
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#define PCI_DEVICE_ID_INTEL_PMT_DG1 0x490e
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#define PCI_DEVICE_ID_INTEL_PMT_OOBMSM 0x09a7
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#define PCI_DEVICE_ID_INTEL_PMT_TGL 0x9a0d
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static const struct pci_device_id pmt_pci_ids[] = {
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{ PCI_DEVICE_DATA(INTEL, PMT_ADL, &tgl_info) },
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{ PCI_DEVICE_DATA(INTEL, PMT_DG1, &dg1_info) },
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{ PCI_DEVICE_DATA(INTEL, PMT_OOBMSM, NULL) },
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{ PCI_DEVICE_DATA(INTEL, PMT_TGL, &tgl_info) },
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{ }
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};
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MODULE_DEVICE_TABLE(pci, pmt_pci_ids);
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static struct pci_driver pmt_pci_driver = {
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.name = "intel-pmt",
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.id_table = pmt_pci_ids,
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.probe = pmt_pci_probe,
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.remove = pmt_pci_remove,
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};
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module_pci_driver(pmt_pci_driver);
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MODULE_AUTHOR("David E. Box <david.e.box@linux.intel.com>");
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MODULE_DESCRIPTION("Intel Platform Monitoring Technology PMT driver");
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MODULE_LICENSE("GPL v2");
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