2015-10-26 12:02:25 +03:00
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/* QLogic qed NIC Driver
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*
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* Copyright (c) 2015 QLogic Corporation
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*
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* This software is available under the terms of the GNU General Public License
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* (GPL) Version 2, available from the file COPYING in the main directory of
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* this source tree.
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*/
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#ifndef _QED_IF_H
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#define _QED_IF_H
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/netdevice.h>
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#include <linux/pci.h>
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#include <linux/skbuff.h>
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#include <linux/io.h>
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#include <linux/compiler.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/slab.h>
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#include <linux/qed/common_hsi.h>
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#include <linux/qed/qed_chain.h>
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2015-11-30 13:25:03 +03:00
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enum qed_led_mode {
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QED_LED_MODE_OFF,
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QED_LED_MODE_ON,
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QED_LED_MODE_RESTORE
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};
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2015-10-26 12:02:25 +03:00
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#define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
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(void __iomem *)(reg_addr))
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#define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
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#define QED_COALESCE_MAX 0xFF
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/* forward */
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struct qed_dev;
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struct qed_eth_pf_params {
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/* The following parameters are used during HW-init
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* and these parameters need to be passed as arguments
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* to update_pf_params routine invoked before slowpath start
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*/
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u16 num_cons;
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};
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struct qed_pf_params {
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struct qed_eth_pf_params eth_pf_params;
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};
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enum qed_int_mode {
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QED_INT_MODE_INTA,
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QED_INT_MODE_MSIX,
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QED_INT_MODE_MSI,
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QED_INT_MODE_POLL,
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};
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struct qed_sb_info {
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struct status_block *sb_virt;
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dma_addr_t sb_phys;
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u32 sb_ack; /* Last given ack */
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u16 igu_sb_id;
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void __iomem *igu_addr;
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u8 flags;
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#define QED_SB_INFO_INIT 0x1
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#define QED_SB_INFO_SETUP 0x2
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struct qed_dev *cdev;
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};
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struct qed_dev_info {
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unsigned long pci_mem_start;
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unsigned long pci_mem_end;
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unsigned int pci_irq;
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u8 num_hwfns;
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u8 hw_mac[ETH_ALEN];
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2016-02-15 21:22:35 +03:00
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bool is_mf_default;
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2015-10-26 12:02:25 +03:00
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/* FW version */
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u16 fw_major;
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u16 fw_minor;
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u16 fw_rev;
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u16 fw_eng;
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/* MFW version */
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u32 mfw_rev;
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u32 flash_size;
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u8 mf_mode;
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};
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enum qed_sb_type {
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QED_SB_TYPE_L2_QUEUE,
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};
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enum qed_protocol {
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QED_PROTOCOL_ETH,
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};
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struct qed_link_params {
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bool link_up;
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#define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0)
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#define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1)
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#define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
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#define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
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2016-04-29 03:20:52 +03:00
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#define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4)
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2015-10-26 12:02:25 +03:00
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u32 override_flags;
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bool autoneg;
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u32 adv_speeds;
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u32 forced_speed;
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#define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0)
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#define QED_LINK_PAUSE_RX_ENABLE BIT(1)
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#define QED_LINK_PAUSE_TX_ENABLE BIT(2)
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u32 pause_config;
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2016-04-29 03:20:52 +03:00
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#define QED_LINK_LOOPBACK_NONE BIT(0)
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#define QED_LINK_LOOPBACK_INT_PHY BIT(1)
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#define QED_LINK_LOOPBACK_EXT_PHY BIT(2)
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#define QED_LINK_LOOPBACK_EXT BIT(3)
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#define QED_LINK_LOOPBACK_MAC BIT(4)
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u32 loopback_mode;
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2015-10-26 12:02:25 +03:00
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};
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struct qed_link_output {
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bool link_up;
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u32 supported_caps; /* In SUPPORTED defs */
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u32 advertised_caps; /* In ADVERTISED defs */
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u32 lp_caps; /* In ADVERTISED defs */
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u32 speed; /* In Mb/s */
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u8 duplex; /* In DUPLEX defs */
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u8 port; /* In PORT defs */
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bool autoneg;
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u32 pause_config;
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};
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2016-05-11 16:36:14 +03:00
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struct qed_probe_params {
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enum qed_protocol protocol;
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u32 dp_module;
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u8 dp_level;
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bool is_vf;
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};
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2015-10-26 12:02:25 +03:00
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#define QED_DRV_VER_STR_SIZE 12
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struct qed_slowpath_params {
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u32 int_mode;
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u8 drv_major;
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u8 drv_minor;
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u8 drv_rev;
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u8 drv_eng;
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u8 name[QED_DRV_VER_STR_SIZE];
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};
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#define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
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struct qed_int_info {
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struct msix_entry *msix;
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u8 msix_cnt;
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/* This should be updated by the protocol driver */
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u8 used_cnt;
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};
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struct qed_common_cb_ops {
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void (*link_update)(void *dev,
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struct qed_link_output *link);
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};
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2016-04-29 03:20:52 +03:00
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struct qed_selftest_ops {
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/**
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* @brief selftest_interrupt - Perform interrupt test
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*
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* @param cdev
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*
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* @return 0 on success, error otherwise.
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*/
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int (*selftest_interrupt)(struct qed_dev *cdev);
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/**
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* @brief selftest_memory - Perform memory test
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*
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* @param cdev
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*
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* @return 0 on success, error otherwise.
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*/
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int (*selftest_memory)(struct qed_dev *cdev);
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/**
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* @brief selftest_register - Perform register test
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*
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* @param cdev
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*
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* @return 0 on success, error otherwise.
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*/
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int (*selftest_register)(struct qed_dev *cdev);
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/**
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* @brief selftest_clock - Perform clock test
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*
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* @param cdev
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*
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* @return 0 on success, error otherwise.
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*/
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int (*selftest_clock)(struct qed_dev *cdev);
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};
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2015-10-26 12:02:25 +03:00
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struct qed_common_ops {
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2016-04-29 03:20:52 +03:00
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struct qed_selftest_ops *selftest;
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2015-10-26 12:02:25 +03:00
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struct qed_dev* (*probe)(struct pci_dev *dev,
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2016-05-11 16:36:14 +03:00
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struct qed_probe_params *params);
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2015-10-26 12:02:25 +03:00
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void (*remove)(struct qed_dev *cdev);
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int (*set_power_state)(struct qed_dev *cdev,
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pci_power_t state);
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void (*set_id)(struct qed_dev *cdev,
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char name[],
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char ver_str[]);
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/* Client drivers need to make this call before slowpath_start.
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* PF params required for the call before slowpath_start is
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* documented within the qed_pf_params structure definition.
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*/
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void (*update_pf_params)(struct qed_dev *cdev,
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struct qed_pf_params *params);
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int (*slowpath_start)(struct qed_dev *cdev,
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struct qed_slowpath_params *params);
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int (*slowpath_stop)(struct qed_dev *cdev);
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/* Requests to use `cnt' interrupts for fastpath.
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* upon success, returns number of interrupts allocated for fastpath.
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*/
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int (*set_fp_int)(struct qed_dev *cdev,
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u16 cnt);
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/* Fills `info' with pointers required for utilizing interrupts */
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int (*get_fp_int)(struct qed_dev *cdev,
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struct qed_int_info *info);
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u32 (*sb_init)(struct qed_dev *cdev,
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struct qed_sb_info *sb_info,
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void *sb_virt_addr,
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dma_addr_t sb_phy_addr,
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u16 sb_id,
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enum qed_sb_type type);
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u32 (*sb_release)(struct qed_dev *cdev,
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struct qed_sb_info *sb_info,
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u16 sb_id);
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void (*simd_handler_config)(struct qed_dev *cdev,
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void *token,
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int index,
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void (*handler)(void *));
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void (*simd_handler_clean)(struct qed_dev *cdev,
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int index);
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2016-04-22 08:41:03 +03:00
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/**
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* @brief can_link_change - can the instance change the link or not
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*
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* @param cdev
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*
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* @return true if link-change is allowed, false otherwise.
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*/
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bool (*can_link_change)(struct qed_dev *cdev);
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2015-10-26 12:02:25 +03:00
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/**
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* @brief set_link - set links according to params
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*
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* @param cdev
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* @param params - values used to override the default link configuration
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*
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* @return 0 on success, error otherwise.
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*/
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int (*set_link)(struct qed_dev *cdev,
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struct qed_link_params *params);
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/**
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* @brief get_link - returns the current link state.
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*
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* @param cdev
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* @param if_link - structure to be filled with current link configuration.
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*/
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void (*get_link)(struct qed_dev *cdev,
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struct qed_link_output *if_link);
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/**
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* @brief - drains chip in case Tx completions fail to arrive due to pause.
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*
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* @param cdev
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*/
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int (*drain)(struct qed_dev *cdev);
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/**
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* @brief update_msglvl - update module debug level
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*
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* @param cdev
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* @param dp_module
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* @param dp_level
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*/
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void (*update_msglvl)(struct qed_dev *cdev,
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u32 dp_module,
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u8 dp_level);
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int (*chain_alloc)(struct qed_dev *cdev,
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enum qed_chain_use_mode intended_use,
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enum qed_chain_mode mode,
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u16 num_elems,
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size_t elem_size,
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struct qed_chain *p_chain);
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void (*chain_free)(struct qed_dev *cdev,
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struct qed_chain *p_chain);
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2015-11-30 13:25:03 +03:00
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/**
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* @brief set_led - Configure LED mode
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*
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* @param cdev
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* @param mode - LED mode
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*
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* @return 0 on success, error otherwise.
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*/
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int (*set_led)(struct qed_dev *cdev,
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enum qed_led_mode mode);
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2015-10-26 12:02:25 +03:00
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};
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#define MASK_FIELD(_name, _value) \
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((_value) &= (_name ## _MASK))
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#define FIELD_VALUE(_name, _value) \
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((_value & _name ## _MASK) << _name ## _SHIFT)
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#define SET_FIELD(value, name, flag) \
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do { \
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(value) &= ~(name ## _MASK << name ## _SHIFT); \
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(value) |= (((u64)flag) << (name ## _SHIFT)); \
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} while (0)
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#define GET_FIELD(value, name) \
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(((value) >> (name ## _SHIFT)) & name ## _MASK)
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/* Debug print definitions */
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#define DP_ERR(cdev, fmt, ...) \
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pr_err("[%s:%d(%s)]" fmt, \
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__func__, __LINE__, \
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DP_NAME(cdev) ? DP_NAME(cdev) : "", \
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## __VA_ARGS__) \
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#define DP_NOTICE(cdev, fmt, ...) \
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do { \
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if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
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pr_notice("[%s:%d(%s)]" fmt, \
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__func__, __LINE__, \
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DP_NAME(cdev) ? DP_NAME(cdev) : "", \
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## __VA_ARGS__); \
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\
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} \
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} while (0)
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#define DP_INFO(cdev, fmt, ...) \
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do { \
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if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \
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pr_notice("[%s:%d(%s)]" fmt, \
|
|
|
|
__func__, __LINE__, \
|
|
|
|
DP_NAME(cdev) ? DP_NAME(cdev) : "", \
|
|
|
|
## __VA_ARGS__); \
|
|
|
|
} \
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
#define DP_VERBOSE(cdev, module, fmt, ...) \
|
|
|
|
do { \
|
|
|
|
if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \
|
|
|
|
((cdev)->dp_module & module))) { \
|
|
|
|
pr_notice("[%s:%d(%s)]" fmt, \
|
|
|
|
__func__, __LINE__, \
|
|
|
|
DP_NAME(cdev) ? DP_NAME(cdev) : "", \
|
|
|
|
## __VA_ARGS__); \
|
|
|
|
} \
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
enum DP_LEVEL {
|
|
|
|
QED_LEVEL_VERBOSE = 0x0,
|
|
|
|
QED_LEVEL_INFO = 0x1,
|
|
|
|
QED_LEVEL_NOTICE = 0x2,
|
|
|
|
QED_LEVEL_ERR = 0x3,
|
|
|
|
};
|
|
|
|
|
|
|
|
#define QED_LOG_LEVEL_SHIFT (30)
|
|
|
|
#define QED_LOG_VERBOSE_MASK (0x3fffffff)
|
|
|
|
#define QED_LOG_INFO_MASK (0x40000000)
|
|
|
|
#define QED_LOG_NOTICE_MASK (0x80000000)
|
|
|
|
|
|
|
|
enum DP_MODULE {
|
|
|
|
QED_MSG_SPQ = 0x10000,
|
|
|
|
QED_MSG_STATS = 0x20000,
|
|
|
|
QED_MSG_DCB = 0x40000,
|
|
|
|
QED_MSG_IOV = 0x80000,
|
|
|
|
QED_MSG_SP = 0x100000,
|
|
|
|
QED_MSG_STORAGE = 0x200000,
|
|
|
|
QED_MSG_CXT = 0x800000,
|
|
|
|
QED_MSG_ILT = 0x2000000,
|
|
|
|
QED_MSG_ROCE = 0x4000000,
|
|
|
|
QED_MSG_DEBUG = 0x8000000,
|
|
|
|
/* to be added...up to 0x8000000 */
|
|
|
|
};
|
|
|
|
|
2016-02-15 21:22:35 +03:00
|
|
|
enum qed_mf_mode {
|
|
|
|
QED_MF_DEFAULT,
|
|
|
|
QED_MF_OVLAN,
|
|
|
|
QED_MF_NPAR,
|
|
|
|
};
|
|
|
|
|
2015-10-26 12:02:25 +03:00
|
|
|
struct qed_eth_stats {
|
|
|
|
u64 no_buff_discards;
|
|
|
|
u64 packet_too_big_discard;
|
|
|
|
u64 ttl0_discard;
|
|
|
|
u64 rx_ucast_bytes;
|
|
|
|
u64 rx_mcast_bytes;
|
|
|
|
u64 rx_bcast_bytes;
|
|
|
|
u64 rx_ucast_pkts;
|
|
|
|
u64 rx_mcast_pkts;
|
|
|
|
u64 rx_bcast_pkts;
|
|
|
|
u64 mftag_filter_discards;
|
|
|
|
u64 mac_filter_discards;
|
|
|
|
u64 tx_ucast_bytes;
|
|
|
|
u64 tx_mcast_bytes;
|
|
|
|
u64 tx_bcast_bytes;
|
|
|
|
u64 tx_ucast_pkts;
|
|
|
|
u64 tx_mcast_pkts;
|
|
|
|
u64 tx_bcast_pkts;
|
|
|
|
u64 tx_err_drop_pkts;
|
|
|
|
u64 tpa_coalesced_pkts;
|
|
|
|
u64 tpa_coalesced_events;
|
|
|
|
u64 tpa_aborts_num;
|
|
|
|
u64 tpa_not_coalesced_pkts;
|
|
|
|
u64 tpa_coalesced_bytes;
|
|
|
|
|
|
|
|
/* port */
|
|
|
|
u64 rx_64_byte_packets;
|
2016-04-22 08:41:01 +03:00
|
|
|
u64 rx_65_to_127_byte_packets;
|
|
|
|
u64 rx_128_to_255_byte_packets;
|
|
|
|
u64 rx_256_to_511_byte_packets;
|
|
|
|
u64 rx_512_to_1023_byte_packets;
|
|
|
|
u64 rx_1024_to_1518_byte_packets;
|
|
|
|
u64 rx_1519_to_1522_byte_packets;
|
|
|
|
u64 rx_1519_to_2047_byte_packets;
|
|
|
|
u64 rx_2048_to_4095_byte_packets;
|
|
|
|
u64 rx_4096_to_9216_byte_packets;
|
|
|
|
u64 rx_9217_to_16383_byte_packets;
|
2015-10-26 12:02:25 +03:00
|
|
|
u64 rx_crc_errors;
|
|
|
|
u64 rx_mac_crtl_frames;
|
|
|
|
u64 rx_pause_frames;
|
|
|
|
u64 rx_pfc_frames;
|
|
|
|
u64 rx_align_errors;
|
|
|
|
u64 rx_carrier_errors;
|
|
|
|
u64 rx_oversize_packets;
|
|
|
|
u64 rx_jabbers;
|
|
|
|
u64 rx_undersize_packets;
|
|
|
|
u64 rx_fragments;
|
|
|
|
u64 tx_64_byte_packets;
|
|
|
|
u64 tx_65_to_127_byte_packets;
|
|
|
|
u64 tx_128_to_255_byte_packets;
|
|
|
|
u64 tx_256_to_511_byte_packets;
|
|
|
|
u64 tx_512_to_1023_byte_packets;
|
|
|
|
u64 tx_1024_to_1518_byte_packets;
|
|
|
|
u64 tx_1519_to_2047_byte_packets;
|
|
|
|
u64 tx_2048_to_4095_byte_packets;
|
|
|
|
u64 tx_4096_to_9216_byte_packets;
|
|
|
|
u64 tx_9217_to_16383_byte_packets;
|
|
|
|
u64 tx_pause_frames;
|
|
|
|
u64 tx_pfc_frames;
|
|
|
|
u64 tx_lpi_entry_count;
|
|
|
|
u64 tx_total_collisions;
|
|
|
|
u64 brb_truncates;
|
|
|
|
u64 brb_discards;
|
|
|
|
u64 rx_mac_bytes;
|
|
|
|
u64 rx_mac_uc_packets;
|
|
|
|
u64 rx_mac_mc_packets;
|
|
|
|
u64 rx_mac_bc_packets;
|
|
|
|
u64 rx_mac_frames_ok;
|
|
|
|
u64 tx_mac_bytes;
|
|
|
|
u64 tx_mac_uc_packets;
|
|
|
|
u64 tx_mac_mc_packets;
|
|
|
|
u64 tx_mac_bc_packets;
|
|
|
|
u64 tx_mac_ctrl_frames;
|
|
|
|
};
|
|
|
|
|
|
|
|
#define QED_SB_IDX 0x0002
|
|
|
|
|
|
|
|
#define RX_PI 0
|
|
|
|
#define TX_PI(tc) (RX_PI + 1 + tc)
|
|
|
|
|
2016-02-28 13:26:52 +03:00
|
|
|
struct qed_sb_cnt_info {
|
|
|
|
int sb_cnt;
|
|
|
|
int sb_iov_cnt;
|
|
|
|
int sb_free_blk;
|
|
|
|
};
|
|
|
|
|
2015-10-26 12:02:25 +03:00
|
|
|
static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
|
|
|
|
{
|
|
|
|
u32 prod = 0;
|
|
|
|
u16 rc = 0;
|
|
|
|
|
|
|
|
prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
|
|
|
|
STATUS_BLOCK_PROD_INDEX_MASK;
|
|
|
|
if (sb_info->sb_ack != prod) {
|
|
|
|
sb_info->sb_ack = prod;
|
|
|
|
rc |= QED_SB_IDX;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Let SB update */
|
|
|
|
mmiowb();
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
*
|
|
|
|
* @brief This function creates an update command for interrupts that is
|
|
|
|
* written to the IGU.
|
|
|
|
*
|
|
|
|
* @param sb_info - This is the structure allocated and
|
|
|
|
* initialized per status block. Assumption is
|
|
|
|
* that it was initialized using qed_sb_init
|
|
|
|
* @param int_cmd - Enable/Disable/Nop
|
|
|
|
* @param upd_flg - whether igu consumer should be
|
|
|
|
* updated.
|
|
|
|
*
|
|
|
|
* @return inline void
|
|
|
|
*/
|
|
|
|
static inline void qed_sb_ack(struct qed_sb_info *sb_info,
|
|
|
|
enum igu_int_cmd int_cmd,
|
|
|
|
u8 upd_flg)
|
|
|
|
{
|
|
|
|
struct igu_prod_cons_update igu_ack = { 0 };
|
|
|
|
|
|
|
|
igu_ack.sb_id_and_flags =
|
|
|
|
((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
|
|
|
|
(upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
|
|
|
|
(int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
|
|
|
|
(IGU_SEG_ACCESS_REG <<
|
|
|
|
IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
|
|
|
|
|
|
|
|
DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);
|
|
|
|
|
|
|
|
/* Both segments (interrupts & acks) are written to same place address;
|
|
|
|
* Need to guarantee all commands will be received (in-order) by HW.
|
|
|
|
*/
|
|
|
|
mmiowb();
|
|
|
|
barrier();
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void __internal_ram_wr(void *p_hwfn,
|
|
|
|
void __iomem *addr,
|
|
|
|
int size,
|
|
|
|
u32 *data)
|
|
|
|
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
for (i = 0; i < size / sizeof(*data); i++)
|
|
|
|
DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void internal_ram_wr(void __iomem *addr,
|
|
|
|
int size,
|
|
|
|
u32 *data)
|
|
|
|
{
|
|
|
|
__internal_ram_wr(NULL, addr, size, data);
|
|
|
|
}
|
|
|
|
|
2016-04-10 12:43:00 +03:00
|
|
|
enum qed_rss_caps {
|
|
|
|
QED_RSS_IPV4 = 0x1,
|
|
|
|
QED_RSS_IPV6 = 0x2,
|
|
|
|
QED_RSS_IPV4_TCP = 0x4,
|
|
|
|
QED_RSS_IPV6_TCP = 0x8,
|
|
|
|
QED_RSS_IPV4_UDP = 0x10,
|
|
|
|
QED_RSS_IPV6_UDP = 0x20,
|
|
|
|
};
|
|
|
|
|
|
|
|
#define QED_RSS_IND_TABLE_SIZE 128
|
|
|
|
#define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
|
2015-10-26 12:02:25 +03:00
|
|
|
#endif
|