2013-05-29 12:12:17 +04:00
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/*
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* Copyright 2012-2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*/
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#include <linux/interrupt.h>
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#include <linux/clockchips.h>
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#include <linux/clk.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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2013-06-25 03:20:08 +04:00
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#include <linux/sched_clock.h>
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2013-05-29 12:12:17 +04:00
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/*
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* Each pit takes 0x10 Bytes register space
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*/
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#define PITMCR 0x00
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#define PIT0_OFFSET 0x100
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#define PITn_OFFSET(n) (PIT0_OFFSET + 0x10 * (n))
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#define PITLDVAL 0x00
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#define PITCVAL 0x04
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#define PITTCTRL 0x08
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#define PITTFLG 0x0c
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#define PITMCR_MDIS (0x1 << 1)
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#define PITTCTRL_TEN (0x1 << 0)
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#define PITTCTRL_TIE (0x1 << 1)
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#define PITCTRL_CHN (0x1 << 2)
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#define PITTFLG_TIF 0x1
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static void __iomem *clksrc_base;
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static void __iomem *clkevt_base;
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static unsigned long cycle_per_jiffy;
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static inline void pit_timer_enable(void)
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{
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__raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL);
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}
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static inline void pit_timer_disable(void)
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{
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__raw_writel(0, clkevt_base + PITTCTRL);
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}
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static inline void pit_irq_acknowledge(void)
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{
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__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
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}
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2015-10-20 11:02:38 +03:00
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static u64 notrace pit_read_sched_clock(void)
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2013-05-29 12:12:17 +04:00
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{
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2014-03-06 02:11:08 +04:00
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return ~__raw_readl(clksrc_base + PITCVAL);
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2013-05-29 12:12:17 +04:00
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}
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static int __init pit_clocksource_init(unsigned long rate)
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{
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/* set the max load value and start the clock source counter */
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__raw_writel(0, clksrc_base + PITTCTRL);
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__raw_writel(~0UL, clksrc_base + PITLDVAL);
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__raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL);
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2013-07-19 03:21:29 +04:00
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sched_clock_register(pit_read_sched_clock, 32, rate);
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2013-05-29 12:12:17 +04:00
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return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate,
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300, 32, clocksource_mmio_readl_down);
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}
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static int pit_set_next_event(unsigned long delta,
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struct clock_event_device *unused)
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{
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/*
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* set a new value to PITLDVAL register will not restart the timer,
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* to abort the current cycle and start a timer period with the new
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* value, the timer must be disabled and enabled again.
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* and the PITLAVAL should be set to delta minus one according to pit
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* hardware requirement.
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*/
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pit_timer_disable();
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__raw_writel(delta - 1, clkevt_base + PITLDVAL);
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pit_timer_enable();
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return 0;
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}
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2015-06-18 13:54:53 +03:00
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static int pit_shutdown(struct clock_event_device *evt)
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2013-05-29 12:12:17 +04:00
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{
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2015-06-18 13:54:53 +03:00
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pit_timer_disable();
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return 0;
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}
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static int pit_set_periodic(struct clock_event_device *evt)
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{
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pit_set_next_event(cycle_per_jiffy, evt);
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return 0;
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2013-05-29 12:12:17 +04:00
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}
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static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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pit_irq_acknowledge();
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/*
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* pit hardware doesn't support oneshot, it will generate an interrupt
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* and reload the counter value from PITLDVAL when PITCVAL reach zero,
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* and start the counter again. So software need to disable the timer
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* to stop the counter loop in ONESHOT mode.
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*/
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2015-06-18 13:54:53 +03:00
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if (likely(clockevent_state_oneshot(evt)))
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2013-05-29 12:12:17 +04:00
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pit_timer_disable();
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct clock_event_device clockevent_pit = {
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.name = "VF pit timer",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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2015-06-18 13:54:53 +03:00
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.set_state_shutdown = pit_shutdown,
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.set_state_periodic = pit_set_periodic,
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2013-05-29 12:12:17 +04:00
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.set_next_event = pit_set_next_event,
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.rating = 300,
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};
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static struct irqaction pit_timer_irq = {
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.name = "VF pit timer",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = pit_timer_interrupt,
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.dev_id = &clockevent_pit,
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};
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static int __init pit_clockevent_init(unsigned long rate, int irq)
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{
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__raw_writel(0, clkevt_base + PITTCTRL);
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__raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
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BUG_ON(setup_irq(irq, &pit_timer_irq));
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clockevent_pit.cpumask = cpumask_of(0);
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clockevent_pit.irq = irq;
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/*
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* The value for the LDVAL register trigger is calculated as:
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* LDVAL trigger = (period / clock period) - 1
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* The pit is a 32-bit down count timer, when the conter value
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* reaches 0, it will generate an interrupt, thus the minimal
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* LDVAL trigger value is 1. And then the min_delta is
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* minimal LDVAL trigger value + 1, and the max_delta is full 32-bit.
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*/
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clockevents_config_and_register(&clockevent_pit, rate, 2, 0xffffffff);
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return 0;
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}
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2016-06-07 00:29:49 +03:00
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static int __init pit_timer_init(struct device_node *np)
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2013-05-29 12:12:17 +04:00
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{
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struct clk *pit_clk;
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void __iomem *timer_base;
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unsigned long clk_rate;
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2016-06-07 00:29:49 +03:00
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int irq, ret;
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2013-05-29 12:12:17 +04:00
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timer_base = of_iomap(np, 0);
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2016-06-07 00:29:49 +03:00
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if (!timer_base) {
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pr_err("Failed to iomap");
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return -ENXIO;
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}
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2013-05-29 12:12:17 +04:00
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/*
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* PIT0 and PIT1 can be chained to build a 64-bit timer,
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* so choose PIT2 as clocksource, PIT3 as clockevent device,
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* and leave PIT0 and PIT1 unused for anyone else who needs them.
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*/
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clksrc_base = timer_base + PITn_OFFSET(2);
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clkevt_base = timer_base + PITn_OFFSET(3);
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irq = irq_of_parse_and_map(np, 0);
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2016-06-07 00:29:49 +03:00
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if (irq <= 0)
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return -EINVAL;
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2013-05-29 12:12:17 +04:00
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pit_clk = of_clk_get(np, 0);
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2016-06-07 00:29:49 +03:00
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if (IS_ERR(pit_clk))
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return PTR_ERR(pit_clk);
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2013-05-29 12:12:17 +04:00
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2016-06-07 00:29:49 +03:00
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ret = clk_prepare_enable(pit_clk);
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if (ret)
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return ret;
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2013-05-29 12:12:17 +04:00
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clk_rate = clk_get_rate(pit_clk);
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cycle_per_jiffy = clk_rate / (HZ);
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/* enable the pit module */
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__raw_writel(~PITMCR_MDIS, timer_base + PITMCR);
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2016-06-07 00:29:49 +03:00
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ret = pit_clocksource_init(clk_rate);
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if (ret)
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return ret;
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2013-05-29 12:12:17 +04:00
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2016-06-07 00:29:49 +03:00
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return pit_clockevent_init(clk_rate, irq);
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2013-05-29 12:12:17 +04:00
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}
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2016-06-07 01:27:44 +03:00
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CLOCKSOURCE_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init);
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