WSL2-Linux-Kernel/arch/xtensa/mm/Makefile

#
# Makefile for the Linux/Xtensa-specific parts of the memory manager.
#

obj-y	 := init.o fault.o tlb.o misc.o cache.o
[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 5 The attached patches provides part 5 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org> 2005-06-24 09:01:24 +04:00			`#`
			`# Makefile for the Linux/Xtensa-specific parts of the memory manager.`
			`#`

[XTENSA] Add support for cache-aliasing Add support for processors that have cache-aliasing issues, such as the Stretch S5000 processor. Cache-aliasing means that the size of the cache (for one way) is larger than the page size, thus, a page can end up in several places in cache depending on the virtual to physical translation. The method used here is to map a user page temporarily through the auto-refill way 0 and of of the DTLB. We probably will want to revisit this issue and use a better approach with kmap/kunmap. Signed-off-by: Chris Zankel <chris@zankel.net> 2007-08-22 21:14:51 +04:00			`obj-y := init.o fault.o tlb.o misc.o cache.o`