2017-11-01 17:09:13 +03:00
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/* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) */
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2012-09-03 16:05:10 +04:00
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/*
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* Video for Linux Two controls header file
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*
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* Copyright (C) 1999-2012 the contributors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Alternatively you can redistribute this file under the terms of the
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* BSD license as stated below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. The names of its contributors may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* The contents of this header was split off from videodev2.h. All control
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* definitions should be added to this header, which is included by
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* videodev2.h.
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*/
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#ifndef __LINUX_V4L2_CONTROLS_H
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#define __LINUX_V4L2_CONTROLS_H
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2018-11-02 14:09:07 +03:00
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#include <linux/types.h>
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2012-09-03 16:05:10 +04:00
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/* Control classes */
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#define V4L2_CTRL_CLASS_USER 0x00980000 /* Old-style 'user' controls */
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#define V4L2_CTRL_CLASS_MPEG 0x00990000 /* MPEG-compression controls */
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#define V4L2_CTRL_CLASS_CAMERA 0x009a0000 /* Camera class controls */
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2013-06-21 09:05:34 +04:00
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#define V4L2_CTRL_CLASS_FM_TX 0x009b0000 /* FM Modulator controls */
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2012-09-03 16:05:10 +04:00
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#define V4L2_CTRL_CLASS_FLASH 0x009c0000 /* Camera flash controls */
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#define V4L2_CTRL_CLASS_JPEG 0x009d0000 /* JPEG-compression controls */
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#define V4L2_CTRL_CLASS_IMAGE_SOURCE 0x009e0000 /* Image source controls */
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#define V4L2_CTRL_CLASS_IMAGE_PROC 0x009f0000 /* Image processing controls */
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#define V4L2_CTRL_CLASS_DV 0x00a00000 /* Digital Video controls */
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2013-06-21 09:05:34 +04:00
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#define V4L2_CTRL_CLASS_FM_RX 0x00a10000 /* FM Receiver controls */
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2014-01-25 06:44:26 +04:00
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#define V4L2_CTRL_CLASS_RF_TUNER 0x00a20000 /* RF tuner controls */
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2014-03-28 20:00:08 +04:00
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#define V4L2_CTRL_CLASS_DETECT 0x00a30000 /* Detection controls */
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2012-09-03 16:05:10 +04:00
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/* User-class control IDs */
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#define V4L2_CID_BASE (V4L2_CTRL_CLASS_USER | 0x900)
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2018-01-04 21:08:56 +03:00
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#define V4L2_CID_USER_BASE V4L2_CID_BASE
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#define V4L2_CID_USER_CLASS (V4L2_CTRL_CLASS_USER | 1)
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2012-09-03 16:05:10 +04:00
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#define V4L2_CID_BRIGHTNESS (V4L2_CID_BASE+0)
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#define V4L2_CID_CONTRAST (V4L2_CID_BASE+1)
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#define V4L2_CID_SATURATION (V4L2_CID_BASE+2)
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#define V4L2_CID_HUE (V4L2_CID_BASE+3)
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#define V4L2_CID_AUDIO_VOLUME (V4L2_CID_BASE+5)
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#define V4L2_CID_AUDIO_BALANCE (V4L2_CID_BASE+6)
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#define V4L2_CID_AUDIO_BASS (V4L2_CID_BASE+7)
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#define V4L2_CID_AUDIO_TREBLE (V4L2_CID_BASE+8)
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#define V4L2_CID_AUDIO_MUTE (V4L2_CID_BASE+9)
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#define V4L2_CID_AUDIO_LOUDNESS (V4L2_CID_BASE+10)
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#define V4L2_CID_BLACK_LEVEL (V4L2_CID_BASE+11) /* Deprecated */
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#define V4L2_CID_AUTO_WHITE_BALANCE (V4L2_CID_BASE+12)
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#define V4L2_CID_DO_WHITE_BALANCE (V4L2_CID_BASE+13)
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#define V4L2_CID_RED_BALANCE (V4L2_CID_BASE+14)
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#define V4L2_CID_BLUE_BALANCE (V4L2_CID_BASE+15)
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#define V4L2_CID_GAMMA (V4L2_CID_BASE+16)
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#define V4L2_CID_WHITENESS (V4L2_CID_GAMMA) /* Deprecated */
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#define V4L2_CID_EXPOSURE (V4L2_CID_BASE+17)
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#define V4L2_CID_AUTOGAIN (V4L2_CID_BASE+18)
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#define V4L2_CID_GAIN (V4L2_CID_BASE+19)
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#define V4L2_CID_HFLIP (V4L2_CID_BASE+20)
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#define V4L2_CID_VFLIP (V4L2_CID_BASE+21)
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#define V4L2_CID_POWER_LINE_FREQUENCY (V4L2_CID_BASE+24)
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enum v4l2_power_line_frequency {
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V4L2_CID_POWER_LINE_FREQUENCY_DISABLED = 0,
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V4L2_CID_POWER_LINE_FREQUENCY_50HZ = 1,
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V4L2_CID_POWER_LINE_FREQUENCY_60HZ = 2,
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V4L2_CID_POWER_LINE_FREQUENCY_AUTO = 3,
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};
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#define V4L2_CID_HUE_AUTO (V4L2_CID_BASE+25)
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#define V4L2_CID_WHITE_BALANCE_TEMPERATURE (V4L2_CID_BASE+26)
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#define V4L2_CID_SHARPNESS (V4L2_CID_BASE+27)
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2018-01-04 21:08:56 +03:00
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#define V4L2_CID_BACKLIGHT_COMPENSATION (V4L2_CID_BASE+28)
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2012-09-03 16:05:10 +04:00
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#define V4L2_CID_CHROMA_AGC (V4L2_CID_BASE+29)
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#define V4L2_CID_COLOR_KILLER (V4L2_CID_BASE+30)
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#define V4L2_CID_COLORFX (V4L2_CID_BASE+31)
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enum v4l2_colorfx {
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V4L2_COLORFX_NONE = 0,
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V4L2_COLORFX_BW = 1,
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V4L2_COLORFX_SEPIA = 2,
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V4L2_COLORFX_NEGATIVE = 3,
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V4L2_COLORFX_EMBOSS = 4,
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V4L2_COLORFX_SKETCH = 5,
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V4L2_COLORFX_SKY_BLUE = 6,
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V4L2_COLORFX_GRASS_GREEN = 7,
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V4L2_COLORFX_SKIN_WHITEN = 8,
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V4L2_COLORFX_VIVID = 9,
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V4L2_COLORFX_AQUA = 10,
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V4L2_COLORFX_ART_FREEZE = 11,
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V4L2_COLORFX_SILHOUETTE = 12,
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V4L2_COLORFX_SOLARIZATION = 13,
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V4L2_COLORFX_ANTIQUE = 14,
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V4L2_COLORFX_SET_CBCR = 15,
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};
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#define V4L2_CID_AUTOBRIGHTNESS (V4L2_CID_BASE+32)
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#define V4L2_CID_BAND_STOP_FILTER (V4L2_CID_BASE+33)
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#define V4L2_CID_ROTATE (V4L2_CID_BASE+34)
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#define V4L2_CID_BG_COLOR (V4L2_CID_BASE+35)
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#define V4L2_CID_CHROMA_GAIN (V4L2_CID_BASE+36)
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#define V4L2_CID_ILLUMINATORS_1 (V4L2_CID_BASE+37)
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#define V4L2_CID_ILLUMINATORS_2 (V4L2_CID_BASE+38)
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#define V4L2_CID_MIN_BUFFERS_FOR_CAPTURE (V4L2_CID_BASE+39)
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#define V4L2_CID_MIN_BUFFERS_FOR_OUTPUT (V4L2_CID_BASE+40)
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#define V4L2_CID_ALPHA_COMPONENT (V4L2_CID_BASE+41)
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#define V4L2_CID_COLORFX_CBCR (V4L2_CID_BASE+42)
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/* last CID + 1 */
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#define V4L2_CID_LASTP1 (V4L2_CID_BASE+43)
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2013-01-29 14:21:02 +04:00
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/* USER-class private control IDs */
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/* The base for the meye driver controls. See linux/meye.h for the list
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* of controls. We reserve 16 controls for this driver. */
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#define V4L2_CID_USER_MEYE_BASE (V4L2_CID_USER_BASE + 0x1000)
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2012-09-03 16:05:10 +04:00
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2013-02-06 19:40:28 +04:00
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/* The base for the bttv driver controls.
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* We reserve 32 controls for this driver. */
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#define V4L2_CID_USER_BTTV_BASE (V4L2_CID_USER_BASE + 0x1010)
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2013-02-15 12:51:21 +04:00
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/* The base for the s2255 driver controls.
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2013-03-29 17:14:32 +04:00
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* We reserve 16 controls for this driver. */
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#define V4L2_CID_USER_S2255_BASE (V4L2_CID_USER_BASE + 0x1030)
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2013-02-15 12:51:21 +04:00
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2015-11-14 00:40:07 +03:00
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/*
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* The base for the si476x driver controls. See include/media/drv-intf/si476x.h
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* for the list of controls. Total of 16 controls is reserved for this driver
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*/
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2013-03-29 17:14:32 +04:00
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#define V4L2_CID_USER_SI476X_BASE (V4L2_CID_USER_BASE + 0x1040)
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2013-03-27 05:47:25 +04:00
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[media] v4l: ti-vpe: Add VPE mem to mem driver
VPE is a block which consists of a single memory to memory path which
can perform chrominance up/down sampling, de-interlacing, scaling, and
color space conversion of raster or tiled YUV420 coplanar, YUV422
coplanar or YUV422 interleaved video formats.
We create a mem2mem driver based primarily on the mem2mem-testdev
example. The de-interlacer, scaler and color space converter are all
bypassed for now to keep the driver simple. Chroma up/down sampler
blocks are implemented, so conversion beteen different YUV formats is
possible.
Each mem2mem context allocates a buffer for VPE MMR values which it will
use when it gets access to the VPE HW via the mem2mem queue, it also
allocates a VPDMA descriptor list to which configuration and data
descriptors are added.
Based on the information received via v4l2 ioctls for the source and
destination queues, the driver configures the values for the MMRs, and
stores them in the buffer. There are also some VPDMA parameters like
frame start and line mode which needs to be configured, these are
configured by direct register writes via the VPDMA helper functions.
The driver's device_run() mem2mem op will add each descriptor based on
how the source and destination queues are set up for the given ctx, once
the list is prepared, it's submitted to VPDMA, these descriptors when
parsed by VPDMA will upload MMR registers, start DMA of video buffers on
the various input and output clients/ports.
When the list is parsed completely(and the DMAs on all the output ports
done), an interrupt is generated which we use to notify that the source
and destination buffers are done. The rest of the driver is quite
similar to other mem2mem drivers, we use the multiplane v4l2 ioctls as
the HW support coplanar formats.
Signed-off-by: Archit Taneja <archit@ti.com>
Acked-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Kamil Debski <k.debski@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
2013-10-16 09:36:47 +04:00
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/* The base for the TI VPE driver controls. Total of 16 controls is reserved for
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* this driver */
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#define V4L2_CID_USER_TI_VPE_BASE (V4L2_CID_USER_BASE + 0x1050)
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2013-12-14 15:28:24 +04:00
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/* The base for the saa7134 driver controls.
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* We reserve 16 controls for this driver. */
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#define V4L2_CID_USER_SAA7134_BASE (V4L2_CID_USER_BASE + 0x1060)
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2015-01-23 18:52:33 +03:00
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/* The base for the adv7180 driver controls.
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* We reserve 16 controls for this driver. */
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#define V4L2_CID_USER_ADV7180_BASE (V4L2_CID_USER_BASE + 0x1070)
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2015-07-09 11:45:47 +03:00
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/* The base for the tc358743 driver controls.
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* We reserve 16 controls for this driver. */
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#define V4L2_CID_USER_TC358743_BASE (V4L2_CID_USER_BASE + 0x1080)
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2017-06-12 16:26:13 +03:00
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/* The base for the max217x driver controls.
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* We reserve 32 controls for this driver
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*/
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#define V4L2_CID_USER_MAX217X_BASE (V4L2_CID_USER_BASE + 0x1090)
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2017-06-10 22:00:29 +03:00
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/* The base for the imx driver controls.
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* We reserve 16 controls for this driver. */
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2018-06-27 21:39:43 +03:00
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#define V4L2_CID_USER_IMX_BASE (V4L2_CID_USER_BASE + 0x10b0)
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2017-06-10 22:00:29 +03:00
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media: atmel: atmel-isc-base: expose white balance as v4l2 controls
This exposes the white balance configuration of the ISC as v4l2 controls
into userspace.
There are 8 controls available:
4 gain controls, sliders, for each of the BAYER components: R, B, GR, GB.
These gains are multipliers for each component, in format unsigned 0:4:9
with a default value of 512 (1.0 multiplier).
4 offset controls, sliders, for each of the BAYER components: R, B, GR, GB.
These offsets are added/substracted from each component, in format signed
1:12:0 with a default value of 0 (+/- 0)
To expose this to userspace, added 8 custom controls, in an auto cluster.
To summarize the functionality:
The auto cluster switch is the auto white balance control, and it works
like this:
AWB == 1: autowhitebalance is on, the do_white_balance button is inactive,
the gains/offsets are inactive, but volatile and readable.
Thus, the results of the whitebalance algorithm are available to userspace
to read at any time.
AWB == 0: autowhitebalance is off, cluster is in manual mode, user can
configure the gain/offsets directly. More than that, if the
do_white_balance button is pressed, the driver will perform
one-time-adjustment, (preferably with color checker card) and the userspace
can read again the new values.
With this feature, the userspace can save the coefficients and reinstall
them for example after reboot or reprobing the driver.
[hverkuil: fix checkpatch warning]
[hverkuil: minor spacing adjustments in the functionality description]
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-01-13 12:48:53 +03:00
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/*
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* The base for the atmel isc driver controls.
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* We reserve 32 controls for this driver.
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*/
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#define V4L2_CID_USER_ATMEL_ISC_BASE (V4L2_CID_USER_BASE + 0x10c0)
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2012-09-03 16:05:10 +04:00
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/* MPEG-class control IDs */
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2013-07-09 08:24:41 +04:00
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/* The MPEG controls are applicable to all codec controls
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* and the 'MPEG' part of the define is historical */
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2012-09-03 16:05:10 +04:00
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2018-01-04 21:08:56 +03:00
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#define V4L2_CID_MPEG_BASE (V4L2_CTRL_CLASS_MPEG | 0x900)
|
|
|
|
|
#define V4L2_CID_MPEG_CLASS (V4L2_CTRL_CLASS_MPEG | 1)
|
2012-09-03 16:05:10 +04:00
|
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|
|
|
|
/* MPEG streams, specific to multiplexed streams */
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_STREAM_TYPE (V4L2_CID_MPEG_BASE+0)
|
2012-09-03 16:05:10 +04:00
|
|
|
enum v4l2_mpeg_stream_type {
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|
V4L2_MPEG_STREAM_TYPE_MPEG2_PS = 0, /* MPEG-2 program stream */
|
|
|
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|
V4L2_MPEG_STREAM_TYPE_MPEG2_TS = 1, /* MPEG-2 transport stream */
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|
V4L2_MPEG_STREAM_TYPE_MPEG1_SS = 2, /* MPEG-1 system stream */
|
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|
V4L2_MPEG_STREAM_TYPE_MPEG2_DVD = 3, /* MPEG-2 DVD-compatible stream */
|
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|
V4L2_MPEG_STREAM_TYPE_MPEG1_VCD = 4, /* MPEG-1 VCD-compatible stream */
|
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|
|
|
V4L2_MPEG_STREAM_TYPE_MPEG2_SVCD = 5, /* MPEG-2 SVCD-compatible stream */
|
|
|
|
|
};
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_STREAM_PID_PMT (V4L2_CID_MPEG_BASE+1)
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|
#define V4L2_CID_MPEG_STREAM_PID_AUDIO (V4L2_CID_MPEG_BASE+2)
|
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#define V4L2_CID_MPEG_STREAM_PID_VIDEO (V4L2_CID_MPEG_BASE+3)
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#define V4L2_CID_MPEG_STREAM_PID_PCR (V4L2_CID_MPEG_BASE+4)
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#define V4L2_CID_MPEG_STREAM_PES_ID_AUDIO (V4L2_CID_MPEG_BASE+5)
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|
#define V4L2_CID_MPEG_STREAM_PES_ID_VIDEO (V4L2_CID_MPEG_BASE+6)
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#define V4L2_CID_MPEG_STREAM_VBI_FMT (V4L2_CID_MPEG_BASE+7)
|
2012-09-03 16:05:10 +04:00
|
|
|
enum v4l2_mpeg_stream_vbi_fmt {
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|
V4L2_MPEG_STREAM_VBI_FMT_NONE = 0, /* No VBI in the MPEG stream */
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|
V4L2_MPEG_STREAM_VBI_FMT_IVTV = 1, /* VBI in private packets, IVTV format */
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|
};
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|
|
/* MPEG audio controls specific to multiplexed streams */
|
2018-01-04 21:08:56 +03:00
|
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|
#define V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ (V4L2_CID_MPEG_BASE+100)
|
2012-09-03 16:05:10 +04:00
|
|
|
enum v4l2_mpeg_audio_sampling_freq {
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|
V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100 = 0,
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|
V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000 = 1,
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|
V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000 = 2,
|
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|
|
|
};
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_AUDIO_ENCODING (V4L2_CID_MPEG_BASE+101)
|
2012-09-03 16:05:10 +04:00
|
|
|
enum v4l2_mpeg_audio_encoding {
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|
V4L2_MPEG_AUDIO_ENCODING_LAYER_1 = 0,
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|
|
|
V4L2_MPEG_AUDIO_ENCODING_LAYER_2 = 1,
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|
V4L2_MPEG_AUDIO_ENCODING_LAYER_3 = 2,
|
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|
|
V4L2_MPEG_AUDIO_ENCODING_AAC = 3,
|
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|
|
V4L2_MPEG_AUDIO_ENCODING_AC3 = 4,
|
|
|
|
|
};
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_AUDIO_L1_BITRATE (V4L2_CID_MPEG_BASE+102)
|
2012-09-03 16:05:10 +04:00
|
|
|
enum v4l2_mpeg_audio_l1_bitrate {
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|
V4L2_MPEG_AUDIO_L1_BITRATE_32K = 0,
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|
|
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|
V4L2_MPEG_AUDIO_L1_BITRATE_64K = 1,
|
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|
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|
V4L2_MPEG_AUDIO_L1_BITRATE_96K = 2,
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|
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|
V4L2_MPEG_AUDIO_L1_BITRATE_128K = 3,
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|
V4L2_MPEG_AUDIO_L1_BITRATE_160K = 4,
|
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|
|
|
V4L2_MPEG_AUDIO_L1_BITRATE_192K = 5,
|
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|
V4L2_MPEG_AUDIO_L1_BITRATE_224K = 6,
|
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|
|
|
V4L2_MPEG_AUDIO_L1_BITRATE_256K = 7,
|
|
|
|
|
V4L2_MPEG_AUDIO_L1_BITRATE_288K = 8,
|
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|
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|
V4L2_MPEG_AUDIO_L1_BITRATE_320K = 9,
|
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|
|
|
V4L2_MPEG_AUDIO_L1_BITRATE_352K = 10,
|
|
|
|
|
V4L2_MPEG_AUDIO_L1_BITRATE_384K = 11,
|
|
|
|
|
V4L2_MPEG_AUDIO_L1_BITRATE_416K = 12,
|
|
|
|
|
V4L2_MPEG_AUDIO_L1_BITRATE_448K = 13,
|
|
|
|
|
};
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_AUDIO_L2_BITRATE (V4L2_CID_MPEG_BASE+103)
|
2012-09-03 16:05:10 +04:00
|
|
|
enum v4l2_mpeg_audio_l2_bitrate {
|
|
|
|
|
V4L2_MPEG_AUDIO_L2_BITRATE_32K = 0,
|
|
|
|
|
V4L2_MPEG_AUDIO_L2_BITRATE_48K = 1,
|
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|
|
|
V4L2_MPEG_AUDIO_L2_BITRATE_56K = 2,
|
|
|
|
|
V4L2_MPEG_AUDIO_L2_BITRATE_64K = 3,
|
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|
|
|
V4L2_MPEG_AUDIO_L2_BITRATE_80K = 4,
|
|
|
|
|
V4L2_MPEG_AUDIO_L2_BITRATE_96K = 5,
|
|
|
|
|
V4L2_MPEG_AUDIO_L2_BITRATE_112K = 6,
|
|
|
|
|
V4L2_MPEG_AUDIO_L2_BITRATE_128K = 7,
|
|
|
|
|
V4L2_MPEG_AUDIO_L2_BITRATE_160K = 8,
|
|
|
|
|
V4L2_MPEG_AUDIO_L2_BITRATE_192K = 9,
|
|
|
|
|
V4L2_MPEG_AUDIO_L2_BITRATE_224K = 10,
|
|
|
|
|
V4L2_MPEG_AUDIO_L2_BITRATE_256K = 11,
|
|
|
|
|
V4L2_MPEG_AUDIO_L2_BITRATE_320K = 12,
|
|
|
|
|
V4L2_MPEG_AUDIO_L2_BITRATE_384K = 13,
|
|
|
|
|
};
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_AUDIO_L3_BITRATE (V4L2_CID_MPEG_BASE+104)
|
2012-09-03 16:05:10 +04:00
|
|
|
enum v4l2_mpeg_audio_l3_bitrate {
|
|
|
|
|
V4L2_MPEG_AUDIO_L3_BITRATE_32K = 0,
|
|
|
|
|
V4L2_MPEG_AUDIO_L3_BITRATE_40K = 1,
|
|
|
|
|
V4L2_MPEG_AUDIO_L3_BITRATE_48K = 2,
|
|
|
|
|
V4L2_MPEG_AUDIO_L3_BITRATE_56K = 3,
|
|
|
|
|
V4L2_MPEG_AUDIO_L3_BITRATE_64K = 4,
|
|
|
|
|
V4L2_MPEG_AUDIO_L3_BITRATE_80K = 5,
|
|
|
|
|
V4L2_MPEG_AUDIO_L3_BITRATE_96K = 6,
|
|
|
|
|
V4L2_MPEG_AUDIO_L3_BITRATE_112K = 7,
|
|
|
|
|
V4L2_MPEG_AUDIO_L3_BITRATE_128K = 8,
|
|
|
|
|
V4L2_MPEG_AUDIO_L3_BITRATE_160K = 9,
|
|
|
|
|
V4L2_MPEG_AUDIO_L3_BITRATE_192K = 10,
|
|
|
|
|
V4L2_MPEG_AUDIO_L3_BITRATE_224K = 11,
|
|
|
|
|
V4L2_MPEG_AUDIO_L3_BITRATE_256K = 12,
|
|
|
|
|
V4L2_MPEG_AUDIO_L3_BITRATE_320K = 13,
|
|
|
|
|
};
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_AUDIO_MODE (V4L2_CID_MPEG_BASE+105)
|
2012-09-03 16:05:10 +04:00
|
|
|
enum v4l2_mpeg_audio_mode {
|
|
|
|
|
V4L2_MPEG_AUDIO_MODE_STEREO = 0,
|
|
|
|
|
V4L2_MPEG_AUDIO_MODE_JOINT_STEREO = 1,
|
|
|
|
|
V4L2_MPEG_AUDIO_MODE_DUAL = 2,
|
|
|
|
|
V4L2_MPEG_AUDIO_MODE_MONO = 3,
|
|
|
|
|
};
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_AUDIO_MODE_EXTENSION (V4L2_CID_MPEG_BASE+106)
|
2012-09-03 16:05:10 +04:00
|
|
|
enum v4l2_mpeg_audio_mode_extension {
|
|
|
|
|
V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_4 = 0,
|
|
|
|
|
V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_8 = 1,
|
|
|
|
|
V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_12 = 2,
|
|
|
|
|
V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_16 = 3,
|
|
|
|
|
};
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_AUDIO_EMPHASIS (V4L2_CID_MPEG_BASE+107)
|
2012-09-03 16:05:10 +04:00
|
|
|
enum v4l2_mpeg_audio_emphasis {
|
|
|
|
|
V4L2_MPEG_AUDIO_EMPHASIS_NONE = 0,
|
|
|
|
|
V4L2_MPEG_AUDIO_EMPHASIS_50_DIV_15_uS = 1,
|
|
|
|
|
V4L2_MPEG_AUDIO_EMPHASIS_CCITT_J17 = 2,
|
|
|
|
|
};
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_AUDIO_CRC (V4L2_CID_MPEG_BASE+108)
|
2012-09-03 16:05:10 +04:00
|
|
|
enum v4l2_mpeg_audio_crc {
|
|
|
|
|
V4L2_MPEG_AUDIO_CRC_NONE = 0,
|
|
|
|
|
V4L2_MPEG_AUDIO_CRC_CRC16 = 1,
|
|
|
|
|
};
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_AUDIO_MUTE (V4L2_CID_MPEG_BASE+109)
|
2012-09-03 16:05:10 +04:00
|
|
|
#define V4L2_CID_MPEG_AUDIO_AAC_BITRATE (V4L2_CID_MPEG_BASE+110)
|
|
|
|
|
#define V4L2_CID_MPEG_AUDIO_AC3_BITRATE (V4L2_CID_MPEG_BASE+111)
|
|
|
|
|
enum v4l2_mpeg_audio_ac3_bitrate {
|
|
|
|
|
V4L2_MPEG_AUDIO_AC3_BITRATE_32K = 0,
|
|
|
|
|
V4L2_MPEG_AUDIO_AC3_BITRATE_40K = 1,
|
|
|
|
|
V4L2_MPEG_AUDIO_AC3_BITRATE_48K = 2,
|
|
|
|
|
V4L2_MPEG_AUDIO_AC3_BITRATE_56K = 3,
|
|
|
|
|
V4L2_MPEG_AUDIO_AC3_BITRATE_64K = 4,
|
|
|
|
|
V4L2_MPEG_AUDIO_AC3_BITRATE_80K = 5,
|
|
|
|
|
V4L2_MPEG_AUDIO_AC3_BITRATE_96K = 6,
|
|
|
|
|
V4L2_MPEG_AUDIO_AC3_BITRATE_112K = 7,
|
|
|
|
|
V4L2_MPEG_AUDIO_AC3_BITRATE_128K = 8,
|
|
|
|
|
V4L2_MPEG_AUDIO_AC3_BITRATE_160K = 9,
|
|
|
|
|
V4L2_MPEG_AUDIO_AC3_BITRATE_192K = 10,
|
|
|
|
|
V4L2_MPEG_AUDIO_AC3_BITRATE_224K = 11,
|
|
|
|
|
V4L2_MPEG_AUDIO_AC3_BITRATE_256K = 12,
|
|
|
|
|
V4L2_MPEG_AUDIO_AC3_BITRATE_320K = 13,
|
|
|
|
|
V4L2_MPEG_AUDIO_AC3_BITRATE_384K = 14,
|
|
|
|
|
V4L2_MPEG_AUDIO_AC3_BITRATE_448K = 15,
|
|
|
|
|
V4L2_MPEG_AUDIO_AC3_BITRATE_512K = 16,
|
|
|
|
|
V4L2_MPEG_AUDIO_AC3_BITRATE_576K = 17,
|
|
|
|
|
V4L2_MPEG_AUDIO_AC3_BITRATE_640K = 18,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_AUDIO_DEC_PLAYBACK (V4L2_CID_MPEG_BASE+112)
|
|
|
|
|
enum v4l2_mpeg_audio_dec_playback {
|
|
|
|
|
V4L2_MPEG_AUDIO_DEC_PLAYBACK_AUTO = 0,
|
|
|
|
|
V4L2_MPEG_AUDIO_DEC_PLAYBACK_STEREO = 1,
|
|
|
|
|
V4L2_MPEG_AUDIO_DEC_PLAYBACK_LEFT = 2,
|
|
|
|
|
V4L2_MPEG_AUDIO_DEC_PLAYBACK_RIGHT = 3,
|
|
|
|
|
V4L2_MPEG_AUDIO_DEC_PLAYBACK_MONO = 4,
|
|
|
|
|
V4L2_MPEG_AUDIO_DEC_PLAYBACK_SWAPPED_STEREO = 5,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_AUDIO_DEC_MULTILINGUAL_PLAYBACK (V4L2_CID_MPEG_BASE+113)
|
|
|
|
|
|
|
|
|
|
/* MPEG video controls specific to multiplexed streams */
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_VIDEO_ENCODING (V4L2_CID_MPEG_BASE+200)
|
2012-09-03 16:05:10 +04:00
|
|
|
enum v4l2_mpeg_video_encoding {
|
|
|
|
|
V4L2_MPEG_VIDEO_ENCODING_MPEG_1 = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_ENCODING_MPEG_2 = 1,
|
|
|
|
|
V4L2_MPEG_VIDEO_ENCODING_MPEG_4_AVC = 2,
|
|
|
|
|
};
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_VIDEO_ASPECT (V4L2_CID_MPEG_BASE+201)
|
2012-09-03 16:05:10 +04:00
|
|
|
enum v4l2_mpeg_video_aspect {
|
|
|
|
|
V4L2_MPEG_VIDEO_ASPECT_1x1 = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_ASPECT_4x3 = 1,
|
|
|
|
|
V4L2_MPEG_VIDEO_ASPECT_16x9 = 2,
|
|
|
|
|
V4L2_MPEG_VIDEO_ASPECT_221x100 = 3,
|
|
|
|
|
};
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_VIDEO_B_FRAMES (V4L2_CID_MPEG_BASE+202)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_GOP_SIZE (V4L2_CID_MPEG_BASE+203)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_GOP_CLOSURE (V4L2_CID_MPEG_BASE+204)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_PULLDOWN (V4L2_CID_MPEG_BASE+205)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_BITRATE_MODE (V4L2_CID_MPEG_BASE+206)
|
2012-09-03 16:05:10 +04:00
|
|
|
enum v4l2_mpeg_video_bitrate_mode {
|
|
|
|
|
V4L2_MPEG_VIDEO_BITRATE_MODE_VBR = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_BITRATE_MODE_CBR = 1,
|
|
|
|
|
};
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_VIDEO_BITRATE (V4L2_CID_MPEG_BASE+207)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_BITRATE_PEAK (V4L2_CID_MPEG_BASE+208)
|
2012-09-03 16:05:10 +04:00
|
|
|
#define V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION (V4L2_CID_MPEG_BASE+209)
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_VIDEO_MUTE (V4L2_CID_MPEG_BASE+210)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_MUTE_YUV (V4L2_CID_MPEG_BASE+211)
|
2012-09-03 16:05:10 +04:00
|
|
|
#define V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE (V4L2_CID_MPEG_BASE+212)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER (V4L2_CID_MPEG_BASE+213)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB (V4L2_CID_MPEG_BASE+214)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE (V4L2_CID_MPEG_BASE+215)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEADER_MODE (V4L2_CID_MPEG_BASE+216)
|
|
|
|
|
enum v4l2_mpeg_video_header_mode {
|
|
|
|
|
V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME = 1,
|
|
|
|
|
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_MAX_REF_PIC (V4L2_CID_MPEG_BASE+217)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE (V4L2_CID_MPEG_BASE+218)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES (V4L2_CID_MPEG_BASE+219)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB (V4L2_CID_MPEG_BASE+220)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE (V4L2_CID_MPEG_BASE+221)
|
|
|
|
|
enum v4l2_mpeg_video_multi_slice_mode {
|
|
|
|
|
V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE = 0,
|
2019-04-24 12:37:49 +03:00
|
|
|
V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB = 1,
|
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|
|
|
V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES = 2,
|
|
|
|
|
#ifndef __KERNEL__
|
|
|
|
|
/* Kept for backwards compatibility reasons. Stupid typo... */
|
2012-09-03 16:05:10 +04:00
|
|
|
V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB = 1,
|
|
|
|
|
V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES = 2,
|
2019-04-24 12:37:49 +03:00
|
|
|
#endif
|
2012-09-03 16:05:10 +04:00
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_VBV_SIZE (V4L2_CID_MPEG_BASE+222)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_DEC_PTS (V4L2_CID_MPEG_BASE+223)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_DEC_FRAME (V4L2_CID_MPEG_BASE+224)
|
2012-10-04 05:19:06 +04:00
|
|
|
#define V4L2_CID_MPEG_VIDEO_VBV_DELAY (V4L2_CID_MPEG_BASE+225)
|
2013-03-17 17:34:04 +04:00
|
|
|
#define V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER (V4L2_CID_MPEG_BASE+226)
|
2014-02-04 13:59:58 +04:00
|
|
|
#define V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE (V4L2_CID_MPEG_BASE+227)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE (V4L2_CID_MPEG_BASE+228)
|
2016-01-19 10:07:09 +03:00
|
|
|
#define V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME (V4L2_CID_MPEG_BASE+229)
|
2012-09-03 16:05:10 +04:00
|
|
|
|
2019-04-24 13:43:47 +03:00
|
|
|
/* CIDs for the MPEG-2 Part 2 (H.262) codec */
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL (V4L2_CID_MPEG_BASE+270)
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|
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|
|
enum v4l2_mpeg_video_mpeg2_level {
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|
|
|
|
V4L2_MPEG_VIDEO_MPEG2_LEVEL_LOW = 0,
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|
|
|
|
V4L2_MPEG_VIDEO_MPEG2_LEVEL_MAIN = 1,
|
|
|
|
|
V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH_1440 = 2,
|
|
|
|
|
V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH = 3,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE (V4L2_CID_MPEG_BASE+271)
|
|
|
|
|
enum v4l2_mpeg_video_mpeg2_profile {
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|
|
|
|
V4L2_MPEG_VIDEO_MPEG2_PROFILE_SIMPLE = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_MPEG2_PROFILE_MAIN = 1,
|
|
|
|
|
V4L2_MPEG_VIDEO_MPEG2_PROFILE_SNR_SCALABLE = 2,
|
|
|
|
|
V4L2_MPEG_VIDEO_MPEG2_PROFILE_SPATIALLY_SCALABLE = 3,
|
|
|
|
|
V4L2_MPEG_VIDEO_MPEG2_PROFILE_HIGH = 4,
|
|
|
|
|
V4L2_MPEG_VIDEO_MPEG2_PROFILE_MULTIVIEW = 5,
|
|
|
|
|
};
|
|
|
|
|
|
2019-03-07 00:13:40 +03:00
|
|
|
/* CIDs for the FWHT codec as used by the vicodec driver. */
|
|
|
|
|
#define V4L2_CID_FWHT_I_FRAME_QP (V4L2_CID_MPEG_BASE + 290)
|
|
|
|
|
#define V4L2_CID_FWHT_P_FRAME_QP (V4L2_CID_MPEG_BASE + 291)
|
|
|
|
|
|
2012-09-03 16:05:10 +04:00
|
|
|
#define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP (V4L2_CID_MPEG_BASE+300)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP (V4L2_CID_MPEG_BASE+301)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP (V4L2_CID_MPEG_BASE+302)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H263_MIN_QP (V4L2_CID_MPEG_BASE+303)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H263_MAX_QP (V4L2_CID_MPEG_BASE+304)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP (V4L2_CID_MPEG_BASE+350)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP (V4L2_CID_MPEG_BASE+351)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP (V4L2_CID_MPEG_BASE+352)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_MIN_QP (V4L2_CID_MPEG_BASE+353)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_MAX_QP (V4L2_CID_MPEG_BASE+354)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM (V4L2_CID_MPEG_BASE+355)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE (V4L2_CID_MPEG_BASE+356)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE (V4L2_CID_MPEG_BASE+357)
|
|
|
|
|
enum v4l2_mpeg_video_h264_entropy_mode {
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC = 1,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_I_PERIOD (V4L2_CID_MPEG_BASE+358)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_LEVEL (V4L2_CID_MPEG_BASE+359)
|
|
|
|
|
enum v4l2_mpeg_video_h264_level {
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_1_0 = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_1B = 1,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_1_1 = 2,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_1_2 = 3,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_1_3 = 4,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_2_0 = 5,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_2_1 = 6,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_2_2 = 7,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_3_0 = 8,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_3_1 = 9,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_3_2 = 10,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_4_0 = 11,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_4_1 = 12,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_4_2 = 13,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_5_0 = 14,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_5_1 = 15,
|
2020-03-17 01:42:30 +03:00
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_5_2 = 16,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_6_0 = 17,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_6_1 = 18,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LEVEL_6_2 = 19,
|
2012-09-03 16:05:10 +04:00
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA (V4L2_CID_MPEG_BASE+360)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA (V4L2_CID_MPEG_BASE+361)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE (V4L2_CID_MPEG_BASE+362)
|
|
|
|
|
enum v4l2_mpeg_video_h264_loop_filter_mode {
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED = 1,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY = 2,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_PROFILE (V4L2_CID_MPEG_BASE+363)
|
|
|
|
|
enum v4l2_mpeg_video_h264_profile {
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE = 1,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_PROFILE_MAIN = 2,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED = 3,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_PROFILE_HIGH = 4,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10 = 5,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422 = 6,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE = 7,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10_INTRA = 8,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422_INTRA = 9,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_INTRA = 10,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_PROFILE_CAVLC_444_INTRA = 11,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_BASELINE = 12,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH = 13,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH_INTRA = 14,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH = 15,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH = 16,
|
2020-03-17 01:42:30 +03:00
|
|
|
V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH = 17,
|
2012-09-03 16:05:10 +04:00
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT (V4L2_CID_MPEG_BASE+364)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH (V4L2_CID_MPEG_BASE+365)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE (V4L2_CID_MPEG_BASE+366)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC (V4L2_CID_MPEG_BASE+367)
|
|
|
|
|
enum v4l2_mpeg_video_h264_vui_sar_idc {
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1 = 1,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_12x11 = 2,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_10x11 = 3,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_16x11 = 4,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_40x33 = 5,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_24x11 = 6,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_20x11 = 7,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_32x11 = 8,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_80x33 = 9,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_18x11 = 10,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_15x11 = 11,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_64x33 = 12,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_160x99 = 13,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_4x3 = 14,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_3x2 = 15,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_2x1 = 16,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED = 17,
|
|
|
|
|
};
|
2012-10-04 05:19:06 +04:00
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING (V4L2_CID_MPEG_BASE+368)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_CURRENT_FRAME_0 (V4L2_CID_MPEG_BASE+369)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE (V4L2_CID_MPEG_BASE+370)
|
|
|
|
|
enum v4l2_mpeg_video_h264_sei_fp_arrangement_type {
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_CHECKERBOARD = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_COLUMN = 1,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_ROW = 2,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_SIDE_BY_SIDE = 3,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TOP_BOTTOM = 4,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TEMPORAL = 5,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_FMO (V4L2_CID_MPEG_BASE+371)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE (V4L2_CID_MPEG_BASE+372)
|
|
|
|
|
enum v4l2_mpeg_video_h264_fmo_map_type {
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES = 1,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_FOREGROUND_WITH_LEFT_OVER = 2,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_BOX_OUT = 3,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN = 4,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN = 5,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_EXPLICIT = 6,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_FMO_SLICE_GROUP (V4L2_CID_MPEG_BASE+373)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_DIRECTION (V4L2_CID_MPEG_BASE+374)
|
|
|
|
|
enum v4l2_mpeg_video_h264_fmo_change_dir {
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_RIGHT = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_LEFT = 1,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_RATE (V4L2_CID_MPEG_BASE+375)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_FMO_RUN_LENGTH (V4L2_CID_MPEG_BASE+376)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_ASO (V4L2_CID_MPEG_BASE+377)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_ASO_SLICE_ORDER (V4L2_CID_MPEG_BASE+378)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING (V4L2_CID_MPEG_BASE+379)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE (V4L2_CID_MPEG_BASE+380)
|
|
|
|
|
enum v4l2_mpeg_video_h264_hierarchical_coding_type {
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P = 1,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER (V4L2_CID_MPEG_BASE+381)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP (V4L2_CID_MPEG_BASE+382)
|
2019-01-10 19:56:09 +03:00
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION (V4L2_CID_MPEG_BASE+383)
|
2019-01-10 19:56:10 +03:00
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET (V4L2_CID_MPEG_BASE+384)
|
2019-03-29 06:20:46 +03:00
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP (V4L2_CID_MPEG_BASE+385)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP (V4L2_CID_MPEG_BASE+386)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP (V4L2_CID_MPEG_BASE+387)
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|
|
|
#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP (V4L2_CID_MPEG_BASE+388)
|
2012-09-03 16:05:10 +04:00
|
|
|
#define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_MPEG_BASE+400)
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|
#define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_MPEG_BASE+401)
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|
#define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_MPEG_BASE+402)
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|
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|
#define V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP (V4L2_CID_MPEG_BASE+403)
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|
|
#define V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP (V4L2_CID_MPEG_BASE+404)
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|
|
#define V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL (V4L2_CID_MPEG_BASE+405)
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|
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|
|
enum v4l2_mpeg_video_mpeg4_level {
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|
V4L2_MPEG_VIDEO_MPEG4_LEVEL_0 = 0,
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|
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|
V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B = 1,
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|
V4L2_MPEG_VIDEO_MPEG4_LEVEL_1 = 2,
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V4L2_MPEG_VIDEO_MPEG4_LEVEL_2 = 3,
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|
V4L2_MPEG_VIDEO_MPEG4_LEVEL_3 = 4,
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V4L2_MPEG_VIDEO_MPEG4_LEVEL_3B = 5,
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|
V4L2_MPEG_VIDEO_MPEG4_LEVEL_4 = 6,
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|
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|
V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 = 7,
|
|
|
|
|
};
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|
#define V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE (V4L2_CID_MPEG_BASE+406)
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|
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|
|
enum v4l2_mpeg_video_mpeg4_profile {
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|
V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE = 0,
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|
V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE = 1,
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|
V4L2_MPEG_VIDEO_MPEG4_PROFILE_CORE = 2,
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V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE_SCALABLE = 3,
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V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_CODING_EFFICIENCY = 4,
|
|
|
|
|
};
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|
#define V4L2_CID_MPEG_VIDEO_MPEG4_QPEL (V4L2_CID_MPEG_BASE+407)
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|
|
|
2013-07-09 08:24:41 +04:00
|
|
|
/* Control IDs for VP8 streams
|
|
|
|
|
* Although VP8 is not part of MPEG we add these controls to the MPEG class
|
|
|
|
|
* as that class is already handling other video compression standards
|
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|
|
|
*/
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|
|
|
|
#define V4L2_CID_MPEG_VIDEO_VPX_NUM_PARTITIONS (V4L2_CID_MPEG_BASE+500)
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|
|
|
|
enum v4l2_vp8_num_partitions {
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|
V4L2_CID_MPEG_VIDEO_VPX_1_PARTITION = 0,
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|
|
|
|
V4L2_CID_MPEG_VIDEO_VPX_2_PARTITIONS = 1,
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V4L2_CID_MPEG_VIDEO_VPX_4_PARTITIONS = 2,
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|
V4L2_CID_MPEG_VIDEO_VPX_8_PARTITIONS = 3,
|
|
|
|
|
};
|
|
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|
#define V4L2_CID_MPEG_VIDEO_VPX_IMD_DISABLE_4X4 (V4L2_CID_MPEG_BASE+501)
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|
#define V4L2_CID_MPEG_VIDEO_VPX_NUM_REF_FRAMES (V4L2_CID_MPEG_BASE+502)
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|
|
enum v4l2_vp8_num_ref_frames {
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|
|
|
V4L2_CID_MPEG_VIDEO_VPX_1_REF_FRAME = 0,
|
|
|
|
|
V4L2_CID_MPEG_VIDEO_VPX_2_REF_FRAME = 1,
|
|
|
|
|
V4L2_CID_MPEG_VIDEO_VPX_3_REF_FRAME = 2,
|
|
|
|
|
};
|
|
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|
|
#define V4L2_CID_MPEG_VIDEO_VPX_FILTER_LEVEL (V4L2_CID_MPEG_BASE+503)
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|
|
|
|
#define V4L2_CID_MPEG_VIDEO_VPX_FILTER_SHARPNESS (V4L2_CID_MPEG_BASE+504)
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|
|
#define V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_REF_PERIOD (V4L2_CID_MPEG_BASE+505)
|
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|
|
#define V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_SEL (V4L2_CID_MPEG_BASE+506)
|
|
|
|
|
enum v4l2_vp8_golden_frame_sel {
|
|
|
|
|
V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_USE_PREV = 0,
|
|
|
|
|
V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_USE_REF_PERIOD = 1,
|
|
|
|
|
};
|
2013-11-15 09:29:22 +04:00
|
|
|
#define V4L2_CID_MPEG_VIDEO_VPX_MIN_QP (V4L2_CID_MPEG_BASE+507)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_VPX_MAX_QP (V4L2_CID_MPEG_BASE+508)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_VPX_I_FRAME_QP (V4L2_CID_MPEG_BASE+509)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_VPX_P_FRAME_QP (V4L2_CID_MPEG_BASE+510)
|
2018-06-18 10:58:52 +03:00
|
|
|
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_VP8_PROFILE (V4L2_CID_MPEG_BASE+511)
|
|
|
|
|
enum v4l2_mpeg_video_vp8_profile {
|
|
|
|
|
V4L2_MPEG_VIDEO_VP8_PROFILE_0 = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_VP8_PROFILE_1 = 1,
|
|
|
|
|
V4L2_MPEG_VIDEO_VP8_PROFILE_2 = 2,
|
|
|
|
|
V4L2_MPEG_VIDEO_VP8_PROFILE_3 = 3,
|
|
|
|
|
};
|
|
|
|
|
/* Deprecated alias for compatibility reasons. */
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_VPX_PROFILE V4L2_CID_MPEG_VIDEO_VP8_PROFILE
|
2018-06-18 10:58:53 +03:00
|
|
|
#define V4L2_CID_MPEG_VIDEO_VP9_PROFILE (V4L2_CID_MPEG_BASE+512)
|
|
|
|
|
enum v4l2_mpeg_video_vp9_profile {
|
|
|
|
|
V4L2_MPEG_VIDEO_VP9_PROFILE_0 = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_VP9_PROFILE_1 = 1,
|
|
|
|
|
V4L2_MPEG_VIDEO_VP9_PROFILE_2 = 2,
|
|
|
|
|
V4L2_MPEG_VIDEO_VP9_PROFILE_3 = 3,
|
|
|
|
|
};
|
2013-07-09 08:24:41 +04:00
|
|
|
|
2018-02-02 15:25:46 +03:00
|
|
|
/* CIDs for HEVC encoding. */
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP (V4L2_CID_MPEG_BASE + 600)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP (V4L2_CID_MPEG_BASE + 601)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP (V4L2_CID_MPEG_BASE + 602)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP (V4L2_CID_MPEG_BASE + 603)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP (V4L2_CID_MPEG_BASE + 604)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_QP (V4L2_CID_MPEG_BASE + 605)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE (V4L2_CID_MPEG_BASE + 606)
|
|
|
|
|
enum v4l2_mpeg_video_hevc_hier_coding_type {
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P = 1,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_LAYER (V4L2_CID_MPEG_BASE + 607)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L0_QP (V4L2_CID_MPEG_BASE + 608)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L1_QP (V4L2_CID_MPEG_BASE + 609)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L2_QP (V4L2_CID_MPEG_BASE + 610)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L3_QP (V4L2_CID_MPEG_BASE + 611)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L4_QP (V4L2_CID_MPEG_BASE + 612)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L5_QP (V4L2_CID_MPEG_BASE + 613)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L6_QP (V4L2_CID_MPEG_BASE + 614)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_PROFILE (V4L2_CID_MPEG_BASE + 615)
|
|
|
|
|
enum v4l2_mpeg_video_hevc_profile {
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE = 1,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10 = 2,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_LEVEL (V4L2_CID_MPEG_BASE + 616)
|
|
|
|
|
enum v4l2_mpeg_video_hevc_level {
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_LEVEL_1 = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_LEVEL_2 = 1,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1 = 2,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_LEVEL_3 = 3,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1 = 4,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_LEVEL_4 = 5,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1 = 6,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_LEVEL_5 = 7,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1 = 8,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2 = 9,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_LEVEL_6 = 10,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1 = 11,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2 = 12,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_FRAME_RATE_RESOLUTION (V4L2_CID_MPEG_BASE + 617)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_TIER (V4L2_CID_MPEG_BASE + 618)
|
|
|
|
|
enum v4l2_mpeg_video_hevc_tier {
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_TIER_MAIN = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_TIER_HIGH = 1,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH (V4L2_CID_MPEG_BASE + 619)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE (V4L2_CID_MPEG_BASE + 620)
|
|
|
|
|
enum v4l2_cid_mpeg_video_hevc_loop_filter_mode {
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED = 1,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY = 2,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2 (V4L2_CID_MPEG_BASE + 621)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2 (V4L2_CID_MPEG_BASE + 622)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE (V4L2_CID_MPEG_BASE + 623)
|
|
|
|
|
enum v4l2_cid_mpeg_video_hevc_refresh_type {
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_REFRESH_NONE = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_REFRESH_CRA = 1,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR = 2,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD (V4L2_CID_MPEG_BASE + 624)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU (V4L2_CID_MPEG_BASE + 625)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED (V4L2_CID_MPEG_BASE + 626)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT (V4L2_CID_MPEG_BASE + 627)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB (V4L2_CID_MPEG_BASE + 628)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID (V4L2_CID_MPEG_BASE + 629)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOOTHING (V4L2_CID_MPEG_BASE + 630)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1 (V4L2_CID_MPEG_BASE + 631)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_INTRA_PU_SPLIT (V4L2_CID_MPEG_BASE + 632)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_TMV_PREDICTION (V4L2_CID_MPEG_BASE + 633)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE (V4L2_CID_MPEG_BASE + 634)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD (V4L2_CID_MPEG_BASE + 635)
|
|
|
|
|
enum v4l2_cid_mpeg_video_hevc_size_of_length_field {
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_SIZE_0 = 0,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_SIZE_1 = 1,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_SIZE_2 = 2,
|
|
|
|
|
V4L2_MPEG_VIDEO_HEVC_SIZE_4 = 3,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L0_BR (V4L2_CID_MPEG_BASE + 636)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L1_BR (V4L2_CID_MPEG_BASE + 637)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L2_BR (V4L2_CID_MPEG_BASE + 638)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L3_BR (V4L2_CID_MPEG_BASE + 639)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L4_BR (V4L2_CID_MPEG_BASE + 640)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L5_BR (V4L2_CID_MPEG_BASE + 641)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L6_BR (V4L2_CID_MPEG_BASE + 642)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_REF_NUMBER_FOR_PFRAMES (V4L2_CID_MPEG_BASE + 643)
|
|
|
|
|
#define V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR (V4L2_CID_MPEG_BASE + 644)
|
|
|
|
|
|
2012-09-03 16:05:10 +04:00
|
|
|
/* MPEG-class control IDs specific to the CX2341x driver as defined by V4L2 */
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_CX2341X_BASE (V4L2_CTRL_CLASS_MPEG | 0x1000)
|
|
|
|
|
#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+0)
|
2012-09-03 16:05:10 +04:00
|
|
|
enum v4l2_mpeg_cx2341x_video_spatial_filter_mode {
|
|
|
|
|
V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_MANUAL = 0,
|
|
|
|
|
V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_AUTO = 1,
|
|
|
|
|
};
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+1)
|
|
|
|
|
#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+2)
|
2012-09-03 16:05:10 +04:00
|
|
|
enum v4l2_mpeg_cx2341x_video_luma_spatial_filter_type {
|
|
|
|
|
V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_OFF = 0,
|
|
|
|
|
V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_HOR = 1,
|
|
|
|
|
V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_VERT = 2,
|
|
|
|
|
V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_HV_SEPARABLE = 3,
|
|
|
|
|
V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_SYM_NON_SEPARABLE = 4,
|
|
|
|
|
};
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+3)
|
2012-09-03 16:05:10 +04:00
|
|
|
enum v4l2_mpeg_cx2341x_video_chroma_spatial_filter_type {
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|
V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_OFF = 0,
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|
V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_1D_HOR = 1,
|
|
|
|
|
};
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE (V4L2_CID_MPEG_CX2341X_BASE+4)
|
2012-09-03 16:05:10 +04:00
|
|
|
enum v4l2_mpeg_cx2341x_video_temporal_filter_mode {
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|
V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_MANUAL = 0,
|
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|
|
V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_AUTO = 1,
|
|
|
|
|
};
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER (V4L2_CID_MPEG_CX2341X_BASE+5)
|
|
|
|
|
#define V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE (V4L2_CID_MPEG_CX2341X_BASE+6)
|
2012-09-03 16:05:10 +04:00
|
|
|
enum v4l2_mpeg_cx2341x_video_median_filter_type {
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|
V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_OFF = 0,
|
|
|
|
|
V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR = 1,
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|
|
|
V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_VERT = 2,
|
|
|
|
|
V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR_VERT = 3,
|
|
|
|
|
V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_DIAG = 4,
|
|
|
|
|
};
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+7)
|
|
|
|
|
#define V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+8)
|
2012-09-03 16:05:10 +04:00
|
|
|
#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM (V4L2_CID_MPEG_CX2341X_BASE+9)
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP (V4L2_CID_MPEG_CX2341X_BASE+10)
|
|
|
|
|
#define V4L2_CID_MPEG_CX2341X_STREAM_INSERT_NAV_PACKETS (V4L2_CID_MPEG_CX2341X_BASE+11)
|
2012-09-03 16:05:10 +04:00
|
|
|
|
|
|
|
|
/* MPEG-class control IDs specific to the Samsung MFC 5.1 driver as defined by V4L2 */
|
|
|
|
|
#define V4L2_CID_MPEG_MFC51_BASE (V4L2_CTRL_CLASS_MPEG | 0x1100)
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY (V4L2_CID_MPEG_MFC51_BASE+0)
|
|
|
|
|
#define V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY_ENABLE (V4L2_CID_MPEG_MFC51_BASE+1)
|
|
|
|
|
#define V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE (V4L2_CID_MPEG_MFC51_BASE+2)
|
|
|
|
|
enum v4l2_mpeg_mfc51_video_frame_skip_mode {
|
|
|
|
|
V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED = 0,
|
|
|
|
|
V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT = 1,
|
|
|
|
|
V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT = 2,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE (V4L2_CID_MPEG_MFC51_BASE+3)
|
|
|
|
|
enum v4l2_mpeg_mfc51_video_force_frame_type {
|
|
|
|
|
V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED = 0,
|
|
|
|
|
V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_I_FRAME = 1,
|
|
|
|
|
V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_NOT_CODED = 2,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING (V4L2_CID_MPEG_MFC51_BASE+4)
|
|
|
|
|
#define V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV (V4L2_CID_MPEG_MFC51_BASE+5)
|
|
|
|
|
#define V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT (V4L2_CID_MPEG_MFC51_BASE+6)
|
|
|
|
|
#define V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF (V4L2_CID_MPEG_MFC51_BASE+7)
|
|
|
|
|
#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY (V4L2_CID_MPEG_MFC51_BASE+50)
|
|
|
|
|
#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK (V4L2_CID_MPEG_MFC51_BASE+51)
|
|
|
|
|
#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH (V4L2_CID_MPEG_MFC51_BASE+52)
|
|
|
|
|
#define V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC (V4L2_CID_MPEG_MFC51_BASE+53)
|
|
|
|
|
#define V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P (V4L2_CID_MPEG_MFC51_BASE+54)
|
|
|
|
|
|
|
|
|
|
/* Camera class control IDs */
|
|
|
|
|
|
2018-01-04 21:08:56 +03:00
|
|
|
#define V4L2_CID_CAMERA_CLASS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x900)
|
|
|
|
|
#define V4L2_CID_CAMERA_CLASS (V4L2_CTRL_CLASS_CAMERA | 1)
|
2012-09-03 16:05:10 +04:00
|
|
|
|
|
|
|
|
#define V4L2_CID_EXPOSURE_AUTO (V4L2_CID_CAMERA_CLASS_BASE+1)
|
|
|
|
|
enum v4l2_exposure_auto_type {
|
|
|
|
|
V4L2_EXPOSURE_AUTO = 0,
|
|
|
|
|
V4L2_EXPOSURE_MANUAL = 1,
|
|
|
|
|
V4L2_EXPOSURE_SHUTTER_PRIORITY = 2,
|
|
|
|
|
V4L2_EXPOSURE_APERTURE_PRIORITY = 3
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_EXPOSURE_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+2)
|
|
|
|
|
#define V4L2_CID_EXPOSURE_AUTO_PRIORITY (V4L2_CID_CAMERA_CLASS_BASE+3)
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_PAN_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+4)
|
|
|
|
|
#define V4L2_CID_TILT_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+5)
|
|
|
|
|
#define V4L2_CID_PAN_RESET (V4L2_CID_CAMERA_CLASS_BASE+6)
|
|
|
|
|
#define V4L2_CID_TILT_RESET (V4L2_CID_CAMERA_CLASS_BASE+7)
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_PAN_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+8)
|
|
|
|
|
#define V4L2_CID_TILT_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+9)
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_FOCUS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+10)
|
|
|
|
|
#define V4L2_CID_FOCUS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+11)
|
|
|
|
|
#define V4L2_CID_FOCUS_AUTO (V4L2_CID_CAMERA_CLASS_BASE+12)
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_ZOOM_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+13)
|
|
|
|
|
#define V4L2_CID_ZOOM_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+14)
|
|
|
|
|
#define V4L2_CID_ZOOM_CONTINUOUS (V4L2_CID_CAMERA_CLASS_BASE+15)
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_PRIVACY (V4L2_CID_CAMERA_CLASS_BASE+16)
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_IRIS_ABSOLUTE (V4L2_CID_CAMERA_CLASS_BASE+17)
|
|
|
|
|
#define V4L2_CID_IRIS_RELATIVE (V4L2_CID_CAMERA_CLASS_BASE+18)
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_AUTO_EXPOSURE_BIAS (V4L2_CID_CAMERA_CLASS_BASE+19)
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE (V4L2_CID_CAMERA_CLASS_BASE+20)
|
|
|
|
|
enum v4l2_auto_n_preset_white_balance {
|
|
|
|
|
V4L2_WHITE_BALANCE_MANUAL = 0,
|
|
|
|
|
V4L2_WHITE_BALANCE_AUTO = 1,
|
|
|
|
|
V4L2_WHITE_BALANCE_INCANDESCENT = 2,
|
|
|
|
|
V4L2_WHITE_BALANCE_FLUORESCENT = 3,
|
|
|
|
|
V4L2_WHITE_BALANCE_FLUORESCENT_H = 4,
|
|
|
|
|
V4L2_WHITE_BALANCE_HORIZON = 5,
|
|
|
|
|
V4L2_WHITE_BALANCE_DAYLIGHT = 6,
|
|
|
|
|
V4L2_WHITE_BALANCE_FLASH = 7,
|
|
|
|
|
V4L2_WHITE_BALANCE_CLOUDY = 8,
|
|
|
|
|
V4L2_WHITE_BALANCE_SHADE = 9,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_WIDE_DYNAMIC_RANGE (V4L2_CID_CAMERA_CLASS_BASE+21)
|
|
|
|
|
#define V4L2_CID_IMAGE_STABILIZATION (V4L2_CID_CAMERA_CLASS_BASE+22)
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_ISO_SENSITIVITY (V4L2_CID_CAMERA_CLASS_BASE+23)
|
|
|
|
|
#define V4L2_CID_ISO_SENSITIVITY_AUTO (V4L2_CID_CAMERA_CLASS_BASE+24)
|
|
|
|
|
enum v4l2_iso_sensitivity_auto_type {
|
|
|
|
|
V4L2_ISO_SENSITIVITY_MANUAL = 0,
|
|
|
|
|
V4L2_ISO_SENSITIVITY_AUTO = 1,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_EXPOSURE_METERING (V4L2_CID_CAMERA_CLASS_BASE+25)
|
|
|
|
|
enum v4l2_exposure_metering {
|
|
|
|
|
V4L2_EXPOSURE_METERING_AVERAGE = 0,
|
|
|
|
|
V4L2_EXPOSURE_METERING_CENTER_WEIGHTED = 1,
|
|
|
|
|
V4L2_EXPOSURE_METERING_SPOT = 2,
|
2013-03-14 14:01:24 +04:00
|
|
|
V4L2_EXPOSURE_METERING_MATRIX = 3,
|
2012-09-03 16:05:10 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_SCENE_MODE (V4L2_CID_CAMERA_CLASS_BASE+26)
|
|
|
|
|
enum v4l2_scene_mode {
|
|
|
|
|
V4L2_SCENE_MODE_NONE = 0,
|
|
|
|
|
V4L2_SCENE_MODE_BACKLIGHT = 1,
|
|
|
|
|
V4L2_SCENE_MODE_BEACH_SNOW = 2,
|
|
|
|
|
V4L2_SCENE_MODE_CANDLE_LIGHT = 3,
|
|
|
|
|
V4L2_SCENE_MODE_DAWN_DUSK = 4,
|
|
|
|
|
V4L2_SCENE_MODE_FALL_COLORS = 5,
|
|
|
|
|
V4L2_SCENE_MODE_FIREWORKS = 6,
|
|
|
|
|
V4L2_SCENE_MODE_LANDSCAPE = 7,
|
|
|
|
|
V4L2_SCENE_MODE_NIGHT = 8,
|
|
|
|
|
V4L2_SCENE_MODE_PARTY_INDOOR = 9,
|
|
|
|
|
V4L2_SCENE_MODE_PORTRAIT = 10,
|
|
|
|
|
V4L2_SCENE_MODE_SPORTS = 11,
|
|
|
|
|
V4L2_SCENE_MODE_SUNSET = 12,
|
|
|
|
|
V4L2_SCENE_MODE_TEXT = 13,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_3A_LOCK (V4L2_CID_CAMERA_CLASS_BASE+27)
|
|
|
|
|
#define V4L2_LOCK_EXPOSURE (1 << 0)
|
|
|
|
|
#define V4L2_LOCK_WHITE_BALANCE (1 << 1)
|
|
|
|
|
#define V4L2_LOCK_FOCUS (1 << 2)
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_AUTO_FOCUS_START (V4L2_CID_CAMERA_CLASS_BASE+28)
|
|
|
|
|
#define V4L2_CID_AUTO_FOCUS_STOP (V4L2_CID_CAMERA_CLASS_BASE+29)
|
|
|
|
|
#define V4L2_CID_AUTO_FOCUS_STATUS (V4L2_CID_CAMERA_CLASS_BASE+30)
|
|
|
|
|
#define V4L2_AUTO_FOCUS_STATUS_IDLE (0 << 0)
|
|
|
|
|
#define V4L2_AUTO_FOCUS_STATUS_BUSY (1 << 0)
|
|
|
|
|
#define V4L2_AUTO_FOCUS_STATUS_REACHED (1 << 1)
|
|
|
|
|
#define V4L2_AUTO_FOCUS_STATUS_FAILED (1 << 2)
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_AUTO_FOCUS_RANGE (V4L2_CID_CAMERA_CLASS_BASE+31)
|
|
|
|
|
enum v4l2_auto_focus_range {
|
|
|
|
|
V4L2_AUTO_FOCUS_RANGE_AUTO = 0,
|
|
|
|
|
V4L2_AUTO_FOCUS_RANGE_NORMAL = 1,
|
|
|
|
|
V4L2_AUTO_FOCUS_RANGE_MACRO = 2,
|
|
|
|
|
V4L2_AUTO_FOCUS_RANGE_INFINITY = 3,
|
|
|
|
|
};
|
|
|
|
|
|
2014-09-03 23:38:39 +04:00
|
|
|
#define V4L2_CID_PAN_SPEED (V4L2_CID_CAMERA_CLASS_BASE+32)
|
|
|
|
|
#define V4L2_CID_TILT_SPEED (V4L2_CID_CAMERA_CLASS_BASE+33)
|
2012-09-03 16:05:10 +04:00
|
|
|
|
2020-05-09 12:04:48 +03:00
|
|
|
#define V4L2_CID_CAMERA_ORIENTATION (V4L2_CID_CAMERA_CLASS_BASE+34)
|
|
|
|
|
#define V4L2_CAMERA_ORIENTATION_FRONT 0
|
|
|
|
|
#define V4L2_CAMERA_ORIENTATION_BACK 1
|
|
|
|
|
#define V4L2_CAMERA_ORIENTATION_EXTERNAL 2
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_CAMERA_SENSOR_ROTATION (V4L2_CID_CAMERA_CLASS_BASE+35)
|
|
|
|
|
|
2012-09-03 16:05:10 +04:00
|
|
|
/* FM Modulator class control IDs */
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_FM_TX_CLASS_BASE (V4L2_CTRL_CLASS_FM_TX | 0x900)
|
|
|
|
|
#define V4L2_CID_FM_TX_CLASS (V4L2_CTRL_CLASS_FM_TX | 1)
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_RDS_TX_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 1)
|
|
|
|
|
#define V4L2_CID_RDS_TX_PI (V4L2_CID_FM_TX_CLASS_BASE + 2)
|
|
|
|
|
#define V4L2_CID_RDS_TX_PTY (V4L2_CID_FM_TX_CLASS_BASE + 3)
|
|
|
|
|
#define V4L2_CID_RDS_TX_PS_NAME (V4L2_CID_FM_TX_CLASS_BASE + 5)
|
|
|
|
|
#define V4L2_CID_RDS_TX_RADIO_TEXT (V4L2_CID_FM_TX_CLASS_BASE + 6)
|
2014-07-21 17:45:37 +04:00
|
|
|
#define V4L2_CID_RDS_TX_MONO_STEREO (V4L2_CID_FM_TX_CLASS_BASE + 7)
|
|
|
|
|
#define V4L2_CID_RDS_TX_ARTIFICIAL_HEAD (V4L2_CID_FM_TX_CLASS_BASE + 8)
|
|
|
|
|
#define V4L2_CID_RDS_TX_COMPRESSED (V4L2_CID_FM_TX_CLASS_BASE + 9)
|
|
|
|
|
#define V4L2_CID_RDS_TX_DYNAMIC_PTY (V4L2_CID_FM_TX_CLASS_BASE + 10)
|
|
|
|
|
#define V4L2_CID_RDS_TX_TRAFFIC_ANNOUNCEMENT (V4L2_CID_FM_TX_CLASS_BASE + 11)
|
|
|
|
|
#define V4L2_CID_RDS_TX_TRAFFIC_PROGRAM (V4L2_CID_FM_TX_CLASS_BASE + 12)
|
|
|
|
|
#define V4L2_CID_RDS_TX_MUSIC_SPEECH (V4L2_CID_FM_TX_CLASS_BASE + 13)
|
|
|
|
|
#define V4L2_CID_RDS_TX_ALT_FREQS_ENABLE (V4L2_CID_FM_TX_CLASS_BASE + 14)
|
|
|
|
|
#define V4L2_CID_RDS_TX_ALT_FREQS (V4L2_CID_FM_TX_CLASS_BASE + 15)
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2012-09-03 16:05:10 +04:00
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#define V4L2_CID_AUDIO_LIMITER_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 64)
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#define V4L2_CID_AUDIO_LIMITER_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 65)
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#define V4L2_CID_AUDIO_LIMITER_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 66)
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#define V4L2_CID_AUDIO_COMPRESSION_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 80)
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#define V4L2_CID_AUDIO_COMPRESSION_GAIN (V4L2_CID_FM_TX_CLASS_BASE + 81)
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#define V4L2_CID_AUDIO_COMPRESSION_THRESHOLD (V4L2_CID_FM_TX_CLASS_BASE + 82)
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#define V4L2_CID_AUDIO_COMPRESSION_ATTACK_TIME (V4L2_CID_FM_TX_CLASS_BASE + 83)
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#define V4L2_CID_AUDIO_COMPRESSION_RELEASE_TIME (V4L2_CID_FM_TX_CLASS_BASE + 84)
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#define V4L2_CID_PILOT_TONE_ENABLED (V4L2_CID_FM_TX_CLASS_BASE + 96)
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#define V4L2_CID_PILOT_TONE_DEVIATION (V4L2_CID_FM_TX_CLASS_BASE + 97)
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#define V4L2_CID_PILOT_TONE_FREQUENCY (V4L2_CID_FM_TX_CLASS_BASE + 98)
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#define V4L2_CID_TUNE_PREEMPHASIS (V4L2_CID_FM_TX_CLASS_BASE + 112)
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enum v4l2_preemphasis {
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V4L2_PREEMPHASIS_DISABLED = 0,
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V4L2_PREEMPHASIS_50_uS = 1,
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V4L2_PREEMPHASIS_75_uS = 2,
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};
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#define V4L2_CID_TUNE_POWER_LEVEL (V4L2_CID_FM_TX_CLASS_BASE + 113)
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#define V4L2_CID_TUNE_ANTENNA_CAPACITOR (V4L2_CID_FM_TX_CLASS_BASE + 114)
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/* Flash and privacy (indicator) light controls */
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#define V4L2_CID_FLASH_CLASS_BASE (V4L2_CTRL_CLASS_FLASH | 0x900)
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#define V4L2_CID_FLASH_CLASS (V4L2_CTRL_CLASS_FLASH | 1)
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#define V4L2_CID_FLASH_LED_MODE (V4L2_CID_FLASH_CLASS_BASE + 1)
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enum v4l2_flash_led_mode {
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V4L2_FLASH_LED_MODE_NONE,
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V4L2_FLASH_LED_MODE_FLASH,
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V4L2_FLASH_LED_MODE_TORCH,
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};
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#define V4L2_CID_FLASH_STROBE_SOURCE (V4L2_CID_FLASH_CLASS_BASE + 2)
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enum v4l2_flash_strobe_source {
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V4L2_FLASH_STROBE_SOURCE_SOFTWARE,
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V4L2_FLASH_STROBE_SOURCE_EXTERNAL,
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};
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#define V4L2_CID_FLASH_STROBE (V4L2_CID_FLASH_CLASS_BASE + 3)
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#define V4L2_CID_FLASH_STROBE_STOP (V4L2_CID_FLASH_CLASS_BASE + 4)
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#define V4L2_CID_FLASH_STROBE_STATUS (V4L2_CID_FLASH_CLASS_BASE + 5)
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#define V4L2_CID_FLASH_TIMEOUT (V4L2_CID_FLASH_CLASS_BASE + 6)
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#define V4L2_CID_FLASH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 7)
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#define V4L2_CID_FLASH_TORCH_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 8)
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#define V4L2_CID_FLASH_INDICATOR_INTENSITY (V4L2_CID_FLASH_CLASS_BASE + 9)
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#define V4L2_CID_FLASH_FAULT (V4L2_CID_FLASH_CLASS_BASE + 10)
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#define V4L2_FLASH_FAULT_OVER_VOLTAGE (1 << 0)
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#define V4L2_FLASH_FAULT_TIMEOUT (1 << 1)
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#define V4L2_FLASH_FAULT_OVER_TEMPERATURE (1 << 2)
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#define V4L2_FLASH_FAULT_SHORT_CIRCUIT (1 << 3)
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#define V4L2_FLASH_FAULT_OVER_CURRENT (1 << 4)
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#define V4L2_FLASH_FAULT_INDICATOR (1 << 5)
|
2014-03-03 13:52:08 +04:00
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#define V4L2_FLASH_FAULT_UNDER_VOLTAGE (1 << 6)
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#define V4L2_FLASH_FAULT_INPUT_VOLTAGE (1 << 7)
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#define V4L2_FLASH_FAULT_LED_OVER_TEMPERATURE (1 << 8)
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2012-09-03 16:05:10 +04:00
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#define V4L2_CID_FLASH_CHARGE (V4L2_CID_FLASH_CLASS_BASE + 11)
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#define V4L2_CID_FLASH_READY (V4L2_CID_FLASH_CLASS_BASE + 12)
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/* JPEG-class control IDs */
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#define V4L2_CID_JPEG_CLASS_BASE (V4L2_CTRL_CLASS_JPEG | 0x900)
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#define V4L2_CID_JPEG_CLASS (V4L2_CTRL_CLASS_JPEG | 1)
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#define V4L2_CID_JPEG_CHROMA_SUBSAMPLING (V4L2_CID_JPEG_CLASS_BASE + 1)
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enum v4l2_jpeg_chroma_subsampling {
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V4L2_JPEG_CHROMA_SUBSAMPLING_444 = 0,
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V4L2_JPEG_CHROMA_SUBSAMPLING_422 = 1,
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V4L2_JPEG_CHROMA_SUBSAMPLING_420 = 2,
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V4L2_JPEG_CHROMA_SUBSAMPLING_411 = 3,
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V4L2_JPEG_CHROMA_SUBSAMPLING_410 = 4,
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V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY = 5,
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};
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#define V4L2_CID_JPEG_RESTART_INTERVAL (V4L2_CID_JPEG_CLASS_BASE + 2)
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#define V4L2_CID_JPEG_COMPRESSION_QUALITY (V4L2_CID_JPEG_CLASS_BASE + 3)
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#define V4L2_CID_JPEG_ACTIVE_MARKER (V4L2_CID_JPEG_CLASS_BASE + 4)
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#define V4L2_JPEG_ACTIVE_MARKER_APP0 (1 << 0)
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#define V4L2_JPEG_ACTIVE_MARKER_APP1 (1 << 1)
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#define V4L2_JPEG_ACTIVE_MARKER_COM (1 << 16)
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#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17)
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#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18)
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|
2013-01-24 11:42:05 +04:00
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2012-09-03 16:05:10 +04:00
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/* Image source controls */
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#define V4L2_CID_IMAGE_SOURCE_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_SOURCE | 0x900)
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#define V4L2_CID_IMAGE_SOURCE_CLASS (V4L2_CTRL_CLASS_IMAGE_SOURCE | 1)
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#define V4L2_CID_VBLANK (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 1)
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#define V4L2_CID_HBLANK (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 2)
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|
#define V4L2_CID_ANALOGUE_GAIN (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 3)
|
2014-05-28 16:38:21 +04:00
|
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|
#define V4L2_CID_TEST_PATTERN_RED (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 4)
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|
#define V4L2_CID_TEST_PATTERN_GREENR (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 5)
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|
#define V4L2_CID_TEST_PATTERN_BLUE (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 6)
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|
|
#define V4L2_CID_TEST_PATTERN_GREENB (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 7)
|
2019-10-07 18:06:33 +03:00
|
|
|
#define V4L2_CID_UNIT_CELL_SIZE (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 8)
|
2012-09-03 16:05:10 +04:00
|
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|
|
|
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|
|
/* Image processing controls */
|
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|
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|
|
#define V4L2_CID_IMAGE_PROC_CLASS_BASE (V4L2_CTRL_CLASS_IMAGE_PROC | 0x900)
|
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|
|
|
#define V4L2_CID_IMAGE_PROC_CLASS (V4L2_CTRL_CLASS_IMAGE_PROC | 1)
|
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|
|
|
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|
|
|
#define V4L2_CID_LINK_FREQ (V4L2_CID_IMAGE_PROC_CLASS_BASE + 1)
|
|
|
|
|
#define V4L2_CID_PIXEL_RATE (V4L2_CID_IMAGE_PROC_CLASS_BASE + 2)
|
2012-10-01 15:17:36 +04:00
|
|
|
#define V4L2_CID_TEST_PATTERN (V4L2_CID_IMAGE_PROC_CLASS_BASE + 3)
|
2016-08-04 19:14:02 +03:00
|
|
|
#define V4L2_CID_DEINTERLACING_MODE (V4L2_CID_IMAGE_PROC_CLASS_BASE + 4)
|
2017-06-08 22:59:58 +03:00
|
|
|
#define V4L2_CID_DIGITAL_GAIN (V4L2_CID_IMAGE_PROC_CLASS_BASE + 5)
|
2013-01-24 11:42:05 +04:00
|
|
|
|
|
|
|
|
/* DV-class control IDs defined by V4L2 */
|
|
|
|
|
#define V4L2_CID_DV_CLASS_BASE (V4L2_CTRL_CLASS_DV | 0x900)
|
|
|
|
|
#define V4L2_CID_DV_CLASS (V4L2_CTRL_CLASS_DV | 1)
|
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|
|
|
|
|
|
|
|
#define V4L2_CID_DV_TX_HOTPLUG (V4L2_CID_DV_CLASS_BASE + 1)
|
|
|
|
|
#define V4L2_CID_DV_TX_RXSENSE (V4L2_CID_DV_CLASS_BASE + 2)
|
|
|
|
|
#define V4L2_CID_DV_TX_EDID_PRESENT (V4L2_CID_DV_CLASS_BASE + 3)
|
|
|
|
|
#define V4L2_CID_DV_TX_MODE (V4L2_CID_DV_CLASS_BASE + 4)
|
|
|
|
|
enum v4l2_dv_tx_mode {
|
|
|
|
|
V4L2_DV_TX_MODE_DVI_D = 0,
|
|
|
|
|
V4L2_DV_TX_MODE_HDMI = 1,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_DV_TX_RGB_RANGE (V4L2_CID_DV_CLASS_BASE + 5)
|
|
|
|
|
enum v4l2_dv_rgb_range {
|
|
|
|
|
V4L2_DV_RGB_RANGE_AUTO = 0,
|
|
|
|
|
V4L2_DV_RGB_RANGE_LIMITED = 1,
|
|
|
|
|
V4L2_DV_RGB_RANGE_FULL = 2,
|
|
|
|
|
};
|
|
|
|
|
|
2016-01-27 16:31:39 +03:00
|
|
|
#define V4L2_CID_DV_TX_IT_CONTENT_TYPE (V4L2_CID_DV_CLASS_BASE + 6)
|
|
|
|
|
enum v4l2_dv_it_content_type {
|
|
|
|
|
V4L2_DV_IT_CONTENT_TYPE_GRAPHICS = 0,
|
|
|
|
|
V4L2_DV_IT_CONTENT_TYPE_PHOTO = 1,
|
|
|
|
|
V4L2_DV_IT_CONTENT_TYPE_CINEMA = 2,
|
|
|
|
|
V4L2_DV_IT_CONTENT_TYPE_GAME = 3,
|
|
|
|
|
V4L2_DV_IT_CONTENT_TYPE_NO_ITC = 4,
|
|
|
|
|
};
|
|
|
|
|
|
2013-01-24 11:42:05 +04:00
|
|
|
#define V4L2_CID_DV_RX_POWER_PRESENT (V4L2_CID_DV_CLASS_BASE + 100)
|
|
|
|
|
#define V4L2_CID_DV_RX_RGB_RANGE (V4L2_CID_DV_CLASS_BASE + 101)
|
2016-01-27 16:31:39 +03:00
|
|
|
#define V4L2_CID_DV_RX_IT_CONTENT_TYPE (V4L2_CID_DV_CLASS_BASE + 102)
|
2013-01-24 11:42:05 +04:00
|
|
|
|
2013-03-27 05:47:23 +04:00
|
|
|
#define V4L2_CID_FM_RX_CLASS_BASE (V4L2_CTRL_CLASS_FM_RX | 0x900)
|
|
|
|
|
#define V4L2_CID_FM_RX_CLASS (V4L2_CTRL_CLASS_FM_RX | 1)
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_TUNE_DEEMPHASIS (V4L2_CID_FM_RX_CLASS_BASE + 1)
|
|
|
|
|
enum v4l2_deemphasis {
|
|
|
|
|
V4L2_DEEMPHASIS_DISABLED = V4L2_PREEMPHASIS_DISABLED,
|
|
|
|
|
V4L2_DEEMPHASIS_50_uS = V4L2_PREEMPHASIS_50_uS,
|
|
|
|
|
V4L2_DEEMPHASIS_75_uS = V4L2_PREEMPHASIS_75_uS,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_RDS_RECEPTION (V4L2_CID_FM_RX_CLASS_BASE + 2)
|
2014-07-21 17:45:40 +04:00
|
|
|
#define V4L2_CID_RDS_RX_PTY (V4L2_CID_FM_RX_CLASS_BASE + 3)
|
|
|
|
|
#define V4L2_CID_RDS_RX_PS_NAME (V4L2_CID_FM_RX_CLASS_BASE + 4)
|
|
|
|
|
#define V4L2_CID_RDS_RX_RADIO_TEXT (V4L2_CID_FM_RX_CLASS_BASE + 5)
|
|
|
|
|
#define V4L2_CID_RDS_RX_TRAFFIC_ANNOUNCEMENT (V4L2_CID_FM_RX_CLASS_BASE + 6)
|
|
|
|
|
#define V4L2_CID_RDS_RX_TRAFFIC_PROGRAM (V4L2_CID_FM_RX_CLASS_BASE + 7)
|
|
|
|
|
#define V4L2_CID_RDS_RX_MUSIC_SPEECH (V4L2_CID_FM_RX_CLASS_BASE + 8)
|
2013-03-27 05:47:23 +04:00
|
|
|
|
2014-01-25 06:44:26 +04:00
|
|
|
#define V4L2_CID_RF_TUNER_CLASS_BASE (V4L2_CTRL_CLASS_RF_TUNER | 0x900)
|
|
|
|
|
#define V4L2_CID_RF_TUNER_CLASS (V4L2_CTRL_CLASS_RF_TUNER | 1)
|
|
|
|
|
|
2014-02-05 05:13:44 +04:00
|
|
|
#define V4L2_CID_RF_TUNER_BANDWIDTH_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 11)
|
|
|
|
|
#define V4L2_CID_RF_TUNER_BANDWIDTH (V4L2_CID_RF_TUNER_CLASS_BASE + 12)
|
2015-10-10 19:50:58 +03:00
|
|
|
#define V4L2_CID_RF_TUNER_RF_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 32)
|
2014-02-05 05:13:44 +04:00
|
|
|
#define V4L2_CID_RF_TUNER_LNA_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 41)
|
|
|
|
|
#define V4L2_CID_RF_TUNER_LNA_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 42)
|
|
|
|
|
#define V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 51)
|
|
|
|
|
#define V4L2_CID_RF_TUNER_MIXER_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 52)
|
|
|
|
|
#define V4L2_CID_RF_TUNER_IF_GAIN_AUTO (V4L2_CID_RF_TUNER_CLASS_BASE + 61)
|
|
|
|
|
#define V4L2_CID_RF_TUNER_IF_GAIN (V4L2_CID_RF_TUNER_CLASS_BASE + 62)
|
2014-02-07 09:46:16 +04:00
|
|
|
#define V4L2_CID_RF_TUNER_PLL_LOCK (V4L2_CID_RF_TUNER_CLASS_BASE + 91)
|
2014-01-25 06:44:26 +04:00
|
|
|
|
2014-03-28 20:00:08 +04:00
|
|
|
|
|
|
|
|
/* Detection-class control IDs defined by V4L2 */
|
|
|
|
|
#define V4L2_CID_DETECT_CLASS_BASE (V4L2_CTRL_CLASS_DETECT | 0x900)
|
|
|
|
|
#define V4L2_CID_DETECT_CLASS (V4L2_CTRL_CLASS_DETECT | 1)
|
|
|
|
|
|
|
|
|
|
#define V4L2_CID_DETECT_MD_MODE (V4L2_CID_DETECT_CLASS_BASE + 1)
|
|
|
|
|
enum v4l2_detect_md_mode {
|
|
|
|
|
V4L2_DETECT_MD_MODE_DISABLED = 0,
|
|
|
|
|
V4L2_DETECT_MD_MODE_GLOBAL = 1,
|
|
|
|
|
V4L2_DETECT_MD_MODE_THRESHOLD_GRID = 2,
|
|
|
|
|
V4L2_DETECT_MD_MODE_REGION_GRID = 3,
|
|
|
|
|
};
|
|
|
|
|
#define V4L2_CID_DETECT_MD_GLOBAL_THRESHOLD (V4L2_CID_DETECT_CLASS_BASE + 2)
|
|
|
|
|
#define V4L2_CID_DETECT_MD_THRESHOLD_GRID (V4L2_CID_DETECT_CLASS_BASE + 3)
|
|
|
|
|
#define V4L2_CID_DETECT_MD_REGION_GRID (V4L2_CID_DETECT_CLASS_BASE + 4)
|
|
|
|
|
|
2012-09-03 16:05:10 +04:00
|
|
|
#endif
|
